JP2016195196A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a parasitic capacitance caused by a protection film on a gate electrode.SOLUTION: A semiconductor device having a first region R1 with a MIM capacitor, and a second region R2 with a field-effect transistor, comprises: a semiconductor laminate 101; a lower electrode 121 provided in the first region R1; an insulating film 122 provided in the first region R1; a source electrode 107 provided in the second region R2; a drain electrode 105; a gate electrode 106; a first protection film 102 provided at a part not provided with the source electrode 107, the drain electrode 105, or the gate electrode 106, in the second region; a second protection film 112 provided on a surface of the insulating film; an upper electrode 123 provided above the lower electrode; and a third protection film 141 provided on a surface of the upper electrode 123. A sum of a film thickness of the second protection film 112 on the gate electrode 106 and a film thickness of the third protection film 141 is smaller than a sum of a film thickness of the insulating film 122 and a film thickness of the second protection film 112.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a semiconductor device.

By using an MMIC amplifier having an FET including a HEMT (High Electron Mobility Transistor) and a MESFET (Metal Semiconductor Field Effect Transistor) and an MIM (Metal Insulator Metal) capacitor, the radar device and the microwave communication device can be downsized. .
In a semiconductor device such as an MMIC amplifier in which an MIM capacitor and an HEMT are formed on the same substrate, the insulating film of the MIM capacitor is made to have a desired film thickness, and the gate protective film of the HEMT is made thin to reduce parasitic capacitance. Is desirable.

JP 2010-129690 A

  Provided is a semiconductor device capable of reducing parasitic capacitance caused by a protective film on a gate electrode.

  According to the embodiment, a semiconductor device having a first region having an MIM capacitor and a second region having a field effect transistor adjacent to the first region, wherein the semiconductor is stacked on the substrate. A lower electrode provided on a top surface of a part of the semiconductor stack in the first region, an insulating film provided on a surface of the lower electrode in the first region, and a second region Provided between the source electrode provided on the semiconductor laminate, the drain electrode provided on the semiconductor laminate in the second region, and the source electrode and drain electrode in the second region A gate electrode; at least a part of the upper surface of the semiconductor stack in the first region where the lower electrode is not provided; and the source electrode, the drain electrode, or the gate electrode in the second region. A first protective film provided in a portion not provided; a surface of the insulating film; an upper surface of the first protective film; a surface of the source electrode; a surface of the gate electrode; and a surface of the drain electrode A second protective film provided on the upper electrode; an upper electrode provided on the upper surface of the second protective film above the lower electrode; and provided on the surface of the upper electrode and on the surface of the second protective film. And a third protective film provided. The second region of the semiconductor includes an electron supply layer and a channel layer, and the sum of the thickness of the second protective film and the thickness of the third protective film on the gate electrode is the lower electrode and It is smaller than the sum of the film thickness of the insulating film and the film thickness of the second protective film between the upper electrode.

1 is a plan view of a semiconductor device according to a first embodiment. (A) is a schematic cross-sectional view along the line А-А in FIG. FIG. 5B is a circuit diagram illustrating parasitic capacitance in the vicinity of the gate electrode. (A) is a schematic cross section explaining to the formation of a semiconductor laminated body among the manufacturing methods of the semiconductor device concerning a 1st embodiment. FIG. 5B is a schematic cross-sectional view illustrating the formation of the isolation region in the semiconductor device manufacturing method according to the first embodiment. FIG. 4C is a schematic cross-sectional view illustrating the formation of the insulating film in the semiconductor device manufacturing method according to the first embodiment. FIG. 6D is a schematic cross-sectional view illustrating the formation of the first protective film in the method for manufacturing the semiconductor device according to the first embodiment. (A) is a schematic cross section explaining formation of an ohmic electrode among the manufacturing methods of the semiconductor device concerning a 1st embodiment. FIG. 5B is a schematic cross-sectional view illustrating the formation of the gate electrode in the method for manufacturing the semiconductor device according to the first embodiment. (C) is a schematic cross section explaining formation of a lower electrode and a pad electrode in the manufacturing method of the semiconductor device concerning a 1st embodiment. (A) is a schematic cross section explaining formation of an insulating film among the manufacturing methods of the semiconductor device concerning a 1st embodiment. FIG. 5B is a schematic cross-sectional view illustrating the formation of an insulating film in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 4C is a schematic cross-sectional view illustrating the formation of the second protective film in the method for manufacturing the semiconductor device according to the first embodiment. (A) is a schematic cross section explaining formation of an upper electrode among the manufacturing methods of the semiconductor device concerning a 1st embodiment. FIG. 6B is a schematic cross-sectional view illustrating the formation of a third protective film in the method for manufacturing a semiconductor device according to the first embodiment. It is a schematic cross-sectional view illustrating a semiconductor device according to a comparative example. It is sectional drawing explaining the semiconductor device which concerns on 2nd Embodiment. (A) is a schematic cross section explaining formation of an upper electrode among the manufacturing methods of the semiconductor device concerning a 2nd embodiment. FIG. 6B is a schematic cross-sectional view illustrating the formation of a second protective film in the method for manufacturing a semiconductor device according to the second embodiment. It is sectional drawing explaining the semiconductor device which concerns on 3rd Embodiment. It is a schematic cross section explaining formation of the 1st protective film among the manufacturing methods of the semiconductor device concerning a 3rd embodiment. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a plan view of the semiconductor device according to the present embodiment.
In the semiconductor device according to the present embodiment, the MIM capacitor and the HEMT are formed on the same substrate.

First, the configuration of the semiconductor device 100 according to the present embodiment will be described.
As illustrated in FIG. 1, the semiconductor device 100 according to the present embodiment includes a HEMT 110 provided on a substrate 101. The HEMT 110 includes a finger-shaped source electrode 107, a finger-shaped drain electrode 105, and a gate electrode 106 between the source electrode 107 and the drain electrode 105. Further, the semiconductor device 100 includes an MIM capacitor 104 provided on the substrate 101. An isolation region 103 is provided between the MIM capacitor 104 and the HEMT 110.

FIG. 2A is a schematic cross-sectional view along the line А-А in FIG.
As shown in FIG. 2, the semiconductor device 100 according to the present embodiment includes an MIM capacitor region R <b> 1 and a HEMT region R <b> 2 that is a part of the HEMT 110.

In the lowermost layer of the semiconductor device 100, the semiconductor stacked body 101 is provided over the entire surface of the MIM capacitor region R1 and the HEMT region R2. The semiconductor stacked body 101 is formed by stacking a substrate 101a, a buffer layer 101e, a channel layer 101b, and an electron supply layer 101c in this order.
The buffer layer 101e is a semiconductor containing, for example, gallium nitride (GaN). The channel layer 101b is a semiconductor containing gallium nitride, for example. The electron supply layer 101c is, for example, a semiconductor that forms a heterojunction with the channel layer 101b and includes, for example, Al _0.2 Ga _0.8 N.

The electrons that have moved from the electron supply layer 101c to the channel layer 101b form a two-dimensional electron gas layer (2DEG) 101d on the channel layer 101b, and become a high mobility and high density electron gas.
The buffer layer 101e, the channel layer 101b, and the electron supply layer 101c around the MIM capacitor region R1 and the HEMT region R2 are provided with an isolation region 103 whose resistance is increased by ion implantation or the like. Thereby, in the HEMT region R2, it is possible to suppress leakage of electrons that have moved from the electron supply layer 101c to the channel layer 101b to other circuit elements such as an MIM capacitor.

  In the MIM capacitor region R1, a lower electrode 121 is provided on a part of the upper surface of the semiconductor stacked body 101. An insulating film 122 is provided on the surface of the lower electrode 121 and on a part of the upper surface of the semiconductor stacked body 101.

  In the HEMT region R2, a source electrode 107, a gate electrode 106, and a drain electrode 105 are provided on the semiconductor stacked body 101 in order from the MIM capacitor region R1 side.

  On the surface of the insulating film 122 in the MIM capacitor region R1, on the semiconductor stacked body 101 where the lower electrode 121 is not provided, and on the semiconductor stacked body 101 in the HEMT region R2, the source electrode 107, the drain electrode 105, or A first protective film 102 is provided in a portion where the gate electrode 106 is not provided.

  On the entire surface of the MIM capacitor region R1 and the HEMT region R2, that is, on the surface of the insulating film 122, on the upper surface of the first protective film 102, on the surface of the source electrode 107, on the surface of the gate electrode 106, and on the surface of the drain electrode 105. Two protective films 112 are provided.

  An upper electrode 123 is provided on the upper surface of the second protective film 112 above the lower electrode 121. A third protective film 141 is provided on the surface of the upper electrode 123 and the surface of the second protective film 112.

  A part of the source electrode 107 is adjacent to the first protective film 102 through the boundary surface 131. The source electrode 107 is formed of an ohmic electrode 118 provided on the semiconductor stacked body 101 and a pad electrode 119 provided thereon. The length of the pad electrode 119 in the direction from the source electrode 107 to the drain electrode 105 is smaller than the length of the ohmic electrode 118 in the direction from the source electrode 107 to the drain electrode 105, and has a convex shape when viewed from the direction perpendicular to the paper surface. doing. The pad electrode 119 is provided to reduce the wiring resistance value to the source electrode 107.

  The gate electrode 106 is formed of a gate electrode lower portion 108 provided on the semiconductor stacked body 101 and a gate electrode upper portion 109 provided thereon. The length of the gate electrode upper portion 109 in the direction from the source electrode 107 to the drain electrode 105 is larger than the length of the gate electrode lower portion 108 in the direction from the source electrode 107 to the drain electrode 105, and is substantially as viewed from the direction perpendicular to the paper surface. T-shaped. The gate electrode upper portion 109 is provided to reduce the wiring resistance value to the gate electrode lower portion 108.

The drain electrode 105 is formed of an ohmic electrode 128 provided on the semiconductor stacked body 101 and a pad electrode 129 provided thereon. The length of the pad electrode 129 in the direction from the source electrode 107 to the drain electrode 105 is smaller than the length of the ohmic electrode 128 in the direction from the source electrode 107 to the drain electrode 105, and has a convex shape when viewed from the direction perpendicular to the paper surface. doing. The pad electrode 129 is provided to reduce the wiring resistance value to the drain electrode 105.
The lower electrode 121, the upper electrode 123, the separation region 103, the source electrode 107, the gate electrode 106, and the drain electrode 105 extend in a direction perpendicular to the paper surface.

The thickness of the source electrode 107 is approximately the same as the thickness of the drain electrode 105. The gate electrode 106 is thinner than the source electrode 107.
The film thickness t102 of the first protective film 102 is, for example, 200 to 500 mm.
The film thickness of the ohmic electrode 118 is approximately the same as the film thickness of the ohmic electrode 128 and is thicker than the film thickness of the first protective film 102.
The total film thickness of the film thickness t105 of the second protective film 112 on the gate electrode 106 and the film thickness t104 of the third protective film 141 is, for example, 500 mm.
The total film thickness t101 of the insulating film 122 sandwiched between the lower electrode 121 and the upper electrode 123 and the film thickness t103 of the second protective film 112 is the film thickness t105 of the second protective film 112 on the gate electrode 106. And the total thickness of the third protective film 141 and the thickness t104, for example, 2000 mm.
In the semiconductor device 100 according to the present embodiment, an example in which one MIM capacitor 104 is provided is shown, but the present invention is not limited to this.

Next, a method for manufacturing the semiconductor device 100 according to the present embodiment will be described.
FIG. 3A is a schematic cross-sectional view illustrating the process up to the formation of the substrate 101 in the semiconductor device manufacturing method according to the present embodiment.
First, the buffer layer 101e, the channel layer 101b, and the electron supply layer 101c are laminated and formed in this order on the substrate 101a using the MOCVD (Metal Organic Chemical Vapor Deposition) method, the MBE (EMolecular Beam Epitaxy) method, or the like.

FIG. 3B is a schematic cross-sectional view for explaining the formation of the isolation region 103 in the semiconductor device manufacturing method according to the present embodiment.
When the buffer layer 101e, the channel layer 101b, and the electron supply layer 101c are formed of a semiconductor containing gallium nitride, for example, argon (Аr) ions or the like are implanted into a desired portion to form the isolation region 103.

  Note that the isolation region 103 specifies a range to be removed by lithography, and after selectively removing a part of the semiconductor stacked body 101 by performing etching, the removed portion includes, for example, silicon nitride (SiN) or the like. Alternatively, the insulating material may be embedded.

FIG. 3C is a schematic cross-sectional view illustrating the formation of the insulating film 152 in the semiconductor device manufacturing method according to the present embodiment.
For example, silicon nitride (SiN) is deposited on the semiconductor stacked body 101 and the isolation region 103 to form the insulating film 152. The film thickness t102 of the insulating film 152 is, for example, 200 to 500 mm.

FIG. 3D is a schematic cross-sectional view illustrating the formation of the openings 161, 162, 163, and 164 in the semiconductor device manufacturing method according to the present embodiment.
In the insulating film 152, a range to be removed by lithography is specified, and the insulating film 152 is selectively removed by performing etching. The remainder is the first protective film 102. The removed portion in the MIM capacitor region R1 is referred to as an opening 164. The removed portions in the HEMT region R2 are defined as openings 161, 162, and 163 in order from the MIM capacitor region R1 side.

FIG. 4A is a schematic cross-sectional view illustrating the formation of ohmic electrodes 118 and 128 in the method for manufacturing a semiconductor device according to this embodiment.
In the opening 161 on the semiconductor stacked body 101, for example, aluminum (Аl), titanium (Ti), platinum (Pt), and gold (Аu) are deposited in this order to form the ohmic electrode 118. At the same time, for example, aluminum, titanium, platinum, and gold are vapor-deposited in this order in the opening 163 to form the ohmic electrode 128. Thereafter, annealing is performed at about 600 ° C. to about 700 ° C.

FIG. 4B is a schematic cross-sectional view illustrating the formation of the gate electrode 106 in the method for manufacturing the semiconductor device according to the present embodiment.
In the opening 162 on the semiconductor stacked body 101, for example, nickel (Ni) and gold (Аu) are deposited to form the gate electrode 106 including the gate electrode lower part 108 and the gate electrode upper part 109.

FIG. 4C is a schematic cross-sectional view illustrating the formation of the lower electrode 121, the pad electrode 119, and the pad electrode 129 in the semiconductor device manufacturing method according to the present embodiment.
A lower electrode 121 is formed by vapor-depositing a metal on a part of the upper surface of the semiconductor stacked body 101 in the MIM capacitor region R2. At the same time, metal is vapor-deposited on a part of the upper surface of the ohmic electrodes 118 and 128 to form the pad electrodes 119 and 129, and the source electrode 107 and the drain electrode 105 including the ohmic electrodes 118 and 128 and the pad electrodes 119 and 129 are formed. To do.

FIG. 5A is a schematic cross-sectional view illustrating the formation of the insulating film 172 in the semiconductor device manufacturing method according to the present embodiment.
An insulating film 172 is formed by depositing, for example, silicon nitride on the entire surface of the wafer, that is, on the entire surface of the MIM capacitor region R1 and the HEMT region R2. The etching rate of the insulating film 172 with respect to the etching solution is set higher than the etching rate of the first protective film 102 with respect to the etching solution. In addition, the insulating film 172 over the lower electrode 121 is formed thick.

FIG. 5B is a schematic cross-sectional view illustrating the formation of the insulating film 122 in the method for manufacturing the semiconductor device according to the present embodiment.
In the insulating film 172, a range to be removed by lithography is specified, and etching is performed to remove the insulating film 172 in the HEMT region R2. At this time, the etching rate of the insulating film 172 is about 30 times the etching rate of the first protective film 102 already annealed. Therefore, the insulating film 172 in the HEMT region R2 is removed, and the first protective film 102 remains without being removed. The portion that remains without the insulating film 172 being removed is referred to as an insulating film 122.

FIG. 5C is a schematic cross-sectional view illustrating the formation of the second protective film 112 in the semiconductor device manufacturing method according to the present embodiment.
For example, silicon nitride is deposited on the entire surface of the wafer, that is, the entire surface of the MIM capacitor region R1 and the HEMT region R2, to form the second protective film 112. At this time, in order to reduce the influence of the parasitic capacitance generated by the second protective film 112 on the gate electrode 106, the second protective film 112 is formed thin.

FIG. 6A is a schematic cross-sectional view illustrating the formation of the upper electrode 123 in the semiconductor device manufacturing method according to the present embodiment.
A metal is deposited on the second protective film 112 above the lower electrode 121 to form the upper electrode 123.

FIG. 6B is a schematic cross-sectional view illustrating the formation of the third protective film 141 in the method for manufacturing the semiconductor device according to this embodiment.
For example, silicon nitride is deposited on the entire surface of the MIM capacitor region R1 and the HEMT region R2 to form the third protective film 141. At this time, the third protective film 141 is formed thin in order to reduce the influence of the parasitic capacitance generated by the third protective film 141 above the gate electrode 106. The total film thickness t105 of the second protective film 112 on the gate electrode 106 and the film thickness t104 of the third protective film 141 is, for example, 500 mm.

Next, the operation of the semiconductor device 100 according to this embodiment will be described.
As shown in FIG. 2A, in the MIM capacitor region R1, a capacitor C11 is formed by the lower electrode 121 and the upper electrode 123, and the insulating film 122 and the second protective film 112 sandwiched therebetween. Yes. When the total film thickness t101 of the insulating film 122 and the film thickness t103 of the second protective film 112 is increased, the withstand voltage V11 of the capacitor C11 increases and the capacitance value per unit area decreases. The capacity is adjusted to a desired value by the film thickness and the electrode area.

  Since the second protective film 112 extends to the HEMT region R2 with the same film thickness, it is preferable that the film thickness t102 is constant and the film thickness t101 is changed to obtain a desired breakdown voltage.

In the HEMT region R2, a parasitic capacitance C12 is generated by the second protective film 112 and the third protective film 141 on the gate electrode 106. As shown in FIG. 2B, the parasitic capacitance C12 includes a gate C / drain D capacitance C _gd , a gate G / source S capacitance C _gs, and a drain D / source S capacitance C _ds . The capacitance value of the parasitic capacitance C12 varies depending on the total thickness of the film thickness t105 of the second protective film 112 and the film thickness t104 of the third protective film 141. When the total film thickness is increased, the parasitic capacitance C12 increases, and the gain and efficiency of the semiconductor device 100 decrease.

Therefore, in the semiconductor device 100 according to the present embodiment, the total film thickness t101 of the insulating film 122 and the film thickness t103 of the second protective film 112 is greater than or equal to a film thickness that provides a desired breakdown voltage. Form. The total film thickness of the film thickness t101 and the film thickness t103 satisfying this is, for example, 2000 mm, and the withstand voltage at this time is about 100V.
In addition, the total film thickness of the film thickness t104 and the film thickness t105 is formed thin, and the deterioration of the high frequency characteristics due to the parasitic capacitance C12 is suppressed. For example, the film thickness t104 is formed thinner than the film thickness t101. The total film thickness of the film thickness t104 and the film thickness t105 is, for example, 500 mm.

Next, effects of the semiconductor device according to the present embodiment will be described.
In the semiconductor device 100 according to the present embodiment, the total film thickness of the film thickness t101 and the film thickness t103 is formed with a film thickness equal to or greater than a film thickness that provides a desired breakdown voltage. The total film thickness of the film thickness t104 and the film thickness t105 is formed thin.

Thereby, in the HEMT region R2, a semiconductor device that can reduce the parasitic capacitance C12 caused by the second protective film 122 and the third protective film 141 on the gate electrode 106 can be provided. For example, when the parasitic capacitance C12 decreases by 20%, the gain of the semiconductor device 100 increases by 1 dB. Further, a desired breakdown voltage can be ensured in the MIM capacitor region R1.
In the method for manufacturing the semiconductor device 300 according to the present embodiment, the surface of the semiconductor stacked body 101 can be protected by covering it with an insulating film 152 as shown in FIG.

  In the semiconductor device 100 according to the present embodiment, an example in which a HEMT is provided is shown, but the present invention is not limited to this, and a field effect transistor other than a HEMT may be used.

(Comparative example of the first embodiment)
FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device according to this comparative example.
As shown in FIG. 7, the semiconductor device 200 according to this comparative example is different from the first embodiment described above in that the insulating film 211 extends to the HEMT region R2. Thus, the film thickness t202 of the insulating film 211 on the lower electrode 221 is approximately equal to the total film thickness of the film thickness t203 of the insulating film 211 on the gate electrode 206 and the film thickness t205 of the second protective film 212. It has become.

  When the film thickness t202 of the insulating film 211 in the MIM capacitor region R1 is formed to such a thickness that a desired breakdown voltage can be obtained, the film thickness t203 of the insulating film 211 on the gate electrode 206 in the HEMT region R2 is also t202. The film thickness is about the same, and the influence of the parasitic capacitance C22 generated thereby becomes large. On the other hand, when the film thickness t203 is formed thin in order to reduce the influence of the parasitic capacitance C22, it is difficult to obtain a desired breakdown voltage in the HEMT region R2.

  That is, in the semiconductor device 200 according to this comparative example, it is difficult to secure a desired breakdown voltage in the MIM capacitor region R1 and reduce the parasitic capacitance caused by the protective film on the gate electrode in the HEMT region R2.

(Second Embodiment)
FIG. 8 is a cross-sectional view illustrating a semiconductor device according to this embodiment.
The semiconductor device 300 according to the present embodiment differs from the semiconductor device 100 according to the first embodiment described above in the following (a) to (c).
(A) The upper electrode 323 is provided on the insulating film 322 in the MIM capacitor region R1.
(B) A second protective film 312 is provided so as to cover the upper electrode 323.
(C) Because of the above (b), a protective film corresponding to the third protective film 141 shown in FIG. 1 is not provided.
Other configurations in the present embodiment are the same as those in the first embodiment.

Next, a method for manufacturing the semiconductor device 300 according to the present embodiment will be described.
Up to the formation of the insulating film 322 (see FIG. 5B) is the same as the method for manufacturing the semiconductor device according to the first embodiment described above. However, the film thickness t301 of the insulating film 322 on the lower electrode 321 is, for example, 2000 mm.

FIG. 9A is a schematic cross-sectional view illustrating the formation of the upper electrode 323 in the semiconductor device manufacturing method according to the present embodiment.
A metal is deposited on the insulating film 322 of the lower electrode 321 to form the upper electrode 323.

FIG. 9B is a schematic cross-sectional view illustrating the formation of the second protective film 312 in the semiconductor device manufacturing method according to the present embodiment.
For example, silicon nitride is deposited on the entire surface of the wafer, that is, on the entire surface of the MIM capacitor region R1 and the HEMT region R2, thereby forming the second protective film 312. At this time, in order to reduce the influence of the parasitic capacitance generated by the second protective film 312 on the gate electrode 306, the second protective film 312 is formed thin. The film thickness t305 of the second protective film 312 on the gate electrode 306 is, for example, 500 mm.
The manufacturing method other than the above in this embodiment is the same as that in the first embodiment.

Next, the operation of the semiconductor device 300 according to this embodiment will be described.
As shown in FIG. 8, in the MIM capacitor region R1, a capacitor C31 is formed by a lower electrode 321 and an upper electrode 323 and an insulating film 322 sandwiched therebetween. When the film thickness t301 of the insulating film 322 is increased, the withstand voltage V31 of the capacitor C31 increases, and the capacitance value per unit area decreases. The capacity is adjusted to a desired value by the film thickness and the electrode area.

  In the HEMT region R2, a parasitic capacitance C32 is generated by the second protective film 312 on the gate electrode 306. The capacitance value of the parasitic capacitance C32 varies depending on the film thickness t305 of the second protective film 312. When the film thickness t305 is formed thick, the parasitic capacitance C32 increases, and the gain and efficiency of the semiconductor device 300 decrease.

  Therefore, in the semiconductor device 300 according to the present embodiment, the film thickness t301 of the insulating film 322 is formed with a film thickness equal to or larger than a film thickness at which a desired breakdown voltage can be obtained. The film thickness t301 that satisfies this is, for example, 2000 mm, and the withstand voltage at this time is about 100V.

In addition, the film thickness t305 is formed to be thin, and the deterioration of the high frequency characteristics due to the parasitic capacitance C32 is suppressed. For example, the film thickness t305 is formed thinner than the film thickness t301. The film thickness t305 is, for example, 500 mm.
Operations other than those described above in the present embodiment are the same as those in the first embodiment described above.

Next, effects of the semiconductor device 300 according to the present embodiment will be described.
The semiconductor device 300 according to the present embodiment does not require the third protective film 141 shown in FIG. 1 compared to the semiconductor device 100 according to the first embodiment described above. Thereby, the process of forming a 3rd protective film can be reduced. In addition, the protective film over the gate electrode 306 can be formed thinner to further reduce the parasitic capacitance.
The effects of the present embodiment other than those described above are the same as those of the second embodiment described above.

(Third embodiment)
FIG. 10 is a cross-sectional view illustrating a semiconductor device according to this embodiment.
In the semiconductor device 400 according to the present embodiment, as compared with the semiconductor device 100 according to the first embodiment described above, between the semiconductor stacked body 401 and the lower electrode 421 and in the semiconductor stacked layer in the MIM capacitor region R1. The difference is that the first protective film 402 is also provided between the body 401 and the insulating film 422.
Other configurations in the present embodiment are the same as those in the first embodiment.

Next, a method for manufacturing the semiconductor device 400 according to the present embodiment will be described.
Up to the formation of the insulating film 152 (see FIG. 3C) is the same as the semiconductor device manufacturing method according to the first embodiment described above.

FIG. 11 is a schematic cross-sectional view for explaining the formation of the first protective film 402 in the semiconductor device manufacturing method according to the present embodiment.
In the insulating film 152, a range to be removed by lithography is specified, and the insulating film 152 is selectively removed by performing etching, and the remaining portion is used as the first protective film 402. At this time, the insulating film on the semiconductor stacked body 401 in the MIM capacitor region R1 is not removed but left as the first protective film 402.

  The process from the formation of the ohmic electrode to the formation of the third protective film is the same as in the first embodiment. Manufacturing methods and operations other than those described above in the present embodiment are the same as those in the first embodiment described above.

Next, effects of the semiconductor device 400 according to the present embodiment will be described.
In the method for manufacturing the semiconductor device 400 according to the present embodiment, as shown in FIG. 11, the semiconductor stacked body 401 in the MM capacitor region R1 can be protected by covering it with the first protective film insulating film 402.
The effects of the present embodiment other than those described above are the same as those of the first embodiment described above.

(Fourth embodiment)
FIG. 12 is a cross-sectional view illustrating a semiconductor device according to this embodiment.
The semiconductor device 500 according to the present embodiment is located between the semiconductor stacked body 501 and the lower electrode 521 in the MIM capacitor region R1 as compared with the semiconductor device 300 according to the second embodiment (see FIG. 8). In addition, the first protective film 502 is also provided between the semiconductor stacked body 501 and the insulating film 522.
Other configurations in the present embodiment are the same as those in the second embodiment described above.

Next, a method for manufacturing the semiconductor device 500 according to the present embodiment will be described.
The manufacturing method of the semiconductor device 500 according to the present embodiment is selectively removed by removing the insulating film 152 shown in FIG. 3C as compared with the manufacturing method of the semiconductor device according to the second embodiment described above. In the step of forming the first protective film 502, the difference is that the insulating film on the semiconductor stacked body 501 in the MIM capacitor region R1 is not removed but left as the first protective film 502.
Manufacturing methods and operations other than those described above in the present embodiment are the same as those in the second embodiment described above.

Next, effects of the semiconductor device 500 according to the present embodiment will be described.
In the step of forming the first protective film 502 of the manufacturing method of the semiconductor device 400 according to the present embodiment, the semiconductor stacked body 501 in the MIM capacitor region R1 is covered with the first protective film insulating film 502 to be protected. it can.
The effects of the present embodiment other than those described above are the same as those of the second embodiment described above.

  According to the embodiment described above, it is possible to provide a semiconductor device capable of reducing the parasitic capacitance caused by the protective film on the gate electrode.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof.

100, 200, 300, 400, 500 Semiconductor device, 101, 201, 301, 401, 501 Semiconductor stack, 101a, 301a, 401a, 501a Substrate, 101b, 301b, 401b, 501b Channel layer, 101c, 301c, 401c, 501c Electron supply layer, 101d, 301d, 401d, 501d Two-dimensional electron gas layer, 101e, 301e, 401e, 501e Buffer layer, 102, 202, 302, 402, 502 First protective film, 103, 303, 403, 503 Separation Region, 161, 162, 163, 164 opening, 105, 205, 305, 405, 505 drain electrode, 106, 206, 306, 406, 506 gate electrode, 107, 207, 307, 407, 507 source electrode, 108, 208, 308, 40 , 508 Lower gate electrode, 109, 209, 309, 409, 509 Upper gate electrode, 118, 318, 418, 518, 128, 328, 428, 528 Ohmic electrode, 119, 319, 419, 519, 129, 329, 429 529 Pad electrode, 112, 212, 312, 412, 512 Second protective film, 141, 341, 441 Third protective film, 121, 221, 321, 421, 521 Lower electrode, 122, 221, 322, 422, 522 , 152, 352, 172, 372 Insulating film, 123, 223, 323, 423, 523 Upper electrode, 131, 231, 331, 431, 531 Boundary surface, 132, 232, 332, 432, 532 End surface, 133, 233, 333, 433, 533 End face, 104 MIM capacitor, R1 MIM Capacitor region, R2 HEMT region, C11, C21, C31, C51 capacitor, C12, C22, C32, C52 parasitic capacitance, C _gd gate-drain capacitance, C _gs gate-source capacitance, C _ds drain-source capacitance, G gate, D drain, S source, t101, t102, t103, t104, t105, t202, t203, t205, t301, t305, t401, t403, t501, t505 film thickness, V11, V31

Claims (12)

A semiconductor device comprising: a first region having an MIM capacitor; and a second region having a field effect transistor adjacent to the first region,
A semiconductor laminate in which a semiconductor is laminated on a substrate;
A lower electrode provided on an upper surface of a part of the semiconductor stacked body in the first region;
An insulating film provided on the surface of the lower electrode in the first region;
A source electrode provided on the semiconductor laminate in the second region;
A drain electrode provided on the semiconductor laminate in the second region;
A gate electrode provided between the source electrode and the drain electrode in the second region;
At least a part of the upper surface of the semiconductor stacked body in the first region where the lower electrode is not provided, and the source electrode, the drain electrode or the gate electrode in the second region are not provided A first protective film provided on the portion;
A second protective film provided on the surface of the insulating film, on the upper surface of the first protective film, on the surface of the source electrode, on the surface of the gate electrode, and on the surface of the drain electrode;
An upper electrode provided on the upper surface of the second protective film above the lower electrode;
A third protective film provided on the surface of the upper electrode and on the surface of the second protective film;
With
The second region of the semiconductor includes an electron supply layer and a channel layer,
The sum of the thickness of the second protective film on the gate electrode and the thickness of the third protective film is equal to the thickness of the insulating film and the second protection between the lower electrode and the upper electrode. A semiconductor device smaller than the sum of the film thicknesses.   The semiconductor device according to claim 1, further comprising an isolation region provided between the first region and the second region on the substrate.   The semiconductor device according to claim 2, wherein the isolation region is formed by ion implantation.   The semiconductor device according to claim 1, further comprising a buffer layer provided between the substrate and the semiconductor.   The semiconductor device according to claim 1, wherein at least one of the first protective film, the second protective film, and the third protective film includes silicon nitride.   2. The semiconductor device according to claim 1, wherein a total thickness of the insulating film and the second protective film is 2000 angstroms or less.   2. The semiconductor device according to claim 1, wherein a total film thickness of the second protective film and the third protective film is 500 angstroms or less.   2. The semiconductor device according to claim 1, wherein the lower electrode is provided on a region of the upper surface of the semiconductor stack in the first region that is not covered with the first protective film.   The semiconductor device according to claim 1, wherein the first protective film covers a surface of the semiconductor stacked body in the first region, and the lower electrode is provided on the first protective film. A semiconductor device comprising: a first region having an MIM capacitor; and a second region having a field effect transistor adjacent to the first region,
A semiconductor laminate in which a semiconductor is laminated on a substrate;
A lower electrode provided above the semiconductor stack in the first region;
An insulating film provided on the surface of the lower electrode in the first region;
A source electrode provided on the semiconductor laminate in the second region;
A drain electrode provided on the semiconductor laminate in the second region;
A gate electrode provided between the source electrode and the drain electrode in the second region;
First protection provided in at least a partial region of the upper surface of the semiconductor stacked body in the first region, and a portion of the second region where the source electrode, the drain electrode, or the gate electrode is not provided. A membrane,
An upper electrode provided on the upper surface of the insulating film above the lower electrode;
Second protection provided on the surface of the upper electrode, on the surface of the insulating film, on the upper surface of the first protective film, on the surface of the source electrode, on the surface of the gate electrode, and on the surface of the drain electrode A membrane,
With
The second region of the semiconductor includes at least an electron supply layer and a channel layer,
A semiconductor device in which a film thickness of the second protective film on the gate electrode is smaller than a film thickness of the insulating film between the lower electrode and the upper electrode.   The semiconductor device according to claim 10, wherein the lower electrode is provided on a region of the upper surface of the semiconductor stacked body in the first region that is not covered with the first protective film.   The semiconductor device according to claim 10, wherein the first protective film covers a surface of the semiconductor stacked body in the first region, and the lower electrode is provided on the first protective film.

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