JP2016181567A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP2016181567A JP2016181567A JP2015060238A JP2015060238A JP2016181567A JP 2016181567 A JP2016181567 A JP 2016181567A JP 2015060238 A JP2015060238 A JP 2015060238A JP 2015060238 A JP2015060238 A JP 2015060238A JP 2016181567 A JP2016181567 A JP 2016181567A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 125000000217 alkyl group Chemical group 0.000 claims abstract description 91
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- 239000002052 molecular layer Substances 0.000 claims abstract description 22
- 238000009413 insulation Methods 0.000 abstract 2
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- 239000002243 precursor Substances 0.000 description 29
- 238000000034 method Methods 0.000 description 25
- 239000002904 solvent Substances 0.000 description 23
- 230000015572 biosynthetic process Effects 0.000 description 21
- 238000005755 formation reaction Methods 0.000 description 21
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 15
- 238000005259 measurement Methods 0.000 description 14
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- 239000010703 silicon Substances 0.000 description 9
- 229910000449 hafnium oxide Inorganic materials 0.000 description 8
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 8
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- 150000004756 silanes Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000003808 silyl group Chemical group [H][Si]([H])([H])[*] 0.000 description 2
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- GFJGILDCJZMQTN-UHFFFAOYSA-N trichloro(8-trichlorosilyloctyl)silane Chemical compound Cl[Si](Cl)(Cl)CCCCCCCC[Si](Cl)(Cl)Cl GFJGILDCJZMQTN-UHFFFAOYSA-N 0.000 description 2
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- ROFVEXUMMXZLPA-UHFFFAOYSA-N Bipyridyl Chemical class N1=CC=CC=C1C1=CC=CC=N1 ROFVEXUMMXZLPA-UHFFFAOYSA-N 0.000 description 1
- XMWRBQBLMFGWIX-UHFFFAOYSA-N C60 fullerene Chemical class C12=C3C(C4=C56)=C7C8=C5C5=C9C%10=C6C6=C4C1=C1C4=C6C6=C%10C%10=C9C9=C%11C5=C8C5=C8C7=C3C3=C7C2=C1C1=C2C4=C6C4=C%10C6=C9C9=C%11C5=C5C8=C3C3=C7C1=C1C2=C4C6=C2C9=C5C3=C12 XMWRBQBLMFGWIX-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 125000002008 alkyl bromide group Chemical group 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- MWPLVEDNUUSJAV-UHFFFAOYSA-N anthracene Chemical class C1=CC=CC2=CC3=CC=CC=C3C=C21 MWPLVEDNUUSJAV-UHFFFAOYSA-N 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
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- 230000005484 gravity Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000007062 hydrolysis Effects 0.000 description 1
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- IQPQWNKOIGAROB-UHFFFAOYSA-N isocyanate group Chemical group [N-]=C=O IQPQWNKOIGAROB-UHFFFAOYSA-N 0.000 description 1
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- IEQIEDJGQAUEQZ-UHFFFAOYSA-N phthalocyanine Chemical class N1C(N=C2C3=CC=CC=C3C(N=C3C4=CC=CC=C4C(=N4)N3)=N2)=C(C=CC=C2)C2=C1N=C1C2=CC=CC=C2C4=N1 IEQIEDJGQAUEQZ-UHFFFAOYSA-N 0.000 description 1
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- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000005428 wave function Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5664—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using organic memory material storage elements
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
【解決手段】実施形態の半導体記憶装置は、半導体層と、制御ゲート電極と、半導体層と制御ゲート電極との間に設けられた有機分子層と、有機分子層と半導体層との間に設けられ、アルキル鎖を含む第1の層と、第1の層と有機分子層との間に設けられシロキサンを含む第2の層と、を有する第1の絶縁層と、を備える
【選択図】図1
Description
本実施形態の半導体記憶装置は、半導体層と、制御ゲート電極と、半導体層と制御ゲート電極との間に設けられた有機分子層と、有機分子層と半導体層との間に設けられ、アルキル鎖を含む第1の層と、第1の層と有機分子層との間に設けられシロキサンを含む第2の層と、を有する第1の絶縁層と、を備える。
本実施形態の半導体記憶装置は、複数のアルキル層と複数のシロキサン層が交互に積層される以外は、第1の実施形態と同様である。したがって、第1の実施形態と重複する内容については記述を省略する。
本実施形態の半導体記憶装置は、無機物のトンネル絶縁層を備えないこと以外は、第1の実施形態と同様である。したがって、第1の実施形態と重複する内容については記述を省略する。
本実施形態の半導体記憶装置は、メモリセルのトランジスタが電子をキャリアとするn型トランジスタであること以外は、第1の実施形態と同様である。したがって、第1の実施形態と重複する内容については記述を省略する。
本実施形態の半導体記憶装置は、絶縁層と制御ゲート電極とが交互に積層される積層体と、複数の制御ゲート電極に対向して設けられる半導体層と、半導体層と制御ゲート電極との間に設けられる有機分子層と、有機分子層と半導体層との間に設けられ、アルキル鎖を含む第1の層と、第1の層と有機分子層との間に設けられシロキサンを含む第2の層と、を有する第1の絶縁層と、を備える。
図10は、本実施形態の変形例1の半導体記憶装置の断面図である。図9の断面図に対応する断面を示す。ブロック絶縁層18が制御ゲート電極20と絶縁層44との間に沿って設けられる。ブロック絶縁層18は、Z方向のメモリセル毎に分断されている。
図11は、本実施形態の変形例2の半導体記憶装置の断面図である。図9の断面図に対応する断面を示す。変形例1同様、ブロック絶縁層18が制御ゲート電極20と絶縁層44との間に沿って設けられる。ブロック絶縁層18は、Z方向のメモリセル毎に分断されている。更に、トンネル絶縁層12、有機トンネル絶縁層14、及び電荷蓄積層16もZ方向のメモリセル毎に分断されている。
第1及び第2の実施形態に対応する膜構造を作成して評価した。
第4の実施形態に対応する膜構造を作成して評価した。
実施例1同様、第1の実施形態に対応する膜構造を作成して評価した。ただし、実施例1で行ったアルキル層/シロキサン層の形成工程は行わなかった。これ以外は実施例1と同様のため、記述を省略する。
実施例1、比較例1同様、第1の実施形態に対応する膜構造を作成して評価した。ただし、実施例1で行ったアルキル層/シロキサン層の形成工程を行わず、代わりにサーマル式のALD装置に導入し、150℃で酸化シリコンを成膜した。膜厚測定の結果、酸化シリコンの膜厚は1nm程度であった。この工程変更以外は実施例1と同様のため、記述を省略する。
実施例2同様、第4の実施形態に対応する膜構造を作成して評価した。ただし、実施例2で行ったアルキル層/シロキサン層の形成工程は行わなかった。これ以外は実施例2と同様のため、記述を省略する。
実施例2、比較例3同様、第4の実施形態に対応する膜構造を作成して評価した。ただし、実施例2で行ったアルキル層/シロキサン層形成の工程を除き、代わりにサーマル式のALD装置に導入し、150℃で酸化シリコンを成膜した。膜厚測定の結果、酸化シリコンの膜厚は1nm程度であった。この工程変更以外は実施例2と同様のため、省略する。
12 トンネル絶縁層(第2の絶縁層)
14 有機トンネル絶縁層(第1の絶縁層)
14a アルキル層(第1の層)
14b シロキサン層(第2の層)
16 電荷蓄積層(有機分子層)
18 ブロック絶縁層(第3の絶縁層)
20 制御ゲート電極
44 絶縁層
60 積層体
Claims (1)
- 半導体層と、
制御ゲート電極と、
前記半導体層と前記制御ゲート電極との間に設けられた有機分子層と、
前記有機分子層と前記半導体層との間に設けられ、アルキル鎖を含む第1の層と、前記第1の層と前記有機分子層との間に設けられシロキサンを含む第2の層と、を有する第1の絶縁層と、
を備える半導体記憶装置。
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