JP2016178333A - Resin sealed type semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resin sealed type semiconductor device that is adaptive to multiple pins and has a high reliability, and to provide a method of manufacturing such a resin sealed type semiconductor device more easily with stability.SOLUTION: A resin sealed type semiconductor device is configured to have: a circuit part that comprises a plurality of terminal parts each comprising an internal terminal surface and an external terminal surface front and rear integrally, so that the external terminal surfaces form one flat plane; a semiconductor element electrically connected with internal terminal surfaces of the terminal parts by a wire; and a resin member that encapsulates the terminal parts, the semiconductor element, and the wire in a state where at least the external terminal surfaces of the terminal parts are exposed. Each terminal part is configured to have a base, and a surface noble metal layer that configures the internal terminal surface, and have at least one of a recessed part and a rough surface on a side wall surface of the base.SELECTED DRAWING: Figure 15

Description

  The present invention relates to a resin-encapsulated semiconductor device and a method for manufacturing the same.

In recent years, semiconductor devices have been increasingly integrated and highly functional, as represented by LSI ASICs, due to advances in high integration and miniaturization technologies, and the trend toward higher performance and lighter and shorter electronic devices. It is going on. In such highly integrated and highly functional semiconductor devices, it is required to increase the total sum of external terminals (pins) and further increase the number of terminals (pins).
As a package structure that enables high integration and miniaturization in a semiconductor device, for example, there is a surface mount package having a structure in which external leads protrude from a side surface of a resin package such as QFP (Quad Flat Package). However, this QFP package has a problem of mounting efficiency and mountability due to deformation of external leads and the like. For this reason, a semiconductor element and a circuit connected thereto are provided on one side of the substrate, and the other side of the substrate is provided. A resin-encapsulated semiconductor device called BGA (Ball Grid Array) has been developed in which an external terminal electrode connected to the above circuit is provided, and a solder ball as an external terminal is disposed thereon. However, this BGA has a complicated structure in which a circuit provided on one surface of a substrate and an external terminal electrode provided on the other surface are electrically connected through a through hole, and the through-hole is affected by the thermal expansion of the resin. The hole may be broken, and there are many problems in terms of reliability in manufacturing.

  For this reason, a surface mount type such as a QFN (Quad Flat Non-Leaded Package) or SON (Small Outline Non-Leaded Package) having a structure that is not provided with a substrate and is exposed on the back surface of the resin package without protruding external leads. A package has been developed. Such a method for manufacturing a semiconductor device is, for example, by disposing a photosensitive dry film resist on a conductive substrate, forming a resist pattern by exposure / development, and conducting electroplating through this resist pattern. A lead frame in which a metal terminal portion and a die pad are formed is prepared. Then, a semiconductor element is mounted on the die pad of the lead frame via an insulating member, and necessary electrical connection between the terminal of the semiconductor element and the terminal portion of the lead frame is performed using a wire or the like. Sealing is performed using a resin member on the substrate, and then the conductive substrate is peeled off to obtain a resin-sealed semiconductor device. However, when the semiconductor device is peeled from the conductive substrate, the sealing resin member and the terminal part or die pad are peeled off due to the applied force, or the terminal part or die pad is easily cracked, which is problematic in terms of reliability. It was.

  For this reason, when forming the terminal part and the die pad by electroplating on the conductive substrate, by performing plating formation exceeding the thickness of the resist pattern, the terminal part integrally provided with a hook-shaped overhanging part on the peripheral part; There has been proposed a semiconductor device having a structure in which a die pad is formed and adhesion between a terminal part or die pad and a sealing resin member is improved (Patent Document 1). Further, a semiconductor device having a structure in which the adhesion between the terminal portion or die pad and the sealing resin member is improved by making the surface of the terminal portion or die pad formed on the conductive substrate rough is proposed. (Patent Document 2).

JP 2003-174121 A JP 2009-141274 A

  However, when the terminal part and die pad that are integrally provided with a ridge-shaped overhanging part at the periphery are formed by electroplating, if a thin dry film resist is used to reduce the thickness of the terminal part or die pad, the overhanging with the conductive substrate It becomes difficult to remove the resist pattern sandwiched between the portions. For this reason, the thickness of the terminal portion and the die pad cannot be reduced. Therefore, it takes time to form the terminal portion and the die pad, which hinders the reduction of the manufacturing cost. Furthermore, since it becomes difficult to remove the resist pattern as the space of the adjacent terminal portion becomes narrower, the terminal portion provided with the overhang portion needs to be separated from the adjacent terminal portion by the width of the overhang portion, As a result, the degree of freedom in design is low, and there has been a limit to reducing the thickness and size of surface mount packages.

In addition, when forming a terminal portion or die pad having a rough surface, the above-described problem in removing the resist pattern is solved. However, if the surface of the terminal portion or die pad is only rough, for example, mounting is performed. When the size of the semiconductor element is increased, there is a problem that the portion where the die pad surface and the sealing resin member are in close contact with each other decreases, and the improvement in the adhesion with the sealing resin member is insufficient.
The present invention has been made in view of the above circumstances, and a resin-encapsulated semiconductor device that can cope with an increase in the number of pins and has high reliability, and such a resin-encapsulated semiconductor device can be stably provided. It is an object of the present invention to provide a manufacturing method for manufacturing more easily.

In order to achieve such an object, the resin-encapsulated semiconductor device of the present invention includes a plurality of terminal portions each having an internal terminal surface and an external terminal surface integrated with each other so that the external terminal surface forms a single plane. A circuit part; a semiconductor element electrically connected to the internal terminal surface of the terminal part by a wire; and at least the external terminal surface of the terminal part exposed, the terminal part, the semiconductor element, A resin member that seals the wire, the terminal portion includes a base portion, a surface noble metal layer constituting the internal terminal surface, and at least one of a concave portion and a rough surface on the side wall surface of the base portion. It was set as the structure which has.
As another aspect of the present invention, the terminal portion has a base noble metal layer constituting an external terminal surface on the opposite side of the surface of the base having the surface noble metal layer.
As another aspect of the present invention, the circuit part has a die pad on a plane formed by the terminal part, and the die pad has a base part and a surface noble metal layer constituting an internal surface for mounting a semiconductor element. And it was set as the structure which has at least one of a recessed part and a rough surface in the side wall surface of the said base.
As another aspect of the present invention, the die pad has a base noble metal layer on the opposite side of the surface of the base having the surface noble metal layer.
As another aspect of the present invention, the concave portion is configured to be a concave portion continuous along one plane formed by the terminal portion.
As another aspect of the present invention, the concave portion is configured to exist in multiple stages in the thickness direction of the circuit portion.
As another aspect of the present invention, the concave portion present on the side wall surface of the base portion of the circuit portion together with the rough surface is configured to be located closer to the outside of the resin member than the rough surface.
As another aspect of the present invention, the exposed external terminal surface of the terminal portion is provided with solder balls.

A method for manufacturing a resin-encapsulated semiconductor device according to the present invention includes a substrate and a circuit unit positioned on the substrate, and the circuit unit is a surface positioned on the base and the surface of the base opposite to the substrate side. A lead frame for a semiconductor device having a noble metal layer and having at least one of a concave portion and a rough surface on a side wall surface of the base portion, a semiconductor element mounted on the lead frame for the semiconductor device, and a terminal of the semiconductor element And the surface noble metal layer of the terminal portion of the lead frame for a semiconductor device is connected using a wire, and the terminal portion, the semiconductor element, and the wire are sealed with a resin member on the substrate to form a semiconductor device, The resin-sealed semiconductor device was peeled from the substrate.
As another aspect of the present invention, the circuit portion of the lead frame for a semiconductor device is configured to have a base noble metal layer between the base portion and the substrate.
As another aspect of the present invention, the concave portion of the lead frame for a semiconductor device is configured to be a concave portion continuous in a direction parallel to the substrate surface.
As another aspect of the present invention, the concave portion of the lead frame for a semiconductor device is configured to exist in multiple stages in the thickness direction of the circuit portion.
As another aspect of the present invention, the concave portion present on the side wall surface of the base portion of the circuit portion together with the rough surface is configured to be positioned closer to the substrate than the rough surface.
As another aspect of the present invention, the circuit portion of the lead frame for a semiconductor device includes a plurality of terminal portions, and the terminal portion has a surface on the substrate side constituting an external terminal surface, and is opposite to the external terminal surface. The surface of was supposed to constitute the internal terminal surface.
As another aspect of the present invention, the circuit portion of the lead frame for a semiconductor device further includes a die pad, and the die pad is configured such that a surface opposite to the substrate side is an internal surface for mounting a semiconductor element. .

  The resin-encapsulated semiconductor device of the present invention can cope with the increase in the number of pins and has high reliability. The method for producing a resin-encapsulated semiconductor device of the present invention can produce such a resin-encapsulated semiconductor device stably and simply.

FIG. 1 is a plan view showing an embodiment of a lead frame for a semiconductor device according to the present invention. 2 is a schematic cross-sectional view taken along line AA of the lead frame for a semiconductor device shown in FIG. FIG. 3 is a diagram for explaining a circuit portion, and is an enlarged view of a portion surrounded by a chain line of the lead frame for a semiconductor device shown in FIG. FIG. 4 is a partially enlarged view corresponding to FIG. 3 for explaining another embodiment of the lead frame for a semiconductor device of the present invention. FIG. 5 is a partially enlarged view corresponding to FIG. 3 for explaining another embodiment of the lead frame for a semiconductor device of the present invention. FIG. 6 is a partially enlarged view corresponding to FIG. 3 for explaining another embodiment of the lead frame for a semiconductor device of the present invention. FIG. 7 is a plan view showing another embodiment of the lead frame for a semiconductor device of the present invention. 8 is a schematic cross-sectional view taken along line BB of the lead frame for a semiconductor device shown in FIG. FIG. 9 is a plan view showing another embodiment of the lead frame for a semiconductor device of the present invention. 10 is a schematic cross-sectional view taken along line CC of the lead frame for a semiconductor device shown in FIG. FIG. 11 is a process diagram showing an example of manufacturing a lead frame for a semiconductor device according to the present invention. FIG. 12 is a process diagram showing an example of manufacturing a lead frame for a semiconductor device according to the present invention. FIG. 13 is a process diagram showing an example of manufacturing a lead frame for a semiconductor device according to the present invention. FIG. 14 is a process diagram showing an example of manufacturing a lead frame for a semiconductor device according to the present invention. FIG. 15 is a process diagram for explaining an example of manufacturing a resin-encapsulated semiconductor device using the lead frame for a semiconductor device of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Lead frame for semiconductor devices]
FIG. 1 is a plan view showing an embodiment of a lead frame for a semiconductor device according to the present invention, and FIG. 2 is a schematic sectional view taken along line AA of the lead frame for a semiconductor device shown in FIG.
1 and 2, a lead frame 11 for a semiconductor device according to the present invention includes a substrate 12 and a circuit portion 13 located on one surface of the substrate 12. The circuit portion 13 includes a rectangular die pad 13B. The die pad 13B is composed of a plurality of terminal portions 13A arranged at predetermined intervals in one row in the four directions.

The substrate 12 is made of a conductive substrate such as copper, copper alloy, iron-nickel alloy, iron-nickel-chromium alloy, iron-nickel-carbon alloy, or at least Cu, Ni, Ag, Any of insulating substrates having a conductive layer made of Pd, Au, or the like or an alloy thereof may be used. In addition, in the manufacture of a resin-encapsulated semiconductor device using the lead frame for a semiconductor device of the present invention, a metal layer (for example, copper) that can be dissolved and removed for peeling the resin-encapsulated semiconductor device and the substrate 12. A substrate on which a layer or the like is previously formed may be used.
The circuit part 13 has a base and a surface noble metal layer located on the surface of the base opposite to the substrate side, and has a recess on the side wall surface of the base. FIG. 3 is a diagram for explaining a circuit portion, and is an enlarged view of a portion surrounded by a chain line of the lead frame for a semiconductor device shown in FIG. In the example shown in FIG. 3, the terminal portion 13A and the die pad 13B constituting the circuit portion 13 are each composed of a base portion 14, a surface noble metal layer 15 located on the surface 14a opposite to the substrate 12 side of the base portion 14, and a base portion. 14 has a base noble metal layer 16 located on the surface 14b on the substrate 12 side. Further, the side wall surface 14 c of the base portion 14 has a concave portion 17.

  The terminal portion 13A constituting the circuit portion 13 and the base portion 14 of the die pad 13B can have a single layer structure made of any one kind of metal such as Cu or Ni, or a multilayer structure made of two or more kinds of metals. . Further, the surface noble metal layer 15 can have a single layer structure made of any one kind of noble metal such as Ag, Au, Pd, or a multilayer structure made of two or more kinds of noble metals. The surface noble metal layer 15 of the terminal portion 13A forms an internal terminal surface, and the surface noble metal layer 15 of the die pad 13B forms an internal surface for mounting a semiconductor element. In addition, the base noble metal layer 16 can have a single layer structure made of any one kind of noble metal such as Au, Pd, Ag, or the like, or a multilayer structure made of two or more kinds of noble metals. From the substrate 12 side, Au / Pd can be laminated in this order. The base noble metal layer 16 of the terminal portion 13A forms an external terminal surface. The surface noble metal layer 15 and the base noble metal layer 16 are formed on the side wall surface 14c of the base portion 14 of the circuit portion 13 (terminal portion 13A, die pad 13B) in the recess 17 (or in the manufacture of a lead frame for a semiconductor device to be described later. When forming a rough surface (to be described later), the desired pattern shape and dimensions of the circuit portion 13 are maintained. In addition, the base noble metal layer 16 is formed of a metal (for example, Cu) in which the substrate 12 can be dissolved and removed, or a metal layer (for example, a Cu layer) in which the substrate 12 can be dissolved and removed is formed on an insulating substrate. In this case, in the manufacture of a semiconductor device to be described later, the substrate 12 is reliably removed.

  The thickness of the circuit portion 13 composed of the terminal portion 13A and the die pad 13B is set such that the terminal portion 13A takes into account the engagement with the resin member by the concave portion 17 (or a rough surface as will be described later) on the side wall surface 14c of the base portion 14. And the thickness of the die pad 13B can be set in the direction of decreasing the thickness, for example, 5 to 50 μm, preferably 5 to 40 μm. Moreover, each layer which comprises the circuit part 13 can set the thickness of the base 14 in 5-50 micrometers, Preferably it is 5-40 micrometers, and the thickness of the surface noble metal layer 15 is 0.001-10 micrometers, Preferably Can be set in the range of 0.1 to 5 μm, and the thickness of the base noble metal layer 16 can be set in the range of 0.001 to 1 μm, preferably 0.01 to 0.5 μm.

In the illustrated example, the recess 17 that the circuit portion 13 has on the side wall surface 14 c of the base portion 14 is a recess that continues along the direction parallel to the surface of the substrate 12. Therefore, in each terminal part 13A and die pad 13B, the recessed part 17 exists continuously over the entire periphery of the side wall surface 14c of the base part 14. The width W (see FIG. 3) of the concave portion 17 may be the same as or less than the thickness of the base portion 14, and the depth D (see FIG. 3) of the concave portion 17 is, for example, 0 .1 to 40 μm, preferably 1 to 10 μm. When the depth D of the recess 17 is less than 0.1 μm, in the manufacture of the resin-encapsulated semiconductor device using the lead frame for a semiconductor device of the present invention, the engagement between the recess 17 and the resin member becomes insufficient, When the resin-encapsulated semiconductor device is peeled from the substrate 12, the resin member and the circuit portion 13 may be peeled off or the circuit portion 13 may be cracked. On the other hand, when the depth D of the recess 17 exceeds 40 μm, the surface noble metal layer 15 protrudes greatly in a bowl shape and the engagement between the recess 17 and the resin member is sufficient, but the resin-encapsulated semiconductor device from the substrate 12 In peeling off, stress concentrates on the surface noble metal layer 15 and may cause breakage, which is not preferable.
In addition, the recessed part 17 which the side wall surface 14c of the base 14 has may be a thing in which several recessed parts were provided in the desired position along the direction parallel to the surface of the board | substrate 12. FIG.

FIG. 4 is a partially enlarged view corresponding to FIG. 3 for explaining another embodiment of the lead frame for a semiconductor device of the present invention. In FIG. 4, a semiconductor device lead frame 21 of the present invention comprises a substrate 22 and a circuit portion 23 located on one surface of the substrate 22. The circuit portion 23 includes a rectangular die pad 23B and the die pad. Each terminal 23A is composed of a plurality of terminal portions 23A arranged at predetermined intervals in one row in the four directions 23B.
The lead frame 21 for a semiconductor device has a structure in which the circuit portion 23 is different from the circuit portion 13 in the lead frame 11 for semiconductor device described above, but the arrangement of the circuit portion 23 is the circuit portion 13 in the lead frame 11 for semiconductor device described above. The substrate 22 is the same as the substrate 12 described above.
The circuit portion 23 includes a terminal portion 23A and a die pad 23B. The base portion 24, a surface noble metal layer 25 positioned on the surface 24a opposite to the substrate 22 side of the base portion 24, and a surface 24b of the base portion 24 on the substrate 22 side. A base noble metal layer 26 is located. A rough surface 28 is provided on the side wall surface 24 c of the base 24. The material of the base portion 24 constituting the circuit portion 23 is the same as that of the base portion 14, and the surface noble metal layer 25 can be the same as the surface noble metal layer 15. 26 may be the same as the above-described base noble metal layer 16.

The rough surface 28 that the circuit portion 23 has on the side wall surface 24c of the base portion 24 exists in the entire region of the side wall surface 24c in the illustrated example, and the average roughness Ra of the rough surface 28 is 0.1 μm or more, preferably 0. It can set in the range of 2-1 micrometer. When the average roughness Ra of the rough surface 28 is less than 0.1 μm, in the manufacture of the resin-encapsulated semiconductor device using the lead frame for a semiconductor device of the present invention, the engagement between the rough surface 28 and the resin member is not good. This is not preferable because the resin member and the circuit portion 23 may be peeled off or the circuit portion 23 may be cracked when the resin-encapsulated semiconductor device is peeled from the substrate 22. In the present invention, the average roughness Ra is measured using Vertscan R5300 manufactured by Ryoka System Co., Ltd.
The rough surface 28 does not exist over the entire side wall surface 24c, but the width of the rough surface 28 may be smaller than the thickness of the base 24, and a plurality of rough surfaces along the direction parallel to the surface of the substrate 22 may be used. May be provided at a desired position.

FIG. 5 is a partially enlarged view corresponding to FIG. 3 for explaining another embodiment of the lead frame for a semiconductor device of the present invention. In FIG. 5, a semiconductor device lead frame 31 of the present invention comprises a substrate 32 and a circuit portion 33 located on one surface of the substrate 32. The circuit portion 33 includes a rectangular die pad 33B and the die pad. Each terminal portion 33A includes a plurality of terminal portions 33A arranged at predetermined intervals in one row in the four directions 33B.
The semiconductor device lead frame 31 has a structure in which the circuit portion 33 is different from the circuit portion 13 in the semiconductor device lead frame 11 described above. However, the circuit portion 33 is arranged in the circuit portion 13 in the semiconductor device lead frame 11 described above. The substrate 32 is the same as the substrate 12 described above.

  The circuit portion 33 includes a terminal portion 33A and a die pad 33B. The base portion 34, a surface noble metal layer 35 positioned on the surface 34a opposite to the substrate 32 side of the base portion 34, and a surface 34b of the base portion 34 on the substrate 32 side. An underlying noble metal layer 36 is located. A recess 37 is formed on the side wall surface 34 c of the base 34. The material of the base part 34 constituting the circuit part 33 may be the same as that of the base part 14, and a noble metal thin film so as to be parallel to the substrate 32 at a boundary part between a concave part 37a and a concave part 37b described later. May be provided. The surface noble metal layer 35 constituting the circuit portion 33 can be the same as the surface noble metal layer 15, and the base noble metal layer 36 can be the same as the base noble metal layer 16.

In the illustrated example, the concave portion 37 that the circuit portion 33 has on the side wall surface 34 c of the base portion 34 includes a concave portion 37 a and a concave portion 37 b that exist in two stages in the thickness direction of the circuit portion 33, and the concave portions 37 a and 37 b It is continuous along the direction parallel to the surface of. Therefore, in each of the terminal portions 33A and the die pad 33B, there are continuous two-step concave portions 37a and 37b over the entire periphery of the side wall surface 34c of the base portion 34. The width W of the recess 37 (see FIG. 5) may be the same as the thickness of the base 34, and the width Wa of the recess 37a and the width Wb of the recess 37b (see FIG. 5) may be the same. Well, it may be different. Further, the depth Da of the concave portion 37a and the depth Db (see FIG. 5) of the concave portion 37b may be the same or different, for example, 0.1 to 40 μm, preferably 1 to It can be set within a range of 10 μm. When the depth Da of the recess 37a and the depth Db of the recess 37b are less than 0.1 μm, in the manufacture of the resin-encapsulated semiconductor device using the lead frame for a semiconductor device of the present invention, the recess 37 and the resin member Since the engagement becomes insufficient and the resin-encapsulated semiconductor device is peeled from the substrate 32, the resin member and the circuit portion 33 may be peeled off or the circuit portion 33 may be cracked. On the other hand, when the depth D of the concave portion 37, in particular, the depth Da of the concave portion 37a exceeds 40 μm, the surface noble metal layer 35 protrudes greatly in a bowl shape, and the engagement between the concave portion 37 and the resin member is sufficient, but the substrate 32 In the separation of the resin-encapsulated semiconductor device from the stress, stress may concentrate on the surface noble metal layer 35 and cause damage, which is not preferable.
The concave portions 37a and 37b of the side wall surface 34c of the base portion 34 may each be provided with a plurality of concave portions at desired positions along a direction parallel to the surface of the substrate 32. Further, the number of steps of the recess 37 may be three or more.

FIG. 6 is a partially enlarged view corresponding to FIG. 3 for explaining another embodiment of the lead frame for a semiconductor device of the present invention. In FIG. 6, a lead frame 41 for a semiconductor device according to the present invention includes a substrate 42 and a circuit portion 43 located on one surface of the substrate 42. The circuit portion 43 includes a rectangular die pad 43B and the die pad. Each of the four terminal portions 43B is composed of a plurality of terminal portions 43A arranged at predetermined intervals in one row.
The lead frame 41 for a semiconductor device has a structure in which the circuit unit 43 is different from the circuit unit 13 in the lead frame 11 for semiconductor device described above, but the circuit unit 43 is arranged in the circuit unit 13 in the lead frame 11 for semiconductor device described above. The substrate 42 is the same as the substrate 12 described above.

  The circuit portion 43 includes a terminal portion 43A and a die pad 43B. The base portion 44, a surface noble metal layer 45 positioned on the surface 44a opposite to the substrate 42 side of the base portion 44, and a surface 34b of the base portion 44 on the substrate 42 side. An underlying noble metal layer 46 is located. The side wall surface 44 c of the base portion 44 has a recess 47 and a rough surface 48. The material of the base portion 44 constituting the circuit portion 43 may be the same as that of the above-described base portion 14, and the portion where the rough surface 48 of the side wall surface 44 c is present has fine holes or is discontinuous. It may be provided with a noble metal thin film. The surface noble metal layer 45 constituting the circuit unit 43 can be the same as the surface noble metal layer 15, and the base noble metal layer 46 can be the same as the base noble metal layer 16.

  In the illustrated example, the concave portion 47 that the circuit portion 43 has on the side wall surface 44 c of the base portion 44 is located on the lower side in the thickness direction of the base portion 44, and is continuous along the surface parallel to the surface of the substrate 42. Further, the rough surface 48 that the circuit portion 43 has on the side wall surface 44 c of the base portion 44 is located on the upper side in the thickness direction of the base portion 44. Therefore, in each of the terminal portions 43A and the die pad 43B, there is a recess 47 continuously over the entire periphery of the lower side wall surface 44c in the thickness direction of the base portion 44, and the upper side of the base portion 44 in the thickness direction. A rough surface 48 exists over the entire circumference of the side wall surface 44c. The width W1 of the concave portion 47 and the width W2 of the rough surface 48 (see FIG. 6) may be the same or different, and the total (W1 + W2) is the same as the thickness of the base 44, or Or less than the thickness. Moreover, the depth D (refer FIG. 6) of the recessed part 47 can be set, for example in the range of 0.1 micrometer or more, Preferably it is 1-40 micrometers, More preferably, it is 1-10 micrometers. Further, the average roughness Ra of the rough surface 48 can be set in the range of 0.1 μm or more, preferably 0.2 to 1 μm. When the depth D of the concave portion 47 is less than 0.1 μm, or the average roughness Ra of the rough surface 48 is less than 0.1 μm, a resin-encapsulated semiconductor device using the lead frame for a semiconductor device of the present invention is manufactured. In this case, the engagement between the concave portion 47 and the rough surface 48 and the resin member becomes insufficient, and the resin member and the circuit portion 43 are peeled off or the circuit portion 43 is cracked when the resin-encapsulated semiconductor device is peeled from the substrate 42. Is not preferable.

  In addition, the recessed part 47 which the side wall surface 44c of the base 44 has may be a thing in which the several recessed part was provided in the desired position along the direction parallel to the surface of the board | substrate 42. FIG. Further, the rough surface 48 may be formed by providing a plurality of rough surfaces at desired positions along a direction parallel to the surface of the substrate 42. Moreover, the recessed part 47 may be multistage like said recessed part 37. FIG.

Further, the lead frame for a semiconductor device of the present invention may not include a die pad as a circuit portion. FIG. 7 is a plan view illustrating an embodiment of a lead frame for a semiconductor device of the present invention that does not include a die pad, and FIG. 8 is a schematic cross-sectional view of the lead frame for a semiconductor device shown in FIG. is there.
7 and 8, a lead frame 51 for a semiconductor device according to the present invention includes a substrate 52 and a circuit portion 53 provided on one surface of the substrate 52. The circuit portion 53 is a semiconductor element to be mounted. Are formed of a plurality of terminal portions 53A arranged at a predetermined interval so as to correspond to the outer shape (shape indicated by a chain line in FIG. 7).
The substrate 52 constituting the semiconductor device lead frame 51 is the same as the substrate 12 described above.

  The plurality of terminal portions 53A constituting the circuit portion 53 have a base portion 54 and a surface noble metal layer 55 located on the surface of the base portion 54 opposite to the substrate 52 side, and the base portion 54 has a substrate 52 side. The base noble metal layer 56 is located on the surface of the substrate. Furthermore, the side wall surface of the base portion 54 has at least one of a concave portion and a rough surface. The basic structure of the terminal portion 53A is the same as that of any of the above-described terminal portions 13a, 23a, 33a, and 43a, except that the terminal portion 53A has a size that allows a semiconductor element to be placed on a part of the surface noble metal layer 55. It can be.

FIG. 9 is a plan view showing another embodiment of the lead frame for a semiconductor device of the present invention that does not include a die pad, and FIG. 10 is a schematic view taken along line CC of the lead frame for a semiconductor device shown in FIG. It is sectional drawing.
9 and 10, a lead frame 61 for a semiconductor device according to the present invention includes a substrate 62 and a circuit portion 63 provided on one surface of the substrate 62. The circuit portion 63 has a semiconductor element at the center. Are arranged with a plurality of terminal portions 63A arranged at a predetermined interval so as to surround the arrangement portion (the portion indicated by a chain line in FIG. 9).
The substrate 62 constituting the semiconductor device lead frame 61 is the same as the substrate 12 described above.

The plurality of terminal parts 63A constituting the circuit part 63 have a base part 64 and a surface noble metal layer 65 located on the surface of the base part 64 opposite to the substrate 62 side, and the base part 64 side of the base part 64 It has the base noble metal layer 66 located on the surface. Further, the side wall surface of the base portion 64 has at least one of a concave portion and a rough surface. The basic structure of the terminal portion 63A can be the same as any of the terminal portions 13a, 23a, 33a, and 43a.
In such a lead frame for a semiconductor device according to the present invention, the circuit portion located on the substrate has at least one of a concave portion and a rough surface on the side wall surface of the base portion. When the stop is performed, the recess and / or the rough surface engages with the resin member to securely fix the circuit portion. Therefore, when the resin-encapsulated semiconductor device is peeled from the substrate, the resin member and the circuit portion Can be prevented from peeling off and cracks can be prevented from entering the circuit portion, and a highly reliable resin-encapsulated semiconductor device can be manufactured. Furthermore, the lead frame for a semiconductor device according to the present invention can reduce the thickness of the circuit portion, can further reduce the space between adjacent circuit portions, and has a high degree of design freedom.

  In addition, the shape, arrangement, number, and the like of the circuit portion of the above-described lead frame for a semiconductor device are examples, and are not limited thereto. In addition, the lead frame for a semiconductor device of the present invention may have a plurality of surfaces with a plurality of circuit portions provided on a substrate. Furthermore, the lead frame for a semiconductor device of the present invention may not be provided with a base noble metal layer.

[Example of lead frame for semiconductor devices]
Next, a method for manufacturing a lead frame for a semiconductor device according to the present invention will be described.
FIG. 11 is a process diagram showing an example of manufacturing the semiconductor device lead frame 11 shown in FIGS. 11A shows a cross section corresponding to FIG. 2, and FIGS. 11B and 11C show cross sections corresponding to FIG.
In FIG. 11, first, a resist pattern 19 is formed on both surfaces of the substrate 12 (FIG. 11A). The resist pattern 19 has an opening 19a at a portion corresponding to a portion where the circuit portion 13 is to be formed on one surface of the substrate 12, and the substrate 12 is exposed to the opening 19a. The substrate 12 includes a conductive substrate such as an iron-nickel alloy, an iron-nickel-chromium alloy, or an iron-nickel-carbon alloy, and a conductive layer made of Cu, Ni, Ag, Pd, Au, or an alloy thereof on the surface. Insulating substrates can be used. The resist pattern 19 is formed with a thickness equal to or greater than the set thickness of the laminate including the base noble metal layer 16, the base portion 14, and the surface noble metal layer 15 to be formed in a later step.

  In the manufacture of a resin-encapsulated semiconductor device using the lead frame 11 for a semiconductor device, a surface treatment is performed in advance so as to make the one surface of the substrate 12 uneven so that the circuit portion 13 can be easily separated from the substrate 12. In addition, it is preferable to take a measure such as performing a peeling treatment to give peelability. Examples of the surface treatment here include blasting by sandblasting, and examples of the peeling treatment include a method of forming an oxide film on the surface of the substrate 12.

  Next, a metal is deposited on the substrate 12 through the resist pattern 19 by electroplating, and the base noble metal layer 16, the base 14, and the surface noble metal layer 15 are laminated, and then the resist pattern 19 is removed (FIG. 11 (B)). The base noble metal layer 16 can have a single-layer structure made of any one of Au, Pd, and Ag, or a multi-layer structure made of two or more kinds of noble metals. From the side, the layers can be stacked in the order of Au / Pd. The base portion 14 can have a single layer structure made of any one of Cu and Ni, or a multilayer structure made of two or more metals. The surface noble metal layer 15 can have a single layer structure made of any one kind of Ag, Au, and Pd, or a multilayer structure made of two or more kinds of noble metals. As described above, since the resist pattern 19 is formed with a thickness equal to or greater than the set thickness of the laminate including the base noble metal layer 16, the base 14, and the surface noble metal layer 15, the metal for forming the surface noble metal layer 15 is a resist. The surface noble metal layer 15, which is the uppermost layer, does not deposit laterally along the surface of the pattern 19, and fits in the opening 19 a of the resist pattern 19. Therefore, the removal of the resist pattern 19 can be easily performed without being subjected to a structural failure of the laminate composed of the base noble metal layer 16, the base 14, and the surface noble metal layer 15.

  Next, etching is performed on the exposed side wall surface 14c of the base portion 14 to form a recess portion 17 to form a circuit portion 13 including a plurality of terminal portions 13A and a die pad 13B. Is obtained (FIG. 11C). Examples of the etching solution to be used include, for example, when the base noble metal layer 16 is Au / Pd, the base portion 14 is Ni, and the surface noble metal layer 15 is Ag. The recesses 17 having a desired depth can be formed by appropriately setting the concentration, etching time, etching temperature, stirring conditions, and the like.

FIG. 12 is a process diagram showing an example of manufacturing the lead frame 21 for a semiconductor device shown in FIG.
In the manufacture of the lead frame 21 for a semiconductor device, first, as in the manufacture of the lead frame 11 for a semiconductor device described above, a resist pattern is formed on the substrate 22, and a metal is deposited on the substrate 22 through this resist pattern. Then, the base noble metal layer 26, the base 24, and the surface noble metal layer 25 are stacked, and then the resist pattern is removed (FIG. 12A).
Next, the exposed side wall surface 24c of the base portion 24 is etched to form a rough surface 28, and a circuit portion 23 including a plurality of terminal portions 23A and a die pad 23B is formed. 21 is obtained (FIG. 12B). Examples of the etching solution to be used include NCH manufactured by Nippon Chemical Industry Co., Ltd. when the base noble metal layer 26 is Au / Pd, the base 24 is Ni, and the surface noble metal layer 25 is Ag. The rough surface 28 having a desired average roughness Ra can be formed by appropriately setting etching time, etching temperature, stirring conditions, and the like.

FIG. 13 is a process diagram showing a manufacturing example of the semiconductor device lead frame 31 shown in FIG.
In the manufacture of the lead frame 31 for a semiconductor device, first, as in the manufacture of the lead frame 11 for a semiconductor device described above, a resist pattern 39 is formed on the substrate 32, and a desired noble metal is formed on the substrate 32 via the resist pattern 39. Is deposited to form a base noble metal layer 26, and then a metal for forming the base 34 is deposited to a desired thickness to form a base thin film 34 '(FIG. 13A). The thickness of the base thin film 34 'determines the width Wb of the recess 37b described above.
Next, an intermediate layer is formed by depositing, by electroplating, one or more of metals having etching selectivity with respect to the metal for forming the base 34, for example, noble metals such as Au, Ag, Pd, and Cu. 34 ″ is deposited on the base thin film 34 ′. The thickness of the intermediate layer 34 ″ can be, for example, in the range of 0.05 to 5 μm. Thereafter, a metal for forming the base 34 is deposited on the intermediate layer 34 ″ to a desired thickness to form a base thin film 34 ′, and then a surface noble metal layer 35 is laminated (FIG. 13B). The thickness of the base thin film 34 'determines the width Wa of the recess 37a.

  Next, the resist pattern 39 is removed to expose the base noble metal layer 36, base 34 (base thin film 34 ′ / intermediate layer 34 ″ / base thin film 34 ′), surface noble metal layer 35, and the base 34 side. Etching is performed on the wall surface 34c to form a recess 37a and a recess 37b, and a circuit portion 33 including a plurality of terminal portions 33A and a die pad 33B is formed to obtain a lead frame 31 for a semiconductor device (FIG. 13C). In the etching of the side wall surface 34c of the base portion 34, the base portion 34 has a laminated structure in which the intermediate layer 34 ″ is sandwiched by the base thin film 34 ′, so that etching at the portion where the intermediate layer 34 ″ exists is hindered. The two-stage recesses 37a and 37b corresponding to each base thin film 34 'are formed.For example, the base noble metal layer 36 is Au / Pd and the base thin film 3 is used as the etching solution. When ′ is Ni, the intermediate layer 34 ″ is Au, and the surface noble metal layer 35 is Ag, the Mekku Mover Mover NH-1865 manufactured by Mec Co., Ltd. can be exemplified, and the concentration of etching solution, etching time, etching temperature, stirring conditions Etc. can be set as appropriate to form the recesses 37a and 37b having a desired depth. When the base thin film 34 ′ is Ni and the intermediate layer 34 ″ is Au, Au forming the intermediate layer 34 ″ diffuses over time into the base thin film 34 ′ that sandwiches the Au, but usually this diffusion is almost not. Since the two-stage recesses 37a and 37b are formed at the stage where the process is not started, there is no problem.

FIG. 14 is a process diagram showing an example of manufacturing the lead frame 41 for a semiconductor device shown in FIG.
In the manufacture of the lead frame 41 for a semiconductor device, first, as in the manufacture of the lead frame 11 for a semiconductor device described above, a resist pattern is formed on the substrate 42, and a metal is deposited on the substrate 42 through this resist pattern. Then, the base noble metal layer 46, the base 44, and the surface noble metal layer 45 are stacked, and then the resist pattern is removed (FIG. 14A).

  Next, a resist 49 ′ is disposed on the substrate 42 on the surface where the laminated body composed of the base noble metal layer 46, the base 44, and the surface noble metal layer 45 is present so as to be thinner than the laminated body. The position of the surface 49 ′ a of the resist 49 ′ is a boundary position between the concave portion 47 and the rough surface 48 located on the side wall surface 44 c of the base portion 44 in the lead frame 41 for a semiconductor device. Thereafter, a noble metal is deposited on the exposed laminate, and a noble metal layer 45 ′ is formed on the side wall of the laminate (FIG. 14B). Unlike the surface noble metal layer 45, the noble metal layer 45 'is not a dense film, and a rough surface 48 can be formed on the side wall surface 44c of the base portion 44 where the noble metal layer 45' is formed by etching in a later step. Shall. Since such a noble metal layer 45 'is also formed on the surface noble metal layer 45, it is preferable to deposit the same noble metal as the surface noble metal layer 45, and the concentration of plating solution, plating time, current value, plating temperature, plating solution It can be formed by appropriately setting the stirring conditions and the like, and for example, it can be a thin film having fine pores with a thickness of about 3 to 50 nm or a discontinuous thin film.

  Next, the resist 49 ′ is removed to expose the laminated body including the base noble metal layer 46, the base 44, the surface noble metal layer 45, and the noble metal layer 45 ′, and etching is performed on the side wall surface 44 c of the base 44 to form the recess 47. Then, a rough surface 48 is formed, and a circuit portion 43 including a plurality of terminal portions 43A and a die pad 43B is formed to obtain a lead frame 41 for a semiconductor device (FIG. 14C). In the etching of the base portion 44 on the side wall surface 44c, a portion where the noble metal layer 45 'does not exist (the lower side in the thickness direction of the base portion 44) is exposed to the etching solution to form the concave portion 47. On the other hand, at the portion where the noble metal layer 45 ′ is present (upper side in the thickness direction of the base portion 44), the rough surface 48 is formed by the etching solution that can pass through the noble metal layer 45 ′. As the etching solution to be used, for example, when the base noble metal layer 46 is Au / Pd, the base 44 is Ni, the surface noble metal layer 45 and the noble metal layer 45 ′ are Ag, NCH manufactured by Nippon Chemical Industry Co., Ltd. can be used. The concave surface 47 having a desired depth and the rough surface 28 having a desired average roughness Ra can be formed by appropriately setting the concentration of the etching solution, the etching time, the etching temperature, the stirring conditions, and the like.

  The lead frame for a semiconductor device of the present invention can be manufactured as in the above-described manufacturing example, and it is difficult to remove a resist pattern as a conventional lead frame for a semiconductor device having a protruding portion on a terminal portion or a die pad. There are no restrictions on the thickness of the terminal part and die pad, and the space between adjacent terminal parts due to the above. Therefore, the thickness of the circuit portion can be reduced, and the space between adjacent circuit portions can be narrowed, resulting in a high degree of design freedom.

[Production example of resin-encapsulated semiconductor device]
Next, an example of manufacturing a resin-encapsulated semiconductor device using the lead frame for a semiconductor device of the present invention will be described with reference to FIG. 15 taking the lead frame 11 for a semiconductor device shown in FIGS. 1 to 3 as an example. .
First, the semiconductor element 105 is mounted on the surface noble metal layer 15 (internal surface) of the die pad 13B of the lead frame 11 for a semiconductor device via the insulating member 106 (FIG. 15A). Next, the terminal 105a of the semiconductor element 105 and the surface noble metal layer 15 (internal terminal surface) of the terminal portion 13A of the lead frame 11 for a semiconductor device are connected using the wire 107 (FIG. 15B). Thereafter, the terminal portion 13A, the die pad 13B, the semiconductor element 105, and the wire 107 are sealed with the resin member 108 over the substrate 12 (FIG. 15C).
Next, the resin-encapsulated semiconductor device is peeled from the substrate 12 (FIG. 15D), and then solder balls 109 are attached to the exposed external terminal surface of the terminal portion 103 (the base noble metal layer 16 of the terminal portion 13A). Thus, the resin-encapsulated semiconductor device 101 is obtained.
In such a resin-encapsulated semiconductor device 101, the recess 17 of the terminal portion 13 </ b> A and the die pad 13 </ b> B engages with the resin member 108 to securely fix the circuit portion 13. When the device 101 is peeled off, the resin member 108 and the circuit portion 13 are prevented from being peeled off, and the circuit portion 13 is prevented from cracking.

Next, the present invention will be described in more detail with specific examples.
[Example 1]
First, a 0.15 mm thick copper plate (TEC64T 1 / 2H) was prepared as a substrate, and a photosensitive resist film (AQ-4038 manufactured by Asahi Kasei E-Materials Co., Ltd.) was laminated on the conductive substrate, and desired. The resist pattern (thickness 40 μm) was formed on both surfaces of the substrate by exposing through a photomask and developing. This resist pattern had an opening at a portion corresponding to the formation portion of the circuit portion on one surface of the substrate, and the substrate was exposed to this opening. In addition, the space | interval between the opening parts corresponded to the terminal part of a circuit part among this opening part was 200 micrometers.
Next, four layers of Au, Pd, Ni, and Ag are laminated in the order of the following electroplating conditions to form a base noble metal layer (Au / Pd layer), a base (Ni layer), and a surface noble metal layer (Ag layer). Thus, a laminate having a thickness of about 20 μm was formed.

<Au plating>
The substrate is immersed in an electroplating solution (a potassium cyanide cyanide solution), the substrate is used as a negative electrode, the anode (Ti / Pt electrode) is used as a positive electrode, and plating is performed at a current density of 0.3 A / dm ² for 40 seconds. About 0.04 μm Au plating was applied.
<Pd plating>
The substrate is immersed in an electroplating solution (ammonia-based Pd solution), the substrate is used as a negative electrode, the anode (Ti / Pt electrode) is used as a positive electrode, and plating is performed at a current density of 3 A / dm ² for 20 seconds. 15 μm Pd plating was applied.

<Ni plating>
Dipping the substrate in an electroplating solution (nickel sulfamate solution), using the substrate as the negative electrode, and using the anode (S round nickel; manufactured by Shimura Chemical Co., Ltd.) as the positive electrode, electricity for 20 minutes at a current density of 5 A / dm ² Plating was performed, and Ni plating of about 20 μm was performed.
<Ag plating>
The substrate is immersed in an electroplating solution (potassium cyanide cyanide solution), the substrate is used as a negative electrode, the anode (Ti / Pt electrode) is used as a positive electrode, and plating is performed at a current density of 0.4 A / dm ² for 20 seconds. About 0.1 μm of Ag plating was applied.

Next, the resist pattern was dissolved and removed with an alkaline aqueous solution or an organic solvent to obtain a lead frame having a circuit portion (terminal portion, die pad) on one surface of the substrate. Thereafter, the lead frame was etched under the following conditions.
<Etching conditions>
・ Etching method: Immersion method ・ Etching solution: MEC REMOVER NH-1865 manufactured by MEC
Etching time: 5 minutes Etching solution temperature: 30 ° C
By this etching process, a recess having a width of 20 μm corresponding to the thickness of the base and a depth of 5 μm is formed on the side wall surface of the base of the circuit portion, and the semiconductor device lead of the present invention as shown in FIG. Got a frame.

[Example 2]
In the same manner as in Example 1, a resist pattern was formed on the substrate.
Further, in the same manner as in Example 1, a base noble metal layer (Au / Pd layer), a base (Ni layer), and a surface noble metal layer (Ag layer) were formed, and a laminate having a thickness of about 20 μm was formed.
Next, the resist pattern was dissolved and removed with an alkaline aqueous solution or an organic solvent to obtain a lead frame having a circuit portion (terminal portion, die pad) on one surface of the substrate. Thereafter, the lead frame was etched under the following conditions.
<Etching conditions>
・ Etching method: Dipping method ・ Etching solution: NCH manufactured by Nippon Chemical Industry Co., Ltd.
Etching time: 1 minute Etching solution temperature: 30 ° C
By this etching process, a rough surface was formed on the entire side wall surface of the base portion of the circuit portion, and a lead frame for a semiconductor device according to the present invention as shown in FIG. 4 was obtained. The average roughness Ra of this rough surface was 0.2 μm. The average roughness Ra was measured using Vertscan R5300 manufactured by Ryoka System Co., Ltd.

[Example 3]
In the same manner as in Example 1, a resist pattern was formed on the substrate.
Next, 6 layers of Au, Pd, Ni, Au, Ni, and Ag were laminated in the order of the following electroplating conditions, and the base noble metal layer (Au / Pd layer), base (base thin film (Ni layer) / intermediate layer ( Au layer) / base thin film (Ni layer)) and surface noble metal layer (Ag layer) were formed to form a laminate having a thickness of about 30 μm.
<Au plating (underlying precious metal layer)>
The substrate is immersed in an electroplating solution (a potassium cyanide cyanide solution), the substrate is used as a negative electrode, the anode (Ti / Pt electrode) is used as a positive electrode, and plating is performed at a current density of 0.3 A / dm ² for 40 seconds. About 0.04 μm Au plating was applied.

<Pd plating>
The substrate is immersed in an electroplating solution (ammonia-based Pd solution), the substrate is used as a negative electrode, the anode (Ti / Pt electrode) is used as a positive electrode, and plating is performed at a current density of 3 A / dm ² for 20 seconds. 15 μm Pd plating was applied.
<Ni plating (base film, common twice)>
Dipping the substrate in an electroplating solution (nickel sulfamate solution), using the substrate as the negative electrode, and using the anode (S round nickel; manufactured by Shimura Chemical Co., Ltd.) as the positive electrode, electricity for 14 minutes at a current density of 5 A / dm ² Plating was performed, and Ni plating of about 14 μm was performed.
<Au plating (base intermediate layer)>
Dipping the substrate in an electroplating solution (Au potassium cyanide solution), plating the substrate for 120 seconds at a current density of 0.3 A / dm ² with the substrate as the negative electrode and the anode (Ti / Pt electrode) as the positive electrode, About 0.13 μm Au plating was applied.
<Ag plating>
The substrate is immersed in an electroplating solution (potassium cyanide cyanide solution), the substrate is used as a negative electrode, the anode (Ti / Pt electrode) is used as a positive electrode, and plating is performed at a current density of 0.4 A / dm ² for 20 seconds. About 0.1 μm of Ag plating was applied.

Next, the resist pattern was dissolved and removed with an alkaline aqueous solution or an organic solvent to obtain a lead frame having a circuit portion (terminal portion, die pad) on one surface of the substrate. Thereafter, the lead frame was etched under the following conditions.
<Etching conditions>
・ Etching method: Immersion method ・ Etching solution: MEC REMOVER NH-1865 manufactured by MEC
Etching time: 5 minutes Etching solution temperature: 30 ° C

  By this etching process, a two-step recess was formed on the side wall surface of the base portion of the circuit portion, and a lead frame for a semiconductor device of the present invention as shown in FIG. 5 was obtained. Of the two-stage recesses formed, the recesses on the substrate side were 14 μm wide and 3 μm deep, and the recesses on the surface noble metal layer side were 14 μm wide and 3 μm deep.

[Example 4]
In the same manner as in Example 1, a resist pattern was formed on the substrate.
Further, in the same manner as in Example 1, a base noble metal layer (Au / Pd layer), a base (Ni layer), and a surface noble metal layer (Ag layer) were formed to form a laminate having a thickness of about 30 μm.
Next, the resist pattern is dissolved and removed with an alkaline aqueous solution or an organic solvent, and then a resist (manufactured by Asahi Kasei E-Materials Co., Ltd.) is formed on the substrate on which the laminate composed of the base noble metal layer, the base, and the surface noble metal layer exists. AQ-2058) was disposed to form a resist layer having a thickness of 20 μm. Therefore, about 10 μm from the surface of the laminate was exposed by protruding from the resist layer.
Next, a noble metal layer was formed by laminating an Ag layer under the following electroplating conditions on the laminate exposed from the resist layer <Ag plating>
The substrate is immersed in an electroplating solution (potassium cyanide cyanide solution), the substrate is used as a negative electrode, the anode (Ti / Pd electrode) is used as a positive electrode, and plating is performed at a current density of 0.4 A / dm ² for 10 seconds. About 50 nm of Ag plating was applied.

Next, the resist layer was dissolved and removed with an alkaline aqueous solution or an organic solvent to obtain a lead frame having a circuit portion (terminal portion, die pad) on one surface of the substrate. Thereafter, the lead frame was etched under the following conditions.
<Etching conditions>
・ Etching method: Dipping method ・ Etching solution: NCH manufactured by Nippon Chemical Industry Co., Ltd.
Etching time: 1 minute Etching solution temperature: 30 ° C
By this etching process, a concave portion and a rough surface were formed on the side wall surface of the base portion of the circuit portion, and a lead frame for a semiconductor device of the present invention as shown in FIG. 6 was obtained. The formed recess had a width of 14 μm and a depth of 3 μm, and the rough surface had a width of 10 μm and an average roughness Ra of 0.2 μm.

[Comparative example]
In the same manner as in Example 1, a resist pattern was formed on the substrate.
Next, four layers of Au, Pd, Ni, and Ag were laminated in the same manner as in Example 1 except that the energization time for Ni plating conditions was 60 minutes, and the base noble metal layer (Au / Pd layer) and base (Ni Layer) and a surface noble metal layer (Ag layer) to form a laminate having a thickness of about 55 μm. In this laminate, the upper part of the base (Ni layer) and the surface noble metal layer (Ag layer) protruded along the surface of the resist pattern with a length of 10 μm in the lateral direction.
Next, the resist pattern was dissolved and removed with an alkaline aqueous solution or an organic solvent to obtain a lead frame for a semiconductor device having a circuit portion (terminal portion, die pad) on one surface of the substrate. This circuit part has a hook-shaped protruding part in the peripheral part. However, in the dissolution removal of the resist pattern, it is difficult to remove the resist pattern sandwiched between the overhanging portion and the substrate, particularly between adjacent terminal portions, and the same processing as in Examples 1 to 4 When dissolution and removal were performed at the concentration and temperature, a resist pattern remained partially even after processing for 4 times the processing time, and complete removal was difficult.

[Evaluation of lead frames for semiconductor devices]
A semiconductor element (with a smaller area than the die pad) is mounted on the die pad of the semiconductor device lead frame (Examples 1 to 4 and Comparative Example) manufactured as described above via an insulating member (die attach agent), The terminal of this semiconductor element and the internal terminal surface of the terminal part of the lead frame for a semiconductor device were connected using a wire. Next, on the substrate, the die pad, the terminal portion, the semiconductor element, and the wire were sealed with a resin member (a novolac resin (MP-8000 manufactured by Nitto Denko Corporation)). Thereafter, the substrate was etched with an ammonia-based etching solution to separate the resin-encapsulated semiconductor device from the substrate, thereby obtaining a resin-encapsulated semiconductor device.
All of the obtained resin-encapsulated semiconductor devices had good adhesion between the die pad and terminal portion and the resin member. From this, the lead frame for a semiconductor device of the present invention is easy to manufacture, but with respect to the improvement of reliability by engagement with a resin member, it is for a conventional semiconductor device having a hook-shaped overhanging portion on a terminal portion or a die pad. It was confirmed that the same effect as the lead frame was achieved.

  The present invention is useful in manufacturing a resin-encapsulated semiconductor device.

11, 21, 31, 41, 51, 61 ... Lead frame for semiconductor device 12, 22, 32, 42, 52, 62 ... Substrate 13, 23, 33, 43, 53, 63 ... Circuit part 13A, 23A, 33A, 43A, 53A, 63A ... Terminal part 13B, 23B, 33B, 43B ... Die pad 14, 24, 34, 44, 54, 64 ... Base part 14c, 24c, 34c, 44c ... Side wall surface 15, 25, 35, 45, 55, 65: surface noble metal layer 16, 26, 36, 46, 56, 66 ... base noble metal layer 17, 37 (37a, 37b), 47 ... concave portion 28, 48 ... rough surface

In order to achieve such an object, the resin-encapsulated semiconductor device of the present invention includes a plurality of terminal portions each having an internal terminal surface and an external terminal surface integrated with each other so that the external terminal surface forms a single plane. A circuit part; a semiconductor element electrically connected to the internal terminal surface of the terminal part by a wire; and at least the external terminal surface of the terminal part exposed, the terminal part, the semiconductor element, A resin member that seals the wire, and the terminal portion includes a base portion made of one kind of metal and a surface noble metal layer that constitutes the internal terminal surface, and a recess is formed in a side wall surface of the base portion. The concave portion is a concave portion that is continuous in a direction parallel to the one plane, and is present in multiple stages in the thickness direction of the terminal portion, the thickness of the base portion is in the range of 5 to 50 μm, and the surface noble metal layer the thickness in the range of 0.001~10μm It was Do configuration.
Another aspect of the present invention, the terminal portion may have a underlying noble metal layer constituting the external terminal surface opposite to the surface provided with the surface noble metal layer of the base, the thickness of the underlying noble metal layer is 0.001 was in the range der so that construction of the ~1μm.
As another aspect of the present invention, the circuit unit has a die pad on a plane formed by the terminal unit, the semiconductor element is located on the die pad via an insulating member, and the die pad is one type And a surface noble metal layer constituting an inner surface for mounting a semiconductor element, and a recess on the side wall surface of the base , the recess extending along a direction parallel to the one plane. In addition to continuous recesses, the recesses exist in multiple stages in the thickness direction of the die pad, the base has a thickness in the range of 5 to 50 μm, and the surface noble metal layer has a thickness in the range of 0.001 to 10 μm .
Another aspect of the present invention, the die pad may have a underlying noble metal layer on the opposite side of the interior surface of the semiconductor element mounting of the base, the thickness of the underlying noble metal layer area by der of 0.001~1μm The configuration is as follows.
A resin-encapsulated semiconductor device according to the present invention includes a circuit unit including a plurality of terminal portions each having an internal terminal surface and an external terminal surface integrated with each other so that the external terminal surface forms a single plane, and an internal terminal of the terminal unit A semiconductor element electrically connected to the surface by a wire, and a resin member that seals the terminal portion, the semiconductor element, and the wire in a state where at least the external terminal surface of the terminal portion is exposed. The terminal portion has a base portion and a surface noble metal layer constituting the internal terminal surface, and has a concave portion and a rough surface on the side wall surface of the base portion, and the concave portion is more than the rough surface. It was set as the structure located in the external terminal surface side.
As another aspect of the present invention, the terminal portion has a base noble metal layer constituting an external terminal surface on the opposite side of the surface of the base having the surface noble metal layer.
As another aspect of the present invention, the circuit portion has a die pad on a plane formed by the terminal portion, the semiconductor element is located on the die pad via an insulating member, and the die pad has a base portion. And a surface noble metal layer constituting an inner surface for mounting a semiconductor element, and having a recess and a rough surface on the side wall surface of the base, the recess being closer to the outside of the resin member than the rough surface. It was set as the structure which is located.
As another aspect of the present invention, the die pad has a base noble metal layer on the side opposite to the inner surface for mounting the semiconductor element of the base.
As another aspect of the present invention, the concave portion is configured to be a concave portion continuous along one plane formed by the terminal portion.
As another aspect of the present invention, the concave portion is configured to exist in multiple stages in the thickness direction of the circuit portion .
As the onset light other embodiments, and configured as comprising a solder ball to the external terminal face of the terminal portion exposed.
The resin-encapsulated semiconductor device according to the present invention includes a circuit unit including a plurality of terminal units each having an internal terminal surface and an external terminal surface integrated with each other, and an electrical connection between the internal terminal surface of the terminal unit and the wire by a wire. A semiconductor element, and a resin member that seals the terminal part, the semiconductor element, and the wire in a state where at least an external terminal surface of the terminal part is exposed, and the terminal part includes a base part, It has a surface noble metal layer constituting an internal terminal surface, a base noble metal layer constituting an external terminal surface on the opposite side of the surface of the base having the surface noble metal layer, and a recess and a rough surface on the side wall surface of the base The base noble metal layer exposed from the resin member as an external terminal surface and the resin member form a single plane.
A resin-encapsulated semiconductor device according to the present invention includes a circuit unit including a plurality of terminal portions each having an internal terminal surface and an external terminal surface integrated with each other so that the external terminal surface forms a single plane, and an internal terminal of the terminal unit A semiconductor element electrically connected to the surface by a wire, and a resin member that seals the terminal portion, the semiconductor element, and the wire in a state where at least the external terminal surface of the terminal portion is exposed. The terminal portion has a base portion and a surface noble metal layer constituting the internal terminal surface, and has at least one of a concave portion and a rough surface on the side wall surface of the base portion, and the plurality of terminal portions are The semiconductor element is arranged so as to correspond to the outer shape of the semiconductor element, and the inner terminal surface side of the terminal portion is a semiconductor element mounting surface in which a part of the surface noble metal layer forms a plane, and the semiconductor element Through an insulating member on the semiconductor element mounting surface Was such that the position configuration Te.

A method for manufacturing a resin-encapsulated semiconductor device according to the present invention includes a substrate and a circuit unit positioned on the substrate, the circuit unit includes a plurality of terminal units, and the terminal unit has a surface on the substrate side. configure the external terminal face, the surface of the external terminal face opposite to configure the internal terminal face, said terminal portion base consisting of one metal, located on the surface opposite to the substrate side of the base portion And having a surface noble metal layer constituting the internal terminal surface , and having a recess on the side wall surface of the base, the recess being a recess continuous in a direction parallel to the substrate surface, and the circuit present in the thickness direction of the parts in multiple stages, the thickness is 5~50μm of range of the base, the thickness of the surface noble metal layer to prepare a semiconductor device lead frame area by der of 0.001 to 10, the semiconductor device A semiconductor element is mounted on the lead frame for use with the terminal of the semiconductor element. , Said said surface noble metal layer of the terminal portion of the lead frame for a semiconductor device, is connected with the wire, on the substrate, the terminal portion, the semiconductor element, the semiconductor and the wire is sealed by a resin member The device was configured such that a resin-sealed semiconductor device was peeled from the substrate.
Another aspect of the present invention, the circuit portion of the semiconductor device lead frame, underlying noble metal layer have a, the thickness of the underlying noble metal layer is in the range of 0.001~1μm between the substrate and the base It was der so that configuration.
A method for manufacturing a resin-encapsulated semiconductor device according to the present invention includes a substrate and a circuit unit positioned on the substrate, the circuit unit includes a plurality of terminal units, and the terminal unit has a surface on the substrate side. An external terminal surface is configured, and a surface opposite to the external terminal surface forms an internal terminal surface, and the terminal portion is located on a surface of the base opposite to the substrate side of the base and the internal terminal surface A lead frame for a semiconductor device that has a surface noble metal layer that comprises a concave portion and a rough surface on a side wall surface of the base, and the concave portion is located closer to the substrate than the rough surface, A semiconductor element is mounted on a lead frame for a semiconductor device, and a terminal of the semiconductor element and the surface noble metal layer of the terminal portion of the lead frame for the semiconductor device are connected using a wire, and on the substrate, The terminal part, the semiconductor element, and the wire as a resin member Ri sealed with a semiconductor device, a semiconductor device resin-sealed was configured such that the peeling from the substrate.
As another aspect of the present invention, the circuit portion of the lead frame for a semiconductor device is configured to have a base noble metal layer between the base portion and the substrate .
As another aspect of the present invention, the concave portion of the lead frame for a semiconductor device is configured to be a concave portion continuous in a direction parallel to the substrate surface.
As another aspect of the present invention, the concave portion of the lead frame for a semiconductor device is configured to exist in multiple stages in the thickness direction of the circuit portion .
As the onset light other embodiments, wherein the circuit portion of the lead frame for a semiconductor device further comprises a die pad, the die pad Ri interior surface der for surface opposite to the semiconductor element mounting and the substrate side, the semiconductor the device was mounted to so that configuration to the inner surface for said semiconductor element mounting.

Claims (15)

A plurality of terminal portions each having an internal terminal surface and an external terminal surface integrated with each other electrically connected to the circuit portion including the external terminal surface so as to form a flat surface, and the internal terminal surface of the terminal portion by a wire; And a resin member that seals the terminal portion, the semiconductor element, and the wire in a state where at least the external terminal surface of the terminal portion is exposed,
The terminal portion includes a base portion and a surface noble metal layer constituting the internal terminal surface, and has at least one of a concave portion and a rough surface on a side wall surface of the base portion. apparatus.   2. The resin-encapsulated semiconductor device according to claim 1, wherein the terminal portion includes a base noble metal layer constituting an external terminal surface on a side opposite to a surface of the base portion including the surface noble metal layer.   The circuit portion has a die pad on a plane formed by the terminal portion, the die pad having a base and a surface noble metal layer constituting an internal surface for mounting a semiconductor element, and on the side of the base The resin-encapsulated semiconductor device according to claim 1, wherein the wall surface has at least one of a concave portion and a rough surface.   4. The resin-encapsulated semiconductor device according to claim 3, wherein the die pad has a base noble metal layer on a side opposite to a surface of the base having the surface noble metal layer. 5.   5. The resin-encapsulated semiconductor device according to claim 1, wherein the concave portion is a concave portion that is continuous along one plane formed by the terminal portion.   The resin-encapsulated semiconductor device according to claim 1, wherein the recesses are present in multiple stages in the thickness direction of the circuit unit.   The said recessed part which exists in the side wall surface of the base part of the said circuit part with the said rough surface is located in the outer side of the said resin member rather than the said rough surface, The Claim 1 thru | or 6 characterized by the above-mentioned. Resin-sealed semiconductor device.   The resin-encapsulated semiconductor device according to claim 1, further comprising a solder ball on an exposed external terminal surface of the terminal portion. A substrate and a circuit portion located on the substrate, the circuit portion having a base and a surface noble metal layer located on a surface opposite to the substrate side of the base, and on a side wall surface of the base Preparing a lead frame for a semiconductor device having at least one of a recess and a rough surface;
A semiconductor element is mounted on the lead frame for a semiconductor device, and a terminal of the semiconductor element and a surface noble metal layer of a terminal portion of the lead frame for the semiconductor device are connected using a wire,
On the substrate, the terminal portion, the semiconductor element, and the wire are sealed with a resin member to form a semiconductor device,
A method for producing a resin-encapsulated semiconductor device, comprising: peeling a resin-encapsulated semiconductor device from the substrate.   The method for manufacturing a resin-encapsulated semiconductor device according to claim 9, wherein the circuit portion of the lead frame for a semiconductor device has a base noble metal layer between the base portion and the substrate.   11. The method for manufacturing a resin-encapsulated semiconductor device according to claim 9, wherein the concave portion of the lead frame for a semiconductor device is a concave portion continuous in a direction parallel to the substrate surface.   The method for manufacturing a resin-encapsulated semiconductor device according to claim 9, wherein the recesses of the lead frame for a semiconductor device are present in multiple stages in the thickness direction of the circuit portion.   13. The resin seal according to claim 9, wherein the concave portion existing on the side wall surface of the base portion of the circuit portion together with the rough surface is located on the substrate side with respect to the rough surface. A manufacturing method of a stationary semiconductor device.   The circuit portion of the lead frame for a semiconductor device includes a plurality of terminal portions, and the surface of the terminal portion constitutes an external terminal surface, and the surface opposite to the external terminal surface constitutes an internal terminal surface. A method for manufacturing a resin-encapsulated semiconductor device according to any one of claims 9 to 13, wherein:   15. The circuit part of the lead frame for a semiconductor device further comprises a die pad, and the surface of the die pad opposite to the substrate side is an internal surface for mounting a semiconductor element. A method for manufacturing a resin-encapsulated semiconductor device according to any one of the above.

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