JP6539928B2 - Lead frame for mounting a semiconductor device and method of manufacturing the same - Google Patents

Description

  The present invention relates to a lead frame for mounting a semiconductor device and a method of manufacturing the same.

  2. Description of the Related Art In recent years, the demand for miniaturization of semiconductor devices has been increased mainly for portable devices, and various structures and manufacturing methods of semiconductor devices have been proposed. These are called CSP (Chip Scale Package), and include one in which an external connection terminal is formed directly on a semiconductor element, and one in which an external connection terminal is formed using a resin substrate, a lead frame or the like.

  Although various semiconductor devices using lead frames have been proposed, a semiconductor device described in Patent Document 1 can be mentioned as an example that can handle multiple pins. That is, in the semiconductor device described in Patent Document 1, a resist mask subjected to predetermined patterning is formed on both sides of a conductive metal plate, and a conductive metal is plated on the metal plate exposed from the resist mask. As a plating layer. Then, using the plated layer on the front surface side as a mask, etching is performed from the front surface side to secure a semiconductor element mounting region, form a lead portion for external connection, and remove the resist mask to mount the semiconductor element. First, a lead frame is formed. Then, the semiconductor element is mounted on the formed lead frame for mounting a semiconductor element, wire bonding is performed, resin sealing is performed, the metal plate at a predetermined location is removed using the plating layer on the back side as a mask, and the die pad portion and the lead portion are A separated semiconductor device is manufactured. According to this method, it is possible to miniaturize a semiconductor device having 100 or more pins.

JP 2007-150372 A

  However, in the process of assembling the semiconductor device described in Patent Document 1, although the metal plate at a predetermined location is etched away after resin sealing, the metal plate to be removed is not partially melted away. There is a case where a part remains and terminals can not be separated independently.

  FIG. 6 is a view showing an etching process after resin sealing of the conventional semiconductor device. As shown in FIG. 6, the metal plate is completely etched between the semiconductor element mounting region 220 and the lead portion 230, and both are completely separated, but between the adjacent lead portions 230. A metal plate has been left. If a metal plate remains between the lead portions 230, the semiconductor device electrically shorts between the terminals, resulting in a serious defect. This is because, in the etching step after resin sealing, the flow of the etching solution is worse in places where the distance between the terminals is narrower than in the other regions. That is, when the flow of the etching solution is poor, new etching is not supplied to the portion, and the etching rate becomes slow.

  In order to prevent this, it is possible to prevent the etching residue by lengthening the etching time, but the portions of other terminals may be etched more than necessary and the terminal shape may become smaller than a predetermined size. . Further, when etching is performed using the plating layer as a resist mask, there is a problem that the metal portion of the lower surface of the plating layer is etched more than necessary and the peripheral portion of the plating layer becomes plating burrs, resulting in a decrease in yield and cost.

  Therefore, the present invention has been made in view of the above, and when a semiconductor device is completed by etching away a metal plate at a predetermined location after resin sealing, an etching residue occurs between terminals etc. at the time of etching removal. It is an object of the present invention to provide a lead frame for mounting a semiconductor device which does not affect other terminals and a method of manufacturing the same.

In order to achieve the above object, a lead frame for mounting a semiconductor device according to an aspect of the present invention,
A semiconductor element mounting area provided in a predetermined area on the surface side of the metal plate;
A predetermined recessed area is provided on the surface side of the metal plate, a non-recessed area other than the recessed area is provided on the upper surface, and a plurality of pillars protruding beyond the recessed area are provided around the semiconductor element mounting area. Lead parts provided,
It is at least a part of the back side of the region between the adjacent lead portions, and the distance between the lead portions is 1/2 or less from the distance between the semiconductor element mounting region and the lead portion And a recess provided in the area
The depth of the recess on the back surface side is shallower than the depth of the depression region on the surface side,
It is a flat surface between the back surface side of the said semiconductor element mounting area | region and the back surface side of the said lead part.

A method of manufacturing a semiconductor element mounting lead frame according to another aspect of the present invention is a method of manufacturing a semiconductor element mounting lead frame having a semiconductor element mounting region and a plurality of lead portions provided around the semiconductor element mounting region.
A resist forming step of forming a resist on the front surface and the back surface of the region forming the lead portion of the metal plate and the back surface between the semiconductor element mounting region and the lead portion;
Etching is simultaneously performed from both sides of the metal plate to form the surface side of the lead portion in a columnar shape, and the back surface between the semiconductor element mounting region and the lead portion is not etched but the adjacent lead portion Recessed area shallower than the etching depth on the surface side in a region on the back surface between the lead area and the semiconductor element mounting area and the lead area in which the distance between the lead areas is 1/2 or less And an etching process to form

  According to the present invention, it is possible to maintain the shape of leads without generating etching residue between adjacent lead portions, and to prevent the influence on adjacent lead portions such as plating burrs.

FIG. 1 is a cross-sectional view showing an example of a lead frame for mounting a semiconductor element according to an embodiment of the present invention. FIG. 1 is a cross-sectional view showing an example of a semiconductor device using a lead frame for mounting a semiconductor element according to an embodiment of the present invention. It is the figure which showed the series of processes of the first half of an example of the manufacturing method of the lead frame for semiconductor element mounting concerning the embodiment of the present invention. Fig.3 (a) is the figure which showed an example of the metal plate preparation process. FIG. 3B is a view showing an example of the first resist mask forming step. FIG. 3C is a view showing an example of the plating process. It is the figure which showed the series of processes of the second half of an example of the manufacturing method of the lead frame for semiconductor element loading concerning the embodiment of the present invention. FIG. 4A is a view showing an example of the second resist mask forming step. FIG. 4B is a view showing an example of the etching process. FIG.4 (c) is the figure which showed an example of the resist mask peeling process. FIG. 7 is a diagram showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5A is a cross-sectional view showing an example of a semiconductor element mounting / bonding / resin sealing process. FIG.5 (b) is the figure which showed an example of the etching process after resin sealing. It is the figure which showed the etching process after resin sealing of the conventional semiconductor device.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing an example of a semiconductor device mounting lead frame according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing an example of a semiconductor device using the semiconductor device mounting lead frame according to the embodiment of the present invention.

  As shown in FIG. 1, a semiconductor element mounting lead frame 100 according to an embodiment of the present invention is configured using a metal plate 10. The metal plate 10 may be made of various metal materials, but may be made of, for example, copper or a copper alloy having a thickness of 0.1 mm to 0.15 mm.

  The semiconductor element mounting lead frame 100 according to the present embodiment includes a die pad portion 20, a lead portion 30, a recess 50, and a plating layer 60. The plating layer 60 includes a plating layer 61 provided on the top surface of the lead portion 30, a plating layer 62 provided on the bottom surface of the lead portion 30, and a plating layer 63 provided on the back surface of the die pad portion 20.

  The die pad portion 20 is a region for mounting a semiconductor element. In FIG. 2, the semiconductor element 110 is mounted on the surface of the die pad portion 20, and the semiconductor device 150 is configured as a whole.

  As shown in FIG. 2, the die pad portion 20 is often formed in the central region of the semiconductor device 150. In addition, since the metal plate 10 is made of a single metal material, the metal plate 10 itself does not have a front surface and a back surface, but in the present embodiment, a semiconductor element on which the semiconductor element 110 is mounted for convenience. The mounting surface is referred to as the front side or the front side, and the opposite side is referred to as the back side or the back side. In FIG. 1 and FIG. 2, the upper surface is the front surface, and the lower surface is the back surface.

  The lead portion 30 is a connection terminal formed around the die pad portion 20 and electrically connected from the electrode of the semiconductor element 110 using the bonding wire 120. A plurality of lead portions 30 are generally provided around the periphery of one die pad portion 20, and play a role of electrically connecting the terminals (electrodes) of the semiconductor element 110 to the outside. As shown in FIG. 1, the lead portion 30 may be provided in a double annular shape including an inner lead portion 30 closer to the die pad portion 20 and a lead portion 30 slightly away from the die pad portion 20.

  As shown in FIG. 1, the lead portion 30 is configured to have a columnar shape by forming the recessed region 40 by etching from the surface side. That is, the lead portion which is not etched by removing the metal plate 10 from the surface to the middle without etching through the metal plate 10 by etching and forming the depressed region 40 in which the non-recessed region 41 is left. A shape 30 protrudes upward in a columnar shape relatively to the recessed area 40. Since the lead portions 30 are connected to each other and to the metal plate 10 via the non-recessed regions 41, there is no risk of detachment from the metal plate 10. That is, the semiconductor element mounting lead frame 100 has the columnar lead portion 30 formed by etching on the front surface side, but the back surface side is not etched except for the recess 50, and the material surface of the metal plate 10 Since it is left as it is, in the state of the lead frame 100, the die pad portion 20 and the lead portion 30 do not need to be connected to the outer frame of the lead frame 100, and can be freely arranged. Therefore, the die pad portion 20 and the lead portion 30 can be configured to have a free planar shape, and the die pad portion 20 and the lead portion 30 can be arranged with high density. For this reason, only the die pad portion 20 and the lead portion 30 necessary for the semiconductor device 150 can be disposed, and the plurality of semiconductor devices 150 can be disposed with an interval of the minimum cutting width.

  Incidentally, as shown in FIG. 2, at the stage of manufacturing the semiconductor device 150, the metal plate 10 other than the die pad portion 20 and the lead portion 30 is removed, and the die pad portion 20 and the lead portion 30 are independent shapes not connected to each other. And fixed by the sealing resin 130.

  The die pad portion 20 is included in the metal plate 10 remaining on the lower side by the etching process in the semiconductor element mounting region in FIG. Thereafter, an example is described in which the resin sealing is performed and the etching process after the resin sealing is performed by removing a predetermined portion of the metal plate 10 from the lower side. The die pad portion 20 can also be formed by etching similarly to the lead portion 30. In addition, after the semiconductor element mounting area is secured, resin sealing is performed, and in the etching step after resin sealing, the remaining part of the semiconductor element mounting area is removed to expose the bottom surface of the semiconductor element 110 from the sealing resin 130. It is also good.

  As shown in FIG. 1, the semiconductor element mounting lead frame 100 according to the present embodiment has a recess 50 on the back surface side of the region between the adjacent lead portions 30. The recess 50 is formed by etching the metal plate 10 from the back surface side.

  As described above, in the conventional lead frame for mounting a semiconductor element having a flat back surface, etching is performed when a metal plate at a predetermined location is etched from the back surface after resin sealing in a semiconductor device assembly process. As a result, the metal plate to be removed may not be completely melted and a part of the metal plate may remain, and the lead portions may not be separated and independent. Such a defect is likely to occur in a portion where the distance between the lead portions is short and the flow of the etching solution is worse than other regions. This is because if the flow of the etching solution is bad, the etching rate becomes slow because a new etching is not supplied to the portion. The pattern of the lead frame is substantially composed of a die pad portion and a lead portion. In addition, the number of pins has been increased for integration of semiconductor elements and high density mounting. For this reason, the distance between the lead portions is narrowed, and the difference between the distance between the die pad portion and the lead portion is twice or more. The etching width causes a difference in etching rate, which causes a difference in etching depth. Generally, the variation in the etching depth can be reduced by adjusting the shape or position of a resist mask which is an etching mask at the time of etching, or by the etching condition at the time of etching. However, in the etching process after resin sealing, the etching mask used at this time is a plating layer formed on the back surface of the metal plate. Since this plating layer becomes an external connection terminal portion, its shape and position can not be changed. For this reason, the above-described means generally used can not be used, and the difference in etching width is likely to occur as the difference in etching depth. In particular, when the difference in etching width is twice or more, the occurrence of defects is remarkable. In addition, extending the etching time until there is no residual metal plate in the portion where the etching rate is slow arises another problem. That is, the shape of the external connection terminal may be smaller than a predetermined size. In addition, the metal portion of the lower surface of the plating layer is etched more than necessary, and the peripheral portion of the plating layer is likely to become plating burrs, and in some cases, the plating burrs may fall off to cause electrical short failure of the semiconductor device. . For this reason, it is difficult to extend the etching time.

  Therefore, in the embodiment of the present invention, in the gap region between the lead portions in which the depth at the time of etching is reduced, etching is performed from the back surface side at the lead frame stage to form the recess 50. Thus, it is possible to maintain the balance with the region where the progress of the etching is fast, and to align the end timing of the etching as a whole. In the region to be etched from the back surface, at least the region in which the distance between the leads is 1/2 or less is determined by the distance between the die pad and the lead.

  In addition, the etching amount from the back surface at the time of forming the recessed part 50 is 5 micrometers-20 micrometers. That is, the depth from the flat surface of the back surface of the recess 50 is 5 to 20 μm. The factor causing the difference in the etching amount depends on the pattern shape, the type of etching solution, the concentration, etc. as described above. Therefore, the etching depth is adjusted so that the etching residue does not occur. Naturally, the recess 50 is set not to penetrate the surface side in combination with the etching on the surface side.

  Next, a method of manufacturing a lead frame according to an embodiment of the present invention will be described using FIGS. 3 and 4. FIG. 3 is a view showing a series of processes in the first half of an example of a method of manufacturing a lead frame for mounting a semiconductor device according to an embodiment of the present invention. FIG. 4 is a view showing a series of processes in the second half of the example of the method of manufacturing the lead frame for mounting a semiconductor device according to the embodiment of the present invention. Here, an example of a type in which a semiconductor region is secured and a die pad portion is formed by etching after resin sealing will be described. The type in which the die pad portion on which the semiconductor element is mounted is formed in the same manner as the lead portion or the type in which the die pad portion is not formed will be described with appropriate reference.

  Fig.3 (a) is the figure which showed an example of the metal plate preparation process. In the metal plate preparing step, a metal plate 10 to be a material of the semiconductor element mounting lead frame 100 is prepared. As the metal plate 10, various plate-like metal materials may be used depending on the application, but a high strength one is preferable, and a metal plate 10 made of copper or a copper alloy may be used. The thickness of the metal plate 10 is usually selected in the range of 100 to 200 μm in consideration of ease of handling and the like.

  FIG. 3B is a view showing an example of the first resist mask forming step. The first resist mask formation step specifically includes a resist coating step, an exposure step, and a development step. First, pretreatment is performed to remove foreign matter and impurities on the surface of the metal plate 10, and a resist 70 is coated on both sides. Although various resist materials may be used as the resist 70, for example, a dry film resist may be used. Further, when a dry film resist is used for the resist 70, the type and thickness of the dry film resist are not particularly limited, but a negative type in which the photosensitive portion is usually cured is used. Besides this, a positive type dry film resist may be used. Alternatively, a liquid photoresist may be applied. For example, a commercially available dry film resist is attached by a laminator. Next, resist masks 75 and 76 for forming necessary plating are formed on the front surface side (semiconductor element mounting surface side) and the back surface side (external connection portion side). The formation of the resist masks 75 and 76 is a general method, the resist 70 is exposed using a mask for exposure having a predetermined pattern formed thereon, and the openings 71 are formed by development, and the resist is formed on both sides. The masks 75 and 76 are formed. The die pad portion 20 has a pattern in which the plating layer 63 is not formed on the front surface side and the plating layer 63 is formed on the back surface side. In the case where the die pad portion 20 is formed in the same manner as the lead portion 30, the pattern is such that the plating layer 63 is formed on both the front and back sides. When the die pad portion is not formed, it is assumed that the plating layer 63 is not formed on the front and back sides.

FIG. 3C is a view showing an example of the plating process. In the plating step, general plating pretreatment is performed on the metal plate 10 exposed from the openings 71 of the formed resist masks 75 and 76, and then the necessary plating layers 61, 62 and 63 are formed. The masks 75 and 76 are peeled off. The plating layers 61, 62, 63 may use various metal materials, but noble metals such as gold (Au), silver (Ag), platinum (Pt), etc. may be used as the plating layers 61, 62, 63.
Multilayer plating of three layers of nickel (Ni), palladium (Pd), and gold (Au) may be used. FIG. 3C shows a state after plating and before peeling of the resist masks 75 and 76.

  FIG. 4A is a view showing an example of the second resist mask forming step. The second resist mask formation step specifically includes a resist coating step, an exposure step, and a development step. The resist 72 is coated again on both sides of the metal plate 10 on which the plating layers 61, 62, 63 are formed, and the pattern of the semiconductor element mounting lead frame 100 on the surface side is wider than the plating layer 61 formed. A resist mask 77 covering the area is formed. Note that the resist mask 77 is formed by forming an opening 73 in the resist 72. Further, on the back surface side, the resist mask 78 is formed such that the area where the recess 50 is formed between the adjacent lead portions 30 is the opening 73. The pattern of the resist mask 78 is appropriately adjusted and set in the shape, position, etc. of the resist 72 so that the entire etching depth is uniform and completed simultaneously in the etching step after resin sealing when the semiconductor device 150 is manufactured. .

  Here, the resist masks 77 and 78 of the portions to be the lead portions 30 to be wire bonded are the plating layers 61 and 62 of the lead portions 20 and the die pad portions 30 already formed when the metal plate 10 is dissolved by etching. , 63 so as to leave the surface of the metal plate 10 wider. By doing so, it is possible to prevent part of the plating layers 61, 62, 63 from becoming burrs or falling off and causing problems in the subsequent steps.

  In the die pad portion 20, the resist 72 is not provided on the front surface side, and the resist 72 is provided on the back surface side. When the die pad portion 72 is formed in the same manner as the lead portion 73, the resist 72 is coated on both the front and back sides. When the die pad portion 20 is not formed, the surface side is not covered with the resist 72, and the back side is covered with the resist 72.

  FIG. 4B is a view showing an example of the etching process. In the etching step, etching is performed using the formed resist masks 77 and 78 as etching masks. In the etching from the surface side, the etching is performed to a depth of about half to about 90% of the thickness of the metal plate 10. The depth of this etching can be arbitrarily selected in consideration of the etching from the back side after resin sealing.

  By performing the etching process of the metal plate 10 from the front surface side, the recess-shaped region 40 is formed in the region where the opening 73 is formed. The portion to be the lead portion 30 covered with the resist 72 is formed in a columnar shape having a recessed portion 42 on the side surface and a non-recessed region 41 on the upper surface. The upper surface of the lead portion 30 has a configuration in which a plating layer 61 for wire bonding is formed in an area smaller than the planar shape of the upper surface, and the lower surface has a configuration in which a plating layer 62 for external connection is formed. Function.

  Further, from the back surface side, the etching process is performed on a region where the distance between the adjacent lead portions 30 is narrow, and the concave portion 50 is formed. The etching depth of the recess 50 is 5 μm to 20 μm. In the etching from the front side and the etching from the back side, the etching is performed in consideration of not penetrating the front and back.

  FIG.4 (c) is the figure which showed an example of the resist mask peeling process. In the resist mask peeling step, the resist mask 77 on the front side and the resist mask 78 on the back side are peeled off. Thus, the semiconductor element mounting lead frame 100 according to the embodiment of the present invention is completed. The peeling of the resist masks 77 and 78 may be performed using a predetermined peeling liquid.

  In addition, after the resist mask peeling process of FIG. 4C, if necessary, it may be cut into a predetermined size to make the lead frame for mounting a semiconductor element into a sheet shape.

  Next, a method of manufacturing a semiconductor device using the lead frame for mounting a semiconductor device according to the embodiment of the present invention will be described with reference to FIG. FIG. 5 is a view showing an example of a method of manufacturing a semiconductor device according to the embodiment of the present invention.

  FIG. 5A is a cross-sectional view showing an example of a semiconductor element mounting / bonding / resin sealing process. In the semiconductor element mounting step, the semiconductor element 110 is mounted on the die pad portion 20 of the lead frame 100 for mounting a semiconductor element. Thereafter, in the bonding step, the electrode 111 of the semiconductor element 110 and the lead portion 30 are wire-bonded by the bonding wire 120. Thereafter, in the resin sealing step, the surface side of the semiconductor element mounting lead frame 100 is sealed with a sealing resin 130.

  FIG.5 (b) is the figure which showed an example of the etching process after resin sealing. In the etching process after resin sealing, etching is performed using the plating layers 62 and 63 on the back surface side of the semiconductor element mounting lead frame 100 as an etching mask. Predetermined portions of the die pad portion 20 and the lead portion 30 excluding the plated layers 62 and 63 are removed by etching.

  In the region between the adjacent lead portions 30, the etching rate is slow because the distance between the plating layers 62 is narrow, but since the recess 50 is formed in the region, the etching rate is small even if the etching amount is small Area and the etching depth are balanced, the etching is completed substantially simultaneously, and the metal plate 10 can be removed. Thereby, each lead part 30 and die pad part 20 become independent, respectively.

  Finally, the semiconductor device is cut into predetermined dimensions to obtain the semiconductor device.

  As described above, by using the semiconductor element mounting lead frame 100 according to the present embodiment, in the etching from the back surface side after resin sealing when manufacturing the semiconductor device 150, the adjacent lead portions 30 are insulated from each other. While being securable, it can prevent that a plating burr generate | occur | produces between the die pad part 20 and the lead part 30. FIG.

  Next, one embodiment of the lead frame for mounting a semiconductor device of the present invention will be described. In addition, the same referential mark shall be given to the components corresponding to each component of embodiment described so far for easy understanding.

Example 1
A dry film resist 70 (2558 manufactured by Asahi Kasei Co., Ltd.) was laminated on both sides of a copper-based alloy material (EFTEC 64-T manufactured by Furukawa Electric Co., Ltd.) having a thickness of 0.125 mm as the metal plate 10.

  Next, exposure was performed on both sides in a predetermined pattern, and development was performed to form resist masks 75 and 76 in which portions requiring plating were opened. The die pad portion had a pattern in which there was no plating layer on the upper surface and the plating layer on the lower surface.

  Next, 1 μm of Ni, 0.07 μm of Pd, and 0.003 μm of Au are sequentially plated on the metal plate 10 exposed from the openings 71 of the formed resist masks 75 and 76 in a thickness of 0.003 μm, 63 was formed.

  Next, the resist masks 75 and 76 are peeled off, and the same dry film resist 72 as described above is laminated on both sides of the metal plate 10 on which the plating layers 61, 62 and 63 are formed, and the semiconductor element is mounted. The exposed surface side was exposed by development with a pattern 50 μm larger than the formed plating layer to form a resist mask 77 larger 50 μm than the plating layer. Then, on the back surface side of the opposite surface, a resist opening is formed in a portion where the gap between adjacent lead portions is 100 μm or less (the distance between the lead portions is 1/2 or less from the distance between the die pad portion and the leads) A resist mask 78 was formed to provide 73.

  Next, etching was performed for 2 minutes at a spray pressure of 0.5 MPa using an etching solution with a liquid temperature of 40 ° C., and etching was performed to a depth of about 80 μm from the surface side to form a columnar part 1. At this time, the back side was also etched to a depth of 20 μm.

  Thereafter, the resist masks on both sides were peeled off to obtain a semiconductor element mounting lead frame 100.

  Next, using this lead frame 100, the semiconductor element 110 was mounted on the die pad portion 20 using silver paste or the like, and the semiconductor element 110 and the lead portion 30 were connected by a gold bonding wire 120 with a diameter of 20 μm. Thereafter, after sealing using an epoxy-based sealing resin 130, etching was performed using an alkaline copper etching solution. Finally, the semiconductor device was cut to a predetermined size.

Example 2
In Example 2, plated layers were formed on the upper and lower surfaces of the die pad portion, and a pattern having the same configuration as that of the lead portion was used. Further, in the etching step, the etching depth is about 90 μm from the surface side, and 10 μm from the back surface side. The other conditions were the same as in Example 1.

[Comparative example]
On the other hand, as a comparative example, it was set as the pattern which does not form a recessed part without etching on the back surface side. The other conditions were the same as in Example 1.

  In the above-mentioned Example 1 and 2 and a comparative example, the etching state was checked at the etching process after resin sealing. About Example 1 and 2, there was no remainder of the metal plate between lead parts, and it was good. In the comparative example, the metal plate was partially left between the leads and a short circuit occurred.

  As described above, according to the semiconductor element mounting lead frame according to the embodiment, the residual metal between the lead portions can be reliably removed, and highly reliable electrical performance can be obtained.

  Although the preferred embodiments and examples of the present invention have been described above in detail, the present invention is not limited to the above-described embodiments and examples, and the above-described embodiments and examples are possible without departing from the scope of the present invention. Various modifications and substitutions may be made to the embodiments.

DESCRIPTION OF SYMBOLS 10 metal plate 20 die pad part 30 lead part 40 hollow area 41 non-well area 50 recessed part 60-63 plated layer 70, 72 resist 71, 73 opening 75-78 resist mask 100 lead frame for semiconductor element mounting 110 semiconductor element 111 electrode 120 bonding Wire 130 Sealing resin 150 Semiconductor device

Claims (10)

A semiconductor element mounting area provided in a predetermined area on the surface side of the metal plate;
A predetermined recessed area is provided on the surface side of the metal plate, a non-recessed area other than the recessed area is provided on the upper surface, and a plurality of pillars protruding beyond the recessed area are provided around the semiconductor element mounting area. Lead parts provided,
It is at least a part of the back side of the region between the adjacent lead portions, and the distance between the lead portions is 1/2 or less from the distance between the semiconductor element mounting region and the lead portion And a recess provided in the area
The depth of the recess on the back surface side is shallower than the depth of the depression region on the surface side,
A semiconductor element mounting lead frame, wherein a flat surface is between the back surface side of the semiconductor element mounting region and the back surface side of the lead portion.   The semiconductor device mounting lead frame according to claim 1, wherein the concave portion is an etched portion formed by etching.   The semiconductor device mounting lead frame according to claim 1, wherein the predetermined recessed area is an etching processed area formed by etching.   The semiconductor element mounting lead frame according to any one of claims 1 to 3, wherein a plating layer is provided on the upper surface and the back surface of the lead portion, and the plating layer is not provided in the recess.   The semiconductor element mounting region has the same non-recessed region on the top surface as the lead portion, has a pillar shape protruding from the recessed region, and is provided with a plating layer having the same configuration as the lead portion. 5. A lead frame for mounting a semiconductor device according to item 4. A method of manufacturing a semiconductor element mounting lead frame having a semiconductor element mounting region and a plurality of lead portions provided around the semiconductor element mounting region, comprising:
A resist mask forming step of forming a resist mask on the surface and the back surface of a region of the metal plate where the lead portion is to be formed, and the back surface between the semiconductor element mounting region and the lead portion;
Etching is simultaneously performed from both sides of the metal plate to form the surface side of the lead portion in a columnar shape, and the back surface between the semiconductor element mounting region and the lead portion is not etched but the adjacent lead portion Recessed area shallower than the etching depth on the surface side in a region on the back surface between the lead area and the semiconductor element mounting area and the lead area in which the distance between the lead areas is 1/2 or less And an etching step of forming a lead frame for mounting a semiconductor element.   The method for manufacturing a semiconductor element mounting lead frame according to claim 6, wherein a resist mask is formed entirely on the back surface of the metal plate other than the back surface of the region where the recess is to be formed in the resist mask formation step.   The method for manufacturing a semiconductor element mounting lead frame according to claim 6, wherein the semiconductor element mounting area is processed into a recess in the etching step.   9. The method according to claim 7, further comprising a plating step of forming a plating layer on the surface and back surface of the region for forming the lead portion and the back surface of the region for forming the semiconductor element mounting region before the resist mask formation step. The manufacturing method of the lead frame for semiconductor element mounting as described.   10. The method of manufacturing a lead frame for mounting a semiconductor element according to claim 9, further comprising a plating mask formation step of forming a plating mask before the plating step.

Images