JP2016165912A - Electronic control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic control device which can surely prevent the occurrence of a phenomenon that a task is not executed in a specified phase accompanied by the changeover of a cores for executing the task, and the duplicate execution of the task.SOLUTION: This electronic control device 10 comprises a microcomputer 100 mounted with a plurality of cores C1, C2, and executes a synchronous task in synchronization with a phase of a rotation angle in the cores C1, C2. The electronic control device 10 comprises a first storage part 131 which stores a core number indicating the synchronization task execution core, and a second storage part 132 which stores a changeover phase indicating a phase when the synchronization task execution core is switched. The electronic control device 10 switches the synchronization task execution core on the basis of the core number which is stored in the first storage part 131 and the changeover phase which is stored in the second storage part 132.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic control device including a multi-core microcomputer equipped with a plurality of cores.

  As an electronic control device provided in a vehicle, a device including a multi-core microcomputer (hereinafter also referred to as “multi-core microcomputer”) equipped with a plurality of cores has been put into practical use. A multi-core microcomputer performs distributed processing of a plurality of tasks executed in control by a plurality of cores. Since the processing load on each core is reduced, complex processing can be executed at a relatively high speed.

  In such an electronic control device, dynamic switching of cores that execute tasks is performed so that only the processing load in some cores does not become too large (see, for example, Patent Document 1 below).

  For example, when the processing load of the first core to which execution of a certain task is assigned is large and the processing load of the second core is small, the core that executes the task is switched from the first core to the second core.

  Incidentally, some tasks executed by the electronic control device should be executed in synchronization with the phase of the rotation angle (such as the crank angle of the internal combustion engine) in the control target device. An example of such a task is calculation of fuel injection timing that is started every time the crank angle reaches a predetermined phase. In addition, calculation of ignition timing that is started every time the crank angle reaches a predetermined phase can be mentioned.

JP 2014-78078 A

  In the electronic control device as described above, depending on the timing at which the core that executes the task is switched, the task to be executed when the phase of the rotation angle becomes a specific phase is not executed by any core in the phase. Cases may arise. In addition, the task that should be executed when the phase of the rotation angle reaches a specific phase may be executed repeatedly by a plurality of cores.

  Such a phenomenon is that the timing at which task processing is started differs between cores, and the switching of a core that executes a task is performed asynchronously with the timing at which task processing is started. to cause.

  The present invention has been made in view of such problems. The purpose of the present invention is that a task is not executed in a specific phase, or a task is executed redundantly, when a core for executing the task is switched. An object of the present invention is to provide an electronic control device that can reliably prevent the phenomenon.

  In order to solve the above-described problems, an electronic control device according to the present invention includes a multi-core microcomputer equipped with a plurality of cores, and the electronic control device executes a task in synchronization with the phase of the rotation angle in the core. A first storage unit that stores a core number indicating a task execution core that executes a task, and a second storage unit that stores a switching phase indicating a phase when the task execution core is switched. The task execution core is switched based on the core number stored in the first storage unit and the switching phase stored in the second storage unit.

  In the electronic control device having such a configuration, switching of task execution cores is performed based on information (core number and switching phase) set and stored in advance.

  For example, a core that has executed a task before switching performs switching to a state in which the task is not executed at the timing when the phase becomes the switching phase. Further, the core that will execute the task after switching performs switching to the state in which the task is executed at the timing when the phase becomes the switching phase.

  In this way, the timing (phase) at which the state is switched can be made to coincide in all the cores. As a result, a phenomenon that a task is not executed by any core in a specific phase and a phenomenon that a task is executed repeatedly by a plurality of cores are surely prevented.

  According to the present invention, there is provided an electronic control device capable of reliably preventing a phenomenon in which a task is not executed in a specific phase or a phenomenon in which a task is executed repeatedly due to switching of a core for executing the task. Is done.

It is a figure which shows typically the structure of the electronic control apparatus which concerns on embodiment of this invention. It is a time chart for demonstrating the switching of the synchronous task execution core performed with the electronic controller of FIG. It is a time chart for demonstrating the switching of the synchronous task execution core performed with the electronic controller of FIG. It is a flowchart which shows the flow of the process performed with the electronic controller of FIG. It is a figure which shows the processing load of the core in the electronic controller of FIG. It is a figure which shows the processing load of the core in the electronic controller of FIG. It is a figure which shows the processing load of the core in the electronic controller of FIG. It is a flowchart which shows the flow of the process performed with the electronic controller of FIG. It is a state transition diagram of a core when switching of a synchronous task execution core is performed. It is a time chart for demonstrating switching of the synchronous task execution core performed by the electronic control which concerns on the comparative example of this invention. It is a time chart for demonstrating switching of the synchronous task execution core performed by the electronic control which concerns on the comparative example of this invention. It is a time chart for demonstrating switching of the synchronous task execution core performed by the electronic control which concerns on the comparative example of this invention. It is a time chart for demonstrating switching of the synchronous task execution core performed by the electronic control which concerns on the comparative example of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In order to facilitate the understanding of the description, the same constituent elements in the drawings will be denoted by the same reference numerals as much as possible, and redundant description will be omitted.

  The electronic control device 10 according to the present embodiment is configured as a control device (engine control ECU) for controlling the operation of the internal combustion engine 20 (engine) in the vehicle. For example, the electronic control unit 10 controls the opening / closing operation of an injector (not shown) in the internal combustion engine 20, that is, fuel injection, based on a signal from a crank angle sensor (not shown) provided in the internal combustion engine 20.

  In such control, some tasks processed by the electronic control device 10 are periodically processed in synchronization with a change in the phase of the rotation angle (crank angle) of the crankshaft. For example, the calculation for determining the fuel injection timing of the injector is processed every time the phase increases by 30 degrees. In the following description, a task processed in synchronization with the phase of the rotation angle as described above is referred to as a “synchronization task”.

  Prior to the description of the synchronization task processing by the electronic control device 10, the configuration of the electronic control device 10 will be described. The electronic control device 10 includes an input circuit 11, an output circuit 12, and a microcomputer 100.

  The input circuit 11 is a circuit serving as a communication interface for receiving various sensor signals from the internal combustion engine 20 to be controlled. The sensor signal includes a signal transmitted from the crank angle sensor, that is, a signal indicating the phase of the crank angle.

  The output circuit 12 is a circuit serving as a communication interface for outputting a drive signal for switching opening and closing of the injector to the internal combustion engine 20. Note that a drive signal for operating a device other than the injector (for example, a spark plug) may be transmitted from the output circuit 12 together with the drive signal.

  The microcomputer 100 is a microcomputer that constitutes a main part of the electronic control device 10. The microcomputer 100 includes a CPU 110, a ROM 120, a RAM 130, and an I / O 140.

  The CPU 110 is a central processing unit for performing calculations necessary for executing control, that is, task processing. The CPU 110 has three cores (C0, C1, and C2), and is a so-called multi-core processing device. That is, the microcomputer 100 is configured as a multi-core microcomputer.

  The ROM 120 is a read-only semiconductor memory. The ROM 120 stores a program executed by the CPU 110, various maps necessary for controlling the internal combustion engine 20, and the like.

  The RAM 130 is a rewritable semiconductor memory. The RAM 130 temporarily stores calculation results for control. In the present embodiment, a first storage unit 131 and a second storage unit 132 are secured as storage locations for information in the RAM 130. Information written and stored in the first storage unit 131 and information written and stored in the second storage unit 132 will be described later.

  The I / O 140 is an interface portion for communication between another ECU mounted on the vehicle and the microcomputer 100. The above communication via the I / O 140 is controlled by the CPU 110.

  The configuration of the electronic control device 10 as described above is the same as that of the conventional electronic control except that the first storage unit 131 and the second storage unit 132 are secured in the RAM 130.

  In controlling the operation of the internal combustion engine 20, the electronic control unit 10 performs various tasks in addition to the synchronization task described above. In the present embodiment, a plurality of tasks including a synchronization task are distributedly processed by the core C1 and the core C2.

  The core C0 controls the overall operation of the CPU 110. Specifically, tasks to be processed are assigned to each of the core C1 and the core C2. Note that such overall control may be performed in parallel with task processing by either the core C1 or the core C2 that performs task processing. In that case, a dedicated core for performing overall control is not required like the core C0 in the present embodiment.

  The task distribution is performed so that the processing loads of the core C1 and the core C2 are approximately equal. However, for example, when the rotational speed of the internal combustion engine 20 increases with a change in the running state of the vehicle, the processing load of one of the core C1 and the core C2 is increased due to an increase in the frequency of execution of some tasks. However, in some cases, the processing load becomes significantly larger than the other processing load.

  Such a bias in processing load is not preferable in view of effective utilization of the processing capacity of the CPU 110. Therefore, the CPU 110 is configured to dynamically switch the core that executes the processing of the synchronization task so that only the processing load in some cores does not become too large. For example, when the processing of the synchronization task is being performed by the core C1, if the processing load of the core C1 becomes too large, the core that executes the processing of the synchronization task is switched from the core C1 to the core C2.

  In the following description, the core that executes the processing of the synchronous task among the cores C1 and C2 is also referred to as a “synchronous task execution core”. The process performed by the core C0 to switch the synchronous task execution core is also referred to as “switching process”. As will be described later, the timing at which the core C0 performs the switching process and the timing at which the synchronous task execution core is actually switched do not necessarily match in this embodiment.

  Before describing specific modes of switching processing performed in the present embodiment and advantages thereof, modes of switching processing conventionally performed will be described. 10 to 13 are time charts showing the flow of switching processing executed by the electronic control device according to the comparative example (conventional example) of the present invention. The hardware configuration of the electronic control device is the same as that of the electronic control device 10 shown in FIG.

  This will be described with reference to FIG. FIG. 10 shows an example in which the switching process is executed at time t125 and the synchronous task execution core is switched from the core C1 to the core C2.

  The synchronization task is executed whenever the information transmitted from the crank angle sensor of the internal combustion engine 20 to the electronic control unit, that is, the phase of the rotation angle of the crankshaft (hereinafter referred to as “sensor phase”) changes by 30 degrees. Is done. Specifically, every time the sensor phase increases by 30 degrees, such as 60 degrees, 90 degrees, 120 degrees, and 150 degrees, the synchronization task is executed in the synchronization task execution core. The sensor phase returns to 0 degrees when it increases to 720 degrees, and increases again by 30 degrees as the internal combustion engine 20 operates.

  In the example of FIG. 10, the core C1 that is the synchronous task execution core before the time t125 starts the processing of the synchronous task at the time t110 after the sensor phase becomes 90 degrees. Note that the timing at which the sensor phase reaches 90 degrees does not necessarily coincide with the timing (time t110) at which the synchronization task processing is started. Such timing mismatch is due to the fact that the core C1 is also processing tasks other than the synchronous task, and the start timing of the synchronous task processing is slightly delayed. The time from when the sensor phase becomes 90 degrees to when the processing of the synchronous task is started varies depending on the processing load of the synchronous task execution core.

  Thereafter, the switching process is executed by the core C0 at a time t125 after the time t110. The synchronous task execution core is switched from the core C1 to the core C2. Thereafter, even if the sensor phase is increased by 30 degrees, the core C1 is in a state where the synchronous task is not processed (hereinafter, this state is referred to as “non-execution state”), and the core C2 has a sensor phase of 30. Each time it increases, a state in which a synchronous task is processed (hereinafter, this state is referred to as an “execution state”).

  When the sensor phase becomes 120 degrees after time t125, the core C1 is in a non-execution state. For this reason, the core C1 does not start the synchronous task processing. A time t130 shown in FIG. 10 is a time when the execution of the synchronous task corresponding to the sensor phase of 120 degrees is started, assuming that the core C1 is in the execution state.

  The core C2 is not a synchronous task execution core but is in a non-execution state before time t125. For this reason, even if the sensor phase is 90 degrees, the synchronization task processing is not started. A time t120 shown in FIG. 10 is a time at which the execution of the synchronous task corresponding to the sensor phase of 90 degrees is started in the core C2, assuming that the core C2 is in an execution state.

  As shown in the figure, time t110 and time t120 do not match each other. This is because the time from when the sensor phase becomes 90 degrees to when the processing of the synchronization task is started varies depending on the processing load of the cores C1 and C2. In the example of FIG. 10, an example is shown in which the time t120 at which the core C2 starts processing is later than the time t110 at which the core C1 starts processing. However, depending on the processing load of each of the core C1 and the core C2, these contexts may be interchanged.

  At time t125 after time t120, the core C0 performs the switching process. When the sensor phase becomes 120 degrees after time t125, the core C2 is in an execution state. For this reason, the core C2 starts the process of the synchronous task corresponding to the sensor phase of 120 degrees (time t140). In the example of FIG. 10, the time t140 is later than the time t130.

  As described above, when the switching process by the core C0 is executed at the time t125, the synchronization task corresponding to the sensor phase of 90 degrees is performed only by the core C1, and the synchronization task corresponding to the sensor phase of 120 degrees is the core C2. Only done. As a result, similarly to the case where the switching process is not performed, the control of the internal combustion engine 20 by the electronic control device 10 is normally performed.

  Another example will be described with reference to FIG. The example of FIG. 11 is different from the example of FIG. 10 in that the timing at which the switching process is performed is a time t135 after the time t130 and before the time t140.

  Also in this example, the process of the synchronization task corresponding to the sensor phase of 90 degrees is started at the core C1 (time t110) and is not started at the core C2 (time t120).

  At time t130, since the core C1 is a synchronous task execution core at this time and is in an execution state, the core C1 starts processing of the synchronous task corresponding to the sensor phase of 120 degrees. Thereafter, the switching process is performed at time t135, but since the core C1 has already performed the synchronization task process, the process is continued without being interrupted.

  At time t140 after time t135, the core C2 is switched to the synchronous task execution core at this time, and is in an execution state. For this reason, the core C2 starts the process of the synchronous task corresponding to the sensor phase of 120 degrees.

  As a result, the processing of the synchronization task corresponding to the sensor phase of 120 degrees is started in both the core C1 and the core C2. In this case, there is a possibility that some trouble may occur in the control of the internal combustion engine 20 because the drive signal is transmitted twice to the internal combustion engine 20.

  As described above, in the conventional electronic control apparatus, depending on the timing at which the switching process is performed, there may occur a case where the synchronization task is repeatedly processed by a plurality of cores. Hereinafter, such a phenomenon is also referred to as “duplication of processing”.

  Next, switching processing of the electronic control device according to the comparative example of the present invention will be described with reference to FIG. FIG. 12 shows an example in which the switching process is executed at time t126 and the synchronous task execution core is switched from the core C1 to the core C2.

  In FIG. 12, the time at which the processing of the synchronization task corresponding to the sensor phase of 90 degrees is started at the core C1 is shown as time t121. Further, when the core C2 is in the execution state, the time when the execution of the synchronous task corresponding to the sensor phase of 90 degrees is started at the core C2 is indicated as a time t111. In the example of FIG. 12, time t121 is later than time t111.

  Similarly, in FIG. 12, the time at which the processing of the synchronization task corresponding to the sensor phase of 120 degrees is started at the core C2 is shown as time t131. In addition, when the core C1 is in the execution state, the time when the execution of the synchronous task corresponding to the sensor phase of 120 degrees is started in the core C1 is indicated as a time t141. In the example of FIG. 12, time t141 is later than time t131.

  Prior to time t126, the core C1, which is a synchronous task execution core, starts synchronous task processing at time t121 after the sensor phase reaches 90 degrees. Thereafter, the switching process is executed by the core C0 at a time t126 after the time t121. The synchronous task execution core is switched from the core C1 to the core C2.

  When the sensor phase becomes 120 degrees after time t126, the core C1 is in a non-execution state. For this reason, at time t141, the core C1 does not start the process of the synchronization task.

  The core C2 is not a synchronous task execution core but is in a non-execution state before time t126. For this reason, even if the sensor phase becomes 90 degrees, the core C2 does not start the processing of the synchronization task.

  After the time t126 when the switching process is executed by the core C0, when the sensor phase becomes 120 degrees, the core C2 is in the execution state. For this reason, the core C2 starts processing of the synchronization task corresponding to the sensor phase of 120 degrees (time t131).

  As described above, when the switching process by the core C0 is executed at the time t126, the synchronization task corresponding to the sensor phase of 90 degrees is performed only by the core C1, and the synchronization task corresponding to the sensor phase of 120 degrees is the core C2. Only done. As a result, similarly to the case where the switching process is not performed, the control of the internal combustion engine 20 by the electronic control device 10 is normally performed.

  Another example will be described with reference to FIG. The example of FIG. 13 is different from the example of FIG. 12 in that the timing at which the switching process is performed is a time t136 after the time t131 and before the time t141.

  Also in this example, the processing of the synchronization task corresponding to the sensor phase of 90 degrees is started at the core C1 (time t121) and is not started at the core C2 (time t111).

  At time t131, since the core C2 is not yet a synchronous task execution core at this time and is in a non-execution state, the core C2 does not start the synchronous task processing corresponding to the sensor phase of 120 degrees.

  At time t141 after time t136, the core C1 is no longer a synchronous task execution core at this time, and is in a non-execution state. For this reason, the core C1 does not start the process of the synchronous task corresponding to the sensor phase of 120 degrees.

  As a result, the process of the synchronization task corresponding to the sensor phase of 120 degrees is not started in either the core C1 or the core C2. In this case, since a drive signal is not transmitted to the internal combustion engine 20, there is a possibility that some trouble may occur in the control of the internal combustion engine 20.

  As described above, in the conventional electronic control apparatus, a part of the synchronization task may not be processed depending on the timing at which the switching process is performed. Hereinafter, such a phenomenon is also referred to as “processing omission”.

  As described above, the process overlap and the process omission are that when the sensor phase becomes a specific phase, the timing at which the corresponding synchronous task process starts is different between the cores, and the switching process is performed. This is because the switching process is performed asynchronously with the start timing of the synchronous task and the like.

  The present invention makes it possible to perform a switching process while reliably preventing process overlap and process omission. An overview of the switching process in the present embodiment will be described with reference to FIGS.

  FIG. 2 is a time chart showing the flow of the switching process executed by the electronic control device 10. The state of the RAM 130 is schematically shown in the upper part of the time chart.

  The timing at which the synchronization task is executed in this embodiment is the same as the timing in the comparative example described with reference to FIGS. That is, also in the present embodiment, every time the sensor phase increases by 60 degrees, 90 degrees, 120 degrees, 150 degrees, or 30 degrees, the synchronous task is executed in the synchronous task execution core.

  FIG. 2 shows an example in which the switching process is executed at time t35 and the synchronous task execution core is switched from the core C1 to the core C2. Prior to time t35, the core C1, which is a synchronous task execution core, starts processing of the synchronous task at time t10 after the sensor phase reaches 90 degrees. The timing at which the sensor phase reaches 90 degrees does not necessarily coincide with the timing at which the synchronization task processing is started. The reason is as already described in the description of the comparative example.

  The first storage unit 131 of the RAM 130 stores a numerical value (core number) indicating a synchronous task execution core. In the case of the example in FIG. 2, “1”, which is a numerical value indicating the core C <b> 1, is stored in the first storage unit 131 in the period before time t <b> 35. In a period after the time t35, the first storage unit 131 stores “2” that is a numerical value indicating the core C2.

  When the sensor phase changes from 90 degrees to 120 degrees after time t10, the processing of the synchronization task corresponding to 120 degrees is started by the core C1 (time t30). In the example of FIG. 2, the time t35 when the switching process is performed is after the time t30 when the core C1 starts the process of the synchronization task.

  The switching process in the present embodiment is performed by the core C0 rewriting the core number stored in the first storage unit 131. For example, when the synchronous task execution core is changed from the core C1 to the core C2, the core number stored in the first storage unit 131 is rewritten from 1 to 2.

  Further, the core C0 rewrites the switching number stored in the second storage unit 132 at the same time as rewriting the core number stored in the first storage unit 131. The “switching phase” is a phase indicating the timing at which the state (execution state or non-execution state) of each core is to be switched. That is, the switching (change) of the synchronous task execution core is not performed at the time t35 when the switching process is executed, but the sensor phase matches the switching phase stored in the second storage unit 132. Sometimes done.

  In the example of FIG. 2, the core number stored in the first storage unit 131 is rewritten from 1 to 2 at time t <b> 35. Further, the value of the switching phase stored in the second storage unit 132 is rewritten to 150 degrees.

  In the present embodiment, each core (core C1, core C2) refers to the core number stored in the first storage unit 131 prior to performing the synchronization task processing. Further, the switching phase stored in the second storage unit 132 is also referred to.

  At this time, if the read core number is a numerical value indicating the core, the core is switched from the non-execution state to the execution state only when the sensor phase matches the switching phase. On the other hand, when the read core number is not a numerical value indicating the core, the core switches from the execution state to the non-execution state only when the sensor phase matches the switching phase.

  At time t30, the switching process by the core C0 has not yet been performed, and the core number stored in the first storage unit 131 remains at 1. For this reason, the core C1 remains in the execution state after the time t30, and starts the synchronous task processing at the time t30.

  Thereafter, the switching process is performed at time t35 and the core number of the first storage unit 131 is rewritten, but since the core C1 has already performed the synchronization task, the process continues without interruption. Is done.

  When the sensor phase becomes 150 degrees after time t35, the core C1 refers again to the core number of the first storage unit 131 and the switching phase of the second storage unit 132 (time t50). At time t50, the core number stored in the first storage unit 131 is 2, which does not match the numerical value (1) indicating the core C1.

  Further, the switching phase of the second storage unit 132 is 150 degrees, which matches the sensor phase at time t50. For this reason, the core C1 switches from the execution state to the non-execution state at time t50, and does not start the synchronous task processing at time t50.

  The core C2 is not a synchronous task execution core but is in a non-execution state before time t35. For this reason, even if the sensor phase is 90 degrees, the synchronization task processing is not started. In FIG. 2, when the core C2 is in an execution state, the time when the execution of the synchronous task corresponding to the sensor phase of 90 degrees is started in the core C2 is shown as time t20.

  At time t35 after time t20, the switching process is executed by the core C0. When the sensor phase reaches 120 degrees, the core C2 refers to the core number of the first storage unit 131 and the switching phase stored in the second storage unit 132 (time t40). In the example of FIG. 2, the time t40 is after the time t35 when the switching process is executed.

  At time t40, the core number stored in the first storage unit 131 is 2, which matches the number corresponding to the core C2. However, the switching phase stored in the second storage unit 132 is 150 degrees and does not coincide with the sensor phase (120 degrees) at time t40. For this reason, the core C2 does not switch to the execution state at time t40, and remains in the non-execution state after time t40. For this reason, even if the sensor phase becomes 120 degrees, the synchronous task processing is not started at time t40.

  When the sensor phase becomes 150 degrees after time t40, the core C2 refers to the core number of the first storage unit 131 and the switching phase stored in the second storage unit 132 again (time t60). At time t60, the core number stored in the first storage unit 131 is 2, which matches the numerical value (2) indicating the core C2. Further, the switching phase stored in the second storage unit 132 is 150 degrees, which coincides with the sensor phase (150) at time t60. For this reason, the core C2 switches from the non-execution state to the execution state at time t60, and starts synchronous task processing at time t60.

  In the example shown in FIG. 2, the time t30 when the core C1 starts processing of the synchronization task corresponding to the phase of 120 degrees, the time t40 when the core C2 starts the processing of the synchronization task corresponding to the phase of 120 degrees, Switching processing is executed at time t35, which is between. That is, the switching process is executed at the same timing as in the comparative example described with reference to FIG.

  However, in the present embodiment, there is no duplication of processing as in the case of FIG. 11, and the processing of the synchronization task corresponding to 120 degrees is started only in the core C1.

  FIG. 3 is also a time chart showing the flow of switching processing executed by the electronic control device 10. As in the case of FIG. 2, the state of the RAM 130 is schematically shown in the upper part of the time chart.

  FIG. 3 shows an example in which the switching process is executed at time t16 and the synchronous task execution core is switched from the core C1 to the core C2. At time t16, the core number stored in the first storage unit 131 is rewritten from 1 to 2. The switching phase stored in the second storage unit 132 is rewritten to 120 degrees.

  In FIG. 3, the time at which the processing of the synchronous task corresponding to the sensor phase of 90 degrees is started at the core C1 is shown as time t21. Further, when the core C2 is in the execution state, the time when the execution of the synchronous task corresponding to the sensor phase of 90 degrees is started in the core C2 is indicated as time t11. In the example of FIG. 3, the time t21 is a time later than the time t11. The time t16 when the switching process is executed is after the time t11 and before the time t21.

  Similarly, in FIG. 3, the time at which the processing of the synchronization task corresponding to the sensor phase of 120 degrees is started at the core C2 is shown as time t31. Further, when the core C1 is in the execution state, the time when the execution of the synchronous task corresponding to the sensor phase of 120 degrees is started in the core C1 is indicated as time t41. In the example of FIG. 3, time t41 is later than time t31.

  When the sensor phase reaches 90 degrees, the core C1 refers to the core number of the first storage unit 131 and the switching phase stored in the second storage unit 132 (time t21).

  At time t21, the core number stored in the first storage unit 131 is 2, and does not match the number corresponding to the core C1. For this reason, the core C1 will no longer be a synchronous task execution core, and will switch from an execution state to a non-execution state.

  However, at this time, the switching phase stored in the second storage unit 132 is 120 degrees, which does not coincide with the sensor phase (90 degrees) at time t21. For this reason, the core C1 does not yet switch to the non-execution state at the time t21 and continues to be in the execution state. For this reason, at time t21 when the sensor phase is 90 degrees, the core C1 starts processing of the synchronization task.

  When the sensor phase reaches 120 degrees after time t21, the core C1 refers to the core number of the first storage unit 131 and the switching phase of the second storage unit 132 again (time t41). At time t41, the core number stored in the first storage unit 131 is 2, which does not match the numerical value (1) indicating the core C1.

  Further, the switching phase of the second storage unit 132 is 120 degrees, which coincides with the sensor phase at time t41. For this reason, the core C1 switches from the execution state to the non-execution state at time t41, and does not start the synchronous task processing at time t41.

  At time t11, the core C2 refers to the core number of the first storage unit 131 and the switching phase stored in the second storage unit 132. At time t11, the core number stored in the first storage unit 131 is 1, and does not match the numerical value (2) indicating the core C2. For this reason, the core C2 that has been in the non-execution state until then remains in the non-execution state even after time t11. The core C2 does not start the synchronization task processing at time t11.

  When the sensor phase reaches 120 degrees, the core C2 refers again to the core number of the first storage unit 131 and the switching phase stored in the second storage unit 132 (time t31). At time t31, the core number stored in the first storage unit 131 is 2, which matches the numerical value (2) indicating the core C2.

  Further, the switching phase of the second storage unit 132 is 120 degrees, which coincides with the sensor phase at time t31. For this reason, the core C2 switches from the non-execution state to the execution state, and starts processing of the synchronous task at time t31.

  In the example shown in FIG. 3, the time t11 at which the core C2 starts the processing of the synchronization task corresponding to the phase of 90 degrees, the time t21 at which the core C1 starts the processing of the synchronization task corresponding to the phase of 90 degrees, The switching process is executed at time t16 between the two. That is, the switching process is executed at the same timing as in the comparative example described with reference to FIG.

  However, in the present embodiment, the processing omission as in the case of FIG. 13 does not occur, and the processing of the synchronization task corresponding to 90 degrees is started in the core C1.

  With reference to FIG. 4, the specific content of the process performed in the electronic control apparatus 10 is demonstrated. A series of processes shown in FIG. 4 is repeatedly executed in the core C0 of the microcomputer 100 every time a predetermined period elapses. The process may be executed in parallel with the process such as the synchronization task in either the core C1 or the core C2.

  In the first step S01, the necessity of the switching process is determined. That is, it is determined whether or not the processing load is uneven in the core C1 and the core C2. The determination will be described with reference to FIG.

  FIG. 5 shows an example of the processing load of one core (core C1 or the like) when 20 control of the internal combustion engine is performed by the electronic control unit 10. Specifically, the time PT1 when processing other than the synchronization task is performed, the time PT2 when processing of the synchronization task is performed, and the free time DT where no processing is performed occupy each time in a predetermined time. An example ratio is shown.

  In the example of FIG. 5A, the sum of the time PT1 and the time PT2, that is, the total time during which some processing is performed in the core is relatively short, and the ratio of the time in the predetermined time is a threshold value. It is less than TH. In other words, the processing load of the core is relatively small, and the core is in a state where there is room to perform additional processing.

  On the other hand, in the example of FIG. 5B, the sum of the time PT1 and the time PT2 exceeds the threshold value TH. That is, the processing load of the core is relatively large, and the core is in a state close to the limit of processing capacity.

  Returning to FIG. 4, the description will be continued. In step S01, it is determined that the switching process is necessary only when the ratio of the sum of the time PT1 and the time PT2 to the predetermined time exceeds the threshold value TH. In other words, it is determined that the switching process is necessary only when the ratio of the idle time DT in the predetermined period falls below a threshold value (a value obtained by subtracting the threshold value TH from 100%).

  On the other hand, when the ratio of the sum of the time PT1 and the time PT2 in the predetermined time does not exceed the threshold value TH, it is determined that the switching process is unnecessary. In other words, when the ratio of the free time DT in the predetermined period does not fall below the threshold value (a value obtained by subtracting the threshold value TH from 100%), it is determined that the switching process is unnecessary.

  If it is determined in step S01 that the switching process is not necessary, the series of processes shown in FIG. 4 is terminated. On the other hand, when it is determined that the switching process is necessary, the process proceeds to step S02. In step S02, the core number (execution core number) of the core that executes the synchronization task after the switching process is determined.

  A method for determining a new execution core number after the switching process will be described with reference to FIGS. 6 and 7 show examples of the processing loads of the core C1 and the core C2 when 20 control of the internal combustion engine is performed by the electronic control unit 10. FIG. 6 and 7, as in FIG. 5, each of the time PT1 when processing other than the synchronization task is performed, the time PT2 when processing of the synchronization task is performed, and the free time DT where no processing is performed. The example of the ratio which each time occupies in predetermined time is shown in figure.

  6 and 7, the core C1 is a synchronous task execution core. For this reason, time PT1, time PT2, and idle time DT exist for the core C1. On the other hand, since the core C2 is not a synchronous task execution core, there is no time PT2 when the processing of the synchronous task is performed for the core C2.

  Here, the sum of the time PT2 and the idle time DT per the predetermined time is defined as “total time”. The total time T1 for the core C1 is the sum of the time PT2 and the free time DT. On the other hand, the total time T2 for the core C2 is the same as the idle time DT (since there is no time PT2). In the example of FIG. 6, the total time T2 in the core C2 is longer than the total time T1 in the core C1.

  Returning to FIG. 4, the description will be continued. In step S02, after calculating the total time (T1, T2) in each of the cores (C1, C2), the core number indicating the core (core C2 in the example of FIG. 6) corresponding to the longest of them is obtained. , A new execution core number.

  That is, the new execution core number is determined such that the free time DT of the synchronous task execution core after the switching process is longer than the free time DT of the synchronous task execution core before the switching process.

  If the total time T1 is longer than the total time T2 as in the example shown in FIG. 7, the core corresponding to the longest total time is the core C1 that is a synchronous task execution core. become. In this case, the execution core number remains unchanged at 1. As described above, when the execution core number changes, the execution core number does not change when the idle time DT of the synchronous task execution core becomes short.

  In step S03 following step S02, it is determined whether or not the execution core number changes. That is, it is determined whether or not the execution core number determined in step S02 is different from the core number of the synchronous task execution core before the switching process is performed.

  If the execution core number does not change, it means that the switching process is unnecessary, and thus the series of processes shown in FIG. 4 is terminated. When the execution core number changes, the process proceeds to step S04.

  In step S04, the switching phase is determined. The switching phase is determined based on the phase at the time when the processing of FIG. 4 is performed. Specifically, the phase (120 degrees in this case) in which the rotation synchronization task is executed next to the sensor phase (for example, 90 degrees) at the time point is determined as the switching phase.

As an example of an equation for determining the switching phase (Pn) as described above, the following equation (1) is given.
Pn = ((((Pc / 30) +1)% 24) × 30 (1)
In the above equation (1), Pc is the current sensor phase. “/” Is an operator for calculating a quotient, and “%” is an operator for calculating a remainder.

  Note that the method for determining the switching phase is not limited to the above. For example, the phase (in this case, 150 degrees) in which the rotation synchronization task is executed next to the sensor phase (for example, 90 degrees) at the current time may be determined as the switching phase.

  In step S05 following step S04, the switching phase determined in step S04 is written in the second storage unit 132. In step S06 following step S05, the execution core number determined in step S02 is written into the first storage unit 131.

  The flow of processing executed by the core C1 and the core C2 will be described with reference to FIG. The process shown in FIG. 8 is repeatedly executed every time the sensor phase changes by 30 degrees in each of the core C1 and the core C2. Note that the timing at which the sensor phase changes by 30 degrees (the timing at which the sensor phase becomes 90 degrees, etc.) does not necessarily coincide with the timing at which the processing of FIG. 8 is started. The reason is as already described in the description of the comparative example.

  In the first step S11, the core number (execution core number) stored in the first storage unit 131 is read. In the subsequent step S12, the switching phase stored in the second storage unit 132 is read out.

  In step S13 following step S12, the future state (execution state or non-execution state) is determined based on the read execution core number and switching phase and the current core state (execution state or non-execution state). Determine and switch.

  As already described, in this embodiment, when the execution core number of the first storage unit 131 is a numerical value indicating the core, the core has the sensor phase as the switching phase of the second storage unit 132. Only when they match, the non-execution state switches to the execution state. On the other hand, when the core number of the first storage unit 131 is not a numerical value indicating the core, the core is changed from the execution state to the non-execution state only when the sensor phase matches the switching phase of the second storage unit 132. Switch to.

  A specific determination method in step S13 for performing state switching as described above will be described with reference to FIG. FIG. 9 is a state transition diagram for each of the core C1 and the core C2.

  A description will be given taking the core C1 as an example. For example, the core C1 is in the execution state (ST1) in the initial state before the first switching process is performed as before the time t16 in FIG.

  At the timing when the sensor phase changes and the synchronization task is to be executed, the core C1 in the execution state determines whether or not the following condition B is satisfied.

  Condition B is that the read execution core number does not match the core number indicating the core (in this example, core C1), and the read switching phase is the same as the current sensor phase. What you are doing.

  Only when the condition B is satisfied, the core C1 switches from the execution state (ST1) to the non-execution state (ST2). For example, at time t21 in FIG. 3, the read execution core number (2) does not match the core number (1) indicating the core C1, and therefore satisfies the first half of the condition B. However, since the read switching phase (120) does not match the sensor phase (90 degrees) at time t21, the latter half of the condition B is not satisfied. For this reason, at the time t21, the execution state (ST1) is not switched to the non-execution state (ST2).

  After the core C1 enters the non-execution state, the core C1 determines whether or not the following condition A is satisfied when it is time to execute the synchronization task again.

  Condition A is that the read execution core number matches the core number indicating the core (core C1 in this example), and the read switching phase matches the current sensor phase. It is that.

  The core C1 switches from the non-execution state (ST2) to the execution state (ST1) only when such a condition A is satisfied.

  The same applies to the core C2. For example, the core C2 is in the non-execution state (ST2) in the initial state before the first switching process is performed as before the time t35 in FIG.

  At the timing when the sensor phase changes and the synchronization task is to be executed, the core C2 that is in the non-execution state determines whether or not the above condition A is satisfied. The core C2 switches from the non-execution state (ST2) to the execution state (ST1) only when the condition A is satisfied. For example, at time t40 in FIG. 2, the read execution core number (2) matches the core number (2) indicating the core C2, so the first half of the condition A is satisfied. However, since the read switching phase (150) does not coincide with the sensor phase (120 degrees) at time t40, the latter half of the condition A is not satisfied. For this reason, at time t40, the non-execution state (ST2) is not switched to the execution state (ST1).

  After the core C2 enters the non-execution state, when it is time to execute the synchronization task again, the core C2 determines whether the condition B is satisfied. The core C2 switches from the execution state (ST1) to the non-execution state (ST2) only when the condition B is satisfied.

  Returning to FIG. In step S14 following step S13, it is determined whether or not the cell is in an execution state as a result of step S13. If it is in the execution state, the synchronous task is executed (step S15). If not in the execution state, the process shown in FIG. 8 is terminated without executing the synchronization task.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the present invention as long as they have the characteristics of the present invention. For example, the elements included in each of the specific examples described above and their arrangement, materials, conditions, shapes, sizes, and the like are not limited to those illustrated, but can be changed as appropriate. Moreover, each element with which each embodiment mentioned above is provided can be combined as long as technically possible, and the combination of these is also included in the scope of the present invention as long as it includes the features of the present invention.

10: Electronic control unit 11: Input circuit 12: Output circuit 20: Internal combustion engine 100: Microcomputer C0, C1, C2: Core 131: First storage unit 132: Second storage unit

Claims (9)

An electronic control device (10) comprising a multi-core microcomputer (100) equipped with a plurality of cores (C0, C1, C2), and executing a task in synchronization with the phase of the rotation angle in the core,
A first storage unit (131) for storing a core number indicating a task execution core for executing the task;
A second storage unit (132) for storing a switching phase indicating a phase when the task execution core is switched,
The electronic control device, wherein the task execution core is switched based on the core number stored in the first storage unit and the switching phase stored in the second storage unit. Each said core is
When the core number stored in the first storage unit indicates the core,
The electronic control device according to claim 1, wherein the electronic control device is configured to switch to the task execution core when the phase becomes the switching phase stored in the second storage unit.   The electronic control device according to claim 2, wherein the switching phase stored in the second storage unit is determined based on a phase at a time when the switching phase is determined. .   The electronic control device according to claim 3, wherein the switching phase stored in the second storage unit is a phase after the phase at which the switching phase is determined.   The switching phase stored in the second storage unit is a phase in which the task is executed next to a phase at a time when the switching phase is determined. Electronic control unit.   The electronic control according to claim 1, wherein the core number stored in the first storage unit is determined based on an arithmetic processing load of each of the cores at a predetermined time. apparatus. The task execution core switching is as follows.
The electronic control device according to claim 6, wherein the electronic control device is performed only when the total idle time of processing of the task execution core in the predetermined time is below a threshold value. The calculation processing load in each of the cores is
Of the predetermined time, a first time that is a total time for the task to be executed in the core;
The electronic control device according to claim 6, wherein the electronic control device is calculated based on a second time that is a total of idle times of processing of the core among the predetermined time. The performance of each of the cores is the same as each other,
The sum of the first time and the second time calculated for the task execution core;
Comparing the second time calculated for the core other than the task execution core,
The electronic control device according to claim 8, wherein the core number indicating the core corresponding to the longest of these is stored in the first storage unit.

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