JP7226064B2 - electronic controller - Google Patents

Description

The present invention relates to electronic control units.

An electronic control device equipped with a microcomputer with multiple cores (hereinafter referred to as a microcomputer) may execute control with high reproducibility, and such a microcomputer often adopts the AMP type architecture. ing.

JP 2014-78078 A JP 2018-067135 A

Since the AMP-type architecture is executed according to the control assigned to each core in advance by the designer, it is necessary to predict the processing load in advance and to appropriately assign the control.
However, in an electronic control unit having a complicated control system such as engine control, the processing load fluctuates depending on the operating state of the engine. In addition, when the processing load varies depending on the core, it is necessary to select the performance of the microcomputer according to the core with the high processing load, which also affects the cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electronic control device capable of reducing variations in processing loads caused by a plurality of cores and increasing the processing performance of a microcomputer.

According to the first aspect of the invention, the plurality of cores execute assigned core-fixed control and at the same time, assigned core-variable control corresponding to the operating state of the controlled object.

A block diagram showing the configuration of an engine ECU in the first embodiment. Diagram showing the control state corresponding to the operating state Diagram showing the control state of a typical area (part 1) Diagram showing the control state of a typical area (Part 2) Flowchart showing core pinning control Flowchart showing core variable control by core A Flowchart showing core variable control by cores B to N A diagram showing control states corresponding to operating states in the second embodiment. A diagram showing control states corresponding to operation states in the third embodiment.

A plurality of embodiments will be described below with reference to the drawings. In several embodiments, functionally or structurally corresponding parts are given the same reference numerals.
(First embodiment)
A first embodiment applied to an engine ECU will be described with reference to FIGS. 1 to 7. FIG.
An engine ECU 1 (corresponding to an electronic control unit) shown in FIG. An input circuit 3 receives detection signals from sensors required for engine control. The output circuit 4 outputs drive signals to various actuators for engine control. The communication circuit 5 is connected to other ECUs by an in-vehicle network using CAN as a communication protocol, for example. CAN is a registered trademark.

The microcomputer 2 includes a plurality of cores A to N, a ROM 6 (corresponding to a storage unit) storing programs, a RAM 7 for storing work data, and an I/O 8 communicating with the communication circuit 5 .
The ROM 6 stores a program for executing a plurality of core fixed control and a plurality of core variable control as a program. Core fixed control is control with a high degree of reproducibility, and employs an AMP-type architecture in which cores to be assigned are defined. The number of core fixing controls corresponding to each core A to N is stored in the ROM 6 .

Core variable control is a control in which the importance of reproducibility is low, and the assigned core is not specified, but the assigned core corresponds to the operating state (equivalent to the operating state) of the engine (equivalent to the controlled object). A defined AMP type architecture is adopted. In other words, although core variable control is not strictly an AMP type architecture, it can be said that it is an AMP type architecture under the condition that the operating state of the engine is the same. The core variable control is stored in the ROM 6 by the number corresponding to the design specifications.

The operating state of the engine is, for example, engine speed, engine load factor, engine coolant temperature, and the like. In the core variable control, the designer defines the cores to be allocated according to the operating state of the engine so that the processing load of each core A to N is leveled.

A procedure for allocating core variable control to each core A to N based on the operating state of the engine will be described below. First, the operating state of the engine will be explained. As shown in FIG. 2, the operating state of the engine is represented by two-dimensional coordinates with the engine speed on the x-axis and the engine load factor on the y-axis. It is divided into multiple areas. In this embodiment, two thresholds are set on the x-axis and the y-axis to divide the driving state into nine regions 1-1, 1-2, 1-3 . . . 3-3. However, by setting at least one threshold value for each coordinate axis, it may be divided into four or more.

Tasks executed by fixed core control include injection control, ignition control, A/F (Air/fuel ratio) control, KCS (Knock Control System) control, electronic throttle control, supercharging control, and ISC (Idle Speed Control) control. , cruise control, OBD (On-board diagnostics) control, etc., but not limited to these.
Tasks executed by the core variable control include, but are not limited to, air conditioner control, engine water temperature control, immobilizer control, G sensor control, charging control, and the like.

The engine water temperature control is control for driving the fan and switching the switching valve of the engine water passage in order to appropriately control the engine water temperature. Air conditioner control is control to stop the compressor of the air conditioner, which is a load on the engine, when the driver performs an operation to accelerate the vehicle.

Now, when the driver turns on the ignition switch, power is supplied to the engine ECU 1 from the battery, and each core A to N is activated.
When activated, each core A to N reads the core fixing control shown in FIG. 5 from the ROM 6 and executes it. In this core fixed control, each core A to N executes the assigned fixed control (S101).

Further, each of the cores A to N, when activated, reads the core variable control from the ROM 6 and executes it. In this case, core A (corresponding to a specific core) and cores B to N have different core variable control operations. That is, in the core variable control shown in FIG. 6, the core A judges the area (S201), notifies the other cores B to N of the area (S202), and then performs the core variable control assigned based on the area. (S203).

On the other hand, in the core variable control shown in FIG. 7, the cores B to N determine whether the area has been notified from the core A (S301: NO), and if notified (S301: YES), based on the area The assigned core variable control is executed (S302).

As described above, each of the cores A to N executes the assigned core fixed control and at the same time performs the assigned core variable control based on the operating state of the engine.
Note that core variable control may not be assigned to cores A to N in some areas, and cores to which core variable control is not assigned will not execute core variable control.

The fixed core control and the variable core control will be specifically described. An example in which the microcomputer 2 is provided with four cores A to D will be described, but the number of cores is not limited to four, and any number of cores may be provided.

The core fixing control executed by cores A to N is set as follows. Core A executes assigned ISC control, electronic throttle control, and supercharging control. Core B executes assigned KCS control and ignition control. Core C executes assigned injection control and A/F control. Core D executes assigned cruise control control and OBD control.

As shown in FIG. 3, the processing load due to the core fixing control by each core A to D varies depending on the operating state of the engine. For example, the supercharging control executed by the core A controls the closing force of the wastegate valve in a region where the engine load is high, and executes control to realize the required driving force. Therefore, the supercharging control in the region 3-3 has a larger processing load than in the case of the region 1-1.

In this way, since the processing load of core fixed control executed by cores A to D differs depending on the area, the processing load is leveled when each core A to D executes core variable control in addition to core fixed control. A core variable control assigned to each core A to D corresponding to the area is stipulated.

Regions 1-1 and 3-3 partitioned corresponding to the engine speed and the engine load factor will be described below as representative regions. The core fixed control and the core variable control corresponding to these regions 1-1 and 3-3 are only exemplified for explanation, and may differ from the actual ones.

In area 1-1 shown in FIG. 3, the processing load on core A is the largest, and the processing load on core B is the smallest. Therefore, core variable control is not assigned to core A, heat management control and air conditioner control are assigned to core B, immobilizer control is assigned to core C, and G sensor control and charging control are assigned to core D. equalizes the processing load of each core A to D.

In area 3-3 shown in FIG. 4, the processing load on core B is the largest and the processing load on core C is the smallest. Therefore, as core variable control, air conditioner control and heat management control are assigned to core A, core variable control is not assigned to core B, immobilizer control and G sensor control are assigned to core C, and charging control is assigned to core D. equalizes the processing load of each core A to D.
Similarly, by assigning core variable control to each core AD corresponding to each area, the processing load of each core AD is leveled.

According to such an embodiment, the following effects can be obtained.
Each core A to D executes assigned core fixed control and at the same time, assigned core variable control corresponding to the operating state of the engine. The processing loads of cores A to D can be leveled.

The core A determines the operating state of the engine and notifies the other cores B to D of the determination result, and the other cores B to D are allocated core variables based on the determination results notified from the core A. Since control is executed, the processing load on the other cores B to D can be reduced.

Since the operating state of the engine is divided into a plurality of regions by setting two threshold values on the coordinate axes of the two-dimensional coordinates represented by the two parameters, each core Core variable control can be appropriately assigned to AD.

(Second embodiment)
A second embodiment will be described with reference to FIG. This second embodiment is characterized in that the operating state of the engine is represented by three-dimensional coordinates.
As shown in FIG. 8, the operating state of the engine is represented by three-dimensional coordinates with the engine speed on the x-axis, the engine load factor on the y-axis, and the engine water temperature on the z-axis. By setting one threshold on the axis, it is divided into eight regions 1-1-1, 1-1-2, 1-2-1, .

As in the first embodiment, core fixed control assigned to each core A to D is defined, and core variable control to be assigned to each core A to D corresponding to the area is also defined. The core variable control assigned to each core AD is defined so that the processing load of each core AD is leveled.
Each of the cores A to D executes assigned core fixed control and at the same time, assigned core variable control corresponding to the operating state of the engine.

According to this embodiment, since the operating state of the engine is divided into a plurality of areas by three-dimensional coordinates represented by three parameters, it is possible to divide the operating state of the engine into more detailed areas. can.

(Third embodiment)
A third embodiment will be described with reference to FIG. This third embodiment is characterized in that the regions are divided according to the operating state of the engine.
As shown in FIG. 9, when the throttle opening of the accelerator is less than 1 degree, the region A is the idling ON state, and when the throttle opening is 1 degree or more, the region B is the idling OFF state.
Each of the cores A to D executes the allocated core fixed control, and at the same time, executes the core variable control allocated corresponding to the region corresponding to the throttle opening, as in the above embodiments.

According to such an embodiment, since the areas are divided corresponding to the operating states of the engine, the core variable control can be assigned to each of the cores A to D based on the operating state of the engine instead of the operating state of the engine. It is possible to expand the scope of application.

(Other embodiments)
A dedicated core may be provided for determining the operating state of the engine and notifying the other cores of the determination result.
Each core may determine the operating state of the engine and execute the corresponding core variable control based on the determination result.

The operating state of the engine may be divided into areas that combine the operating state of the engine described in the first and second embodiments and the operation state described in the third embodiment.
The present invention may be applied to a microcomputer that controls the operational states of various controlled objects without being limited to the operational states of the engine.

Although the present disclosure has been described with reference to embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

In the drawings, 1 is an engine ECU (electronic control unit), 2 is a microcomputer, 6 is a ROM (storage unit), A is a core (specific core), and B to N are cores.

Claims (4)

An electronic control device equipped with a microcomputer (2),
The microcomputer
a storage unit (6) storing a program for executing a plurality of fixed core controls and a plurality of variable core controls;
a plurality of cores that execute the allocated core fixed control and at the same time execute the core variable control allocated corresponding to the operating state of a controlled object divided into a plurality of areas ;
with
The core variable control assigned to each core corresponding to the region is defined so that the processing load when each core executes the core variable control in addition to the core fixed control is leveled,
a specific core among the plurality of cores determines an area corresponding to the operating state of the control target, and notifies the cores other than the specific core of the determination result;
An electronic control device in which the cores other than the specific core execute the core variable control assigned based on the determination result notified from the specific core. 2. The electronic control device according to claim 1, wherein the operating state of the controlled object is represented by coordinate axes, and is partitioned into a plurality of areas by setting at least one threshold on the coordinate axes. 3. The electronic control device according to claim 1 , wherein said areas are partitioned corresponding to operation states of said control object . The core fixation control is a control with high importance of reproducibility,
The electronic control unit according to any one of claims 1 to 3 , wherein the core variable control is control with low reproducibility .

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