JP2009093344A - Microcomputer, method of using the same, and electronic control unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute certain programs while prohibiting interrupt without increasing a processing load on a CPU and the volume of the programs. <P>SOLUTION: In a microcomputer 3 mounted on an onboard electronic control unit (ECU) 1, an interrupt mask determination part 17 monitors the address of a program executed by the CPU 5 to determine whether or not the address value is within a specific address range shown by information in an address range register 17a, and if determining that it is within the address range, outputs an interrupt mask signal to an interrupt controller 11. An AND circuit 11c in the interrupt controller 11 then prohibits an interrupt request signal to be output to the CPU 5. The microcomputer 3 executes the programs while prohibiting interrupt only by storing the programs in the specific address range in memories 7 and 9. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a microcomputer and an electronic control device including the microcomputer.

  Conventionally, in a microcomputer, as a method for prohibiting an interrupt during execution of a program, a process for prohibiting an interrupt is performed at the head of the program (that is, a program to be executed in an interrupt disabled state). Thus, a programming method is used in which processing for canceling the prohibition of interrupt is performed at the end of the program.

Further, Patent Document 1 compares an address accessed by a program being executed with an address of an access permission area set in the program area setting register for the program, and the address being accessed is an access permission area. It is described that if the address is outside, the CPU is interrupted to notify the unauthorized access.
JP-A-8-272625

  When the above-described conventional programming method is implemented, there is a problem that the CPU needs to execute processing for interrupt prohibition / inhibition cancellation at the beginning and end of the program, respectively, which increases the processing load on the CPU. In particular, when a program that is desired to be executed in an interrupt disabled state is a subroutine that is frequently called, the processing load on the CPU is further increased.

  Further, in the above conventional programming method, since the program capacity (the amount of data constituting the program) increases, the capacity of the memory for storing the program increases, and as a result, the electronic control device equipped with the microcomputer is increased. This will increase the cost.

On the other hand, the technique described in Patent Document 1 cannot solve such a problem.
Therefore, an object of the present invention is to realize that a certain program is executed in an interrupt disabled state without increasing the processing load and program capacity of the CPU.

  In the microcomputer according to claim 1 (hereinafter also referred to as a microcomputer), the CPU executes a program stored in the memory. In particular, interrupt limiting means is provided, and the interrupt limiting means determines whether the address of a program executed by the CPU (hereinafter referred to as an execution address) is within a specific address range on the memory. If it is determined that the execution address is within the specific address range, the CPU is prevented from accepting an interrupt.

  According to this microcomputer, if the program to be executed in the interrupt disabled state is stored in the specific address range of the memory among the programs to be executed by the CPU, the program is interrupted. Can be executed in prohibited state. This is because when the program is executed, the interrupt restriction means prevents the CPU from accepting the interrupt (ie, does not execute the interrupt process).

  Therefore, it is possible to omit the processing for interrupt prohibition and prohibition cancellation by the program, and the processing load and program capacity of the CPU can be reduced. For this reason, the capacity of the memory can also be reduced.

  According to a second aspect of the present invention, in the microcomputer according to the first aspect, the interrupt limiting means monitors the address value output to the address bus between the CPU and the memory when the instruction is fetched. By determining whether the address value is within the specific address range, it is determined whether the execution address is within the specific address range.

  According to this configuration, a part of the interrupt limiting unit that determines whether or not the execution address is within the specific address range (hereinafter referred to as a determination function part) can be configured outside the CPU. It is easy to add or delete judgment function parts.

  Next, in the microcomputer according to claim 3, in the microcomputer according to claims 1 and 2, the interrupt restricting means prevents the interrupt controller provided outside the CPU from outputting an interrupt request signal to the CPU. The CPU does not accept interrupts.

  According to this configuration, a portion of the interrupt limiting means for preventing the CPU from accepting an interrupt (hereinafter referred to as an interrupt disable function portion) can be configured outside the CPU. It is easy to add or delete parts.

  According to a fourth aspect of the present invention, in the microcomputer according to the first to third aspects, an address range setting register in which information indicating the address range on the memory is written by the CPU is provided. The interrupt restricting means handles the address range indicated by the information in the address range setting register as the specific address range. That is, the interrupt restricting means determines whether or not the execution address is within a specific address range indicated by the information in the address range setting register.

  Therefore, the specific address range can be arbitrarily set depending on the contents written to the address range setting register. Therefore, according to this microcomputer, the specific address range can be set according to the size of the program to be executed in the interrupt disabled state, and high versatility can be obtained.

  Next, in the microcomputer according to claim 5, in the microcomputer according to claims 1 to 4, when the CPU executes a state holding instruction for holding the operation state of the interrupt limiting means, the operation state is held by the state holding instruction. Until the CPU executes a release instruction for canceling the state, the interrupt limiting means holds the operation state that is in effect when the state holding instruction is executed. Note that the operating state of the interrupt limiting means is either an operating state in which the CPU does not accept interrupts or an operating state in which the CPU can accept interrupts.

  According to such a microcomputer of claim 5, when the program Pb outside the specific address range is called from the program Pa within the specific address range and the program Pb is executed, the interrupt disabled state is maintained as necessary. You can make it.

  For example, when a subroutine program Pb outside the specific address range is called from another program Pc outside the specific address range, interrupts are not prohibited, but when the subroutine program Pb is called from a program Pa within the specific address range. In some cases, it is desired to continue the interrupt disabled state, that is, to perform processing while taking over the state of the caller. In order to realize this, the state holding instruction is executed when the subroutine program Pb outside the specific address range is called from the program Pa within the specific address range. The program Pa may be created so that the instructions are executed.

  On the other hand, an electronic control device according to a seventh aspect is an electronic control device to which the usage method according to the sixth aspect is applied. That is, an electronic control device according to a seventh aspect is an electronic control device that includes the microcomputer according to any one of the first to fifth aspects, and performs processing for controlling a control target by the microcomputer, and the CPU is used to control the control target. Among the programs to be executed, a program executed in the interrupt disabled state is stored in the specific address range of the memory.

  According to this electronic control device, the required memory capacity can be suppressed by reducing the program capacity, and an increase in cost can be prevented. Further, since the processing load on the CPU is reduced, control performance can be improved.

  Next, in the microcomputer according to the eighth aspect, the CPU executes a program stored in the memory. Also provided is a mask level storing means for storing an interrupt mask level and an interrupt controller. When an interrupt request signal having a priority level higher than the interrupt mask level in the mask level storage means is generated, the interrupt controller causes the CPU to accept the interrupt (that is, to execute an interrupt process corresponding to the interrupt). However, even if an interrupt request signal whose priority level is lower than or equal to the interrupt mask level in the mask level storage means is generated, the interrupt is not accepted by the CPU (that is, the interrupt processing corresponding to the interrupt is not executed). ). Therefore, an interrupt whose priority level is equal to or lower than the interrupt mask level in the mask level storage means is masked (prohibited) without being activated.

In particular, the microcomputer of claim 8 is provided with the following judging means, mask level changing means, and mask level restoring means.
The judging means determines whether or not the execution address, which is the address of the program executed by the CPU, has entered the specific address range from outside the specific address range on the memory, and the execution address is out of the specific address range from the specific address range. It is determined whether or not.

  Then, when it is determined by the determination means that the execution address has entered the specific address range from outside the specific address range, the mask level changing means stores the interrupt mask level in the mask level storage means in the specific storage unit, The interrupt mask level in the mask level storage means is changed to a specific priority level determined for the specific address range.

  When the determination means determines that the execution address has gone out of the specific address range from the specific address range, the mask level restoration means sets the interrupt mask level in the mask level storage means to the interrupt mask level ( That is, when it is determined that the execution address is outside the specific address range and within the specific address range, the mask level changing means restores the original interrupt mask level saved in the storage unit).

  According to such a microcomputer, as described in claim 14, an interrupt whose priority level is equal to or lower than the specific priority level among programs to be executed by the CPU (hereinafter also referred to as an interrupt equal to or lower than a specific priority level). If a program desired to be executed in a state in which the above-described prohibition is prohibited is stored in the specific address range of the memory, the program can be executed in a state in which an interrupt having a specific priority level or lower is prohibited. This is because when executing a program stored in the specific address range, the mask level changing means automatically sets the interrupt mask level in the mask level storage means to the specific priority level.

  Therefore, according to this microcomputer, when there is a program to be executed in a state in which interrupts below a specific priority level are prohibited, processing for prohibiting interrupts below a specific priority level is performed at the head of the program and the program is executed. It is no longer necessary to perform processing for canceling the prohibition of interrupts below a specific priority level at the end of.

  The process for prohibiting interrupts below a specific priority level is a process of rewriting the interrupt mask level in the mask level storage means to a specific priority level, and the prohibition of interrupts below a specific priority level is canceled. As a process for this, a process of returning the interrupt mask level in the mask level storage means to the original interrupt mask level before rewriting to a specific priority level can be considered. And it is not necessary to perform such processing in the program.

For this reason, the processing load and program capacity of the CPU can be reduced, and the capacity of the memory can also be reduced.
Next, in the microcomputer according to claim 9, in the microcomputer according to claim 8, the mask level changing means has a mask level storing means if the interrupt mask level before the change in the mask level storing means is equal to or higher than the specific priority level. The interrupt mask level is not changed.

  According to this configuration, in a state where the interrupt mask level in the mask level storage means is set to be equal to or higher than the specific priority level by a program outside the specific address range, the program from any program outside the specific address range When an internal program is called, the interrupt mask level in the mask level storage means becomes lower than the priority level of the interrupt that the call source program wants to mask (that is, the interrupt that the call source program wants to mask) Can be prevented. In other words, it is possible to guarantee the interrupt mask level set when the calling program is executed.

  Next, in the microcomputer according to claim 10, in the microcomputer according to claims 8 and 9, when the CPU accepts an interrupt and performs interrupt processing, and when returning from the interrupt processing to the original processing, the operation of the determination means Is now prohibited.

This configuration is advantageous because it can solve the following problems (1) and (2).
(1) First, during execution of a program within a specific address range, an interrupt with a higher level than a specific priority level determined for the specific address range occurs, and an interrupt processing program outside the specific address range When is executed, the interrupt mask level during the interrupt processing is set to a level corresponding to the cause of the interrupt. However, in this case, since the execution address moves from within the specific address range to outside the specific address range, when this is determined by the determining means, the mask level restoring means is activated and the mask level storage means The interrupt mask level is set to the interrupt mask level stored in the storage unit at that time.

  (2) Even if the interrupt mask level during interrupt processing is set to a level corresponding to the cause of the interrupt, when returning from interrupt processing to the original processing, the execution address is not within the specified address range. Since it moves to the specific address range, if it is determined by the determining means, the mask level changing means is activated, and the interrupt mask level corresponding to the interrupt factor is stored in the storage unit. Then, when the execution of the program in the specific address range is finished and the program returns to the program outside the specific address range, the interrupt mask level in the mask level storage means cannot be returned to the original value.

  On the other hand, according to the microcomputer of claim 10, when the CPU accepts the interrupt and performs the interrupt process, and when returning from the interrupt process to the original process, the operation of the determining means is prohibited. The mask level restoring means and the mask level changing means do not operate, and the above problem can be solved.

  Next, in the microcomputer according to claim 11, in the microcomputer according to claim 8, the specific address range includes a plurality of partial specific address ranges, and different priority levels are defined for the partial specific address ranges. Yes.

Further, the determination means distinguishes and determines which of the plurality of partial specific address ranges the execution address has entered from outside the specific address range.
The mask level changing unit stores the interrupt mask level in the mask level storage unit in the storage unit when the determination unit determines that the execution address has entered any of the partial specific address ranges from outside the specific address range. After that, the interrupt mask level in the mask level storage means is changed to a specific priority level determined for the partial specific address range in which the execution address is entered this time.

  According to such a microcomputer, as described in claim 16, among the programs to be executed by the CPU, an interrupt whose priority level is N or less (N is a number indicating the priority level) (hereinafter referred to as priority level N or less). If a program to be executed in a state in which interrupt is also prohibited is stored in a partial specific address range whose priority level is set to N among a plurality of partial specific address ranges in the memory, the program is It can be executed in a state in which an interrupt with a priority level N or less is prohibited. Therefore, it is possible to cope with a plurality of programs having different priority levels of interrupts to be prohibited during execution.

  Next, in the microcomputer according to claim 12, in the microcomputer according to claim 11, the mask level changing means sets the interrupt mask level before the change in the mask level storing means to the specific priority level (that is, the execution address is input this time). If it is equal to or higher than the priority level determined for the partial specific address range, the interrupt mask level in the mask level storage means is not changed. And according to this microcomputer, the effect described about the microcomputer of Claim 9 is acquired.

  Next, in the microcomputer according to claim 13, in the microcomputer according to claims 11 and 12, when the CPU accepts an interrupt and performs interrupt processing, and when the interrupt processing returns to the original processing, the operation of the determination means Is now prohibited. And according to this microcomputer, the effect described about the microcomputer of Claim 10 is acquired.

  On the other hand, an electronic control device according to a fifteenth aspect is an electronic control device to which the usage method according to the fourteenth aspect is applied. That is, an electronic control device according to a fifteenth aspect is an electronic control device including the microcomputer according to the eighth to tenth aspects, and performs processing for controlling a control target by the microcomputer, and controls the control target. Among the programs executed by the CPU, a program that is executed in a state in which an interrupt whose priority level is lower than the specific priority level is prohibited is stored in the specific address range of the memory.

  An electronic control device according to a seventeenth aspect is an electronic control device to which the usage method according to the sixteenth aspect is applied. That is, an electronic control device according to a seventeenth aspect is an electronic control device including the microcomputer according to the first to thirteenth aspects, and performs processing for controlling a control target by the microcomputer, and the CPU is used to control the control target. Among programs to be executed, a program that is executed in a state where an interrupt whose priority level is N or less is prohibited is within a partial specific address range in which a priority level is set to N among a plurality of partial specific address ranges in the memory. It is characterized by being stored in.

  According to the electronic control device of the fifteenth and seventeenth aspects, the required memory capacity can be suppressed and the increase in cost can be prevented by reducing the program capacity. Further, since the processing load on the CPU is reduced, control performance can be improved.

  Next, in the microcomputer according to claim 18, the CPU executes the program stored in the memory. In particular, specific interrupt limiting means is provided, and the specific interrupt limiting means determines whether or not an execution address that is an address of a program executed by the CPU is within a specific address range on the memory, and When it is determined that the execution address is within the specific address range, the CPU is prevented from accepting an interrupt of a specific interrupt factor.

  According to this microcomputer, among the programs to be executed by the CPU, the program to be executed in a state where the interruption of the specific interrupt factor is prohibited is stored in a specific address range of the memory. If this is the case, the program can be executed in a state in which interrupts of specific interrupt factors are prohibited. This is because when the program is executed, the CPU does not accept an interrupt with a specific interrupt factor (that is, does not execute an interrupt process with a specific interrupt factor) by the specific interrupt limiting means.

  Therefore, according to this microcomputer, when there is a program to be executed in a state where the interrupt of a specific interrupt factor is prohibited, the process for prohibiting the interrupt of the specific interrupt factor is performed at the head of the program and the end of the program is executed. Thus, it is not necessary to perform processing for canceling the prohibition of interrupt of a specific interrupt factor. For this reason, the processing load and program capacity of the CPU can be reduced, and the capacity of the memory can also be reduced.

  According to a nineteenth aspect of the present invention, there is provided an interrupt factor setting register in which information indicating an interrupt factor is written by the CPU. The specific interrupt limiting means handles the interrupt factor indicated by the information in the interrupt factor setting register as the specific interrupt factor. That is, the specific interrupt limiting means prevents the CPU from accepting an interrupt factor interrupt indicated by the information in the interrupt factor setting register.

  For this reason, the interrupt factor to be prohibited can be arbitrarily set according to the contents written to the interrupt factor setting register. Therefore, according to this microcomputer, high versatility can be obtained.

  Next, in the microcomputer according to claim 20, in the microcomputer according to claim 19, information indicating a plurality of types of interrupt factors can be written in the interrupt factor setting register. According to this configuration, it is possible to specify a plurality of interrupt factors that are prohibited when a program within a specific address range is executed, so that the degree of freedom in program design can be improved.

  Next, in the microcomputer according to claim 21, in the microcomputer according to claims 18 to 20, the specific interrupt limiting means monitors an address value output to an address bus between the CPU and the memory at the time of fetching an instruction. By determining whether the address value on the address bus is within the specific address range, it is determined whether the execution address is within the specific address range.

  According to this configuration, the determination function part for determining whether or not the execution address is within the specific address range in the specific interrupt limiting unit can be configured outside the CPU. And deletion is easy.

  According to a twenty-second aspect of the present invention, in the microcomputer of any of the eighteenth to twenty-first aspects, the specific interrupt limiting means outputs an interrupt request signal of the specific interrupt factor to the CPU from an interrupt controller provided outside the CPU. By preventing this, the CPU is prevented from accepting an interrupt of the specific interrupt factor.

  According to this configuration, a part of the specific interrupt limiting means for preventing the CPU from accepting an interrupt of a specific interrupt factor can be configured outside the CPU. It becomes easy.

  According to a twenty-third aspect of the present invention, in the microcomputer according to any one of the eighteenth to twenty-second aspects, an address range setting register in which information indicating an address range on the memory is written is provided. The specific interrupt limiting means handles the address range indicated by the information in the address range setting register as the specific address range. That is, the specific interrupt limiting unit determines whether or not the execution address is within the specific address range indicated by the information in the address range setting register.

According to this microcomputer, the specific address range can be arbitrarily set according to the contents written in the address range setting register, and high versatility can be obtained.
On the other hand, an electronic control device according to claim 25 is an electronic control device to which the usage method according to claim 24 is applied. That is, an electronic control device according to claim 25 is an electronic control device including the microcomputer according to claim 18 to claim 23, and performs processing for controlling the controlled object by the microcomputer, in order to control the controlled object. Of the programs executed by the CPU, a program that is executed in a state in which the interruption of the specific interrupt factor is prohibited is stored in the specific address range of the memory.

  According to this electronic control device, the required memory capacity can be suppressed by reducing the program capacity, and an increase in cost can be prevented. Further, since the processing load on the CPU is reduced, control performance can be improved.

Hereinafter, an electronic control device according to an embodiment to which the present invention is applied will be described. An electronic control device (hereinafter referred to as an ECU) according to the present embodiment is mounted on, for example, a vehicle and controls a control target such as an engine in the vehicle.
[First Embodiment]
As shown in FIG. 1, the ECU 1 of the first embodiment includes a microcomputer 3 that performs processing for controlling a control target. The microcomputer 3 includes a CPU 5 that executes a program, a ROM 7 and a RAM 9 that store programs executed by the CPU 5, an interrupt controller (INTC) 11, an input port 13, an internal timer 15, and an interrupt mask determination unit. 17. Hereinafter, the ROM 7 and the RAM 9 are collectively referred to as memories 7 and 9.

  The CPU 5 includes a status register 19, and an interrupt mask level (specifically, a digital value indicating the interrupt mask level, hereinafter referred to as IM) is written in the status register 19. ing. This IM is the maximum value of the priority level of interrupts to be masked, and means that interrupts with priority levels below that IM are masked.

The interrupt controller 11 includes a priority order determination unit 11a, a level comparison unit 11b, and an AND circuit 11c.
The interrupt controller 11 receives interrupt request signals (peripheral interrupt request signals) of various interrupt factors from the input port 13 and the internal timer 15.

  For example, among input terminals (not shown) of the input port 13 to which signals from the outside of the microcomputer 3 are input, a predetermined number (two or more in this embodiment) of input terminals are interrupt input terminals for generating external interrupts. It has become. When an input signal to each interrupt input terminal changes in a predetermined state, an interrupt request signal for an external interrupt caused by a change in the state of the input signal to the interrupt input terminal from the input port 13 to the interrupt controller 11 Is output. Further, the internal timer 15 has a plurality of timer functions, and when the set time has been detected by each timer function, the set time of the timer function has passed from the internal timer 15 to the interrupt controller 11. An interrupt request signal for a timer interrupt caused by Although not shown in the figure, an interrupt request signal for a communication interrupt caused by reception of communication data by a communication circuit provided outside or inside the microcomputer 3 is also input to the interrupt controller 11, for example. Is done.

  In the interrupt controller 11, an interrupt request signal from the input port 13 or the internal timer 15 is input to the priority determination unit 11a, and the priority determination unit 11a has a priority level of the input interrupt request signals. The interrupt request signal of the highest interrupt is output to the level comparison unit 11b. The priority level of each interrupt is determined in advance.

  The level comparison unit 11b compares the priority level of the interrupt corresponding to the interrupt request signal output from the priority order determination unit 11a (hereinafter referred to as IL) and the IM stored in the status register 19 of the CPU 5. If “IL> IM” (that is, if IL has a higher level than IM), the level comparison unit 11b outputs the interrupt request signal from the priority determination unit 11a to the logical product circuit 11c. If “IL ≦ IM” (that is, if IL is equal to or less than IM), the interrupt request signal from the priority determination unit 11a is masked without being output to the AND circuit 11c.

  The AND circuit 11c outputs an interrupt request signal from the level comparison unit 11b to the CPU 5 if an interrupt mask signal described later is not output from the interrupt mask determination unit 17. Then, the CPU 5 accepts an interrupt corresponding to the interrupt request signal and executes an interrupt process corresponding to the interrupt request signal. Therefore, when an interrupt mask signal is not output from the interrupt mask determination unit 17, an interrupt request signal for an interrupt having a higher priority level than the IM in the status register 19 is input to the interrupt controller 11. The interrupt request signal with the highest priority level is output from the interrupt controller 11 to the CPU 5, and the CPU 5 executes the corresponding interrupt process.

  If the interrupt mask signal is output from the interrupt mask determination unit 17, the logical product circuit 11 c masks the interrupt request signal from the level comparison unit 11 b without outputting it to the CPU 5. Therefore, when an interrupt mask signal is output from the interrupt mask determination unit 17, even if an interrupt request signal is output from the level comparison unit 11b of the interrupt controller 11, the CPU 5 does not accept an interrupt. In this embodiment, the interrupt mask signal is a high active signal.

Next, the interrupt mask determination unit 17 includes an address range register 17a and an address comparison unit 17b.
Information indicating an arbitrary address range on the memories 7 and 9 is written by the CPU 5 in the address range register 17a. The CPU 5 writes address range information in the address range register 17a by executing an initial routine that is started immediately after the operation is started. The information includes, for example, the start address and end address of the address range.

  Then, the address comparison unit 17b monitors an address value (that is, an address of a program executed by the CPU 5) output to the address bus 21 as an instruction fetch bus between the CPU 5 and the memories 7 and 9 when the CPU 5 fetches the instruction. Then, it is determined whether the address value is within the address range indicated by the information in the address range register 17a. If it is determined that the address value is within the address range, the interrupt mask is sent to the interrupt controller 11. Output a signal.

  In such a microcomputer 3, when the CPU 3 is executing a program stored in the address range indicated by the information in the address range register 17 a among the storage areas of the memories 7 and 9, the interrupt mask determination unit 17. Interrupt mask signal is output to the interrupt controller 11. When the interrupt mask signal is output, even if an interrupt request signal of an interrupt having a higher priority level than the IM in the status register 19 is input to the interrupt controller 11, the interrupt request signal is not output to the CPU 5, The CPU 5 does not accept interrupts. That is, interrupts are prohibited. Therefore, the address range indicated by the information in the address range register 17a is an interrupt prohibited address range (that is, an address range where interrupts are prohibited).

  Therefore, in the ECU 1 of the present embodiment, programming is performed so that information on a specific address range in the memories 7 and 9 is written in the address range register 17a, and a program to be executed by the CPU 5 (program for controlling the control target) is stored. Among them, a program to be executed in the interrupt disabled state is stored in the specific address range.

  For example, as shown in FIG. 2, the address range from address A to address B in the address space (program storage area) for storing programs in the memories 7 and 9 may be executed in an interrupt enabled state. X programs are stored. Then, in the process X program, a process that may be executed in the interrupt enabled state is performed in the first S110, and in the next S120, the program of the process A to be executed in the interrupt disabled state is called as a subroutine call. The program for processing A is stored in the address range from address C to address D. Further, information indicating the address range from the C address to the D address is written in the address range register 17a.

  For this reason, when the process A program is called from the process X program, the interrupt controller described above is executed while the process A program is being executed (from the time when the program jumps to the program). The operation of the AND circuit 11c and the interrupt mask determination unit 17 in the CPU 11 prevents the CPU 5 from accepting an interrupt, and the process A program is executed in an interrupt disabled state.

  According to the microcomputer 3 provided in the ECU 1 of the first embodiment as described above, when there is a program to be executed in the interrupt disabled state, a process for prohibiting the interrupt is performed at the head of the program and the end of the program is performed. This eliminates the need for programming to cancel the prohibition of the interrupt (permit the interrupt). Since such processing can be omitted, the processing load and program capacity of the CPU 3 can be reduced, and further, the memory capacity for storing the program can be reduced.

  And according to ECU1 of this embodiment provided with such a microcomputer 3, the increase in cost can be prevented by reducing the memory capacity, and the processing load of the CPU 5 is further reduced, so that the control performance is improved. be able to.

  Further, according to the microcomputer 3 of the present embodiment, the interrupt prohibited address range can be arbitrarily set depending on the contents written to the address range register 17a. Therefore, the address range can be set according to the size of the program to be executed in the interrupt disabled state, and high versatility can be obtained.

  In the microcomputer 3 of the present embodiment, the interrupt mask determination unit 17 provided outside the CPU 5 monitors the address value on the address bus 21 so that the execution address of the CPU 5 is an address set by the address range register 17a. Since it is determined whether or not it is within the range, it is easy to add or delete the interrupt mask determination unit 17. Further, the AND circuit 11c provided outside the CPU 5 prevents the interrupt request signal from being output from the interrupt controller 11 to the CPU 5, thereby preventing the CPU 5 from accepting the interrupt. It is easy to add or delete 11c.

  In the microcomputer 3, the interrupt prohibition address range may be fixed. In this case, for example, a configuration in which a fixed value is set in advance in a portion corresponding to the address range register 17a is conceivable.

Further, an AND circuit 11c may be provided in the CPU 5, and an interrupt request signal from the interrupt controller 11 may be masked on the CPU 5 side.
Further, the interrupt mask determination unit 17 may be provided in the CPU 5. In that case, for example, the value of the program counter in the CPU 5 can be monitored to determine whether or not the value is within the interrupt prohibited address range.

On the other hand, in the above-described embodiment, the interrupt mask determination unit 17 and the AND circuit 11c correspond to the interrupt limiting unit. The address range register 17a corresponds to an address range setting register.
[Second Embodiment]
The ECU 1 of the second embodiment is different from the first embodiment in the following points.

First, a 1-bit state change prohibition register 17c is added to the interrupt mask determination unit 17 in the microcomputer 3.
Then, “1” is written in the state change prohibition register 17c when the CPU 5 executes a predetermined bit set instruction, and “0” is written when the CPU 5 executes a predetermined bit clear instruction.

  Further, when “1” is written in the state change prohibition register 17c, the interrupt mask determination unit 17 holds the determination result of the address comparison unit 17b, and as a result, the output from the address comparison unit 17b to the interrupt controller 11 (ie, , The state of whether or not to output an interrupt mask signal) is held. When “0” is written in the state change prohibiting register 17c, the holding state is released.

  Therefore, when the address comparison unit 17b outputs an interrupt mask signal, if “1” is written in the state change prohibit register 17c, a state in which the CPU 5 does not accept an interrupt (interrupt disabled state) is maintained. Become.

  According to the microcomputer 3 of the second embodiment, when the program Pb outside the interrupt prohibited address range is called from the program Pa within the interrupt prohibited address range and the program Pb is executed, if necessary, The interrupt disabled state can be maintained.

  More specifically, for example, when a subroutine program Pb outside the interrupt prohibition address range is called from another program Pc outside the interrupt prohibition address range, the interrupt is not prohibited, but the subroutine program Pb is not interrupted within the interrupt prohibition address range. When called from the program Pa, there is a case where it is desired to continue the interrupt disabled state.

  In this case, when calling the subroutine program Pb outside the interrupt prohibition address range from the program Pa within the interrupt prohibition address range, a bit set instruction (corresponding to a state holding instruction) for the state change prohibition register 17c is executed. Then, the program Pa may be created so that the bit clear instruction (corresponding to the canceling instruction) for the state change prohibition register 17c is executed when returning from the called subroutine program Pb to the original program Pa.

In addition, when “1” is written in the state change prohibiting register 17c, the output of the address comparison unit 17b itself may be latched instead of the determination result of the address comparison unit 17b. Further, the instruction for holding / releasing the state is not limited to the bit set instruction / bit clear instruction for the state change prohibition register 17c, but may be another dedicated instruction, for example.
[Third Embodiment]
Compared with the first embodiment, the ECU 1 of the third embodiment shown in FIG. 4 differs in the microcomputer 3 in the following points.

  First, the interrupt mask determination unit 17 and the AND circuit 11c in the interrupt controller 11 are deleted. For this reason, the interrupt request signal from the level comparison unit 11b is output to the CPU 5 unconditionally.

  Further, the CPU 5 has address ranges PA1 to PAn in which priority levels of interrupts (n in this embodiment, 1 to n, where n is an integer equal to or greater than 2) are defined, and the priority levels determined thereby Address range registers AR1 to ARn are provided for setting address ranges PA1 to PAn in which programs to be executed in a state where the following interrupts are prohibited are stored. In the address range register ARm (m is any one of 1 to n), information indicating an address range PAm that stores a program to be executed in a state in which interrupts corresponding to the priority level (= m) or lower are prohibited. It is written by the CPU 5.

  The CPU 5 writes address range information in each of the address range registers AR1 to ARn by executing an initial routine started immediately after the operation is started. The information includes, for example, the start address and end address of the address range. On the other hand, although not shown in the above embodiment, the CPU 5 is also provided with a program counter 23. Hereinafter, an address range indicated by information written in the address range register ARm is referred to as an address range PAm set by the address range register ARm.

  As shown in FIG. 5, in the address spaces for storing programs in the memories 7 and 9, each of the address ranges PA1 to PAn set by the address range registers AR1 to ARn has a program (control) to be executed by the CPU 5. Stores a program to be executed in a state in which an interrupt having a priority level or lower determined in the address range is prohibited.

  That is, the address range PA1 (addresses C to D in this example) set by the address range register AR1 stores a program to be executed in a state where an interrupt having a priority level of 1 or less is prohibited. In the address range PA2 (addresses E to F in this example) set by AR2, a program to be executed in a state where an interrupt having a priority level of 2 or less is prohibited is stored. Similarly, in the address range PAn (addresses X to Y in this example) set by the address range register ARn, interrupts whose priority level is n or less are prohibited (that is, all interrupts are prohibited). Contains the program you want to run on

  Also, as shown in FIG. 5, the address range is not set by any of the address range registers AR1 to ARn, and the address range other than the address range PA1 to PAn (address A to address B in this example) A program (normal program) that may be executed in a state where all interrupts are permitted is stored.

  Further, as shown in FIG. 4, the CPU 5 is provided with an interrupt mask level control unit 25. The interrupt mask level control unit 25 is a program branch instruction (branch instruction, jump instruction, return subroutine instruction, etc.). When the above is executed, the operation of FIG.

  As shown in FIG. 6, when the interrupt mask level control unit 25 operates, first, the value of the program counter 23 (hereinafter referred to as the PC value), which is the branch destination address, is set by the address range registers AR1 to ARn. It is determined whether it is in any address range PA1 to PAn, and if it is in which address range (S310 to S330), the PC value is in any address range PA1 to PAn. If so, the priority level m corresponding to the address range PAm containing the PC value is stored as an IM candidate value (S340 to S360). For example, if the PC value is within the address range PA1, 1 is stored as the IM candidate value (S340), and if the PC value is within the address range PA2, 2 is stored as the IM candidate value (S350).

Next, it is determined whether or not the in-range flag is turned on (S370). The in-range flag is a flag that is turned on when the PC value is in the address range PA1 to PAn.
If the in-range flag is turned on (S370: YES), it means that the PC value is within the address range PA1 to PAn before the current operation, and thus the operation is ended as it is.

  On the other hand, if the in-range flag is not turned on even though the PC value is in the address range PA1 to PAn (S370: NO), this time, the PC value is in the address range PA1 to PAn from other than the address range PA1 to PAn. Since it is in the range, the in-range flag is turned on (S380).

  Next, the IM (hereinafter also referred to as IM value) in the status register 19 is stored in the stack area in the CPU 5 (S390), and then the IM value and the IM candidate value stored in the above operations of S340 to S360 ( That is, the PC value is compared with the priority level m) determined for the address range PAm that has entered this time, and it is determined whether the IM value is equal to or greater than the IM candidate value (S400).

  If the IM value is equal to or greater than the IM candidate value (S400: YES), the operation is terminated as it is. If the IM value is not equal to or greater than the IM candidate value (S400: NO), the IM value is rewritten to the IM candidate value ( After that, the operation is terminated.

  On the other hand, if it is determined in S310 to S330 that the PC value does not fall within the address range PA1 to PAn (that is, other than the address range PA1 to PAn), is the in-range flag turned on? If the in-range flag is not turned on (S420: NO), it means that the PC value is outside the address range PA1 to PAn before the current operation. finish.

  On the other hand, if the in-range flag is turned on even if the PC value is outside the address range PA1 to PAn (S420: YES), this time, the PC value is within the address range PA1 to PAn but outside the address range PA1 to PAn. Therefore, the in-range flag is turned off (S430). Then, the IM value is returned to the value stored in the stack area by the operation of S390 (S440), and then the operation is terminated.

  In the microcomputer 3 having such an interrupt mask level control unit 25, when the execution address (PC value) of the CPU 5 enters the address range PA1 to PAn from other than the address range PA1 to PAn, the IM value is saved in the stack area. (S390) If the IM value is smaller than the priority level m determined for the address range PAm in which the execution address has entered this time (S400: NO), the IM value is changed to the priority level m. (S410). Then, when the execution address of the CPU 5 goes out of the address range PA1 to PAn to other than the address range PA1 to PAn, the IM value is returned to the original value saved in the stack area (S440).

  Therefore, as can be said with respect to each of the address ranges PA1 to PAn, during execution of a program stored in the address range, an interrupt having a priority level or lower corresponding to the address range is prohibited.

  According to the microcomputer 3 of the third embodiment as described above, among the programs to be executed by the CPU 5, a program to be executed in a state where an interrupt having a priority level of m or lower (hereinafter also referred to as an interrupt having a priority level of m or lower) is prohibited. Is stored in the address range PAm in which the priority level is set to m among the address ranges PA1 to PAn in the memories 7 and 9, and the program is in a state in which interrupts with the priority level of m or less are prohibited. Can be executed.

  Therefore, when there is a program to be executed in a state where an interrupt with a priority level m or lower is prohibited, a process for prohibiting an interrupt with a priority level m or lower is performed at the beginning of the program, and the priority level is set at the end of the program. There is no need to perform processing for canceling the prohibition of interrupts of m or less.

  For this reason, the processing load and program capacity of the CPU 5 can be reduced, and the memory capacity for storing the program can also be reduced. It is also possible to cope with a plurality of programs having different priority levels of interrupts to be prohibited during execution. Further, since the address ranges PA1 to PAn can be arbitrarily set by the address range registers AR1 to ARn17a, high versatility is obtained.

  Furthermore, in the microcomputer 3 of the third embodiment, when the execution address enters any of the address ranges PA1 to PAn from other than the address range PA1 to PAn, the interrupt mask level control unit 25 executes the IM value at that time and the execution When the IM value is equal to or higher than the priority level m (S400: YES), the IM value is not changed when the address is compared with the priority level m determined for the address range PAm that has entered this time. .

  Therefore, when a program in the address range PAm is called from a program other than the address range PA1 to PAn in a state where the IM value is set to the priority level m or higher by a program other than the address range PA1 to PAn, the IM It is possible to prevent the value from becoming lower than the priority level of the interrupt that the calling program wants to mask (that is, the interrupt that the calling program wants to mask interrupts).

  By the way, if the interrupt mask level control unit 25 is not provided in the CPU 5 and an operation similar to that by the interrupt mask level control unit 25 is to be obtained, an interrupt with a priority level m or lower is prohibited. In this case, it is necessary to create a program to be executed as shown in FIG.

  First, the process A program shown in FIG. 7A is a program to be executed in a state in which interrupts with priority level m or lower are prohibited. Then, in the program, in step S210, the interrupt prohibition process shown in FIG. 7B for prohibiting an interrupt having a priority level m or lower is performed.

  As shown in FIG. 7B, in the interrupt prohibition process, first, in S211, the current IM value is stored in the buffer, and in the next S213, the current IM value is the priority of the interrupt to be prohibited. It is determined whether or not the level is equal to or higher than level m. If “IM value ≧ m”, the interrupt prohibition process is terminated as it is. If it is determined in S213 that “IM value ≧ m” is not satisfied, the IM value is rewritten to the priority level m of the interrupt to be prohibited in the next S215, and then the interrupt prohibition process is terminated.

  When such an interrupt prohibition process ends, the process returns to FIG. 7A, and in S220, a process that needs to be executed in a state in which an interrupt with a priority level m or lower is prohibited is performed. When the processing is completed, the interrupt permission processing shown in FIG. 7C for canceling the prohibition of the interrupt with the priority level m or less is performed in the last S230.

  As shown in FIG. 7C, in the interrupt permission process, the IM value is returned to the value stored in the buffer in S211 of FIG. 7B in S231, and then the interrupt permission process. Exit. As a result, the program of FIG.

  As described above, assuming that there is no interrupt mask level control unit 25, at the beginning (S210) and the end (S230) of the program to be executed in the state where the interrupt of the priority level m or lower is prohibited, FIG. However, according to the microcomputer 3 of the third embodiment, it is not necessary to perform such processing, and the processing load and program capacity of the CPU 5 can be reduced.

  And according to ECU1 of 3rd Embodiment provided with the above microcomputers 3, since increase in cost can be prevented by reduction of memory capacity, and also processing load of CPU5 is reduced, control performance Can be increased.

Next, additional functions of the microcomputer 3 according to the third embodiment will be described.
First, as illustrated in FIG. 8, when the program in the addresses A to B in FIG. 5 is being executed, the program sets the IM value to 0, and the program in the addresses A to B 5 is called (program in the address range PA1), the IM value is changed from 0 to 1 by the interrupt mask level control unit 25.

  Then, when the program in the addresses C to D is being executed, an interrupt with a priority level higher than 1 is generated, and the interrupt processing program in the addresses A to B is started. In the execution period of the interrupt process, the IM value needs to be set to a priority level (11 in this example) corresponding to the cause of the interrupt by a function such as the OS.

  After that, the interrupt process is finished, the IM value is returned from 11 to 1 by the function of the OS, etc., and the program in the addresses C to D is finished and the call in the addresses A to B is finished. When returning to the original program, the IM value is returned from 1 to the original 0 by the interrupt mask level control unit 25.

The above is the IM value transition expected originally.
However, as shown in FIG. 9A, when a program in addresses C to D is being executed, if an interrupt program with a priority level higher than 1 is activated, the execution address of the program is changed to an address range. Since the transition is made to addresses A to B other than PA1 to PAn, this is determined by the interrupt mask level control unit 25, and the IM value is returned to 0 which is saved in the stack area at that time. Will be. This is due to the operation of S440 in FIG.

  Also, as shown in FIG. 9B, the IM value during execution of the interrupt process is not returned to 0, but is set to a level (= 11) corresponding to the cause of the interrupt by a function such as the OS. Even when the program is interrupted, when returning from the interrupt processing program to the program in the original address C to address D, the execution address of the program is from address A to address B other than the address range PA1 to PAn to the address range PA1 (C Since the interrupt mask level control unit 25 determines that the priority level (= 11) corresponding to the cause of the interrupt is stored in the stack area. . This is due to the operation of S390 in FIG. Then, when the execution of the program in the addresses C to D is finished and the program returns to the calling program in the addresses A to B, the IM value can be returned to 0 which is the original value. Therefore, it will be set to 11.

  Therefore, in order to solve the above problem in such a case, the operation of the interrupt mask level control unit 25 is performed when the CPU 5 accepts an interrupt and performs an interrupt process, or when returning from the interrupt process to the original process. Of these, at least the operations of S310 to S330 in FIG. 6 may be prohibited. As explained in the above example, when a program in addresses C to D is being executed, an interrupt program with a priority level higher than 1 is started, and the execution address of the program is outside the address range PA1 to PAn. 6, the operation of S440 in FIG. 6 is not performed, and when returning from the interrupt processing program to the program in the original address C to address D in FIG. This is because the operation of S390 is not performed, and the IM value can be transitioned as shown in FIG.

In the third embodiment, the status register 19 corresponds to mask level storage means, and the interrupt mask level control unit 25 corresponds to determination means, mask level changing means, and mask level restoring means. In particular, the portion of the interrupt mask level control unit 25 that performs the operations of S310 to S330, S370, S380, S420, and S430 in FIG. 6 corresponds to the determination unit, and the operations of S340 to S360 and S390 to S410 in FIG. The portion for performing the processing corresponds to the mask level changing means, and the portion for performing the operation of S440 in FIG. 6 corresponds to the mask level restoring means. The stack area corresponds to a specific storage unit. Further, address ranges other than the address ranges PA1 to PAn correspond to outside the specific address range, and each of the address ranges PA1 to PAn corresponds to a specific address range or a partial specific address range.
[Fourth Embodiment]
The ECU 1 of the fourth embodiment shown in FIG. 10 differs from the first embodiment in the microcomputer 3 in the following points.

First, the AND circuit 11c in the interrupt controller 11 is deleted. For this reason, the interrupt request signal from the level comparison unit 11b is output to the CPU 5 unconditionally.
The interrupt controller 11 is provided with an interrupt factor setting register 11d and an interrupt mask unit 11e.

  The interrupt factor setting register 11d is a register for setting an interrupt factor (interrupt factor) to be masked. In the interrupt factor setting register 11d, an interrupt request signal (peripheral interrupt request) input from the input port 13 or the internal timer 15 to the interrupt controller 11 as information indicating the interrupt factor of the interrupt to be masked by the CPU 5 is stored in the interrupt factor setting register 11d. Information indicating one or more of (signal) is written.

  For example, in the present embodiment, the interrupt factor setting register 11d is a register having a plurality of bits corresponding to each interrupt request signal input to the interrupt controller 11, and an interrupt corresponding to a bit in which “1” is written. This means that the request signal is an interrupt request signal due to an interrupt factor of the interrupt to be masked. The CPU 5 writes “1” or “0” in each bit of the interrupt factor setting register 11d by executing an initial routine that is started immediately after the operation starts.

  Then, when the interrupt mask signal is not output from the interrupt mask determination unit 17, the interrupt mask unit 11e outputs an interrupt request signal input to the interrupt controller 11 from the input port 13, the internal timer 15, or the like. All are input to the priority determination unit 11a.

  In addition, when an interrupt mask signal is output from the interrupt mask determination unit 17, the interrupt mask unit 11e includes the interrupt set by the interrupt factor setting register 11d among the interrupt request signals input to the interrupt controller 11. The factor interrupt request signal is prevented from being input to the priority determination unit 11a. That is, the interrupt request signal corresponding to the bit in which “1” is written among the bits of the interrupt factor setting register 11d is prohibited from being input to the priority determination unit 11a.

  Such an interrupt mask unit 11e can be configured by a combination of AND circuits. For example, when describing one interrupt request signal IR1, the interrupt mask unit 11e receives the bit value of the interrupt factor setting register 11d corresponding to the interrupt request signal IR1 and the interrupt mask signal from the interrupt mask determination unit 17. A NAND circuit (negative AND circuit) and an AND circuit (AND circuit) that receives the output of the NAND circuit and the interrupt request signal IR1 can be used. In this configuration, the interrupt request signal IR1 is output from the AND circuit to the priority determination unit 11a.

  In such a microcomputer 3 of the fourth embodiment, as in the first embodiment, the CPU 3 loads a program stored in the address range indicated by the information in the address range register 17a in the storage areas of the memories 7 and 9. If it is being executed, an interrupt mask signal is output from the interrupt mask determination unit 17 to the interrupt controller 11.

  Then, when an interrupt mask signal is output from the interrupt mask determination unit 17, the interrupt request signal of the interrupt factor set by the interrupt factor setting register 11d among the interrupt request signals input to the interrupt controller 11 is determined according to the priority order. Since it is not input to the unit 11a, even if the interrupt request signal is an interrupt request signal of an interrupt having a higher priority level than the IM in the status register 19, it is prevented from being output to the CPU 5. Therefore, the CPU 5 does not accept an interrupt corresponding to the interrupt request signal.

  Therefore, in the fourth embodiment, among the programs to be executed by the CPU 5, a program (hereinafter referred to as a program P 1) that is desired to be executed in a state in which interruption of a specific interrupt factor is prohibited is assigned to a specific address range in the memories 7 and 9. In addition, information on the specific address range is written into the address range register 17a, and information indicating the specific interrupt factor (that is, interrupt factor of an interrupt to be prohibited during execution of the program P1) is set as an interrupt factor. The initial routine is programmed to be written to the register 11d.

  In this way, while the program P1 is being executed, the CPU 5 causes the above-described specific interrupt factor to operate by the action of the interrupt factor setting register 11d, the interrupt mask unit 11e and the interrupt mask determination unit 17 in the interrupt controller 11 described above. This is because no interrupts are accepted.

  Therefore, according to the microcomputer 3 of the fourth embodiment, when there is a program that is desired to be executed in a state where the interrupt of a specific interrupt factor is prohibited, the process for prohibiting the interrupt of the specific interrupt factor at the head of the program It is not necessary to perform programming for canceling the prohibition of interrupt of a specific interrupt factor at the end of the program. For this reason, the processing load and program capacity of the CPU 5 can be reduced, and the memory capacity for storing the program can also be reduced.

  And according to ECU1 of 4th Embodiment provided with such a microcomputer 3, since increase in cost can be prevented by reduction of memory capacity, and also the processing load of CPU5 is reduced, control performance is reduced. Can be increased.

  Further, according to the microcomputer 3 of the fourth embodiment, the interrupt factor to be prohibited can be arbitrarily set according to the contents written in the interrupt factor setting register 11d. Therefore, high versatility can be obtained. Furthermore, since a plurality of interrupt factors to be prohibited can be designated, the degree of freedom in program design can be improved.

  Also in the microcomputer 3 of the fourth embodiment, the address range in which the interrupt of a specific interrupt factor is prohibited can be arbitrarily set depending on the contents written in the address range register 17a, and high versatility is obtained. It is done.

  Furthermore, in the microcomputer 3 of the fourth embodiment, since the interrupt mask determination unit 17, the interrupt factor setting register 11d, and the interrupt mask unit 11e are provided outside the CPU 5, it is easy to add or delete them. is there.

  It should be noted that the address range in which the interrupt of a specific interrupt factor is prohibited may be fixed. In this case, for example, a configuration in which a fixed value is set in advance in a portion corresponding to the address range register 17a is conceivable. Similarly, the factor of the interrupt that is prohibited may be fixed. In this case, for example, a configuration in which a fixed value is set in advance in a portion corresponding to the interrupt factor setting register 11d can be considered.

  On the other hand, in the fourth embodiment, the interrupt mask determination unit 17, the interrupt factor setting register 11d, and the interrupt mask unit 11e correspond to a specific interrupt limiting unit. The interrupt factor setting register 11d corresponds to an interrupt factor setting register.

  As mentioned above, although one Embodiment of this invention was described, this invention is not limited to such Embodiment at all, Of course, in the range which does not deviate from the summary of this invention, it can implement in a various aspect. .

For example, in the third embodiment, the IM value save destination is not limited to the stack area, and may be any storage area in the RAM 9, for example.
In each embodiment, the address range information to be written to the address range registers 17a and AR1 to ARn is not limited to the start address and the final address of the target address range, but any information that can specify the address range. It may be in the form of information. For example, capacity information such as the start address and the number of bytes from the start address may be used. Further, for example, common bit information indicating a bit string composed of bits common to each address in a target address range and non-common bit information indicating a position of a bit that is not common are written in the address range registers 17a and AR1 to ARn. If the bit string ignoring the bit at the position indicated by the non-common bit information in the execution address bit string matches the bit string indicated by the common bit information, the execution address is determined by the address range registers 17a and AR1 to ARn. It can also be configured to determine that it is within the set address range.

It is a block diagram showing the structure of ECU and microcomputer of 1st Embodiment. It is explanatory drawing explaining the usage method and effect | action of the microcomputer of 1st Embodiment. It is a block diagram showing the structure of ECU and microcomputer of 2nd Embodiment. It is a block diagram showing the structure of ECU and microcomputer of 3rd Embodiment. It is explanatory drawing explaining the storage state of the program in the microcomputer of 3rd Embodiment. It is a flowchart showing operation | movement of the interruption mask level control part in the microcomputer of 3rd Embodiment. It is a flowchart explaining the example of a structure of a program on the assumption that the interruption mask level control part is not provided. It is the 1st explanatory view for explaining the additional function of the microcomputer of a 3rd embodiment. It is the 2nd explanatory view for explaining the additional function of the microcomputer of a 3rd embodiment. It is a block diagram showing the structure of ECU and microcomputer of 4th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electronic control unit (ECU), 3 ... Microcomputer (microcomputer), 5 ... CPU, 7 ... ROM, 9 ... RAM, 11 ... Interrupt controller, 11a ... Priority determination part, 11b ... Level comparison part, 11c ... Logic Product circuit, 11d ... Interrupt factor setting register, 11e ... Interrupt mask unit, 13 ... Input port, 15 ... Internal timer, 17 ... Interrupt mask determination unit, 17a, AR1-ARn ... Address range register, 17b ... Address comparison unit, 17c ... State change prohibition register, 19 ... Status register, 21 ... Address bus (instruction fetch bus), 23 ... Program counter, 25 ... Interrupt mask level control unit

Claims (25)

In a microcomputer comprising a CPU and a memory storing a program executed by the CPU,
It is determined whether an address of a program executed by the CPU (hereinafter referred to as an execution address) is within a specific address range on the memory, and it is determined that the execution address is within the specific address range. If there is an interrupt limiting means for preventing the CPU from accepting an interrupt,
A microcomputer characterized by. The microcomputer according to claim 1,
The interrupt limiting unit monitors an address value output to an address bus between the CPU and the memory when the CPU fetches an instruction, and determines whether the address value on the address bus is within the specific address range. Is configured to determine whether the execution address is within the specific address range,
A microcomputer characterized by. The microcomputer according to claim 1 or 2,
The interrupt limiting unit prevents the CPU from accepting an interrupt by preventing an interrupt controller provided outside the CPU from outputting an interrupt request signal to the CPU;
A microcomputer characterized by. The microcomputer according to any one of claims 1 to 3,
An address range setting register in which information indicating an address range on the memory is written by the CPU;
The interrupt limiting unit handles the address range indicated by the information in the address range setting register as the specific address range;
A microcomputer characterized by. The microcomputer according to any one of claims 1 to 4,
When the CPU executes a state holding instruction for holding the operation state of the interrupt limiting unit, the CPU executes a release instruction for releasing the holding of the operation state by the state holding instruction. The interrupt limiting means is when the state holding instruction is executed among an operation state in which the CPU does not accept an interrupt and an operation state in which the CPU can accept an interrupt. To keep the operating state
A microcomputer characterized by. A method of using the microcomputer according to any one of claims 1 to 5,
Of the programs to be executed by the CPU, storing a program to be executed in an interrupt disabled state within the specific address range of the memory;
A method of using a microcomputer characterized by the above. An electronic control device comprising the microcomputer according to any one of claims 1 to 5, wherein the microcomputer performs processing for controlling a controlled object.
Of the programs executed by the CPU to control the control target, a program executed in an interrupt disabled state is stored in the specific address range of the memory,
An electronic control device. CPU,
A memory for storing a program executed by the CPU;
Mask level storage means for storing an interrupt mask level which is the maximum priority level of interrupts to be masked;
When an interrupt request signal having a priority level higher than the interrupt mask level in the mask level storage means is generated, the CPU accepts the interrupt, and an interrupt whose priority level is equal to or lower than the interrupt mask level in the mask level storage means An interrupt controller that prevents the CPU from accepting the interrupt even when a request signal is generated;
In a microcomputer equipped with
Whether an address of a program executed by the CPU (hereinafter referred to as an execution address) has entered the specific address range from outside the specific address range on the memory, and the execution address is within the specific address range from the specific address range. Determination means for determining whether or not the vehicle has gone out of range;
When the determination means determines that the execution address has entered the specific address range from outside the specific address range, the interrupt mask level in the mask level storage means is stored in a specific storage unit, and then the mask level Mask level changing means for changing the interrupt mask level in the storage means to a specific priority level determined for the specific address range;
A mask level for returning the interrupt mask level in the mask level storage means to the interrupt mask level in the storage section when the determination means determines that the execution address is out of the specific address range from the specific address range Recovery means,
A microcomputer comprising: The microcomputer according to claim 8,
The mask level changing means does not change the interrupt mask level in the mask level storage means if the interrupt mask level before the change in the mask level storage means is equal to or higher than the specific priority level. ,
A microcomputer characterized by. The microcomputer according to claim 8 or 9,
When the CPU accepts an interrupt and performs an interrupt process, and when returning from the interrupt process to the original process, the operation of the determination means is prohibited.
A microcomputer characterized by. The microcomputer according to claim 8,
The specific address range includes a plurality of partial specific address ranges, and different priority levels are defined for the partial specific address ranges,
Further, the determination means is configured to distinguish and determine which of the plurality of partial specific address ranges has entered the execution address from outside the specific address range,
The mask level changing means stores the interrupt mask level in the mask level storage means when the determination means determines that the execution address has entered any of the partial specific address ranges from outside the specific address range. The interrupt mask level in the mask level storage means is changed to a specific priority level determined for the partial specific address range in which the execution address has entered this time,
A microcomputer characterized by. The microcomputer according to claim 11, wherein
The mask level changing means does not change the interrupt mask level in the mask level storage means if the interrupt mask level before the change in the mask level storage means is equal to or higher than the specific priority level. ,
A microcomputer characterized by. The microcomputer according to claim 11 or 12,
When the CPU accepts an interrupt and performs an interrupt process, and when returning from the interrupt process to the original process, the operation of the determination means is prohibited.
A microcomputer characterized by. A method of using the microcomputer according to any one of claims 8 to 10,
Storing a program to be executed in a state in which an interrupt whose priority level is equal to or lower than the specific priority level among the programs to be executed by the CPU is prohibited in the specific address range of the memory;
A method of using a microcomputer characterized by the above. An electronic control device comprising the microcomputer according to any one of claims 8 to 10, wherein the microcomputer performs processing for controlling a controlled object.
Among programs executed by the CPU to control the control target, a program executed in a state where an interrupt whose priority level is equal to or lower than the specific priority level is prohibited is stored in the specific address range of the memory. is being done,
An electronic control device. A method of using the microcomputer according to any one of claims 11 to 13,
Among the programs to be executed by the CPU, a program to be executed in a state in which an interrupt whose priority level is N or less (N is a number indicating the priority level) is prohibited is selected from among a plurality of partial specific address ranges in the memory. Is stored in the partial specific address range defined in the N,
A method of using a microcomputer characterized by the above. An electronic control device comprising the microcomputer according to any one of claims 11 to 13, wherein the microcomputer performs processing for controlling a controlled object.
Among programs executed by the CPU to control the control target, a program executed in a state in which an interrupt whose priority level is N or less (N is a number indicating the priority level) is prohibited is a plurality of programs in the memory. Among the partial specific address ranges, the priority level is stored in the partial specific address range defined in N,
An electronic control device. In a microcomputer comprising a CPU and a memory storing a program executed by the CPU,
It is determined whether an address of a program executed by the CPU (hereinafter referred to as an execution address) is within a specific address range on the memory, and it is determined that the execution address is within the specific address range. A specific interrupt limiting means for preventing the CPU from accepting an interrupt of a specific interrupt factor,
A microcomputer characterized by. The microcomputer according to claim 18,
An interrupt factor setting register in which information indicating an interrupt factor is written by the CPU;
The specific interrupt limiting means handles the interrupt factor indicated by the information in the interrupt factor setting register as the specific interrupt factor;
A microcomputer characterized by. The microcomputer according to claim 19,
In the interrupt factor setting register, information indicating a plurality of types of interrupt factors can be written,
A microcomputer characterized by. The microcomputer according to any one of claims 18 to 20,
The specific interrupt limiting unit monitors an address value output to the address bus between the CPU and the memory when the CPU fetches an instruction, and whether or not the address value on the address bus is within the specific address range. Determining whether or not the execution address is within the specific address range,
A microcomputer characterized by. The microcomputer according to any one of claims 18 to 21,
The specific interrupt limiting means prevents the interrupt controller provided outside the CPU from outputting an interrupt request signal of the specific interrupt factor to the CPU, so that the CPU can output the specific interrupt factor. Not accepting any interrupts,
A microcomputer characterized by. The microcomputer according to any one of claims 18 to 22,
An address range setting register in which information indicating an address range on the memory is written by the CPU;
The specific interrupt limiting means handles the address range indicated by the information in the address range setting register as the specific address range;
A microcomputer characterized by. A method of using the microcomputer according to any one of claims 18 to 23,
Of the programs to be executed by the CPU, storing a program to be executed in a state in which interruption of the specific interrupt factor is prohibited, within the specific address range of the memory,
A method of using a microcomputer characterized by the above. An electronic control device comprising the microcomputer according to any one of claims 18 to 23, wherein the microcomputer performs processing for controlling a controlled object.
Of the programs executed by the CPU to control the control target, a program executed in a state in which interruption of the specific interrupt factor is prohibited is stored in the specific address range of the memory,
An electronic control device.

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