JP2010196619A - Control system of internal combustion engine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control system of an internal combustion engine equipped with a multiprocessor, which is not affected by the number of rotations of the internal combustion engine, can equally distribute arithmetic processing load among processors, and reduces load of the entire multiprocessor. <P>SOLUTION: The control system of an internal combustion engine equipped with a multiprocessor includes a routine processing means in which each processor sequentially processes an interrupt routine ca in synchronization with a crank angle. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a control device for an internal combustion engine. In particular, the present invention relates to a control device for an internal combustion engine equipped with a multiprocessor.

  2. Description of the Related Art Conventionally, automobile engine control devices perform fuel injection control, ignition control, and the like based on calculation results using detection values detected by a crank angle sensor, a cam position sensor, and the like.

  Further, conventionally, an automobile engine control device equipped with a multiprocessor is known (see, for example, Patent Documents 1 to 4).

JP-A 61-277849 Japanese Patent Laid-Open No. 10-21001 JP 2005-259023 A JP 2006-17054 A

  However, when an engine control device equipped with a multiprocessor is employed, it is difficult to evenly distribute the processing load to each processor. This is because the load of the arithmetic processing (hereinafter also referred to as “crank angle synchronization processing”) to be executed in synchronization with a certain crank angle (for example, crank angles 30 °, 60 °, 90 °,...) One factor is that it fluctuates according to the number.

  In addition, the order of the arithmetic processing is a factor that makes it difficult to evenly distribute the load.

  Further, when an engine control device equipped with a multiprocessor is employed, it is desirable to reduce synchronous control and exclusive control between the processors to reduce the load on the entire control device. That is, even if the load can be evenly distributed to each processor, if synchronous control or exclusive control is frequently performed, the burden of arithmetic processing other than engine control increases.

  In order to employ a multiprocessor for the engine control device, it is necessary to change the control program to be compatible with the multiprocessor, and at that time, much man-hours are spent on the design of synchronous / exclusive control and reentrant design. There must be. For this reason, it is desired to reduce the above-mentioned man-hours by using an existing program with a proven record as much as possible.

  In addition, when the engine speed is high, such as 10,000 rpm, the crank angle synchronization processing must be processed in an extremely short time, otherwise the use efficiency of the processor is greatly reduced.

  On the other hand, dynamically distributing the load among the processors is not practical in terms of quality assurance.

  In order to solve the above problem, for example, it is conceivable to assign the crank angle synchronization process to only one of the multiprocessors.

  However, in this case, the load on a specific processor varies due to engine rotation fluctuations. Further, even if the processing load can be evenly distributed in accordance with the high engine speed, a specific processor becomes too idle at a low engine speed. Further, even if the number of processors is increased, the load of the crank angle synchronization processing is borne by one processor and cannot be distributed.

  In order to solve the above problem, for example, after a processor generates a crank counter from a crank angle synchronization signal, the crank angle synchronization process of another processor using an inter-processor interrupt of the operating system, etc. It is possible to wake up all of them.

  However, in this case, when the number of processors increases, another problem that the cost of synchronous control and exclusive control increases. In addition, since the crank angle synchronization processing requires order and simultaneity, if the number of processors increases, it becomes more difficult to distribute the processing load.

  The present invention was devised in view of the above-described problems, and in an internal combustion engine control apparatus equipped with a multiprocessor, the processing load on each processor is independent of the rotational speed of the internal combustion engine. It is an object of the present invention to provide a control device for an internal combustion engine that can equally distribute the engine load and suppresses the processing load on the entire multiprocessor.

  As means for solving the above-described problems, the control device for an internal combustion engine of the present invention is configured as follows.

  That is, the control apparatus for an internal combustion engine according to the present invention is characterized in that, in the control apparatus for an internal combustion engine equipped with a multiprocessor, each processor includes a routine processing means for sequentially processing an interrupt routine in synchronization with a crank angle. .

  According to the control apparatus for an internal combustion engine having such a configuration, it is possible to evenly distribute the processing load to each processor without being influenced by the rotational speed of the internal combustion engine. In addition, since distribution of crank angle synchronization processing does not require synchronization control, exclusive control, and the like, an increase in the processing load on the entire multiprocessor can be suppressed accordingly.

  Further, the routine processing means includes, for example, an interrupt signal generating means for generating an interrupt signal for each constant crank angle, and each processor is assigned with the constant crank angle, the crank angle at the time of generating the interrupt signal, and the allocation. Interrupt routine execution availability determination means for determining whether or not to execute the interrupt routine based on the processor identification information.

  According to the present invention, it is possible to evenly distribute the processing load to each processor regardless of the rotational speed of the internal combustion engine. In addition, since the distribution of the crank angle synchronization process does not require synchronization control, exclusive control, etc., it is possible to suppress an increase in the processing load on the entire multiprocessor.

It is a figure which shows the structure of the microcontroller in the control apparatus of the internal combustion engine which concerns on embodiment of this invention. It is a flowchart which shows the procedure of the processing operation in the control apparatus of the internal combustion engine which concerns on embodiment of this invention. 4 is a time chart showing a crank angle, a crank angle synchronization signal, processing contents of a first processor, and processing contents of a second processor when the engine is running at a low speed. 6 is a time chart showing a crank angle, a crank angle synchronization signal, a processing content of a first processor, and a processing content of a second processor when the engine is rotating at a high speed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a microcontroller 1 mounted in an ECU (electronic control unit) that is an engine control device.

  The microcontroller 1 includes an interrupt signal generator 2, a first processor 3, a second processor 4, a ROM (Read Only Memory) 5, a RAM (Random Access Memory) 6, a pulse generation unit 7, and the like. The interrupt signal generator 2 and the first and second processors 3 and 4 are communicably connected via a system bus 8. The first and second processors 3 and 4 and the ROM 5 and RAM 6 are connected via the memory bus 9. It is connected so that it can communicate. The interrupt signal generator 2 and the interrupt controllers 3 a and 4 a of the processors 3 and 4 are connected by an interrupt signal line 11.

  The ECU generates a crank angle synchronization signal for every 30 ° crank angle from a crank rotation signal detected by the crank position sensor by a control unit other than the microcontroller 1 and supplies it to the interrupt signal generation unit 2. input. The crank angle synchronization signal is also input to the processors 3 and 4.

  The interrupt signal generator 2 generates an interrupt signal every 30 ° crank angle based on the input crank angle synchronization signal. The generated interrupt signal is input to the two processors 3 and 4 simultaneously.

  The first and second processors 3 and 4 are SMP type (target type) multiprocessors. Each of the processors 3 and 4 is equipped with interrupt controllers 3a and 4a for detecting an interrupt signal. The two processors 3 and 4 may be composed of a plurality of chips, or may be a single chip multi-core processor. Note that a configuration with low communication cost is preferable.

  ROM 5 and RAM 6 are shared memories of the two processors 3 and 4. That is, the microcontroller 1 employs a UMA (Uniform Memory Access) configuration, and a common physical address space is mapped to the two processors 3 and 4. However, if the access cost to the resources shared by the two processors 3 and 4 can be within an error of several clocks, a NUMA (Non-Uniform Memory Access) configuration can be adopted.

  The pulse generation unit 7 generates and outputs an injector energization signal, an igniter energization signal, a VVT (variable valve timing mechanism) actuator energization signal, and the like in accordance with instructions from the processors 3 and 4.

  Next, the processing operation of the microcontroller 1 will be described based on the flowcharts shown in FIGS.

  When the interrupt signal is generated at every 30 ° crank angle of the engine based on the crank angle synchronization signal, the interrupt signal is detected by the interrupt controllers 3a and 4a of the first and second processors 3 and 4. (ST1).

  Next, each of the processors 3 and 4 calculates the remainder of (CA / 30) / PNUM, and the calculated remainder is its own identification number (in this embodiment, the first processor 3 has an identification number of “0”, It is determined whether or not the two processors 4 are equal to the identification number “1”.) (ST2). Note that CA is a crank angle when an interrupt signal is detected, and PNUM is the number of processors (“2” in this embodiment). The crank angle at the time of detecting the interrupt signal is obtained from the crank angle synchronization signal.

  If an affirmative determination is made in ST2, crank angle synchronization processing (processing that requires calculation every 30 ° crank angle), for example, calculation processing relating to fuel injection control, ignition control, etc. is executed (ST3).

  Next, arithmetic processing other than crank angle synchronization processing (hereinafter also referred to as “crank angle asynchronous processing”), for example, arithmetic processing such as VVT control is executed (ST4). Then, after the crank angle synchronization process and the crank angle asynchronous process are completed, a transition is made to the idle state (idle) (ST5).

  On the other hand, if a negative determination is made in ST2, the processing procedure proceeds to ST5 without performing the processing of ST3 and ST4.

  FIG. 3 is a time chart showing the crank angle (crank angle), the crank angle synchronization signal, the processing content of the first processor 3, and the processing content of the second processor 4 when the engine (6-cylinder engine) is running at a low speed. . When an interrupt signal is generated at every crank angle of 30 ° by the interrupt signal generator 2, the processors 3 and 4 alternately process the interrupt routine. That is, an interrupt signal generated every 30 ° of crank angle is simultaneously detected by the interrupt controllers 3a and 4a of both processors 3 and 4, but when the determination of ST2 is executed in both processors 3 and 4, The processing of the interrupt routine is executed by either one of the processors 3 or 4.

  For example, when an interrupt signal generated when the crank angle is 0 ° is detected by the interrupt controllers 3a and 4a of both the processors 3 and 4, the arithmetic expressions (0/30) / 0 is calculated as the remainder of 2. The crank angle synchronization process ca and the crank angle asynchronous process ms are sequentially executed only by the first processor 3 to which the identification number 0 equal to the calculated value is assigned. In the figure, “idle” indicates that the processor is in an idle state.

  Further, when an interrupt signal generated when the crank angle is 30 ° is detected by the interrupt controllers 3a and 4a of both processors 3 and 4, the arithmetic expressions (30/30) / 2 described above in both processors 3 and 4 are detected. 1 is calculated as the remainder of. Then, only the second processor 4 to which the identification number 1 equal to the calculated value is assigned executes the crank angle synchronization process ca and the crank angle asynchronous process ms as an interrupt routine in order.

  Thereafter, the interrupt signals generated at the crank angles of 60 °, 90 °,... Are also detected by the interrupt controllers 3a and 4a of the processors 3 and 4, and 0, 1, 0, 1,... Are calculated in order. That is, the interrupt routine is alternately processed by the first controller 3 to which the identification number 0 is assigned and the second controller 4 to which the identification number 1 is assigned.

  Note that examples of the crank angle synchronization process ca executed alternately by the processors 3 and 4 include arithmetic processing related to fuel injection control of the first cylinder, arithmetic processing related to ignition control of the first cylinder, and processing of the second cylinder. Arithmetic processing related to fuel injection control, arithmetic processing related to ignition control of the second cylinder,... Arithmetic processing related to fuel injection control of the sixth cylinder, arithmetic processing related to ignition control of the sixth cylinder, and the like.

  FIG. 4 is a time chart showing the crank angle (crank angle), the crank angle synchronization signal, the processing contents of the first processor 3, and the processing contents of the second processor 4 when the engine is rotating at high speed. As shown in this figure, when the engine speed becomes high, the time of the idle state idle is reduced, and the processing time of the crank angle synchronization processing ca and the crank angle asynchronous processing ms is secured.

  Interrupt processes other than the crank angle synchronization process ca and the crank angle asynchronous process ms are processed by depriving the CPU execution right from the crank angle synchronization process ca or the crank angle asynchronous process ms or in an idle state, depending on the priority. .

  Also, as in this embodiment, when the number of crank angle synchronization signals generated in one cycle of engine control (24 in this embodiment) is divisible by the number of processors (2 in this embodiment), the number of cylinders 1 The crank angle synchronization process ca and the crank angle asynchronous process ms are executed by the same processor 3.

  As is apparent from the above description, according to the engine control apparatus of the present invention, it is possible to evenly distribute the processing load to the plurality of processors 3 and 4 regardless of the engine speed.

  As a result, the specifications of parts in the microcontroller 1 can be suppressed. For example, low frequency driving can be employed, thereby allowing low speed transistors to be employed. Further, by employing a low speed transistor, the cost of the parts of the microcontroller 1 can be reduced and the power consumption can be suppressed.

  Further, since the programs related to the crank angle synchronization process ca and the crank angle asynchronous process ms run sequentially, the synchronization control and exclusive control between the processors 3 and 4 can be reduced. Thereby, the reduction of design cost can also be expected.

  Further, since the programs related to the crank angle synchronization processing ca and the crank angle asynchronous processing ms are common to the processors 3 and 4, even when a new processor is added to the microcontroller 1, the amount of software change Is less.

  The present invention can be applied to a control device for an internal combustion engine equipped with a multiprocessor.

DESCRIPTION OF SYMBOLS 1 Microcontroller 2 Interrupt signal generation part 3 1st processor 3a Interrupt controller 4 2nd processor 4a Interrupt controller 11 Interrupt signal line

Claims (2)

In a control device for an internal combustion engine equipped with a multiprocessor,
A control apparatus for an internal combustion engine, characterized in that each processor includes a routine processing means for sequentially processing an interrupt routine in synchronization with a crank angle. The control apparatus for an internal combustion engine according to claim 1,
The routine processing means includes:
An interrupt signal generating means for generating an interrupt signal for each constant crank angle;
Interrupt routine execution availability determination means for determining whether or not to execute an interrupt routine based on the constant crank angle, the crank angle at the time of generation of the interrupt signal, and the assigned processor identification information, for each processor;
A control apparatus for an internal combustion engine, comprising:

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