JP2016127224A - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

Info

Publication number
JP2016127224A
JP2016127224A JP2015002052A JP2015002052A JP2016127224A JP 2016127224 A JP2016127224 A JP 2016127224A JP 2015002052 A JP2015002052 A JP 2015002052A JP 2015002052 A JP2015002052 A JP 2015002052A JP 2016127224 A JP2016127224 A JP 2016127224A
Authority
JP
Japan
Prior art keywords
layer
hard mask
barrier metal
semiconductor device
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015002052A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016127224A5 (https=
Inventor
紘司 原
Koji Hara
紘司 原
信貴 浮ケ谷
Nobutaka Ukigaya
信貴 浮ケ谷
武志 青木
Takeshi Aoki
武志 青木
康博 川端
Yasuhiro Kawabata
康博 川端
順也 玉木
Junya Tamaki
順也 玉木
紀彦 中田
Norihiko Nakata
紀彦 中田
聡志 小川
Satoshi Ogawa
聡志 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2015002052A priority Critical patent/JP2016127224A/ja
Priority to US14/967,815 priority patent/US9627319B2/en
Publication of JP2016127224A publication Critical patent/JP2016127224A/ja
Publication of JP2016127224A5 publication Critical patent/JP2016127224A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/269—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H10P76/2043—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/067—Manufacture or treatment of conductive parts of the interconnections by modifying the pattern of conductive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Drying Of Semiconductors (AREA)
JP2015002052A 2015-01-08 2015-01-08 半導体装置及び半導体装置の製造方法 Pending JP2016127224A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015002052A JP2016127224A (ja) 2015-01-08 2015-01-08 半導体装置及び半導体装置の製造方法
US14/967,815 US9627319B2 (en) 2015-01-08 2015-12-14 Semiconductor device and semiconductor device manufacturing method using patterning and dry etching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015002052A JP2016127224A (ja) 2015-01-08 2015-01-08 半導体装置及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2016127224A true JP2016127224A (ja) 2016-07-11
JP2016127224A5 JP2016127224A5 (https=) 2018-02-15

Family

ID=56359761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015002052A Pending JP2016127224A (ja) 2015-01-08 2015-01-08 半導体装置及び半導体装置の製造方法

Country Status (2)

Country Link
US (1) US9627319B2 (https=)
JP (1) JP2016127224A (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10109523B2 (en) 2016-11-29 2018-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cleaning wafer after CMP
US10510598B2 (en) 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned spacers and method forming same
DE102017118475B4 (de) * 2016-11-29 2022-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Selbstjustierte abstandshalter und verfahren zu deren herstellung
JP6878154B2 (ja) * 2017-06-05 2021-05-26 東京エレクトロン株式会社 エッチング方法およびエッチング装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196376A (ja) * 2000-01-14 2001-07-19 Seiko Epson Corp 半導体装置の製造方法
JP2001210648A (ja) * 2000-01-28 2001-08-03 Matsushita Electric Ind Co Ltd 電子デバイスの製造方法
JP2001358145A (ja) * 2000-06-12 2001-12-26 Matsushita Electric Ind Co Ltd 配線と配線形成方法及び半導体装置
JP2006147846A (ja) * 2004-11-19 2006-06-08 Renesas Technology Corp 半導体装置の製造方法
JP2009110986A (ja) * 2007-10-26 2009-05-21 Tokyo Electron Ltd エッチングマスクの形成方法、制御プログラム及びプログラム記憶媒体
JP2009277753A (ja) * 2008-05-13 2009-11-26 Fujitsu Microelectronics Ltd 半導体装置の製造方法
JP2009295734A (ja) * 2008-06-04 2009-12-17 Sharp Corp 半導体装置の製造装置及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548515B1 (ko) * 2003-07-09 2006-02-02 매그나칩 반도체 유한회사 반도체 소자의 금속 배선의 형성 방법
US7556989B2 (en) * 2005-03-22 2009-07-07 Samsung Electronics Co., Ltd. Semiconductor device having fuse pattern and methods of fabricating the same
KR100703025B1 (ko) * 2005-07-05 2007-04-06 삼성전자주식회사 반도체 장치에서 금속 배선 형성 방법.

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196376A (ja) * 2000-01-14 2001-07-19 Seiko Epson Corp 半導体装置の製造方法
JP2001210648A (ja) * 2000-01-28 2001-08-03 Matsushita Electric Ind Co Ltd 電子デバイスの製造方法
JP2001358145A (ja) * 2000-06-12 2001-12-26 Matsushita Electric Ind Co Ltd 配線と配線形成方法及び半導体装置
JP2006147846A (ja) * 2004-11-19 2006-06-08 Renesas Technology Corp 半導体装置の製造方法
JP2009110986A (ja) * 2007-10-26 2009-05-21 Tokyo Electron Ltd エッチングマスクの形成方法、制御プログラム及びプログラム記憶媒体
JP2009277753A (ja) * 2008-05-13 2009-11-26 Fujitsu Microelectronics Ltd 半導体装置の製造方法
JP2009295734A (ja) * 2008-06-04 2009-12-17 Sharp Corp 半導体装置の製造装置及びその製造方法

Also Published As

Publication number Publication date
US20160204068A1 (en) 2016-07-14
US9627319B2 (en) 2017-04-18

Similar Documents

Publication Publication Date Title
KR100600689B1 (ko) 반도체 장치의 제조 방법
KR101030299B1 (ko) 반도체 소자 및 그의 제조 방법
US9627319B2 (en) Semiconductor device and semiconductor device manufacturing method using patterning and dry etching
US9287228B2 (en) Method for etching semiconductor structures and etching composition for use in such a method
US20180331044A1 (en) Semiconductor device and fabrication method thereof
US8253254B2 (en) Semiconductor device and manufacturing method thereof
CN112838048A (zh) 互连结构以及其制作方法
US7622331B2 (en) Method for forming contacts of semiconductor device
CN120690686A (zh) 金属导电结构的制造方法和半导体器件的制造方法
CN114695252A (zh) 一种金属层的形成方法
US7384823B2 (en) Method for manufacturing a semiconductor device having a stabilized contact resistance
US20150380298A1 (en) Air-Gap Assisted Etch Self-Aligned Dual Damascene
US6576563B2 (en) Method of manufacturing a semiconductor device employing a fluorine-based etch substantially free of hydrogen
KR100866683B1 (ko) 반도체 소자의 캐패시터 형성 방법
US20180350663A1 (en) Method of forming semiconductor device
KR101043734B1 (ko) 반도체 소자 제조 방법
KR100639205B1 (ko) 반도체 소자의 제조방법
US7901976B1 (en) Method of forming borderless contacts
KR100814259B1 (ko) 반도체 소자의 제조 방법
KR20100075067A (ko) 반도체 소자의 금속 구조물 재형성 방법
KR20090056333A (ko) 이미지 센서 및 그의 제조 방법
KR100802311B1 (ko) 씨모스 이미지 센서의 제조방법
KR100701779B1 (ko) 반도체 소자의 콘택 형성 방법
TWI524377B (zh) 一種半導體積體電路之製作方法
US20100167530A1 (en) Method for forming metal line of semiconductor device

Legal Events

Date Code Title Description
RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20171214

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180105

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180105

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20180126

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180928

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20181101

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20181226

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20190530