JP2016111233A - Thin film transistor and manufacturing method of thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor or the like of which characteristics is stable and which has high reliability.SOLUTION: A thin film transistor 1 comprises: a gate electrode 30; an oxide semiconductor layer 50 facing to the gate electrode 30; a gate insulation layer 40 that is disposed between the gate electrode 30 and the oxide semiconductor layer 50; and a source electrode 70S and a drain electrode 70D which are electrically connected to the oxide semiconductor layer 50. The oxide semiconductor layer 50 is constructed by an oxide including at least indium and silicon and includes a first region and a second region that is a region separated from the gate insulation layer 40 than the first region, and concentration of the silicon of the first region is higher than that of the second region.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a thin film transistor and a method for manufacturing the thin film transistor, and more particularly to a thin film transistor using an oxide semiconductor and a method for manufacturing the thin film transistor.

  In general, an active matrix type display such as a liquid crystal display device or an organic EL (Electro Luminescence) display device includes a plurality of thin film transistors (TFTs).

  In recent years, it has been proposed to use an oxide semiconductor as a material for a semiconductor layer (channel layer) of a thin film transistor. An oxide semiconductor is known to have excellent characteristics such as high mobility and deposition on a large-area substrate at a low temperature. For this reason, development of an oxide semiconductor TFT using an oxide semiconductor for a channel layer has been actively performed. As an example of the oxide semiconductor, InGaZnO (Non-Patent Document 1), InSiO (Non-Patent Document 2), or the like can be given.

H.Omura, H.Kumomi, K.Nomura, T.Kamiya, M.Hirano and H.Hosono, J.Appl.Phys., 105, 93712 (2009) N. Mitoma, S. Aikawa, X. Gao, T. Kizu, M. Shimizu, M.-F. Lin, T. Nabatame and K. Tsukagozhi, Appl. Phys. Lett., 104, 102103 (2014)

  A TFT using InSiO as an oxide semiconductor is obtained by adding silicon (Si) having a large binding energy with oxygen to indium oxide (InO) to stabilize the characteristics. Experiments revealed that even TFTs using InSiO have the same resistance to hydrogen (hydrogen resistance) as TFTs using IGZO. Therefore, it is necessary to take measures to suppress the influence of hydrogen even for TFTs using InSiO.

  The present invention has been made to solve such problems, and an object thereof is to provide a thin film transistor having stable characteristics and high reliability, and a method for manufacturing the same.

  In order to achieve the above object, a thin film transistor according to one embodiment of the present invention is provided between a gate electrode, an oxide semiconductor layer facing the gate electrode, and the gate electrode and the oxide semiconductor layer. A gate insulating layer; and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein the oxide semiconductor layer includes an oxide containing at least indium and silicon, And a second region which is a region farther from the gate insulating layer than the first region, and the first region has a silicon concentration higher than that of the second region.

  According to the present invention, since excellent hydrogen resistance is maintained while maintaining excellent TFT characteristics, a thin film transistor having stable characteristics and high reliability can be realized.

It is sectional drawing which shows typically the structure of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the board | substrate preparation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the undercoat layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the gate electrode formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the gate insulating layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the oxide semiconductor layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the protective layer formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the contact hole formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is sectional drawing which shows typically the structure of the source / drain electrode formation process in the manufacturing method of the thin-film transistor which concerns on embodiment. It is a figure which shows the relationship between the silicon concentration of an InSiO film, and the sheet resistance of an InSiO film. FIG. 10 is a diagram for describing a mechanism by which carriers are generated in an oxide semiconductor film by hydrogen. FIG. 10 is a diagram for describing a mechanism in which carriers are not generated by silicon contained in an oxide semiconductor film even when hydrogen enters the oxide semiconductor film. It is a partially cutaway perspective view of an organic EL display device according to an embodiment. FIG. 6 is an electric circuit diagram of a pixel circuit in the organic EL display device shown in FIG. 5. It is sectional drawing which shows typically the structure of the thin-film transistor which concerns on a modification.

<Outline of One Embodiment of the Present Invention>
Although the details will be described later, as a result of investigating the relationship between the silicon concentration of the InSiO film and the TFT characteristics or hydrogen resistance by a follow-up experiment by the inventors, the TFT using InSiO is turned on when the silicon concentration in InSiO is increased. Although the current decreased, the inventors found out that the resistance to hydrogen is improved.

  A thin film transistor according to one embodiment of the present invention uses such a feature, and includes a gate electrode, an oxide semiconductor layer facing the gate electrode, and the gate electrode and the oxide semiconductor layer. A gate insulating layer and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, and the oxide semiconductor layer is made of an oxide containing at least indium and silicon. The first region has a second region that is farther from the gate insulating layer than the first region, and the first region has a higher silicon concentration than the second region.

  According to the above configuration, the region on the front channel side in the oxide semiconductor layer made of InSiO (the first region closer to the gate insulating layer) is the region on the back channel side in the oxide semiconductor layer (the first region separated from the gate insulating layer). The silicon concentration is higher than that in (2 region).

  Accordingly, hydrogen resistance in a region on the front channel side of the oxide semiconductor layer is improved, so that the influence of hydrogen from the front channel side can be suppressed. For example, damage caused by hydrogen diffusing from the gate insulating layer can be suppressed.

  Further, by making the silicon concentration in the region on the back channel side lower than the silicon concentration in the region on the front channel side, the resistance value in the region on the back channel side of the oxide semiconductor layer can be lowered, so that the ON current can be maintained. Good contact between the source and drain electrodes and the oxide semiconductor layer can be expected.

  As described above, in the oxide semiconductor layer made of InSiO, the silicon concentration in the region on the front channel side is higher than that on the region on the back channel side, thereby ensuring excellent hydrogen resistance while maintaining excellent TFT characteristics. Therefore, a highly reliable TFT having stable characteristics can be realized.

  In the thin film transistor according to one embodiment of the present invention, the oxide semiconductor layer includes a first semiconductor layer formed as the first region and a second semiconductor layer formed as the second region. It is good to be.

  With this configuration, hydrogen resistance can be ensured by the first semiconductor layer having a relatively high silicon concentration. In addition, when the oxide semiconductor layer has a stacked structure, the second semiconductor layer and the first semiconductor layer can be formed by continuous film formation by sputtering or the like. Thereby, the production line equipment (existing equipment) of silicon TFTs for liquid crystal displays can be used, and the production cost and production tact can be suppressed.

  In the thin film transistor according to one embodiment of the present invention, the silicon concentration of the first semiconductor layer is preferably 6.5 at% or more.

  Thereby, effective hydrogen tolerance can be ensured in the first semiconductor layer. Therefore, the entry of hydrogen from the front channel side can be effectively suppressed.

  In the thin film transistor according to one embodiment of the present invention, the silicon concentration of the first semiconductor layer is preferably 11.7 at% or more.

  Thereby, the hydrogen tolerance in the first semiconductor layer is dramatically improved. Therefore, the entry of hydrogen from the front channel side can be further suppressed.

  In the thin film transistor according to one embodiment of the present invention, the silicon concentration of the second semiconductor layer is preferably less than 6.5 at%.

  Accordingly, a low resistance region can be formed in the oxide semiconductor layer, so that the ON current can be easily maintained.

  In the thin film transistor according to one embodiment of the present invention, the silicon concentration of the oxide semiconductor layer is preferably higher than the hydrogen concentration contained in the oxide semiconductor layer.

  Thereby, the influence of hydrogen can be further suppressed, so that a TFT having stable characteristics can be obtained.

  In the thin film transistor according to one embodiment of the present invention, the thickness of the first semiconductor layer is preferably 5 nm or more.

  Thereby, the effect which can suppress entry of hydrogen can fully be exhibited. Therefore, a TFT having stable characteristics can be obtained.

  In the thin film transistor according to one embodiment of the present invention, the thickness of the second semiconductor layer is preferably 15 nm or more.

  Accordingly, a sufficiently low resistance region can be secured in the oxide semiconductor layer, so that the ON current can be more easily maintained.

  In the thin film transistor according to one embodiment of the present invention, the oxide semiconductor layer preferably has a thickness of 20 nm or more.

  Thereby, a sufficient channel region can be ensured, so that a TFT having excellent characteristics can be realized. In addition, a processing process (patterning) of the oxide semiconductor layer is sufficiently possible. Furthermore, since the thickness of the first semiconductor layer can be increased to 20 nm or more by setting the thickness of the oxide semiconductor layer to 20 nm or more, even when hydrogen diffuses by annealing treatment or the like, The first semiconductor layer having a high silicon concentration can effectively block entry of hydrogen into the oxide semiconductor layer.

  In the thin film transistor according to one embodiment of the present invention, the silicon concentration in the oxide semiconductor layer is preferably increased continuously as it approaches the interface on the gate insulating layer side.

  Thus, the composition of the oxide semiconductor layer continuously changes, so that defects in the bulk of the oxide semiconductor layer can be suppressed. In addition, defects (interface states) at the interface between the oxide semiconductor layer and the gate insulating layer can be reduced. Therefore, a TFT having further excellent characteristics can be obtained.

  In the thin film transistor according to one embodiment of the present invention, the gate electrode, the gate insulating layer, and the oxide semiconductor layer are stacked over the substrate in this order, and the source electrode and the drain electrode are formed using the oxidation electrode. It may be formed above the physical semiconductor layer.

  With this configuration, the consistency with the production line equipment (existing equipment) of the silicon TFT is increased, so that the production cost can be suppressed.

  In the thin film transistor according to one embodiment of the present invention, a protective layer may be further provided over the oxide semiconductor layer.

  Accordingly, process damage in the region on the back channel side of the oxide semiconductor layer can be reduced. For example, the surface of the oxide semiconductor layer on the back channel side is not exposed in the etching process. For this reason, a TFT having uniform characteristics in the plane can be obtained.

  In the thin film transistor according to one embodiment of the present invention, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in this order on the substrate, and the source electrode and the drain electrode are formed on the gate. The oxide semiconductor layer may be connected to a contact hole formed in the insulating layer.

  With this configuration, the TFT size can be reduced, so that high definition can be achieved. In addition, the parasitic capacitance can be reduced.

  The method for manufacturing a thin film transistor according to one embodiment of the present invention includes a step of forming a gate electrode, a step of forming an oxide semiconductor layer facing the gate electrode, and the gate electrode and the oxide semiconductor layer. A step of forming a gate insulating layer therebetween, and a step of forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein the oxide semiconductor layer includes an oxide containing at least indium and silicon. The first region has a second region that is farther from the gate insulating layer than the first region, and the first region has a higher silicon concentration than the second region.

  Thereby, it is possible to suppress the influence of hydrogen from the back channel side, and it is possible to maintain the excellent TFT characteristics by suppressing the decrease in the ON current. Therefore, a TFT having stable characteristics can be manufactured with a high yield.

<Embodiment>
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Each of the embodiments described below shows a specific example of the present invention. Accordingly, the numerical values, shapes, materials, components, arrangement positions and connection forms of components, steps (steps), order of steps, and the like shown in the following embodiments are merely examples and are intended to limit the present invention. is not. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements.

  Each figure is a schematic diagram and is not necessarily illustrated strictly. Moreover, in each figure, the same code | symbol is attached | subjected about the substantially same component, and the overlapping description is abbreviate | omitted or simplified.

(Thin film transistor structure)
First, a thin film transistor 1 according to an embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor according to an embodiment. FIG. 1 shows a TFT array substrate, and two thin film transistors 1 are shown in FIG.

  As shown in FIG. 1, the thin film transistor 1 is a bottom-gate oxide semiconductor TFT having an oxide semiconductor layer as a channel layer. The thin film transistor 1 in this embodiment is a channel protection type and employs a top contact structure.

  The thin film transistor 1 includes a substrate 10, an undercoat layer 20, a gate electrode 30, a gate insulating layer 40, an oxide semiconductor layer 50, a protective layer 60, a source electrode 70S, and a drain electrode 70D.

  Hereinafter, each component of the thin film transistor 1 according to the present embodiment will be described in detail.

  The substrate 10 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistant glass. The substrate 10 is not limited to a glass substrate. For example, polyimide, polyamide, polyamideimide, polyester, polycarbonate, polymethyl methacrylate, polyurea, polyacetal, polyetherketone, polyetheretherketone, polyetherimide, polyarylate, etc. It may be a plastic substrate (resin substrate) made of a plastic material.

  The substrate 10 may not be a rigid substrate but a flexible substrate (film substrate) having flexibility. Alternatively, a glass substrate may be used as a support substrate, and a plastic material such as polyimide may be formed thereon.

  The undercoat layer 20 is formed on the substrate 10. By forming the undercoat layer 20, it is possible to prevent impurities such as sodium and phosphorus contained in the substrate 10 (glass substrate) or moisture transmitted from the atmosphere from entering the oxide semiconductor layer 50. be able to. The undercoat layer 20 also plays a role of reducing the influence of heat on the substrate 10 in a high-temperature heat treatment process such as laser annealing.

The undercoat layer 20 is a single-layer insulating layer or a laminated insulating layer using an oxide insulating layer or a nitride insulating layer. As an example, the undercoat layer 20 includes a single layer film such as silicon nitride (SiN _x ), silicon oxide (SiO _y ), silicon oxynitride (SiO _y N _x ), or aluminum oxide (AlO _x ), or these A laminated film can be used. The film thickness of the undercoat layer 20 is, for example, about 100 nm to 2000 nm. Note that the undercoat layer 20 is not necessarily formed.

  The gate electrode 30 is located above the substrate 10 and is formed above the substrate 10, for example. In the present embodiment, the gate electrode 30 is patterned in a predetermined shape on the undercoat layer 20. The gate electrode 30 is made of a conductive material and has a single layer structure or a multilayer structure. For example, a metal or an alloy can be used as the conductive material. Examples of the metal or alloy include molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), niobium (Nb), nickel (Ni), titanium (Ti), chromium ( Cr), molybdenum tungsten (MoW), or the like can be used. The film thickness of the gate electrode 2 is, for example, about 20 nm to 500 nm.

  The gate insulating layer 40 is disposed between the gate electrode 30 and the oxide semiconductor layer 50. In the present embodiment, the gate insulating layer 40 is formed at least above the gate electrode 30. Specifically, the gate insulating layer 40 is formed on the entire surface of the undercoat layer 20 so as to cover the gate electrode 30.

The gate insulating layer 40 is made of an electrically insulating material and has a single layer structure or a multilayer structure. Examples of the electrically insulating material include silicon oxide (SiO _y ), silicon nitride (SiN _x ), silicon oxynitride (SiO _y N _x ), aluminum oxide (AlO _z ), and tantalum oxide (TaO _w ). it can. In the present embodiment, the gate insulating layer 40 is, for example, a stacked film of a silicon oxide film and a silicon nitride film. The film thickness of the gate insulating layer 40 can be designed in consideration of the breakdown voltage of the TFT, and is, for example, about 50 nm to 500 nm.

  The oxide semiconductor layer 50 is formed in a predetermined shape over the gate insulating layer 40. The oxide semiconductor layer 50 is used as a channel layer and faces the gate electrode. That is, the oxide semiconductor layer 50 is a semiconductor layer including a region (channel region) facing the gate electrode 30 with the gate insulating layer 40 interposed therebetween.

  As a material of the oxide semiconductor layer 50, for example, a transparent amorphous oxide semiconductor (TAOS) is used. Specifically, it includes an oxide containing at least indium (In) and silicon (Si). In this embodiment, the oxide semiconductor layer 50 contains indium (In), silicon (Si), and oxygen (O), and is composed of InSiO (ISO). The transparent amorphous oxide semiconductor not only has the property of having high mobility, but can be formed at a low temperature, and thus is useful when a plastic material is used as the material of the substrate 10.

  The oxide semiconductor layer 50 includes a first region and a second region that is a region farther from the gate insulating layer 40 than the first region, and the first region has a higher silicon concentration than the second region. ing. That is, the oxide semiconductor layer 50 has a higher silicon concentration in the region on the gate insulating layer 40 side than in the region on the side opposite to the gate insulating layer 40 side (protective layer 60 side). Specifically, a region of the oxide semiconductor layer 50 adjacent to the gate insulating layer 40 (first region) has a silicon concentration higher than that of a region of the oxide semiconductor layer 50 spaced apart from the gate insulating layer 40 (second region). It is high.

  In this embodiment, the oxide semiconductor layer 50 has a stacked structure, for example, a first semiconductor layer 51 formed as a first region closer to the gate insulating layer 40 in the oxide semiconductor layer 50, and an oxide The semiconductor layer 50 has a two-layer structure with a second semiconductor layer 52 formed as a second region far from the gate insulating layer 40. Specifically, the oxide semiconductor layer 50 includes a first semiconductor layer 51 and a second semiconductor layer 52 formed on the first semiconductor layer 51.

  The first semiconductor layer 51 is a high silicon concentration layer having a silicon concentration (Si concentration) higher than that of the second semiconductor layer 52. The first semiconductor layer 51 is a layer on the side of the gate insulating layer 40 in the oxide semiconductor layer 50 (relatively closer to the gate insulating layer 40). In the present embodiment, the first semiconductor layer 51 is a layer below the oxide semiconductor layer 50 ( Lower area).

  On the other hand, the second semiconductor layer 52 is a low silicon concentration layer having a silicon concentration (Si concentration) lower than that of the first semiconductor layer 51. The second semiconductor layer 52 is a layer on the protective layer 60 side (relatively far from the gate insulating layer 40) in the oxide semiconductor layer 50. In the present embodiment, the second semiconductor layer 52 is an upper layer (upper part) of the oxide semiconductor layer 50. Area).

  As described above, in the oxide semiconductor layer 50, the silicon concentration of the first semiconductor layer 51 is higher than the silicon concentration of the second semiconductor layer 52. Although details will be described later, by using the first semiconductor layer 51 having a high silicon concentration, excellent hydrogen resistance can be realized in the upper first semiconductor layer 51. Thereby, the influence of hydrogen from the front channel side (protective layer 60 side) can be suppressed.

  The silicon concentration of the first semiconductor layer 51 is preferably 6.5 at% or more, and preferably 11.7 at% or more. Thereby, since the hydrogen tolerance in the first semiconductor layer 51 is dramatically improved, the influence of hydrogen from the front channel side can be further suppressed.

  Further, the silicon concentration of the second semiconductor layer 52 is preferably less than 6.5 at%. Accordingly, a low resistance region can be formed in the oxide semiconductor layer 50, so that the ON current can be easily maintained.

  As an example, the silicon concentration of the first semiconductor layer 51 is 11.7 at%, and the silicon concentration of the second semiconductor layer 52 is 6.5 at%, but is not limited thereto.

  The first semiconductor layer 51 and the second semiconductor layer 52 are composed of the same element, and both are made of InSiO (InSiO film). In the first semiconductor layer 51 and the second semiconductor layer 52, silicon is mixed in a chemically bonded state.

  The film thickness of the first semiconductor layer 51 is preferably 5 nm or more. Thereby, the first semiconductor layer 51 can sufficiently exert the hydrogen resistance in the oxide semiconductor layer 50. Therefore, the entry of hydrogen can be effectively suppressed.

  The film thickness of the second semiconductor layer 52 is preferably 15 nm or more. Accordingly, a sufficiently low resistance region can be secured in the oxide semiconductor layer 50, so that the ON current can be more easily maintained.

  The total film thickness of the oxide semiconductor layer 50 is preferably 20 nm or more. Thereby, a sufficient channel region can be ensured, so that a TFT having excellent characteristics can be realized. In addition, when the thickness of the oxide semiconductor layer 50 is set to 20 nm or more, the processing process of the oxide semiconductor layer 50 can be sufficiently performed. That is, the oxide semiconductor layer 50 can be easily formed by sputtering or the like and patterned by a photolithography method, an etching method, or the like.

  Further, by setting the thickness of the first semiconductor layer 51 to 20 nm or more, even if hydrogen is diffused by an annealing process or the like, the first semiconductor layer 51 having a high silicon concentration causes the oxide semiconductor layer 50 to have hydrogen. Can be effectively blocked. For example, damage caused by hydrogen diffusing from the gate insulating layer 40 side can be suppressed.

  The silicon concentration of the entire oxide semiconductor layer 50 is preferably higher than at least the hydrogen concentration contained in the entire oxide semiconductor layer 50. Thereby, the influence of hydrogen can be further suppressed.

  The protective layer 60 is formed on the oxide semiconductor layer 50. The protective layer 60 is a channel etching stopper (CES) that protects the channel region in order to prevent the channel region of the oxide semiconductor layer 50 from being etched in the etching process when forming the source electrode 70S and the drain electrode 70D. ) Function as a layer. Accordingly, process damage on the back channel side of the oxide semiconductor layer 50 can be reduced in the bottom-gate TFT. In the present embodiment, the protective layer 60 is an interlayer insulating layer formed on the entire surface of the substrate 10.

  The protective layer 60 is made of an insulating material having an insulating property. As a material of the protective layer 60, for example, a material mainly composed of oxide or oxynitride can be used. As a material containing oxide or oxynitride as a main component, for example, an inorganic substance such as silicon oxide, silicon oxynitride, aluminum oxide, or yttrium oxide can be used. Note that silicon oxide has a lower hydrogen content than silicon nitride. Therefore, by using silicon oxide as the protective layer 60, it is possible to suppress deterioration in characteristics of the oxide semiconductor layer 50 due to hydrogen. Further, the protective layer 60 may have a single layer structure or a laminated structure. In the case of a stacked structure, aluminum oxide has a function of blocking hydrogen and oxygen, and thus, for example, a three-layer stacked structure of silicon oxide, aluminum oxide, and silicon oxide is preferable.

  The material of the protective layer 60 is not limited to an inorganic material, and may be a material mainly composed of an organic material.

  In addition, an opening (contact hole) is formed in the protective layer 60 so as to penetrate a part of the protective layer 60. The oxide semiconductor layer 50 is connected to the source electrode 70S and the drain electrode 70D through the opening of the protective layer 60.

  The source electrode 70S and the drain electrode 70D are formed on the protective layer 60 in a predetermined shape. The source electrode 70 </ b> S and the drain electrode 70 </ b> D are arranged so as to face each other in the horizontal direction of the substrate with a space therebetween, and are electrically connected to the oxide semiconductor layer 50 through openings formed in the protective layer 60. .

  The source electrode 70S and the drain electrode 70D are each made of a conductive material and have a single layer structure or a multilayer structure. For example, a metal or an alloy can be used as the conductive material. As the metal or alloy, for example, aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), titanium (Ti), chromium (Cr), molybdenum tungsten (MoW), or the like can be used. . In the present embodiment, the source electrode 70S and the drain electrode 70D have a three-layer structure of MoW / Al / MoW. The film thickness of the source electrode 70S and the drain electrode 70D can be, for example, about 100 nm to 500 nm.

  Further, the arrangement position of the source electrode 70S and the drain electrode 70D is not limited to the position illustrated in FIG. 1, and may be any position where the source electrode 70S and the drain electrode 70D and the oxide semiconductor layer 50 are electrically connected. Good.

  Although not shown, a passivation layer may be formed in the shape of the protective layer 60 so as to cover the source electrode 70S and the drain electrode 70D. The film thickness of the passivation layer 9 can be, for example, 20 nm or more and 1000 nm or less. The passivation layer 9 is an insulating film made of an inorganic material such as silicon oxide or silicon nitride, and can be formed by plasma CVD (Chemical Vapor Deposition), for example.

(Thin Film Transistor Manufacturing Method)
Next, a method for manufacturing the thin film transistor 1 according to the embodiment will be described with reference to FIGS. 2A to 2H are cross-sectional views schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to the embodiment.

  The manufacturing method of the thin film transistor 1 according to the present embodiment includes a substrate preparation step for preparing the substrate 10, an undercoat layer formation step for forming the undercoat layer 20, a gate electrode formation step for forming the gate electrode 30, and a gate. Gate insulating layer forming step for forming insulating layer 40, oxide semiconductor layer forming step for forming oxide semiconductor layer 50 including first semiconductor layer 51 and second semiconductor layer 52, and protection for forming protective layer 60 A layer forming step, a contact hole forming step of forming a contact hole in the protective layer 60, and a source / drain electrode forming step of forming the source electrode 70S and the drain electrode 70D. After that, a passivation layer forming step for forming a passivation layer may be included as necessary.

  Hereafter, each process of the manufacturing method of the thin-film transistor 1 in this Embodiment is demonstrated in detail.

  First, as shown in FIG. 2A, a substrate 10 is prepared. For example, a glass substrate is prepared as the substrate 10.

  Next, as shown in FIG. 2B, an undercoat layer 20 is formed on the substrate 10. An undercoat layer 20 composed of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like is formed on the substrate 10 by plasma CVD or the like.

  Next, as shown in FIG. 2C, a gate electrode 30 having a predetermined shape is formed above the substrate 10. In the present embodiment, after a metal film (gate metal film) is formed on the undercoat layer 20 by sputtering, the metal film is processed using a photolithography method and a wet etching method to be patterned into a predetermined shape. A gate electrode 30 was formed.

Next, as illustrated in FIG. 2D, the gate insulating layer 40 is formed so as to cover the gate electrode 30. As a method for forming the gate insulating layer 40, for example, a plasma CVD method or the like can be used. As an example, when a silicon nitride film is formed as the gate insulating layer 40 by plasma CVD, a silicon nitride film is obtained by using silane gas (SiH ₄ ), ammonia gas (NH ₃ ), and nitrogen gas (N ₂ ) as an introduction gas. Can be formed.

  Next, as illustrated in FIG. 2E, an oxide semiconductor layer 50 having a predetermined shape is formed above the gate insulating layer 40 so as to face at least the gate electrode 30. In this embodiment, the oxide semiconductor layer 50 including the first semiconductor layer 51 and the second semiconductor layer 52 is formed in an island shape over the gate insulating layer 40.

  Specifically, an InSiO film having a high silicon concentration is formed on the gate insulating layer 40, and then an InSiO film having a low silicon concentration is formed, and then the oxide semiconductor layer 50 having a predetermined shape is formed. Then, a laminated film of an InSiO film having a high silicon concentration and an InSiO film having a low silicon concentration is processed.

As a method for forming the InSiO film, for example, a sputtering method can be used. For example, using a target material containing indium, silicon and oxygen, an argon (Ar) gas as an inert gas and a gas containing oxygen (O ₂ ) as a reactive gas flow into a vacuum chamber. By applying a power density voltage to the target material, an InSiO film can be formed. In this case, as a method for forming InSiO films having different compositions (InSiO films having different Si concentrations), for example, films are sequentially formed in the same chamber using targets made of InSiO having different compositions (InSiO having different Si concentrations). A method of controlling the composition by using a target of In ₂ O ₃ and SiO ₂ , changing the power ratio applied to each target, and simultaneously performing sputter deposition is conceivable.

  Moreover, as a processing method of the laminated film, for example, a photolithography method and an etching method can be used. Specifically, first, a resist having a predetermined shape is formed on a laminated film of InSiO films having different compositions, and the laminated film in a region where the resist is not formed is removed by wet etching, whereby the first semiconductor layer 51 and An island-shaped oxide semiconductor layer 50 including the second semiconductor layer 52 can be formed.

  Next, as illustrated in FIG. 2F, the protective layer 60 is formed so as to cover the oxide semiconductor layer 50. The protective layer 60 is made of, for example, a material mainly composed of oxide or oxynitride, and can be formed using a plasma CVD method. In addition, when forming aluminum oxide or yttrium oxide as the protective layer 60, you may form using sputtering method.

  After that, by performing heat treatment (annealing) as necessary, oxygen defects existing in the oxide semiconductor layer 50 can be complemented, and TFT characteristics can be stabilized. For example, heat treatment may be performed in the air (in an oxygen atmosphere) for 1 hour at a temperature of 300 ° C. to 350 ° C.

  As a heat treatment method, for example, a hot plate, a furnace, laser irradiation, or infrared irradiation can be used. The heat treatment also serves as stabilization treatment of the oxide semiconductor layer by applying energy. The stabilization method is not limited to heat treatment, and the same effect can be obtained by, for example, ultraviolet irradiation or X-ray irradiation. Note that the heat treatment for supplementing oxygen defects in the oxide semiconductor layer 50 (a step for stabilizing the oxide semiconductor layer 50) is performed after the source electrode 70S and the drain electrode 70D are formed, or a subsequent passivation layer. You may carry out after forming.

Next, as illustrated in FIG. 2G, a contact hole CH (opening) is formed in the protective layer 60 so that a part of the oxide semiconductor layer 50 is exposed. Specifically, a part of the protective layer 60 is removed by etching by a photolithography method and an etching method, so that an opening is formed on a connection portion between the source electrode 70S and the drain electrode 70D in the oxide semiconductor layer 50. For example, when the protective layer 60 is a silicon oxide film, the contact hole CH can be formed in the silicon oxide film by a dry etching method using a reactive ion etching (RIE) method. In this case, for example, carbon tetrafluoride (CF ₄ ) and oxygen gas (O ₂ ) can be used as the etching gas.

  Next, as illustrated in FIG. 2H, the source electrode 70 </ b> S and the drain electrode 70 </ b> D connected to the oxide semiconductor layer 50 through the contact hole CH formed in the protective layer 60 are formed. In the present embodiment, for example, after forming a metal film (source / drain metal film) on the protective layer 60 so as to fill the contact hole CH formed in the protective layer 60, the metal is formed by photolithography and wet etching. By processing the film, a source electrode 70S and a drain electrode 70D patterned into a predetermined shape were formed. In this wet etching, the protective layer 60 functions as an etching protective layer.

  Although not shown, a passivation layer may be formed so as to cover the whole. For example, a passivation layer made of silicon nitride, silicon oxide, or the like may be formed on the protective layer 60, the source electrode 70S, and the drain electrode 70D by plasma CVD or the like.

(Function and effect)
Next, functions and effects of the thin film transistor 1 according to this embodiment will be described including the background to the arrival of one embodiment of the present invention.

  A TFT using InGaZnO (IGZO), which is a typical oxide semiconductor, is easily affected by hydrogen, and there is a problem in that TFT characteristics fluctuate during the process during TFT fabrication or during driving after TFT fabrication. is there.

  On the other hand, a TFT using InSiO as an oxide semiconductor is obtained by adding silicon (Si) having a large binding energy with oxygen to indium oxide to stabilize characteristics.

  The inventors conducted a further experiment on the relationship between the silicon concentration of the InSiO film and the hydrogen resistance in realizing the TFT using InSiO.

  Specifically, the inventors of the present invention have four types of InSiO films (30 nm) having different compositions with silicon concentrations of 0.1 at%, 3.3 at%, 6.5 at%, and 11.7% as oxide semiconductor films. Is formed on a glass substrate (6 inch wafer), and a silicon nitride film (SiN: H) containing hydrogen is formed on these InSiO films via a silicon oxide film (SiO film). Resistance was evaluated. The result is shown in FIG.

  FIG. 3 is a diagram showing the relationship (silicon concentration dependence) between the silicon concentration of the InSiO film and the sheet resistance of the InSiO film, and shows the relationship between the silicon concentration of the InSiO film and the hydrogen resistance. That is, FIG. 3 shows the sheet resistance of the InSiO film after the resistance is lowered under the influence of hydrogen of the silicon nitride film. Note that FIG. 3 also illustrates the case where an IGZO film is used as the oxide semiconductor layer for comparison. Further, the sheet resistance of each InSiO film in FIG. 3 is an average value of the sheet resistances at nine points on the wafer.

  As shown in FIG. 3, it was found that the sheet resistance of the InSiO film having a silicon concentration of 0.1 at% and 3.3 at% decreased to about 1 kΩ after the silicon nitride film was formed. It was also found that the InSiO film having a silicon concentration of 3.3 at% suffers hydrogen damage to the same extent as the IGZO film.

  On the other hand, when the silicon concentration in the InSiO film is 6.5 at% or more, the sheet resistance decreases only to about 2 kΩ after the silicon nitride film is formed, and the decrease in the sheet resistance is suppressed and the hydrogen resistance is improved. It was.

  Furthermore, it was found that when the silicon concentration was 11.7 at% or more, the sheet resistance decreased only to around 26 kΩ even after the silicon nitride film was formed, and the decrease in sheet resistance was remarkably suppressed, and the hydrogen resistance was dramatically improved. .

  Here, the influence of hydrogen in the oxide semiconductor film and the effect of improving the hydrogen resistance due to silicon will be described with reference to FIGS. 4A and 4B. 4A is a diagram for describing a mechanism in which carriers are generated in an oxide semiconductor film by hydrogen, and FIG. 4B is a diagram illustrating carriers in silicon contained in an oxide semiconductor film even when hydrogen enters the oxide semiconductor film. It is a figure for demonstrating the mechanism which does not generate | occur | produce.

  As illustrated in FIG. 4A, when hydrogen diffuses and hydrogen enters the oxide semiconductor film, the hydrogen acts as a donor in the oxide semiconductor film. That is, invaded hydrogen is bonded (Metal-O-H (i)) to a state in which the metal included in the oxide semiconductor film and oxygen are bonded, and electrons are released from the hydrogen. As a result, the sheet resistance of the oxide semiconductor film is considered to decrease.

  On the other hand, as shown in FIG. 4B, the hydrogen resistance of the InSiO film having a high silicon concentration is improved by containing silicon in the oxide semiconductor film so that the hydrogen termination site changes from oxygen to silicon (Metal). -O-Si-H). Here, it is generally known that the Si—H bond is electrically inactive. For this reason, in the InSiO film containing silicon, since silicon supplements hydrogen, carriers are not released from hydrogen. As a result, it is assumed that the sheet resistance of the oxide semiconductor film does not decrease.

  From this mechanism, in FIG. 3, when the silicon concentration in the InSiO film is 0.1 at% and 3.3 at%, the sheet resistance greatly decreases in the InSiO film rather than the amount of hydrogen diffused from the silicon nitride. This is presumably because the amount of silicon present in the silicon was small.

  On the other hand, when the silicon concentration in the InSiO film becomes 6.5 at%, the decrease in sheet resistance is suppressed because there is a large amount of silicon present in the InSiO film. In particular, at 11.7 at%, the decrease in sheet resistance is dramatically suppressed because the amount of silicon present in the InSiO film is sufficient relative to the amount of hydrogen diffusing from silicon nitride. It is believed that there is.

  Based on the above additional experiments, the present inventors have found that the hydrogen resistance improves as the silicon concentration of the InSiO film increases. In particular, it has been found that when the silicon concentration in the InSiO film is 11.7 at% or more, the hydrogen resistance is dramatically improved.

  Therefore, in the thin film transistor 1 according to the present embodiment, the oxide semiconductor layer 50 is made of InSiO, and the silicon concentration of the oxide semiconductor layer 50 is gate-insulated in the region closer to the gate insulating layer 40 (first region). It is set to be higher than a region (second region) separated from the layer 40.

  Accordingly, hydrogen resistance in a region on the front channel side (first semiconductor layer 51) of the oxide semiconductor layer 50 is improved, so that the oxide semiconductor layer 50 enters the oxide semiconductor layer 50 from the front channel side (gate insulating layer 40 side). The influence of hydrogen can be suppressed. For example, damage caused by hydrogen diffusing from the gate insulating layer 40 side can be suppressed.

  Further, by making the silicon concentration in the region on the back channel side lower than the silicon concentration in the region on the front channel side, the resistance value in the region on the back channel side of the oxide semiconductor layer 50 can be lowered, so that the ON current can be maintained. In addition, good contact between the source electrode 70S and the drain electrode 70D and the oxide semiconductor layer 50 can be expected.

  On the other hand, in the region on the front channel side (second semiconductor layer 52) of the oxide semiconductor layer 50, the silicon concentration is kept lower than the region on the back channel side. For this reason, since ON current does not fall, the outstanding ON characteristic can be maintained.

  As described above, in the oxide semiconductor layer 50 made of InSiO, the silicon concentration in the region on the front channel side is higher than that in the region on the back channel side, thereby maintaining excellent TFT characteristics and excellent hydrogen resistance. Therefore, a TFT having stable characteristics and high reliability can be realized, and a TFT can be obtained with a high yield.

  In the thin film transistor 1 according to this embodiment, the gate insulating layer 40 in contact with the oxide semiconductor layer 50 (first semiconductor layer 51) is preferably a silicon compound such as a silicon oxide film (SiO).

  Accordingly, since the lattice matching between the oxide semiconductor layer 50 and the gate insulating layer 40 is increased, the interface state between the oxide semiconductor layer 50 and the gate insulating layer 40 can be improved. Accordingly, a highly reliable thin film transistor having high robustness can be realized.

<Display device>
Next, an example in which the thin film transistor 1 according to the above embodiment is applied to a display device will be described with reference to FIGS. In this embodiment, an application example to an organic EL display device will be described.

  FIG. 5 is a partially cutaway perspective view of the organic EL display device according to the embodiment. FIG. 6 is an electric circuit diagram of a pixel circuit in the organic EL display device shown in FIG. Note that the pixel circuit is not limited to the configuration shown in FIG.

  The above-described thin film transistor 1 can be used as a switching transistor SwTr and a driving transistor DrTr of an active matrix substrate in an organic EL display device.

  As shown in FIG. 5, the organic EL display device 100 includes a TFT substrate (TFT array substrate) 110 on which a plurality of thin film transistors are arranged, an anode 131 as a lower electrode (reflection electrode), and an EL layer (light emitting layer) 132. And a laminated structure with an organic EL element (light emitting part) 130 composed of a cathode 133 which is an upper electrode (transparent electrode).

  The thin film transistor 1 described above is used for the TFT substrate 110 in the present embodiment. A plurality of pixels 120 are arranged in a matrix on the TFT substrate 110, and each pixel 120 is provided with a pixel circuit.

  The organic EL element 130 is formed corresponding to each of the plurality of pixels 120, and the light emission of each organic EL element 130 is controlled by a pixel circuit provided in each pixel 120. The organic EL element 130 is formed on an interlayer insulating layer (planarization film) formed so as to cover a plurality of thin film transistors.

  The organic EL element 130 has a configuration in which an EL layer 132 is disposed between the anode 131 and the cathode 133. A hole transport layer is further laminated between the anode 131 and the EL layer 132, and an electron transport layer is further laminated between the EL layer 132 and the cathode 133. Note that another functional layer may be provided between the anode 131 and the cathode 133. The functional layer formed between the anode 131 and the cathode 133 including the EL layer 132 is an organic layer made of an organic material.

  Each pixel 120 is driven and controlled by a respective pixel circuit. The TFT substrate 110 includes a plurality of gate wirings (scanning lines) 140 arranged along the row direction of the pixels 120 and a plurality of gate wirings 140 arranged along the column direction of the pixels 120 so as to intersect the gate wiring 140. Source wiring (signal wiring) 150 and a plurality of power supply wirings (not shown in FIG. 5) arranged in parallel with the source wiring 150 are formed. Each pixel 120 is partitioned by, for example, an orthogonal gate wiring 140 and a source wiring 150.

  The gate wiring 140 is connected to the gate electrode of the switching transistor included in each pixel circuit for each row. The source wiring 150 is connected to the source electrode of the switching transistor for each column. The power supply wiring is connected to the drain electrode of the drive transistor included in each pixel circuit for each column.

  As shown in FIG. 6, the pixel circuit includes a switching transistor SwTr, a driving transistor DrTr, and a capacitor C that stores data to be displayed on the corresponding pixel 120. In the present embodiment, the switching transistor SwTr is a TFT for selecting the pixel 120, and the drive transistor DrTr is a TFT for driving the organic EL element 130.

  The switching transistor SwTr includes a gate electrode G1 connected to the gate wiring 140, a source electrode S1 connected to the source wiring 150, a drain electrode D1 connected to the capacitor C and the gate electrode G2 of the second thin film transistor DrTr, and an oxidation A physical semiconductor layer (not shown). In the switching transistor SwTr, when a predetermined voltage is applied to the connected gate wiring 140 and source wiring 150, the voltage applied to the source wiring 150 is stored in the capacitor C as a data voltage.

  The drive transistor DrTr is connected to the drain electrode D1 of the switching transistor SwTr and the gate electrode G2 connected to the capacitor C, the drain electrode D2 connected to the power supply wiring 160 and the capacitor C, and the anode 131 of the organic EL element 130. A source electrode S2 and an oxide semiconductor layer (not shown) are provided. The drive transistor DrTr supplies a current corresponding to the data voltage held by the capacitor C from the power supply wiring 160 to the anode 131 of the organic EL element 130 through the source electrode S2. Thereby, in the organic EL element 130, a drive current flows from the anode 131 to the cathode 133, and the EL layer 132 emits light.

  Note that the organic EL display device 100 having the above configuration employs an active matrix system in which display control is performed for each pixel 120 located at the intersection of the gate wiring 140 and the source wiring 150. Thereby, the corresponding organic EL element 130 selectively emits light by the switching transistor SwTr and the drive transistor DrTr in each pixel 120, and a desired image is displayed.

  As described above, in the organic EL display device 100 according to the present embodiment, the switching transistor SwTr and the driving transistor DrTr use the thin film transistor 1 having stable characteristics and high reliability. Therefore, an organic EL display device with excellent reliability is realized. it can.

<Modification>
As described above, the thin film transistor according to the present invention has been described based on the embodiment, but the present invention is not limited to the above embodiment.

  For example, in the above embodiment, a bottom-gate thin film transistor in which the gate electrode 30, the gate insulating layer 40, and the oxide semiconductor layer 50 are stacked on the substrate 10 in this order from the bottom is described. Absent.

  For example, as illustrated in FIG. 7, a top-gate thin film transistor in which the oxide semiconductor layer 50, the gate insulating layer 40, and the gate electrode 30 are stacked on the substrate 10 in this order from the bottom may be used. In this case, the source electrode 70S is connected to the source region (low-resistance region) 50S of the oxide semiconductor layer 50 through a contact hole formed in the gate insulating layer 40. The drain electrode 70 </ b> D is connected to the drain region (low resistance region) 50 </ b> D of the oxide semiconductor layer 50 through a contact hole formed in the gate insulating layer 40.

  In this manner, by using a top-gate thin film transistor, the TFT size can be reduced, so that high definition can be achieved. In addition, this configuration can reduce the parasitic capacitance.

  In the above embodiment, the oxide semiconductor layer 50 has a two-layer structure including the second semiconductor layer 52 and the first semiconductor layer 51. However, the present invention is not limited to this. For example, the oxide semiconductor layer 50 may have a three-layer structure. Good. In this case, a third semiconductor layer having a silicon concentration higher than that of the second semiconductor layer 52 can be formed on the second semiconductor layer 52 having a low silicon concentration. Thereby, the influence of hydrogen from the protective layer 60 side can also be suppressed by the third semiconductor layer having a high silicon concentration.

  In addition, the oxide semiconductor layer 50 may not have a layered structure that is clearly divided into a plurality of layers, and may have a silicon concentration gradient in the thickness direction. In this case, for example, the silicon concentration in the oxide semiconductor layer 50 is configured to continuously increase as it approaches the interface on the gate insulating layer 40 side (interface between the gate insulating layer 40 and the oxide semiconductor layer 50). Can do. Accordingly, defects at the interface between the gate insulating layer 40 and the oxide semiconductor layer 50 can be reduced, so that a TFT having more excellent characteristics can be realized.

  In the above embodiment, the channel protective thin film transistor is described. However, the present invention may be applied to a channel etched thin film transistor.

  In the above embodiment, an n-type channel thin film transistor is used. However, a p-type channel thin film transistor may be used.

  Moreover, in the said embodiment, although the organic electroluminescent display apparatus was demonstrated as a display apparatus using a thin-film transistor, it is not restricted to this. For example, the thin film transistor in the above embodiment can also be applied to other display devices such as a liquid crystal display device.

  In addition, the form obtained by making various modifications conceived by those skilled in the art with respect to each embodiment and modification, and the components and functions in each embodiment and modification are arbitrarily set within the scope of the present invention. Forms realized by combining them are also included in the present invention.

  The thin film transistor according to the present invention is widely used in various electric devices having a thin film transistor such as a display such as an organic EL display device, and a television set, a personal computer, a tablet terminal, a mobile phone, and a smartphone using the display. be able to. The display includes a plurality of pixels, and each pixel includes a plurality of subpixels. The subpixel includes a display element (in the case of an organic EL display, an organic EL element) and a drive circuit that drives the display element. Generally, each drive circuit includes at least a selection transistor and a drive transistor. The thin film transistor described above can be used as the selection transistor and the drive transistor.

DESCRIPTION OF SYMBOLS 1 Thin-film transistor 10 Substrate 20 Undercoat layer 30, G1, G2 Gate electrode 40 Gate insulating layer 50 Oxide semiconductor layer 51 First semiconductor layer 52 Second semiconductor layer 60 Protective layer 70S, S1, S2 Source electrode 70D, D1, D2 Drain Electrode 100 Organic EL display device 110 TFT substrate 120 Pixel 130 Organic EL element 131 Anode 132 EL layer 133 Cathode 140 Gate wiring 150 Source wiring 160 Power supply wiring SwTr Switching transistor DrTr Driving transistor C Capacitor

Claims (14)

A gate electrode;
An oxide semiconductor layer facing the gate electrode;
A gate insulating layer disposed between the gate electrode and the oxide semiconductor layer;
A source electrode and a drain electrode electrically connected to the oxide semiconductor layer,
The oxide semiconductor layer includes an oxide containing at least indium and silicon, and includes a first region and a second region that is a region farther from the gate insulating layer than the first region,
The first region has a higher silicon concentration than the second region.
Thin film transistor. The oxide semiconductor layer has a stacked structure including a first semiconductor layer formed as the first region and a second semiconductor layer formed as the second region.
The thin film transistor according to claim 1. The silicon concentration of the first semiconductor layer is 6.5 at% or more.
The thin film transistor according to claim 2. The silicon concentration of the first semiconductor layer is 11.7 at% or more.
The thin film transistor according to claim 2. The silicon concentration of the second semiconductor layer is less than 6.5 at%.
The thin-film transistor of any one of Claims 2-4. The silicon concentration of the oxide semiconductor layer is higher than the hydrogen concentration contained in the oxide semiconductor layer.
The thin film transistor according to any one of claims 2 to 5. The film thickness of the first semiconductor layer is 5 nm or more.
The thin film transistor according to any one of claims 2 to 5. The film thickness of the second semiconductor layer is 15 nm or more.
The thin film transistor according to any one of claims 2 to 7. The oxide semiconductor layer has a thickness of 20 nm or more.
The thin film transistor according to any one of claims 1 to 8. The silicon concentration in the oxide semiconductor layer continuously increases as it approaches the interface on the gate insulating layer side,
The thin film transistor according to claim 1. The gate electrode, the gate insulating layer, and the oxide semiconductor layer are stacked on the substrate in this order,
The source electrode and the drain electrode are formed above the oxide semiconductor layer.
The thin-film transistor of any one of Claims 1-10. Furthermore, a protective layer is provided on the oxide semiconductor layer,
The thin film transistor according to claim 11. The oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked on the substrate in this order,
The source electrode and the drain electrode are connected to the oxide semiconductor layer through a contact hole formed in the gate insulating layer.
The thin-film transistor of any one of Claims 1-10. Forming a gate electrode;
Forming an oxide semiconductor layer facing the gate electrode;
Forming a gate insulating layer between the gate electrode and the oxide semiconductor layer;
Forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,
The oxide semiconductor layer includes an oxide containing at least indium and silicon, and includes a first region and a second region that is a region farther from the gate insulating layer than the first region,
The first region has a higher silicon concentration than the second region.
A method for manufacturing a thin film transistor.

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