JP2016086004A - Print wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent warpage of a printed wiring board.SOLUTION: A printed wiring board according to an embodiment includes a core material having a first surface and a second surface. The number of conductor layers on the first surface of the core material is different from the number of conductor layers on the second surface. A thickness of a second conductor layer on the second surface is larger than a thickness of a first conductor layer on the first surface.SELECTED DRAWING: Figure 4

Description

The present invention relates to a printed wiring board having an insulating substrate, an upper resin insulating layer, a first conductor layer, a lower resin insulating layer, and a second conductor layer.

Japanese Patent Application Laid-Open No. H10-228561 discloses a wiring board with a built-in electronic component. The wiring substrate shown in FIG. 1 of Patent Document 1 has a core substrate having a front surface and a back surface and a recess formed on the back surface side, an electronic component built in the recess of the core substrate, and a surface of the core substrate. It has the insulating layer formed and the insulating layer (solder resist layer) formed on the back surface of the core substrate. According to FIG. 1 of the patent document, the number of insulating layers formed on the surface of the core substrate is three, and the number of insulating layers formed on the back surface of the core substrate is one. . And the insulating layer formed on the back surface of the core substrate is not formed on the concave portion or the electronic component of the core substrate.

JP 2003-046255 A

In the wiring substrate shown in FIG. 1 of Patent Document 1, the number of insulating layers formed on the surface of the core substrate is different from the number of insulating layers formed on the back surface of the core substrate. For this reason, it is considered that the warping of the wiring board increases.

An object of the present invention is to reduce the warpage of a printed wiring board.

A printed wiring board according to the present invention includes an insulating substrate having a first surface and a second surface opposite to the first surface, a first conductor layer formed on the first surface of the insulating substrate, The N-layer upper resin insulation layer laminated on the first surface and the first conductor layer and the (N-1) upper conductor layer formed between the adjacent upper resin insulation layers. A second conductor layer formed on the second surface of the insulating substrate;
The lower side of the (K-1) layer formed between the lower resin insulation layer of the K layer laminated on the second surface and the second conductor layer and the adjacent lower resin insulation layer And a conductor layer. The N is an integer of 2 or more, the K is an integer of 1 or more, the number of N is larger than the number of K, and the thickness of the second conductor layer is all the upper conductor layers. And the thickness of the first conductor layer.

Process drawing which shows the manufacturing method of the printed wiring board which concerns on embodiment of this invention. Process drawing which shows the manufacturing method of the printed wiring board of embodiment. Process drawing which shows the manufacturing method of the printed wiring board of embodiment. 4A shows a partial cross section of the printed wiring board of the embodiment, FIG. 4B shows a partial cross section of the wiring board of the embodiment, and FIG. 4C shows a wiring having solder bumps. The cross section of a board | substrate is shown. FIG. 5A is a schematic diagram of a cross section of the printed wiring board of the embodiment, and FIG. 5B is a diagram illustrating a cross section of an application example of the wiring board of the embodiment. FIG. 6A is a plan view of the first surface of the core substrate of the printed wiring board according to the embodiment, and FIG. 6B is a plan view of the second surface of the core substrate. FIG. 7A is a plan view of the printed wiring board of the embodiment, and FIG. 7B is a plan view of the wiring board. FIG. 7C is a cross-sectional view of a wiring board according to a modification of the embodiment.

FIG. 7A is a plan view of the printed wiring board 100 of the embodiment, and the printed wiring board 100 is formed by a product area 10G and a frame portion 98. FIG. The frame portion 98 surrounds the product area 10G. As shown in FIG. 7A, a plurality of products (wiring boards) 10 are formed in the product area 10G. The products 10 are arranged in a matrix. One product 10 is shown in FIG. FIG. 7B is a plan view of one product (wiring board) 10.

FIG. 5A is a schematic cross-sectional view of the printed wiring board 100 of the embodiment. As shown in FIG. 5A, the wiring board 10 and the printed wiring board 100 of the embodiment have a core substrate 30. The core substrate 30 has an insulating substrate (core material) 20z having a first surface F and a second surface S opposite to the first surface F, and a first conductor layer 34F formed on the first surface F of the insulating substrate 20z. And a second conductor layer 34S formed on the second surface S of the insulating substrate 20z.

The core substrate 30 further includes a through-hole conductor 36 that connects the first conductor layer 34F and the second conductor layer 34S. The through-hole conductor 36 is formed in the through hole 28 that penetrates the insulating substrate 20z. As shown in FIG. 1B, the through hole 28 is formed by a first opening 28F formed on the first surface side and a second opening 28S formed on the second surface side. . The shape of the through hole is an hourglass shape. The through hole 28 and the through hole conductor 36 are manufactured by, for example, a method disclosed in US77786390. The contents of US77786390 are incorporated herein. The first conductor layer and the second conductor layer include a plurality of conductor circuits (not shown), a conductor immediately above the through-hole conductor 36, and a land of a through-hole conductor formed of a conductor formed around the through-hole conductor 36. In-frame circuits 98F and 98S are included. As shown in FIG. 4B, the first conductor layer has a thickness t1, and the second conductor layer has a thickness t2. The thickness t2 is thicker than the thickness t1. The first surface of the core substrate 30 and the first surface of the insulating substrate 20z are the same surface, and the second surface of the core substrate 30 and the second surface of the insulating substrate 20z are the same surface. As shown in FIG. 5A, the core substrate has an opening 26 for containing an electronic component. The opening 26 penetrates the insulating substrate. An electronic component 80 is built in the opening 26.

Upper resin insulating layers 50F, 150F, 250F, and 350F are laminated on the first surface F of the insulating substrate 20z and the first conductor layer 34F. The number of upper resin insulation layers is N. N is an integer of 2 or more. The Nth upper resin insulation layer is the uppermost resin insulation layer. The uppermost resin insulation layer functions as the upper solder resist layer 350F.
Upper conductor layers 58F, 158F, and 258F are formed between adjacent upper resin insulation layers. The upper conductor layer sandwiched between the Nth upper resin insulation layer and the (N-1) th upper resin insulation layer is the uppermost conductor layer 258F. The uppermost conductor layer has upper pads 73F (73FI, 73FO) for mounting the electronic component 90 and the second package substrate 130 shown in FIG. 5B.

Each upper resin insulating layer has an opening. The opening formed in each upper resin insulation layer passes through each upper resin insulation layer.
The upper solder resist layer 350F has an opening 71F (71FI, 71FO), and the uppermost conductor layer 258F exposed by the opening functions as the upper pad 73F. As shown in FIG. 5 and the like, the upper pad exposed by the opening 71FI is the upper first pad 73FI. The upper first pad 73FI is formed substantially at the center of the mounting surface of the wiring board, and a plurality of upper first pads 73FI form a C4 pad group. The upper pad exposed by the opening 71FO is the upper second pad 73FO. The upper second pad 73FO is formed outside the C4 pad group. As shown in FIG. 5B, an electronic component 90 such as an IC chip is mounted on the upper first pad 73FI. The second package substrate 130 is mounted on the wiring substrate via the upper second pad 73FO.

The (N-1) th upper resin insulation layer from the first upper resin insulation layer has openings for via conductors. Via conductors 60F, 160F, and 260F are formed in the opening for the via conductor, and adjacent conductor layers are connected by the via conductor.
Each upper resin insulation layer 50F, 150F, 250F, 350F is formed on the opening 26 containing the core substrate 30 and the electronic component 80, and the first upper resin insulation layer 50F contains the core substrate and the electronic component. The opening 26 to be covered is covered.
In FIG. 5A, the upper resin insulation layers 50F, 150F, 250F, and 350F are four layers. The fourth upper resin insulation layer 350F is an upper solder resist layer. The solder resist layer 350F has an opening 71F that exposes the upper pad 73F.

In the wiring board 10 and the printed wiring board 100 of the embodiment, the upper conductor layers 58F, 158F, and 258F are three layers. The upper conductor layer 58F sandwiched between the first upper resin insulation layer 50F and the second upper resin insulation layer 150F is the first upper conductor layer. The upper conductor layer 158F sandwiched between the second upper resin insulation layer 150F and the third upper resin insulation layer 250F is the second upper conductor layer. An upper conductor layer 258F sandwiched between the third upper resin insulation layer 250F and the fourth upper resin insulation layer 350F is the third upper conductor layer. The third upper conductor layer 258F is the uppermost conductor layer, and the uppermost conductor layer has an upper pad 73F for mounting the electronic component 90 such as an IC chip and the second package substrate 130. The upper pad may not be provided with the upper second pad 73FO but may be formed only by the upper first pad 73FI. The upper pad is exposed through the opening 71F of the upper solder resist layer 350F.

In the wiring board 10 of the embodiment, the first upper resin insulation layer 50F, the second upper resin insulation layer 150F, and the third upper resin insulation layer 250F each have openings for via conductors.
In the wiring substrate 10 of the embodiment, the first upper via conductor 60F is formed in the via conductor opening of the upper resin insulation layer 50F. The first conductor layer 34F and the conductor layer 58F are connected by the via conductor 60F. The electrode 82 and the conductor layer 58F are connected by the via conductor 60F. A second upper via conductor (160F) is formed in the via conductor opening of the upper resin insulation layer (150F). The conductor layer 58F and the conductor layer 158F are connected by the via conductor 160F. A third upper via conductor (260F) is formed in the via conductor opening of the upper resin insulation layer (250F). The conductor layer 158F and the conductor layer 258F are connected by the via conductor 260F.

As shown in FIG. 5A, the lower resin insulating layer 50S is laminated on the second surface S and the second conductor layer 34S of the insulating substrate 20z. The number of lower resin insulation layers is K. K is an integer of 1 or more. The number K is smaller than the number N. The difference between N and K is preferably 2 or less. The warpage of the printed wiring board is reduced. The number of upper resin insulation layers is greater than the number of lower resin insulation layers. The Kth lower resin insulation layer is the lowermost lower resin insulation layer. The lowermost resin insulation layer functions as a lower solder resist layer (lower protective layer).
Each lower resin insulation layer is formed on the opening containing the core substrate and the electronic component, and the first lower resin insulation layer 50S covers the opening 26 containing the core substrate 30 and the electronic component 80. Yes.

When K is 1, the lower resin insulation layer is only the first lower resin insulation layer (the lowermost lower resin insulation layer). There is no lower conductor layer. When K is 1, the lowermost lower resin insulating layer functions as a lower solder resist layer. The lower solder resist layer has an opening 51S. The second conductor layer 34S is exposed through the opening 51S of the lower solder resist layer 50S. The second conductor layer 34S exposed through the opening 51S of the lower solder resist layer 50S functions as the lower pad 53S. As shown in FIG. 4C, the lower solder resist layer 50S may have an opening 51S that exposes the electrode 82 of the electronic component. The wiring board is mounted on the mother board via the lower pad 53S and the electrode 82.
The thickness of all the lower conductor layers 34S is larger than the thickness of all the upper conductor layers 58F, 158F, 258F.

When K is 2 or more, a lower conductor layer is formed between adjacent lower resin insulation layers. The lower conductor layer sandwiched between the Kth lower resin insulation layer and the (K-1) th lower resin insulation layer is the lowermost lower conductor layer. The lowermost lower conductive layer has a lower pad 53S for connecting to the motherboard.

Each lower resin insulating layer has an opening. The opening formed in each lower resin insulation layer penetrates each lower resin insulation layer.
The lower solder resist layer has an opening, and the lowermost conductive layer exposed by the opening functions as a lower pad. The wiring board is connected to the motherboard via the lower pad.
The (K-1) th lower resin insulation layer from the first lower resin insulation layer has openings for via conductors. A lower via conductor is formed in the opening for the via conductor, and adjacent conductor layers are connected by the via conductor.
In FIG. 5A, the number of lower resin insulation layers is one. The first lower resin insulation layer 50S shown in FIG. 5A is the lower solder resist layer 50S. The solder resist layer 50S has an opening 51S. The lower pad 53S and the electrode 82 included in the second conductor layer are exposed through the opening 51S.

As shown in FIG. 5A, the solder bump 76F can be formed on the upper pad 73F exposed from the opening 71F of the upper solder resist layer 350F.
As shown in FIG. 4C, solder bumps 76S can be formed on the pads 53S exposed from the openings 51S of the lower solder resist layer 50S and the electrodes 82 of the electronic component.

FIG. 5B shows an application example 1000 of the wiring board 10 of the embodiment. The application example 1000 is a POP (Package on Package) substrate.
An electronic component 90 such as an IC chip (logic chip) is mounted on the wiring board 10 of the embodiment via the solder bump 76FI on the C4 pad. A first package substrate composed of the wiring substrate 10 and the electronic component 90 is completed. In the application example, the second package substrate 130 is mounted on the first package substrate 120 via the solder bumps 76FO on the second pad (upper second pad) 73FO. The second package substrate 130 includes an upper substrate 110 and an electronic component 190 such as a memory mounted on the upper substrate.
Mold resin 102 is formed between first package substrate 120 and second package substrate 130.
A mold resin 202 for sealing the electronic component 190 is formed on the upper substrate 110.
In FIG. 5B, the connection body 76FO that connects the first package substrate and the second package substrate is a solder bump 76FO. In addition to the solder bumps, examples of the connection body include metal posts such as plating posts and pins. The shape of the plating posts and pins is a cylinder. A right circular cylinder is preferable.
Further, the wiring board 10 may have solder bumps 76S for connecting to the motherboard on the lower pad.

As shown in FIG. 1D, FIG. 2A, and the like, the insulating substrate 20z has an opening 26 for accommodating an electronic component. The opening 26 penetrates the insulating substrate. Since the insulating substrate (core material) 20z of the wiring board of the embodiment has the opening 26, the strength of the wiring board is lowered. In the printed wiring board according to the embodiment, the number of resin insulating layers stacked on the first surface of the core substrate is different from the number of resin insulating layers stacked on the second surface of the core substrate. Therefore, the wiring board of the embodiment is easily warped. Therefore, the printed wiring board 100 is also easily warped.

FIG. 5A is a schematic cross-sectional view of the printed wiring board 100. FIG. 5A is a schematic diagram of a cross section of a printed wiring board existing between X1 and X1 in FIG. FIG. 7A is a view obtained by viewing the printed wiring board 100 from a position above the solder resist layer. FIG. 7A shows the upper solder resist layer 350F, the upper pad 73F exposed from the opening of the upper solder resist layer, and the alignment mark 258FA. FIG. 6A is a plan view of the first surface F of the core substrate 30. FIG. 6A shows the first conductor layer 34F and the first surface of the core material exposed from the first conductor layer 34F. As shown in FIG. 6 (A), the first conductor layer is a first in-frame portion formed in the product area 10G and in the product area first conductor layer 34FP and in the frame portion 98 (98F). It is formed of a conductor layer 34FW. A value obtained by dividing the area of the first conductor layer in the frame by the area of the first surface of the insulating substrate in the frame is 0.15 or less. In the example of FIG. 6A, the first conductor layer in the frame portion is formed only by the alignment mark 34FA.

FIG. 6B is a plan view of the second surface of the core substrate 30. FIG. 6B shows the second conductor layer 34S and the second surface of the core material exposed from the second conductor layer 34S. As shown in FIG. 6 (B), the second conductor layer is the second conductor layer 34SP in the product area formed in the product area 10G and the second in-frame part formed in the frame part 98 (98S). It is formed of a conductor layer 34SW. The second conductor layer 34SW in the frame part covers almost the entire surface of the frame part. The second conductor layer 34SW in the frame portion has a solid pattern. A value obtained by dividing the area of the second conductor layer in the frame by the area of the second surface of the insulating substrate in the frame is 0.85 or more. The core substrate has an alignment mark 34SA on the frame portion 98 of the second surface S. The alignment mark 34SA is formed on the second surface S exposed from the second conductor layer 34SW in the frame portion. FIG. 4A is a cross-sectional view taken along the line X3-X3 in FIG. As shown in FIG. 4A, a solid pattern 34SW (second conductor layer in the frame portion) is formed on the frame portion of the second surface S of the core substrate 30. The solid pattern 34SW has an opening. The second surface of the insulating substrate exposed from the opening functions as the alignment mark 34SA.

As shown in FIG. 4A, the first upper resin insulation layer 50F, the second upper resin insulation layer 150F, and the third upper resin insulation layer 250F have a frame portion 98. A first upper conductor layer 58FW in the frame is formed on the frame of the first upper resin insulation layer 50F. A second upper conductor layer 158FW in the frame is formed on the frame of the second upper resin insulation layer 150F. A third upper conductor layer 258FW in the frame portion is formed on the frame portion of the third upper resin insulation layer 250F.
A value obtained by dividing the area of the first upper conductor layer 58FW in the frame by the area of the first upper resin insulation layer 50F in the frame is greater than 0 and 0.15 or less.
A value obtained by dividing the area of the second upper conductor layer 158FW in the frame by the area of the second upper resin insulation layer 150F in the frame is greater than 0 and 0.15 or less.
A value obtained by dividing the area of the third upper conductor layer 258FW in the frame by the area of the third upper resin insulation layer 250F in the frame is greater than 0 and 0.15 or less.
The first upper conductor layer in the frame portion, the second upper conductor layer in the frame portion, and the third upper conductor layer in the frame portion are preferably formed only by alignment marks.

In the printed wiring board 100 according to the embodiment, the number of the upper resin insulating layers 50F, 150F, 250F, and 350F on the first surface F of the insulating substrate 20z is four, and the lower surface on the second surface S of the insulating substrate 20z. The number of the resin insulation layers 50S on the side is one. The number of N is larger than the number of K. The difference between the two is 3. In the printed wiring board 100, the number of conductor layers 34F, 58F, 158F, 258F on the first surface of the insulating substrate 20z is larger than the number of conductor layers 34S on the second surface of the insulating substrate 20z. In the printed wiring board 100, the volume of the resin and the volume of the conductor are different between the front and back of the core material. The printed wiring board 100 has an asymmetric structure. Here, the front is the first surface, and the back is the second surface. In the printed wiring board 100, since the value of N is larger than the value of K, the volume of the conductor on the first surface F tends to be larger than the volume of the conductor on the second surface S. However, in the printed wiring board 100, the thickness of the second conductor layer 34S is larger than the thickness of the first conductor layer 34F and the thickness of all upper conductor layers. In FIG. 4A, the first upper conductor layer 58F, the second upper conductor layer 158F, and the third upper conductor layer 258F belong to the upper conductor layer. Since the thickness of the second conductor layer 34S is thicker than the thickness of the conductor layers 34F, 58F, 158F, 258F on the first surface F, the volume of the conductor existing on the first surface F and the conductor existing on the second surface S The volume difference between the two becomes smaller. Therefore, according to the printed wiring board 100 of the embodiment, warpage is reduced. Furthermore, among the upper conductor layers 58F, 158F, and 258F, the uppermost conductor layer 258F is the thickest. Since the conductive layers 34S and 258F having a large thickness sandwich the upper resin insulating layers 50F, 150F and 250F and the insulating substrate 20z, the strength of the printed wiring board 100 is increased. Therefore, the printed wiring board 100 can resist stress due to asymmetry. Warpage is reduced.
FIG. 4B shows the thicknesses t1, t2, t3, t4, and t5 of each conductor layer. For example, the thickness t1 of the first conductor layer 34F is 14 μm. The thickness t2 of the second conductor layer 34S is 16 μm. The thickness t3 of the first upper conductor layer 58F is 7.5 μm, the thickness t4 of the second upper conductor layer 158F is 7.5 μm, and the thickness t5 of the third upper conductor layer 258F is 10 μm. is there. That is, the thickness t2 of the second conductor layer 34S is thicker than the thickness t1 of the first conductor layer 34F and the thicknesses t3, t4, and t5 of the conductor layers 58F, 158F, and 258F. In addition, among the upper conductor layers 58F, 158F, and 258F, the third upper conductor layer (the uppermost upper conductor layer) has the largest thickness. The conductor volume is balanced between the front and back sides of the insulating substrate, and the warpage is reduced.

In the printed wiring board 100, the ratio R2 of the area of the second conductor layer 34SW in the frame occupying the area of the frame is larger than the ratio R1 of the area of the first conductor layer 34FW in the frame occupying the area of the frame. Since the frame portion is formed on the outer periphery of the printed wiring board, the warp of the printed wiring board can be reduced by increasing the strength of the frame portion. Since the printed wiring board 100 has an asymmetric structure, if the strength of the frame portion on the first surface F of the insulating substrate 20z and the strength of the frame portion on the second surface S are the same, the stress due to asymmetry is reduced. I can't. However, in the printed wiring board 100, since the area of the second conductor layer 34SW in the frame portion is larger than the area of the first conductor layer 34FW in the frame portion, the reinforcement of the second surface S by the second conductor layer 34SW in the frame portion is the first in the frame portion. It is stronger than the reinforcement of the first surface F by the conductor layer 34FW. Therefore, even if the printed wiring board 100 has an asymmetric structure, warpage is small. The ratio of the area of the first upper conductor layer 58FW in the frame to the area of the frame is the ratio R3. The ratio of the area of the second upper conductor layer 158FW in the frame to the area of the frame is the ratio R4. The ratio of the area of the third upper conductor layer 258FW in the frame to the area of the frame is the ratio R5. The ratio R2 is larger than the ratio R3. The ratio R2 is larger than the ratio R4. The ratio R2 is greater than the ratio R5. In that case, the strength of the frame portion on the second surface of the insulating substrate 20z is stronger than the strength of each frame portion existing on the first surface of the insulating substrate 20z. The stress due to asymmetry can be effectively reduced. In the printed wiring board 100, the ratio R2 is 0.85 or more, and the ratios R1, R3, R4, and R5 are 0.15 or less. Since the difference between the two is large, the warp of the printed wiring board 100 is small. For example, R2 is 0.89, R1 is 0.1, R3 is 0.06, R4 is 0.12, and R5 is 0.15. Of the conductor layers in the frame portion existing on the frame portion of the first surface of the insulating substrate, the ratio of the area of the uppermost conductor layer 258F in the frame portion is the largest. Although the area of the conductor layer in the frame portion formed on the first surface of the insulating substrate 20z is small, the strength of the printed wiring board is effectively increased by increasing the area of the uppermost upper conductor layer in the frame portion. can do. Warpage is reduced.

An example of the ratio of the area of each conductor layer to the area of the product area 10G of the embodiment is shown below. The ratio of the area of the first conductor layer in the product area is the ratio r1. The ratio of the area of the second conductor layer in the product area is the ratio r2. The ratio of the area of the first upper conductor layer in the product area is the ratio r3. The ratio of the area of the second upper conductor layer in the product area is the ratio r4. The ratio of the area of the third upper conductor layer in the product area is the ratio r5. The ratios r1, r3, r4, r5 are 0.54 to 0.58. Among the ratios r1, r3, r4, r5, the ratio r5 is the largest. The ratio r2 is the largest among the ratios r1, r2, r3, r4, r5, and is 0.60 to 0.9. The ratios R1, R2, R3, R4, and R5 are obtained by dividing the area of the conductor layer in each frame by the area of the frame. The ratios r1, r2, r3, r4, and r5 are obtained by dividing the area of the conductor layer in each product area by the area of the product area.

In the printed wiring board of the embodiment, the materials of the upper solder resist layer 350F and the lower solder resist layer 50S are different. The upper solder resist layer is a photocurable resin insulating layer, and the lower solder resist layer is a thermosetting resin insulating layer. Therefore, even if the number of resin insulating layers is different, the warp of the printed wiring board of the embodiment is reduced. The upper solder resist layer is formed of resin and inorganic particles, and the lower solder resist layer is formed of resin and inorganic particles. The lower solder resist layer can have a reinforcing material such as glass cloth or aramid fiber. The upper solder resist layer does not have a reinforcing material.

[Method for Manufacturing Printed Wiring Board of Embodiment]
A method of manufacturing the printed wiring board 100 of the embodiment is shown in FIGS.
An insulating substrate (core material) 20z containing glass cloth, resin, and inorganic particles is prepared. As shown in FIG. 1A, the insulating substrate 20z has a product area 10G and a frame portion 98 surrounding the product area. The starting substrate is formed of copper foils 22F and 22S laminated on both surfaces of the insulating substrate 20z and the insulating substrate 20z (FIG. 1A). The copper foil on the first surface F of the insulating substrate is the first copper foil 22F, and the copper foil on the second surface S of the insulating substrate is the second copper foil 22S.

The first copper foil 22F is irradiated with a CO2 laser. A first opening 28F for forming a through hole for a through-hole conductor is formed in the insulating substrate 20z on the first surface F side of the insulating substrate 20z. The second copper foil 22S is irradiated with a CO2 laser. A second opening 28S connected to the first opening 28F is formed. A through hole 28 for the through hole conductor is formed (FIG. 1B). The first opening 28F tapers from the first surface F toward the second surface S. The second opening 28S tapers from the second surface S toward the first surface F.

An electroless plating film is formed on the side walls of the first copper foil, the second copper foil, and the through hole 28. Thereafter, electrolytic plating films 25F and 25S are formed on the electroless plating film. The electrolytic plating film 25F is an electrolytic plating film formed on the first surface F, and the electrolytic plating film 25S is an electrolytic plating film formed on the second surface S. The current density for forming the electrolytic copper plating film 25S on the second surface is larger than the current density for forming the electrolytic copper plating film 25F on the first surface. Therefore, the thickness of the electrolytic plating film 25S is thicker than the thickness of the electrolytic plating film 25F. A plating film 24 composed of an electroless plating film and an electrolytic plating film on the electroless plating film is formed in the through hole. At the same time, the plating film 24 is formed on the first surface and the second surface of the insulating substrate. The through hole 28 is filled with the electrolytic plating film. An etching resist is formed on the plating film 24. The plating film 24 and the copper foils 22F and 22S exposed from the etching resist are removed. The etching resist is removed. A first conductor layer 34F is formed on the first surface of the insulating substrate. A second conductor layer 34S is formed on the second surface of the insulating substrate. As shown in FIG. 1C, the first conductor layer 34F has a first conductor layer 34FP in the product area and a first conductor layer 34FW in the frame portion, and the second conductor layer 34S is a second conductor layer in the product area. 34SP and 2nd conductor layer 34SW in a frame part. The area of the conductor layer in the product area and the conductor layer in the frame part is adjusted by the pattern of the etching resist. A through-hole conductor 36 that connects the first conductor layer and the second conductor layer is formed in the through hole 28. The thickness t1 of the first conductor layer 34F is 14 μm. The thickness t2 of the second conductor layer 34S is 16 μm. The insulating substrate 20z having the through hole 28, the through hole conductor 36 formed in the through hole 28, the first conductor layer 34F formed on the first surface of the insulating substrate, and the second surface of the insulating substrate are formed. A circuit board 3000 having the second conductor layer 34S is obtained (FIG. 1C). The circuit board 3000 is manufactured by the method disclosed in US77786390.

An opening 26 for accommodating electronic components is formed in the circuit board 3000 by a CO2 gas laser (FIG. 1D). FIG. 6A is a plan view of the first surface F of the core substrate 30 of the printed wiring board 100. FIG. 1D is a cross-sectional view taken along the line X2-X2 in FIG. However, the products in the product area are simplified. Approximately one product is depicted. The first conductor layer 34FW in the frame part is formed of only the alignment mark 34FA. FIG. 6B is a plan view of the second surface S of the core substrate 30 of the printed wiring board 100. The second conductor layer 34SW in the frame portion is formed in a solid pattern. The opening 26 is formed using the alignment mark 34FA included in the first conductor layer 34F or the alignment mark 34SA included in the second conductor layer 34S. The alignment mark 34SA is an opening formed in the second conductor layer 34SW in the frame portion. The alignment mark 34SA is not drawn in FIG.
The core substrate 30 is completed by forming the opening 26 for accommodating electronic components in the circuit board 3000. The first surface F of the core substrate 30 and the first surface of the insulating substrate 20z are the same surface, and the second surface S of the core substrate 30 and the second surface of the insulating substrate 20z are the same surface.

The core substrate is inverted, and a PET film 94 is attached to the first surface of the core substrate 30 (FIG. 1E). The opening 26 is blocked by the PET film 94.

An electronic component 80 such as a multilayer ceramic capacitor is placed on the PET film exposed through the opening 26 for accommodating the electronic component. The electronic component 80 is accommodated in the opening 26 (FIG. 2A). The electronic component 80 is placed using the alignment mark 34SA shown in FIG. The electronic component 80 is held on the PET film 94 by the adhesive force of the PET film 94. The upper surface of the first conductor layer 34F of the core substrate 30 and the upper surface of the electrode 82 of the electronic component 80 are located on substantially the same plane.

A resin film for the lower resin insulating layer 50S is laminated on the second surface of the core substrate 30 and the electronic component. The resin film for the lower resin insulating layer (lower resin film) includes a resin such as epoxy and inorganic particles such as silica. The lower resin film may further include a reinforcing material such as a glass cloth. The lower resin film of the embodiment includes glass cloth, silica particles, and an epoxy resin.
A metal foil 48S such as a copper foil is laminated on the lower resin film. The thickness of the metal foil 48S is 3 μm to 5 μm.
By performing the heat press, the lower resin insulating layer (the lowermost lower resin insulating layer) 50S is formed on the second surface S of the core substrate 30 and the electronic component 80 from the lower resin film. At the same time, the copper foil 48S is bonded onto the lower resin insulating layer 50S. At this time, the resin and inorganic particles contained in the lower resin film flow into the gap between the side wall of the opening 26 and the electronic component 80. The filler 50SS that fills the gap is formed by curing the resin in the gap. The electronic component is built in the core substrate by the filler (FIG. 2B). The electronic component 80 is fixed to the core substrate 30 by the filler 50SS. The filler 50SS and the lower resin insulating layer 50S are formed simultaneously. The lower resin insulating layer includes a resin, inorganic particles, and a reinforcing material. The filler includes a resin and inorganic particles. The resin contained in the filler and the resin contained in the lower resin insulation layer are the same. The inorganic particles contained in the filler and the inorganic particles contained in the lower resin insulating layer are the same.
The lower resin insulation layer 50S is a thermosetting resin insulation layer.

The PET film 94 is removed from the core substrate 30 (FIG. 2C). An intermediate substrate 300 is obtained (FIG. 2C). The intermediate substrate 300 is formed on the core substrate 30, the electronic component 80 built in the core substrate 30, the filler 50SS filling the gap between the electronic component and the core substrate, the second surface of the core substrate, and the electronic component. The lower resin insulation layer 50S and the copper foil 48S on the lower resin insulation layer 50S are provided.

A resin film for the first upper resin insulation layer is laminated on the first surface of the core substrate of the intermediate substrate 300 and the electronic component. The upper resin insulating layer resin film (upper resin film) includes a resin such as epoxy and inorganic particles such as silica. The upper resin film may further include a reinforcing material such as a glass cloth. The upper resin film of the embodiment includes silica particles and an epoxy resin. The first upper resin insulation layer 50F is formed from the upper resin film by heating press (FIG. 2D). The first upper resin insulation layer 50F is a thermosetting resin insulation layer.

Next, an opening 51F for a via conductor is formed in the resin insulating layer 50F with a CO2 gas laser. The opening 51F reaches the electrode 82 and the first conductor layer 34F.
Electroless copper plating layer 52 is formed on resin insulating layer 50F and on the inner wall of opening 51F.
A plating resist is formed on the electroless copper plating layer 52.
Electrolytic copper plating layer 56 is formed on electroless copper plating layer 52 exposed from the plating resist.
The plating resist is removed. The electroless copper plating layer 52 between the electrolytic copper plating layers 56 is removed by etching. A first upper conductor layer 58F is formed on the first upper resin insulation layer 50F. The upper first conductor layer has a first upper conductor layer 58FP in the product area and a first upper conductor layer 58FW in the frame. The first upper conductor layer 58FW in the frame is preferably formed of only alignment marks. At the same time, an upper first via conductor 60F that penetrates the first upper resin insulation layer and reaches the first conductor layer 34F and the electrode 82 is formed (FIG. 3A). The areas of the conductor layers 58FP and 58FW are adjusted by the pattern of the plating resist.

A second upper resin insulation layer 150F is formed on the first upper resin insulation layer 50F and the first upper conductor layer 58F. An opening for the second upper via conductor is formed in the second upper resin insulation layer. The method for forming the second upper resin insulation layer is the same as the method for forming the first upper resin insulation layer. Upper resin insulation layer 150F has an opening for a second upper via conductor. The second upper resin insulation layer 150F is a thermosetting resin insulation layer.
A second upper conductor layer 158F is formed on the second upper resin insulation layer. The second upper conductor layer 158F has a second upper conductor layer 158FP in the product area and a second upper conductor layer 158FW in the frame. The second upper conductor layer 158FW in the frame is preferably formed of only alignment marks. The method for forming the second upper conductor layer is the same as the method for forming the first upper conductor layer. The areas of the conductor layers 158FP and 158FW are adjusted by the pattern of the plating resist.
The thickness t3 of the second upper conductor layer 158F is 7.5 μm.
A second upper via conductor 160F is formed in the opening for the second upper via conductor. The method for forming the second upper via conductor is the same as the method for forming the second upper via conductor.

A third upper resin insulation layer 250F, a third upper conductor layer 258F, and a third upper via conductor 260F are formed in a manner similar to that shown in the previous paragraph. The third upper conductor layer 258F includes a third upper conductor layer 258FP in the product area and a third upper conductor layer 258FW in the frame. The third upper conductor layer 258FW in the frame is preferably formed of an alignment mark and a dummy pattern. By forming a dummy pattern other than the alignment mark, the area of the third upper conductor layer (uppermost conductor layer) 158FW in the frame portion is increased (FIG. 3B). The thickness t5 of the third upper conductor layer is 10 μm. The areas of the conductor layers 258FP and 258FW are adjusted by the pattern of the plating resist.

A fourth upper resin insulation layer 350F is formed on the third upper resin insulation layer 250F and the third upper conductor layer 258F. The fourth upper resin insulation layer is a photo-curing resin insulation layer. Openings 71F (71FI, 71FO) are formed in the fourth upper resin insulation layer by exposure and development (FIG. 3B). The third upper conductor layer is exposed through the opening 71F. The conductor portion exposed through the opening 71F functions as the upper pad 73F (73FI, 73FO). The fourth upper resin insulation layer functions as the upper solder resist layer 350F.

The metal foil 48S on the lower resin insulating layer 50S is removed by etching. The lower resin insulating layer 50S functions as a lower solder resist layer. At this time, a protective film is stuck on the upper solder resist layer so that the upper pad is not dissolved by etching. The upper pad is not exposed. The protective film is not shown in the figure. Further, by removing the metal foil 48S, the rough surface of the metal foil is transferred to the lower solder resist layer 50S. The lower solder resist layer has a rough surface.

An opening 51S is formed by laser in the lower resin insulating layer 50S (FIG. 3C). The opening 51S may be formed by irradiating the metal foil 48S with a laser. The lower pad 53S is exposed through the opening 51S. The lower pad is included in the second conductor layer 34S. An opening 51S exposing the electrode 82 of the electronic component can be formed in the lower solder resist layer (FIG. 3C).

A protective film can be formed on the upper pad 73F (73FI, 73FO) and the lower pad 53S. A protective film can be formed on the electrode 82 of the electronic component exposed from the opening 51S. The protective film is a film for preventing oxidation of the pad and the electrode. The protective film is formed of, for example, a Ni / Au, Ni / Pd / Au, Pd / Au, or OSP (Organic Solderability Preservative) film.

Solder bumps 76FI and 76FO are formed on the upper pads 73FI and 73FO. The solder bump 76FI is formed on the C4 pad (upper first pad) 73FI, and the solder bump 76FO is formed on the upper second pad 73FO. Solder bumps 76S can be formed on the pads 53S on the lower side of the printed wiring board. A wiring board having the solder bumps 76FI, 76FO, and 76S shown in FIG. 4C is completed.

An electronic component 90 is mounted on each product 10 of the printed wiring board via solder bumps 76FI. The first package substrate 120 is completed. At this time, heat of reflow is applied, but in the printed wiring board 100, the thickness of the second conductor layer is larger than the thickness of the first conductor layer. The area of the second conductor layer in the frame portion is larger than the area of the first conductor layer in the frame portion. Therefore, the difference between the volume of the conductor on the first surface F and the volume of the conductor on the second surface is reduced. Warpage of the wiring board and the first package board before and after reflow is small. The second package substrate 130 is mounted on the first package substrate 120 via the solder bumps 76FO. Mold resin 102 is formed between package substrate 10 and second package substrate 130 (FIG. 5B). The POP substrate 1000 is completed. Then, it is divided into individual POP substrates.

[Modification of Embodiment]
FIG. 7C shows a wiring board according to a modification of the embodiment.
In the wiring board according to the modification of the embodiment, the opening 26 for accommodating the electronic component 80 formed in the core substrate 30 has a taper. Other than that, the wiring board of the modified example and the wiring board of the embodiment are the same. The configuration related to the frame is the same in the embodiment and the modified example. Accordingly, except for the shape of the opening 26, the modified printed wiring board and the printed wiring board of the embodiment are the same.
The opening 26 tapers from the second surface S toward the first surface F. The size of the opening 26 on the first surface is smaller than the size of the opening 26 on the second surface. The side wall of the opening is tapered from the second surface S toward the first surface F as shown in FIG. The size of the opening 26 decreases from the second surface toward the first surface.
Since the insulating substrate 20z has a reinforcing material, the rigidity of the insulating substrate 20z is high. Therefore, the insulating substrate 20z can suppress deformation of the resin insulating layer formed on the insulating substrate 20z.
According to the modification, the contact area between the first upper resin insulation layer 50F and the first surface of the core substrate 30 is greater than the contact area between the lower resin insulation layer 50S and the second surface S of the core substrate 30. large.
In the modified example, the number of the upper resin insulation layers on the first surface of the core substrate is larger than the number of the lower resin insulation layers on the second surface of the core substrate. Therefore, the force that the upper resin insulation layer gives to the core substrate is larger than the force that the lower resin insulation layer gives to the core substrate.
The area of the first surface of the core substrate is large, and the force acting on the first surface of the core substrate is large. On the other hand, the area of the second surface of the core substrate is small, and the force acting on the second surface of the core substrate is small. Therefore, when the force per unit area is compared between the first surface and the second surface of the core substrate, the difference between the two becomes small. Or both are substantially equivalent. Therefore, the opening for housing the electronic component formed in the core substrate has a taper from the second surface to the first surface, and even if the number of resin insulating layers on the front and back surfaces of the core substrate is different, the warp does not occur. A small printed wiring board or POP board can be provided. The connection reliability of the wiring board incorporating the electronic component is increased.

[Method of Manufacturing Printed Wiring Board of Modified Example of Embodiment]
In the modification of the embodiment, the opening 26 for accommodating electronic components is formed by irradiating the insulating substrate with laser from the second surface side of the insulating substrate. Otherwise, the manufacturing method of the modified example in FIG. 7C is the same as the manufacturing method of the embodiment.
Since the opening 26 is formed by the laser, the side wall of the opening is tapered from the second surface toward the first surface as shown in FIG. 7C. Examples of lasers are UV lasers and CO2 lasers.

In the printed wiring board of the embodiment and each modified example, it is preferable that the number of N is 2 and the number of K is 1. Alternatively, it is desirable that the number of N is 3 and the number of K is 1. Warpage is reduced.

DESCRIPTION OF SYMBOLS 100 Printed wiring board 10 Product 20z Insulation board 28 Through-hole 30 Core board 34F 1st conductor layer 34S 2nd conductor layer 34SW 2nd conductor layer in a frame part 50F, 50S Resin insulation layer 58F, 58S Conductor layer 60F, 60S Via conductor 80 Electron Parts 98 Frame 10G Product area

Claims (8)

An insulating substrate having a first surface and a second surface opposite to the first surface;
A first conductor layer formed on the first surface of the insulating substrate;
A resin insulation layer above the N layer laminated on the first surface and the first conductor layer;
An upper conductor layer of the (N-1) layer formed between adjacent upper resin insulation layers;
A second conductor layer formed on the second surface of the insulating substrate;
A resin insulation layer below the K layer laminated on the second surface and the second conductor layer;
A printed wiring board comprising a lower conductive layer of the (K-1) layer formed between adjacent lower resin insulating layers,
The N is an integer of 2 or more, the K is an integer of 1 or more, the number of N is larger than the number of K, and the thickness of the second conductor layer is the thickness of all the upper conductor layers. And thicker than the thickness of the first conductor layer. The printed wiring board according to claim 1, wherein the printed wiring board is formed by a product area and a frame portion surrounding the product area, and the first conductor layer is formed in the product area. One conductor layer and a first conductor layer in the frame part formed in the frame part, and the second conductor layer is formed in the second conductor layer in the product area and the frame part formed in the product area. Each upper conductor layer is formed in the product area, and each upper conductor layer is formed in the product area and each upper conductor in the frame part formed in the frame part. Each lower conductor layer is formed of a lower conductor layer in the product area formed in the product area and a lower conductor layer in the frame part formed in the frame portion. The area of the second conductor layer in the frame portion is the first conductor in the frame portion. Larger than the area of the area of the frame portion second conductor layer is larger than the area of the upper conductive layer of each said frame portion. 2. The printed wiring board according to claim 1, wherein the thickness of all the lower conductor layers is greater than the thickness of all the upper conductor layers. 2. The printed wiring board according to claim 1, further comprising an electronic component built-in opening penetrating the insulating substrate and the electronic component housed in the electronic component built-in opening. 3. The printed wiring board according to claim 2, wherein a value obtained by dividing the area of the second conductor layer in the frame by the area of the frame in the second surface is 0.85 or more, A value obtained by dividing the area of one conductor layer by the area of the frame portion in the first plane is 0.15 or less. 6. The printed wiring board according to claim 5, wherein the first conductor layer in the frame portion is formed only with alignment marks. 2. The printed wiring board according to claim 1, wherein the N is 3, the K is 1, and the lower conductor layer does not exist. 3. The printed wiring board according to claim 2, wherein the N is 3, the K is 1, and the lower conductor layer does not exist.

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