JP2012033528A - Aggregate wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an aggregate wiring board having a semiconductor element mounted on a flat wiring board, that can stably provide an electronic device by mounting the board favorably on another circuit board.SOLUTION: An aggregate wiring board 10 comprises: a product block 5 in which compact wiring boards 4 each including a stack of a plurality of insulation resin layers 1a to 1c and conduction layers 2a to 2d, and including a top surface provided with a mount part on which a semiconductor element S is mounted are integrally arranged vertically and horizontally; a frame-shaped marginal region 6 formed integrally around the product block 5; and dummy patterns 8a to 8d including the conduction layers 2a to 2d above and below each of the insulation resin layers 1a to 1c in the marginal region 6. The thermal expansion coefficient of the marginal region 6 is higher in the top surface side than in the lower surface side by increasing the area of the dummy patterns 8a to 8d in the conduction layers 2c and 2d on the lower surface side of the marginal region 6 as compared with the area thereof in the conduction layers 2a and 2b on the upper surface side of the marginal region 6.

Description

  The present invention has a product block in which a plurality of small wiring boards on which semiconductor elements are mounted are arranged in a row in the vertical and horizontal directions, and a frame-shaped discard margin area is integrally disposed around the product block. The present invention relates to an assembled wiring board formed.

  Conventionally, a collective wiring board has been used as a form in which a plurality of small wiring boards for mounting semiconductor elements such as semiconductor integrated circuit elements are handled simultaneously. This collective wiring board is integrally provided with a frame-shaped discard margin area around a product block in which a plurality of small wiring boards are arranged in an integrated manner vertically and horizontally with a cutting area in between. Then, a semiconductor element such as a semiconductor integrated circuit element is mounted on each small wiring board through, for example, solder bumps, and the semiconductor element is resin-sealed by, for example, an underfill method, and then along the cutting region. By cutting in this manner, a large number of electronic devices each having a semiconductor element mounted on a small wiring board are manufactured in an integrated manner.

  Such a collective wiring board is manufactured by, for example, a build-up method. Specifically, an uncured resin sheet is attached to the upper and lower surfaces of an insulating resin layer on which a conductor layer made of copper foil and a copper plating layer is formed, and the resin sheet is thermally cured and a via hole is formed by laser processing. Then, the next insulating resin layer is formed, and the next conductive layer made of a copper plating layer is formed on the surface of the insulating resin layer by a well-known semi-additive method. It is manufactured by laminating the conductor layers.

  In such a collective wiring board, in order to balance the conductor layer in the product block, a large number of dummy patterns made of the same conductor layer as the product block, such as a circle, a rectangle, and a hexagon, are discarded. By arranging the insulating resin layers on the top and bottom of the insulating resin layer, large warpage, twisting, or the like is prevented from occurring in the collective wiring board.

  When mounting a semiconductor element on each wiring board in the product block in this collective wiring board, solder bumps are formed on each wiring board in the product block, and the semiconductor elements are placed on the solder bumps. A method is employed in which the semiconductor element and the wiring board are connected via the melted solder bumps by heating them to a temperature at which the solder bumps melt, and then cooled to room temperature. .

JP 2001-326429 A

  As described above, in the conventional collective wiring board, a dummy pattern that is balanced with the product block is provided in the margin area, so even if the solder bump is heated to a temperature at which it melts, warping and twisting in the product block This is reduced, and the semiconductor element and the wiring board can be connected with molten solder in a substantially flat state. However, after the solder bump is melted and the semiconductor element and the wiring board are connected, when the wiring board on which the semiconductor element is mounted is returned to room temperature, the thermal expansion coefficient of the wiring board is larger than the thermal expansion coefficient of the semiconductor element. Therefore, the wiring board is thermally contracted to a greater extent than the semiconductor element, and as a result, warpage occurs such that the upper surface side of the wiring board becomes a convex surface. When such a warp is large, it is difficult to mount an electronic device having a semiconductor element mounted on the wiring board on another circuit board.

  The present invention has been devised in view of such conventional problems, and the problem to be solved is that the circuit board is large when the semiconductor element is mounted on the wiring board in the product block and returned to room temperature. It is possible to effectively prevent the occurrence of warpage, and thereby stably obtain an electronic device in which a semiconductor element is mounted on a flat wiring board and can be satisfactorily mounted on another circuit board. An object of the present invention is to provide a collective wiring board capable of satisfying the requirements.

  The collective wiring board of the present invention is formed by laminating a plurality of insulating resin layers and conductor layers, and small wiring boards having a mounting portion on which a semiconductor element is mounted on the upper surface are integrally formed in a vertical and horizontal arrangement. A product block and a frame-shaped discard margin area integrally formed around the product block, and a dummy pattern made of the conductor layer is provided above and below each insulating resin layer in the discard margin area. And the thermal expansion coefficient of the abandon margin region is larger than that of the upper surface side by increasing the area of the dummy pattern in the lower conductor layer than the conductor layer on the upper surface side of the abandon margin region. Is also larger on the lower surface side.

  According to the wiring board of the present invention, by increasing the area of the dummy pattern in the conductor layer on the lower surface side than the conductor layer on the upper surface side of the disposal margin region, the thermal expansion coefficient of the disposal margin region is lower on the lower surface side than the upper surface side. Therefore, when a semiconductor element is mounted on each wiring board of the product block, if it is heated above the temperature at which the solder bumps melt, the disposal margin area surrounding the product block is lower on the lower side than on the upper side. Due to the large thermal expansion, as a result, a deformation occurs such that the upper surface of each wiring board in the product block becomes concave due to the difference in thermal expansion between the upper surface side and the lower surface side. And after mounting a semiconductor element on each wiring board in the product block in this state and returning to room temperature, the thermal expansion coefficient of the wiring board is larger than the thermal expansion coefficient of the semiconductor element. As a result, the wiring board that has been deformed so that the upper surface becomes concave when heated is deformed in a direction that becomes flat at room temperature. Therefore, according to the collective wiring board of the present invention, an electronic device in which a semiconductor element is mounted on a flat wiring board and can be satisfactorily mounted on another circuit board can be obtained extremely stably.

FIGS. 1A and 1B are a cross-sectional view and a top view for explaining an example of an embodiment of the collective wiring board of the present invention. FIGS. 2A and 2B are main part plan views for explaining an example of the embodiment of the collective wiring board of the present invention. 3A, 3B, 3C, and 3D are cross-sectional views for explaining a method of manufacturing an electronic device by mounting semiconductor elements on the collective wiring substrate shown in FIGS.

  Next, an example of the embodiment of the collective wiring board of the present invention will be described with reference to FIGS. 1 (a) and 1 (b). As shown in FIG. 1 (a), the collective wiring board 10 of this example includes an interior of an insulating substrate 1 formed by laminating insulating resin layers 1a and 1c for build-up on upper and lower surfaces of a core insulating resin layer 1b. Further, conductor layers 2a, 2b, 2c, 2d made of copper foil or a copper plating layer are laminated on the surface, and protective solder resist layers 3a, 3b are deposited on the upper and lower surfaces thereof. The insulating resin layer 1b is made of a fiber reinforced insulating resin material in which a glass cloth is impregnated with a thermosetting resin. The insulating layers 1a and 1c are made of a filler-containing insulating resin material in which an inorganic insulating filler such as silicon oxide is dispersed in a thermosetting resin. The solder resist layer is made of a filler-containing photosensitive insulating resin material in which an inorganic insulating filler such as silicon oxide is dispersed in a photosensitive thermosetting resin. Those having a thermal expansion coefficient smaller than those of the conductor layers 2a, 2b, 2c, and 2d are used.

  As shown in FIG. 1B, a plurality of small-sized wiring boards 4 for mounting semiconductor elements such as semiconductor integrated circuit elements are arranged in a row in the central portion of the collective wiring board 10 in a vertical and horizontal manner. The product block 5 is formed, and a rectangular frame-shaped discard margin region 6 is formed on the outer periphery of the product block 5 so as to surround the product block 5. In this example, the product block 5 is formed by forming 16 wiring boards 4 in a 4 × 4 array. However, the number and arrangement of the wiring boards 4 arranged in the product block 5 are shown. What is necessary is just to change a method suitably as needed. Further, a plurality of product blocks 5 may be arranged in one collective wiring board 10.

  Each wiring board 4 is formed with a mounting portion for mounting a semiconductor element at the center of the upper surface thereof. As will be described later, the semiconductor element S is bonded to the mounting portion via the solder bumps 9. As shown in FIG. 1A, wiring conductors 7 including conductor layers 2a, 2b, 2c, and 2d are formed in a predetermined pattern from the mounting portion to the lower surface. Further, dummy patterns 8a, 8b, 8c, 8d made of conductor layers 2a, 2b, 2c, 2d are formed in the discard margin region 6.

  Such a collective wiring board 10 is manufactured by a build-up method. Specifically, uncured resin sheets for the insulating resin layers 1a and 1b are bonded to the upper and lower surfaces of the insulating resin layer 1b on which the conductor layers 2b and 2c made of copper foil and copper plating layer are formed, and the resin The sheet is heat-cured and via holes are formed by laser processing to form insulating resin layers 1a and 1b. Next, conductor layers 2a made of a copper plating layer are formed on the surfaces of the insulating resin layers 1a and 1b by a known semi-additive method, Manufactured by forming 2d.

  In the collective wiring board of this example, the areas of the dummy patterns 8 a, 8 b, 8 c, 8 d formed in the discard margin region 6 are different between the upper surface side and the lower surface side of the insulating substrate 1. Specifically, the area of the dummy patterns 8c and 8d on the lower surface side is set to be larger than the area of the dummy patterns 8a and 8b on the upper surface side.

  Here, examples of the dummy patterns 8a, 8b and 8c, 8d are shown in plan views in FIGS. In these drawings, FIG. 2A shows dummy patterns 8a and 8b, and FIG. 2B shows dummy patterns 8c and 8d. Here, only the dummy patterns 8a, 8b, 8c, and 8d are shown for easy understanding, and the display and description of the other wiring conductors 7 are omitted.

  As shown in FIGS. 2A and 2B, the dummy patterns 8a, 8b, 8c, and 8d are mainly a large number of strip-shaped patterns that extend from the product block side 5 to the outer peripheral side of the discard margin area 6. Are arranged at predetermined intervals so as to surround the product block 5. The dummy patterns 8a and 8b on the upper surface side of the insulating substrate 1 and the dummy patterns 8c and 8d on the lower surface side have different widths and lengths of the strip-shaped patterns. In this example, the width and length of each strip pattern in the upper dummy patterns 8a and 8b are smaller than the width and length of the strip patterns in the lower dummy patterns 8c and 8d. Thereby, the areas of the dummy patterns 8c and 8d on the lower surface side are larger than the areas of the dummy patterns 8a and 8b on the upper surface side. As described above, since the area of the dummy patterns 8c and 8d on the lower surface side is larger than the area of the dummy patterns 8a and 8b on the upper surface side, the thermal expansion coefficient on the lower surface side has a thermal expansion coefficient on the upper surface side. It is larger than the expansion coefficient. This is because the thermal expansion coefficients of the copper foils and copper plating layers constituting the dummy patterns 8a, 8b, 8c, and 8d are larger than the thermal expansion coefficients of the insulating resin layers 1a, 1b, and 1c. In the present invention, the area of the dummy patterns 8c and 8d on the lower surface side is larger than the area of the dummy patterns 8a and 8b on the upper surface side in this way, and the thermal expansion coefficient on the lower surface side in the disposal margin region 6 is the thermal expansion on the upper surface side. It is important that it is larger than the coefficient.

  Here, a process of mounting a semiconductor element on the collective wiring board 10 of this example to form an electronic device will be described. First, as shown in FIG. 3A, solder bumps 9 are provided on the collective wiring substrate 10 and the semiconductor element S is placed on the solder bumps 9. At this time, the assembly wiring board 10 is in a substantially flat state at room temperature.

  Next, as shown in FIG. 3B, the assembly wiring board 10 on which the semiconductor element S is placed is heated to a temperature at which the solder bumps 9 melt. Thereby, the solder bump 9 is melted and the semiconductor element S and each wiring board 4 are electrically connected. At this time, in the disposal margin region 6, the coefficient of thermal expansion is larger on the lower surface side than the upper surface side of the insulating substrate 1, so that the lower surface side is more thermally expanded than the upper surface side. Due to the difference in thermal expansion on the lower surface side, deformation occurs such that the upper surface of each wiring board 4 in the product block 5 becomes concave.

  Next, as shown in FIG. 3C, the assembly wiring board 10 to which the semiconductor element S is connected is returned to room temperature. At this time, since the thermal expansion coefficient of the wiring board 4 is larger than the thermal expansion coefficient of the semiconductor element S, the wiring board 4 is thermally contracted more than the semiconductor element S, and as a result, the upper surface becomes concave when heated. The deformed wiring board 4 is deformed in a direction that becomes flat at room temperature.

  Finally, as shown in FIG. 3D, the electronic device in which the semiconductor element S is mounted on the small-sized wiring board 4 by cutting each wiring board 4 in the product block 5 along the cutting region. A large number of 20 are produced simultaneously. At this time, since the wiring board 4 in the manufactured electronic device 20 is flat, the electronic device 20 can be favorably mounted on another circuit board.

  Thus, according to the collective wiring board of the present invention, an electronic device in which a semiconductor element is mounted on a flat wiring board and can be satisfactorily mounted on another circuit board can be obtained extremely stably. In addition, this invention is not limited to an example of the above-mentioned embodiment, and it cannot be overemphasized that a various change is possible if it is the range which does not deviate from the summary of this invention. For example, in the example of the above-described embodiment, the dummy patterns 8a, 8b, 8c, and 8d have a strip shape, but may have other shapes such as a circle, a rectangle, and a hexagon.

DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 1a, 1b, 1c, Insulation resin layer 2a, 2b, 2c, 2d Conductor layer 4 Small wiring board 5 Product block 6 Discard allowance area 8a, 8b, 8c, 8d Dummy pattern

Claims (1)

  A product block formed by laminating a plurality of insulating resin layers and a conductor layer, and having a small wiring board having a mounting portion on which a semiconductor element is mounted on the top surface, which is integrally formed vertically and horizontally, and the product block A collective wiring board having a frame-shaped discard margin region integrally formed around the periphery, and having dummy patterns made of the conductor layers above and below each insulating resin layer in the discard margin region In addition, by increasing the area of the dummy pattern in the conductor layer on the lower surface side than the conductor layer on the upper surface side of the discard margin region, the thermal expansion coefficient of the discard margin region becomes larger on the lower surface side than on the upper surface side. A collective wiring board characterized by comprising:

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