JP2016082661A - Method for suppressing cross current of power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow power converters connected in parallel with each other to continue parallel operation by suppressing cross current even if communication between the power converters stops.SOLUTION: A method detects output current detection values of power converters in two types of load patterns, and on the basis of the output current detection values in the respective load patterns, estimates amplitude difference ΔV1 of output voltage, phase difference Δθ1 of the output voltage among the power converters, and impedance difference R1, X1 between each power converter and a load. On the basis of the amplitude difference ΔV1 of output voltage, the phase difference Δθ1 of the output voltage among power converters, and the impedance difference R1, X1 between each power converter and the load, the method calculates an amplitude command value V1* and a phase command value θ1* of the output voltage of each power converter. The method uses the amplitude command value V1* and the phase command value θ1* to control the amplitude and phase of the output voltage of each power converter.SELECTED DRAWING: Figure 5

Description

  The present invention relates to cross current curtailment (equalization of current duties) of a power conversion device that outputs AC voltage connected in parallel, and in particular, other devices output such as communication between power conversion devices connected in parallel stops. It relates to the suppression of cross current when the current becomes unknown.

  As a problem in the parallel configuration of the uninterruptible power supply devices, a cross current is generated between the uninterruptible power supply devices, resulting in a difference in duty for each uninterruptible power supply device. As a countermeasure, there is a method of suppressing the cross current by detecting the load current and distributing it to each uninterruptible power supply.

  In Non-Patent Document 1, the “PQ drooping method” that gives drooping characteristics to the amplitude and frequency of the output voltage according to the active power and reactive power output from the device, the cross current is detected even if the output current of other devices is unknown. It is described that it can be suppressed to some extent. It also describes that the relationship between active power / reactive power and amplitude / frequency is determined by the internal impedance of the inverter.

  Paragraph [0009] of Patent Document 1 describes that an impedance setting device is used to compensate for a voltage drop in the line impedance and suppress a cross current between devices. However, it does not describe how to adjust the impedance setting device.

  Paragraph [0011] of Patent Document 2 describes that a cross current is detected by detecting a cross current between devices and adjusting a frequency for an effective component of the cross current and a voltage amplitude for an ineffective component. ing.

  Paragraph [0024] of Patent Document 3 describes that the oscillatory cross current of active power can be suppressed by changing the phase of the output voltage of the inverter in accordance with the output of active power.

JP 2004-23922 A Japanese Patent Laid-Open No. 06-276750 JP 2003-111281 A

"Consideration of Parallel Control of CVCF Inverter Focusing on Output Impedance" ELECTRONICS D, Vol.128, No.2, 2008

  Generally, an uninterruptible power supply is used for supplying power to an important load, and the allowable voltage amplitude and frequency fluctuation range is limited. In such a case, the voltage amplitude and frequency that can be dropped by the PQ drooping method are limited, and the effect of suppressing the cross current is reduced.

  The conventional cross current control method requires a function of communicating information (such as an output current detection value of each uninterruptible power supply) between different uninterruptible power supplies. Therefore, when the communication line becomes disconnected due to an accident or the like and communication becomes impossible, the cross current cannot be suppressed.

  Patent Document 1 is a method for suppressing a cross current by compensating for a voltage drop generated by a line impedance of an inverter. This method can be used even when there is a difference in line impedance. Furthermore, if the voltage drop compensation at the load line impedance is omitted, the cross current can be suppressed even if the current output by other devices is unknown. However, if there is an error in the estimation of the line impedance of the inverter, a cross current will be generated. In addition, it is necessary to manually adjust the impedance setting value to suppress the cross current. Further, when there is a deviation in the amplitude or phase of the output voltage due to individual differences of the inverters themselves, a cross current will be generated.

  Further, since the voltage drop due to the line impedance is reduced when the load is lightened, the influence of the amplitude and phase shift of the output voltage is relatively increased. In particular, when there is no load, the current is zero and the voltage drop due to the line impedance is also zero. Therefore, if there is a deviation in the amplitude or phase of the output voltage with no load, the voltage deviation cannot be compensated no matter how the line impedance is adjusted, and the cross current cannot be suppressed.

  Patent Document 2 adds a detector for the total output current of all uninterruptible power supply units, and divides by the number of operating uninterruptible power supply units to obtain the average output current. A cross current is obtained from the difference between the average output current and its own output current, and the frequency and amplitude are adjusted according to the magnitude of the cross current to suppress the cross current. However, the addition of detectors increases the cost, and the wiring is complicated because the same detection signal is distributed and transmitted from the bus board to each uninterruptible power supply.

  In addition, the reliability decreases due to the addition of parts. For example, if the total current detector fails or the detector output becomes zero due to a broken wire, all uninterruptible power supplies operate to make the output current zero, so the output voltage will fluctuate significantly. . Even when the cross current is obtained using communication instead of the detector, if the communication is stopped due to an abnormality, the normal cross current cannot be detected, and the cross current cannot be suppressed.

  Patent Document 3 is a system in which the stability is improved by changing the phase instead of the frequency in the PQ drooping system. However, the effect of suppressing the steady cross current cannot be obtained.

  As described above, in the power converters connected in parallel, even when communication between the power converters is stopped, it is a problem to suppress the cross current and continue the parallel operation.

  The present invention has been devised in view of the above-described conventional problems, and one aspect thereof is that a plurality of power converters that output an AC voltage are connected in parallel, and a cross current that flows between the outputs of each power converter is calculated. A method of suppressing a cross current of a power converter to suppress a filter output current or an inverter output current of each power converter in a plurality of load patterns, and based on a filter output current or an inverter output current of each load pattern, Estimate the output voltage amplitude difference, output voltage phase difference, impedance difference between each power converter and load, and output voltage amplitude difference between each power converter, output voltage Based on the phase difference and the impedance difference between each power converter and the load, the amplitude command value and phase command value of the output voltage of each power converter are calculated, and the amplitude command value and phase And controlling the amplitude and phase of the output voltages of the power converter using a decree value.

  Further, as one aspect thereof, by controlling the amplitude and phase of the output voltage of each power converter in the first load pattern, the deviation of the filter output current or inverter output current of each power converter and the output current command value Stores the amplitude command value of the output voltage between each power converter when the effective value is equal to or less than the first threshold, the phase command value of the output voltage, the output current command value, the filter output current, or the inverter output current, By controlling the amplitude and phase of the output voltage of each power converter with the second load pattern, the effective value of the deviation between the filter output current or inverter output current of each power converter and the output current command value is greater than or equal to the second threshold value. Output voltage amplitude command value, output voltage phase command value, output current command value or filter output current or inverter The force current is stored, and based on the values stored in the first load pattern and the second load pattern, the output voltage amplitude difference between the power converters, the output voltage phase difference, and each power The impedance difference between the converter and the load is calculated and stored, the amplitude difference of the output voltage between the stored power converters, the phase difference of the output voltage, and between each power converter and the load Using the impedance difference as a fixed value for all load patterns, the amplitude command value and the phase command value of the output voltage of each power converter are calculated.

  Moreover, as another aspect, the filter output current of the power converter in two or more types of load patterns is detected, and each power is controlled by controlling the amplitude and phase of the output voltage of each power converter in the first load pattern. The amplitude command value of the output voltage between the power converters and the phase command value of the output voltage when the effective value of the deviation between the filter output current of the converter or the inverter output current and the output current command value is less than the first threshold. And output current command value or filter output current or inverter output current, and filter output of each power converter by controlling amplitude and phase of output voltage of each power converter in the second load pattern It is detected that the effective value of the deviation between the current or inverter output current and the output current command value is larger than the second threshold, and the filter output current or inverse When it is established that the effective value of the deviation between the output current and the output current command value is less than the first threshold value, the output voltage amplitude command value, the output voltage phase command value, and the output current command value at that time Alternatively, the filter output current or the inverter output current is stored, and the amplitude command value of the output voltage at the two time points, the phase command value of the output voltage, and the output current command value, the filter output current, or the inverter output current. Calculate and store the output voltage amplitude difference, output voltage phase difference, and impedance difference between each power converter and the load. If there are three or more load patterns, the third and later In the load pattern, in the same manner as the first load pattern and the second load pattern, the amplitude command value of the output voltage between the power converters, the phase command value of the output voltage, Each time these stored values are updated, the output voltage amplitude command value, output voltage phase command value, and output current command value are updated. The output voltage amplitude difference, the output voltage phase difference, and the impedance difference between each power converter and the load are calculated, and the output voltage amplitude difference and output voltage phase difference of each power converter are calculated. The amplitude command value and the phase command value of the output voltage of each power converter are calculated based on the impedance difference between each power converter and the load.

  In addition, as one aspect thereof, one of the load patterns of the test run is limited to no load, and the amplitude difference and the phase deviation are adjusted so that the cross current does not become zero when the impedance difference is zero and the amplitude is adjusted. Find the difference and phase difference, and adjust the impedance difference between each power converter and the load based on the difference between the output current command value and the filter output current or inverter output current and the load power factor in the other load pattern The amplitude command of the output voltage of each power converter based on the amplitude difference and phase difference obtained at the time of the no-load pattern and the impedance difference between each power converter and the load adjusted at the time of the other load pattern A value and a phase command value are calculated.

  Further, as one aspect thereof, each power conversion device includes a bypass circuit that bypasses the power conversion device. When the bypass power supply is abnormal, the correction value is subtracted from the individual rated frequency of each power conversion device, and the result is integrated to obtain 2π. The output voltage is controlled based on a value obtained by adding the phase command value to the value obtained by multiplying the value, the amplitude command value of the output voltage, and the filter output voltage detection value.

  Further, as one aspect thereof, the harmonic component of the filter output voltage and the harmonic component of the filter output current of each power converter are detected, and the amplitude and phase of the output voltage of each power converter are detected using each harmonic component. adjust.

  Further, as one aspect thereof, when the effective value of the current output current command value is larger than the third threshold value, and the effective value of the output current command value before one calculation cycle is smaller than the third threshold value, one effective cycle before the calculation cycle Adjust the output voltage phase difference and output voltage amplitude difference according to the effective value of the output current command value, the effective value of the current output current command value is smaller than the third threshold value, the output current command one calculation cycle before When the effective value of the value is larger than the third threshold, the effective power component of the output current command value divided by the effective value of the output current command value and the reactive power component of the output current command value are The impedance difference between each power converter and the load is adjusted based on a value obtained by dividing by the value and a value obtained by subtracting the output current command value amplitude one calculation cycle before from the value representing the rated current amplitude. To do.

  According to the present invention, in a power converter connected in parallel, even when communication between the power converters is stopped, it is possible to suppress the cross current and continue the parallel operation.

The circuit diagram which shows the main circuit of the power converter device in Embodiment 1. FIG. The figure which shows the output voltage control block of the inverter in Embodiment 1. FIG. The figure which shows the cross current control control block (before parameter estimation) of the inverter in Embodiment 1. FIG. The figure which shows the parameter estimation block for the cross current of the inverter in Embodiment 1. FIG. The figure which shows the cross current control control block (after parameter estimation) of the inverter in Embodiment 1. FIG. The figure which simplified the parallel connection structure of the power converter device. The figure which shows the parameter estimation block for the cross current of the inverter in Embodiment 2. FIG. The figure which shows the parameter estimation block for the cross current control of the inverter in Embodiment 2. FIG. 9 is a timing chart showing each waveform in the second embodiment. The figure which shows the cross current control block (before estimation) of the inverter in Embodiment 3. The figure which shows the output voltage control block of the inverter in Embodiment 4. FIG. The figure which shows the cross current control block (before estimation) of the inverter in Embodiment 4. The figure which shows the compensation block of a frequency difference. FIG. 10 is a diagram illustrating an output voltage control block of an inverter according to a fifth embodiment. FIG. 20 is a diagram showing main circuit conditions to be verified in the eighth embodiment. The figure which shows a mode that load fluctuation is repeated on the conditions which do not become no load, and voltage characteristics are arrange | equalized. FIG. 10 is a diagram illustrating an output voltage control block of an inverter according to an eighth embodiment. FIG. 10 is a diagram illustrating an operation of an eighth embodiment. The figure which shows the comparison of the necessary adjustment amount by the load before a fluctuation | variation. FIG. 10 is a block diagram illustrating a cross current suppression control unit of a control block according to an eighth embodiment. The figure which shows the output voltage characteristic of the uninterruptible power supply before control. The figure which shows the output voltage characteristic of the uninterruptible power supply after control (when uninterruptible power supply characteristics correspond in average current IdA). The figure which shows the case where the average current after that increases to IdB.

  FIG. 1 shows the main circuit configuration of the uninterruptible power supply devices connected in parallel. In this figure, as an example, three uninterruptible power supply units are connected in parallel.

  Three uninterruptible power supplies UPS1, UPS2, UPS3 are connected in parallel to the AC power supply 1. This AC power supply 1 is also used as a bypass power supply. A load 2 is connected to the three uninterruptible power supply units UPS1 to UPS3.

  The uninterruptible power supply UPS1 is connected to the AC power source 1 and is connected between the converter CNV1 that converts AC power into DC power, the LCL filter 3 that is connected between the AC power source 1 and the converter CNV1, and removes switching noise of the converter CNV1. The capacitor C1 connected to the DC bus of the converter CNV1, the DC power supply 4 for supplying power to the load 2 instead of the AC power supply 1 when a power failure occurs, the DC power supply 4 connected between the DC power supply 4 and the DC bus A chopper CHP1 that boosts the voltage of the inverter, an inverter INV1 that converts DC power output from the converter CNV1 and the chopper CHP1 into AC power and supplies the AC power to the load 2, and a detector 5 that detects an inverter output current Iinv1 of the inverter INV1; An LC filter 6 for removing switching noise of the inverter INV1; A detector 7 for detecting the filter output voltage V1, a detector 8 for detecting the filter output current Iups1, a detector 9 for detecting the bypass voltage Vbyp1, and the AC power supply 1 and the filter output when the uninterruptible power supply UPS1 is abnormal. And a switch TS1 that directly supplies power from the AC power supply 1 to the load 2 while bypassing the uninterruptible power supply UPS1.

  In normal times, the switch TS1 is in an open state. The output terminal of the uninterruptible power supply UPS1 is connected to the parallel connection point by a cable, and the parasitic resistance R1 and inductance component L1 of the cable are shown together. The detector used for control of converter CNV1 and chopper CHP1 is omitted. The uninterruptible power supply devices UPS2 and UPS3 are similarly configured.

  FIG. 2 shows the output voltage control circuit 10 of the inverter INV1. As shown in FIG. 2, in the low-pass filter LPF, PWM switching noise and the like are removed from the detection signal of the filter output voltage V1. Next, based on the internal phase information ωt + θ1 * of the control circuit, the dq converter 11 converts the detection signal on the fixed coordinates of the filter output voltage V1 into the values Vd1 and Vq1 on the rotating coordinates. Here, it is assumed that the d-axis of the rotating coordinate represents a component synchronized with the internal phase, and the q-axis represents a component delayed by 90 deg with respect to the internal phase.

  A subtractor 12 obtains a deviation between this Vd1 and the command value V1 * + Vstd. The amplitude command value V1 * is calculated in a cross current suppression control block described later. Vstd represents the rated voltage amplitude and is 1 on the control circuit. A subtractor 13 obtains a deviation between Vq1 and 0 which is a command value. Usually, the command value of Vq1 is fixed to zero.

  The amplifier AMP1 receives the output (deviation) of the subtractor 12 and performs amplifier processing such as proportional integration. The amplifier AMP2 receives the output (deviation) of the subtractor 13 and performs amplifier processing such as proportional integration. Based on the internal phase information ωt + θ1 * of the control circuit, the dq inverse converter 14 converts the voltage command value on the rotating coordinate output from the amplifiers AMP1 and AMP2 into a value on the fixed coordinate.

  The PWM modulator PWM inputs a voltage command value on fixed coordinates and outputs a gate signal Gate1. The output gate signal Gate1 is input to the inverter INV1. The PLL processor PLL receives a detection signal of the bypass voltage Vbyp1 and outputs a synchronized phase signal ωt. Then, the adder 15 adds a correction phase signal (phase command value) θ1 * to the output result of the PLL processor PLL. The phase signal ωt + θ1 * output from the adder 15 is used for the dq converter 11 and the dq inverse converter 14.

  In addition, although omitted in FIG. 2, different processing is performed on the detection signal of the filter output voltage V1 to improve the waveform distortion, and the result is added to the voltage command value, or the inverter output current is improved to improve stability and response. An appropriate gain process may be performed on the detection signals of Iinv1 and filter output current Iups1 and added to the voltage command value.

  The control block in FIG. 2 is simply intended to make the output voltage of the inverter INV1 a sine wave having an amplitude V1 * + Vstd and a phase command value θ1 *, and has no function of suppressing a cross current alone.

  FIG. 3 shows a cross current suppression control block before parameter estimation of the inverter INV1 in the first embodiment. In this block, the cross current is suppressed by feedback control using communication. The cross current suppression control block is configured as follows.

  First, the dq converter 21 converts the detected value of the filter output current Iups1 into a value on the rotation coordinate based on the internal phase information ωt + θ1 * of the control circuit. The AC component is removed from the output of the dq converter 21 by the low pass filter LPF, and the active power component Id1 and the reactive power component Iq1 in the fundamental wave of the filter output current Iups1 are extracted.

  The filter output current Iups1 may be replaced with the inverter output current Iinv1.

  The active power component Idref of the output current command value and the reactive power component Iqref of the output current command value are obtained by determining one representative uninterruptible power supply and inputting the output current of the representative uninterruptible power supply by communication And Alternatively, an average value of all filter output currents or inverter output currents may be obtained by communication. When the device itself is a representative uninterruptible power supply or an average value is calculated, the active power component Id1 and the reactive power component Iq1 are transmitted to the other uninterruptible power supply. The broken line of FIG. 3 represents the signal transmitted / received between different uninterruptible power supply apparatuses using communication.

  Next, the subtractors 22a and 22b obtain deviations between the output current command values Idref and Iqref and the active power component Id1 and the reactive power component Iq1. The multipliers 23a, 23b, 23c, and 23d receive the outputs (deviations) of the subtracters 22a and 22b, and calculate the products of the coefficients α and β, respectively.

  This coefficient will be described. If α = 1 and β = 0, the voltage amplitude is increased when the active power component Id1 of the output current is smaller than the output current command value Idref, and the reactive power component (delay) Iq1 is smaller than the output current command value Iqref. In this case, the output current is brought closer to the command value by delaying the phase. This is an effective method when the impedance between the uninterruptible power supply devices is resistance.

  If α = 0 and β = 1, the voltage phase is advanced when the active power component Id1 of the output current is smaller than the output current command value Idref, and the reactive power component (lag) Iq1 is smaller than the output current command value Iqref. Increases the voltage amplitude. This is effective when the impedance between the uninterruptible power supply devices is a reactor.

  In general, the impedance between uninterruptible power supplies can be expressed as a series connection of a resistor and a reactor for the fundamental component, and one of the coefficient α and coefficient β is set to 1 according to the larger impedance of the resistor or reactor. Or by setting an intermediate value according to the impedance, the time required to suppress the cross current can be shortened. However, even if the coefficients α and β are set inappropriately, the suppression control does not become unstable because it only takes time to suppress the cross current. For this reason, the coefficients α and β are not subject to automatic adjustment.

  Next, the adder 24a adds the outputs of the multipliers 23a and 23c, and the adder 24b adds the outputs of the multipliers 23b and 23d.

  The outputs of the adders 24a and 24b are subjected to processing such as integration by the amplifiers AMP3 and AMP4 to output the amplitude deviation V1 cmp and the phase deviation θ1 cmp of the cross current suppression feedback.

  The obtained amplitude deviation V1 cmp and phase deviation θ1 cmp are directly used as the amplitude command value V1 * and the phase command value θ1 * by the control as shown in the equation (1).

  By outputting the amplitude command value V1 * and the phase command value θ1 *, feedback that suppresses the cross current is configured.

  FIG. 4 shows a configuration of a parameter estimation block 51a for suppressing cross current in the first embodiment.

  The effective value of the deviation between the filter output current Iups1 and the output current command value is obtained by the following equation (2) using the active power component Id1, the reactive power component Iq1, and the output current command values Idref, Iqref.

  Specifically, the squares of the deviations Idref-Id1, Iqref-Iq1 obtained by the cross current suppression control block are obtained by the multipliers 31a and 31b. The outputs of the multipliers 31a and 31b are added by an adder 32, and the square root of the output of the adder 32 is obtained by an arithmetic unit 33.

  Next, the comparator 34 outputs 1 when the output of the square root obtained by the calculator 33 is less than the first threshold value Itha. Usually, the first threshold Itha is set to a value close to zero, such as 1%.

  When the output of the comparator 34 becomes 1, the hold device 35 continues to output 1. The buffer 36 stores output current command values Idref and Iqref, an amplitude shift V1 cmp, and a phase shift θ1 cmp when the output of the hold device 35 changes from 0 to 1. The stored output current command values Idref, Iqref, amplitude deviation V1 cmp, phase deviation θ1 cmp are IdA, IqA, amplitude command values are V1A *, and phase command value θ1A *.

  Deviations between the output current command values Idref, Iqref, (referred to as IdA, IqA) stored in the buffer 36 and the current output current command values Idref, Iqref are calculated by subtracters 37a, 37b. Then, the squares of the outputs (Idref−IdA, Iqref−IqA) of the subtractors 37a and 37b are obtained by the multipliers 38a and 38b. Next, the adders 39 add the outputs of the multipliers 38a and 38b. Then, the computing unit 40 obtains the square root of the output of the adder 39. When the output of the square root obtained by the computing unit 40 by the comparator 41 exceeds the second threshold value Ithb, 1 is output. Usually, the second threshold value Ithb is set to a large value such as 50%. This is to improve the estimation accuracy by using two measurement points with different load conditions.

  When the AND element 42 detects that the outputs of the two comparators 34 and 41 both output 1, it outputs 1. The hold unit 43 continues to output 1 when the output of the AND element 42 becomes 1. The buffer 44 stores output current command values Idref and Iqref, an amplitude shift V1 cmp, and a phase shift θ1 cmp when the output of the hold device 43 changes from 0 to 1. The stored values are IdB, IqB, amplitude command value V1B *, and phase command value θ1B *, respectively.

  The arithmetic unit 45 inputs the data stored in the buffers 36 and 44, and based on equations (16), (17), (18), and (19) to be described later, impedance difference R1, X1, amplitude difference ΔV1, level. The phase difference Δθ1 is calculated. In the AND element 46, the switch SW is short-circuited only when both of the hold devices 35 and 43 output 1, and the output of the arithmetic unit 45 (the expressions (16), (17), (18), (19) The calculation result is output and used in the cross current control control block.

  Note that the difference between Idref and Iqref stored in the buffers 36 and 44 and Id1 and Iq1 at the time of storage is very small. Therefore, instead of Idref and Iqref, the active power component Id1 and the reactive power component Iq1 in the fundamental wave of the filter output current Iups1 or the inverter output current Iinv may be used as values input to the buffers 36 and 44.

  FIG. 5 shows a cross current suppression control block after parameter estimation of the inverter INV1 in the first embodiment. Based on the internal phase information ωt + θ1 * of the control circuit, the dq converter 50 converts the detected value of the filter output current Iups1 into a value on the rotational coordinates. In the low-pass filter LPF, the AC component is removed from the output of the dq converter 50, and the active power component Id1 and the reactive power component Iq1 that are signals of only the DC component (fundamental wave component) are extracted.

  Multipliers 52a, 52b, 52c, and 52d calculate the products of the active power component Id1 and reactive power component Iq1 and the impedance differences R1 and X1 output from the estimation block 51a. An adder 53a adds the outputs of the multipliers 52a and 52c to obtain a voltage drop Vdrop1. Further, the adder 53b subtracts the output of 52d from the output of the multiplier 52b to obtain the phase delay θdrop1 due to the voltage drop.

  Then, the subtractor 54a subtracts the amplitude difference ΔV1 output from the estimation block 51a from the voltage drop Vdrop1, and outputs an amplitude command value V1 *. Further, the subtractor 54b subtracts the phase difference Δθ1 of the estimation block 51 from the phase delay θdrop1 due to the voltage drop, and outputs a phase command value θ1 *. The amplitude command value V1 * and the phase command value θ1 * output from the subtracters 54a and 54b are input to the inverter control block of FIG.

  The deviation can be canceled by subtracting the amplitude difference ΔV1 and the phase difference Δθ1 obtained by the estimation block 51a from the voltage drop Vdrop1, the phase delay θdrop1 due to the voltage drop. For the impedance differences R1 and X1, for example, if Id1> 0, the product of the impedance difference R1 is added to the voltage command value, and the product of the impedance difference X1 is added as a phase advance command. Thereby, the voltage drop can be canceled by excessively outputting the amount corresponding to the voltage drop at the impedance difference R1, X1 from the uninterruptible power supply UPS. Iq1 is the same as Id1. The amplitude command value V1 * and the phase command value θ1 * obtained as described above are expressed by equation (3).

  At this time, if Vstd = 1, and if Id1 = Id and Iq1 = Iq, the expression (3) coincides with the expressions (12) and (13) described later. If the equations (12) and (13) are satisfied, the cross current does not expand and keeps zero.

  Consider a case where Id1 ≠ Id and Iq1 ≠ Iq and a cross current is generated. The voltage drop of the impedance difference R1, X1 is canceled under the condition including the cross current, but the voltage drop due to the resistance component Rc and the reactance component Xc is not canceled by the control. For example, when the output current of the uninterruptible power supply UPS1 becomes excessive as compared with other uninterruptible power supply apparatuses under the condition of Rc> Xc, the voltage drop due to the resistance component Rc becomes larger than that of the other uninterruptible power supply apparatuses. Therefore, the filter output voltage of the uninterruptible power supply UPS1 is smaller than other uninterruptible power supply apparatuses. Therefore, the output current of itself is decreased, the output current of the other uninterruptible power supply is promoted to increase, and the cross current is decreased. Since it becomes steady where Id1 = Id and Iq1 = Iq finally, the cross current is suppressed.

  With the above operation, by using the estimated parameters, it is possible to suppress the cross current without using the output current or load current detection signal of another uninterruptible power supply. Therefore, the control block of FIG. 5 does not use the output current detection signal of another uninterruptible power supply, unlike FIG.

  In actual operation, the cross current control block shown in FIG. 3 is prepared and a test run is performed. In the trial run, two appropriate dummy loads are prepared (one may be no load). First, operation is performed with the first load, and it is confirmed by the control block that the cross current is close to zero and the value is stored in the buffer 36 of FIG. Next, the load is switched to the second load, and it waits again until the cross current becomes close to zero. After confirming that the value is stored in the buffer 44, the test operation is completed. At this time, parameter estimation is completed by the estimation block 51a of FIG.

  After that, the cross current control control block is switched to that shown in FIG. 5, the load is switched from the dummy load to the actual load, and the actual operation is performed. During this actual operation, the connection line for the output current detection signal of another uninterruptible power supply used during the trial operation may be removed. Moreover, even if a disconnection accident occurs in the connecting line in a state where the wiring is left as it is, the parallel operation of the uninterruptible power supply can be continued while suppressing the cross current.

  In this method, one representative uninterruptible power supply is determined. However, since the representative uninterruptible power supply always has output current command values Idref and Iqref coincide with its own output current, the cross current suppression amplifier and the estimation block 51a operate. do not do. Since the other uninterruptible power supply devices operate so as to match the output current to the representative uninterruptible power supply device, the representative uninterruptible power supply device can suppress the cross current without any particular action. Alternatively, the output current command values Idref and Iqref may be averaged, and adjustment may be performed so that the output current matches the average current in all uninterruptible power supply devices.

  It is assumed that the amplifier of the cross current suppression control block is operated once every fundamental frequency period to several seconds. This is due to the following reason.

  It takes time from when the amplitude command value V1 * and the phase command value θ1 * are updated until it appears as a change in the cross current.

  The communication load is reduced, and the method of the first embodiment can be operated even in an inexpensive communication system.

  The parameter estimation method according to the first embodiment and the principle of suppressing the cross current by it will be described with reference to FIG. The first embodiment is assumed to be applied in a state where the AC power supply is not interrupted and the filter output voltage is synchronized with the bypass voltage so that the power supply can be immediately switched to the bypass power supply. In FIG. 6, only the fundamental wave component is focused for simplification, the inverter of the uninterruptible power supply is replaced with an AC voltage source, the chopper CHP1 and the converter CNV1 are omitted, the internal impedance of the filter and the inverter, and the parasitic impedance of the cable are resisted. And the reactor. It is assumed that the three loads are the same, and that each uninterruptible power supply UPS1 to UPS3 outputs an equal active power component current Id and a delayed reactive power component current Iq. For the sake of explanation, the uninterruptible power supply UPS1 to UPS3 are provided with a switch on a parallel connection bus.

  In the actual configuration, there is no switch and the circuit is always short-circuited. At this time, if the amplitude and phase of the load voltage are expressed by the following equation (4) with the switch open, the potential difference between the switches becomes zero, so that no cross current flows even if the switch is short-circuited.

  Taking the uninterruptible power supply UPS3 as a reference, the rated voltage amplitude is Vstd, the voltage amplitude output from the uninterruptible power supply UPS3 is V, and the voltage phase when the bypass voltage is the reference is θ. The rated voltage amplitude Vstd becomes 1 by normalization on the control circuit. The resistance component of the inverter internal impedance of the uninterruptible power supply UPS3, the filter and cable parasitic impedance is Rc, and the reactance component is Xc. The voltage amplitude output by the uninterruptible power supply UPS1 is added with a value V equal to the uninterruptible power supply UPS3, an amplitude difference ΔV1 therefrom, and V1 * as an amplitude command value by control.

  The same applies to the phase, which can be expressed as the sum of a value θ equal to the uninterruptible power supply UPS3, a phase difference Δθ1, and a phase command value θ1 * by control. The impedance of the uninterruptible power supply UPS1 can also be expressed by the sum of the value resistance component Rc and reactance component Xc equal to the uninterruptible power supply UPS3 and the impedance differences R1 and X1 therefrom. With respect to the uninterruptible power supply UPS3, a relational expression between the bypass voltage and the voltage of the in-phase component can be established as the following expression (5) in a state where the switch is opened.

  This equation (5) represents that the output voltage VL is obtained by subtracting the voltage drop due to the impedance from the output voltage V of the uninterruptible power supply UPS3. As for the reactance component Xc, the voltage drop is advanced by 90 deg with respect to the passing current, so the product of the 90 deg delayed current Iq is the in-phase component. Regarding the bypass voltage and the voltage of the orthogonal component, the relational expression can be established as the following expression (6).

  In this equation (6), the phase delay is positive. The phase lag of the output voltage VL is obtained by adding the phase lag due to the impedance to the phase lag of the output voltage V of the uninterruptible power supply UPS3. Regarding the reactance component Xc, the phase shift due to the in-phase component Id of the passing current is advanced, and therefore subtraction is performed in the equation (6). With respect to the above formula, since the output voltage is controlled by the PLL processor PLL so as to be synchronized with the bypass voltage, θ≈0 and θL≈0 are established. Further, since the amplitude is controlled so as to become the rated voltage Vstd, V≈Vstd and VL≈Vstd. When this is used to approximate equations (5) and (6), equation (7) is obtained. The detection error of the voltage detector is generally 1% amplitude, phase shift 2/3 deg = 0.116 rad, and adjustment is 10% when the impedance between uninterruptible power supply devices is 0.1%, 1% = 0.01 rad = 0.57 deg. The cross current is suppressed. The addition of both is at most about 3% = 0.03 rad, so the application of approximation is reasonable.

  For the uninterruptible power supply UPS1 and UPS2, the following equations (8) and (9) can be obtained by similarly establishing a relational expression and applying approximation.

  The amplitude difference ΔV1 and the phase difference Δθ1 are caused not only by individual differences between apparatuses but also by detector errors and detection signal delays. Impedance differences R1 and X1 represent a cable length shift from the uninterruptible power supply to the parallel connection point, a filter LC manufacturing error, a switching element dead time shift, and the like. If the cross current becomes zero even when the switch of FIG. 6 is short-circuited, since the equation (4) is established even in the open state of the switch, the equation (4) is used, and further from the equations (8) and (9) When the equation (7) is subtracted, the following equations (10) and (11) are obtained.

  For the uninterruptible power supply UPS1, the amplitude command value V1 * and the phase command value θ1 * can be obtained from the equation (10) as in the following equations (12) and (13).

  However, at this stage, since the impedance difference R1, X1, amplitude difference ΔV1, and phase difference Δθ1 are still unknown, the amplitude command value V1 * and the phase command value θ1 * cannot be directly obtained. Therefore, the cross current is detected in the short circuit state, the amplitude command value V1 * and the phase command value θ1 * are adjusted, and the feedback control that suppresses the cross current is configured. The amplitude command value V1 * and the phase command at which the cross current becomes zero. The value θ1 * is obtained by feedback control. Even if the amplitude command value V1 * and the phase command value θ1 * for making the cross current zero are obtained, the unknown in equation (10) is impedance difference R1, X1, amplitude difference ΔV1, phase difference Δθ1 Therefore, it is not possible to obtain an unknown by this alone.

  Therefore, consider a case where the cross current is made zero by feedback control in two ways of output currents IdA, IqA and IdB, IqB by changing the load condition. When the amplitude command values and phase command values for the output currents IdA and IqA are V1A * and θ1A *, and the amplitude command values and phase command values for the output currents IdB and IqB are V1B * and θ1B *, the equation (10) is as follows: (14) and (15).

  From the above equations, the impedance difference R1, X1, the amplitude difference ΔV1, and the phase difference Δθ1 can be obtained as follows.

  By substituting the above results into the equations (12) and (13), and using the output current detection values of the filter currents Id and Iq for the desired load condition without performing feedback, An appropriate amplitude command value V1 * and phase command value θ1 * for making the current zero can be obtained.

  The same applies to the uninterruptible power supply UPS2. The amplitude command value and phase command value of the uninterruptible power supply UPS2 at the output currents IdA and IqA are V2A *, θ2A *, the amplitude command value at the output currents IdB and IqB is V2B *, the phase command value is θ2B *, and these values The following equations (20) to (23) are obtained by substituting the equation (11) and solving the simultaneous equations.

  In the conventional method, it was necessary to shorten the communication cycle as much as possible in order to reduce the transient cross current. However, in the first embodiment, since the cross current suppression by communication is limited to the trial operation, if a device that can withstand the apparatus even if a certain amount of cross current flows is selected as a load used for the trial operation, high-speed communication becomes unnecessary.

  In addition, by estimating the parameters necessary for the cross current suppression control using communication during the trial operation, the cross current can be suppressed without communication between different uninterruptible power supply units in the actual operation.

  Furthermore, since the cross current can be suppressed without communication, wiring of different uninterruptible power supply devices during actual operation is not required. Also, even if there is a wiring, it is not used, so disconnection due to an accident of the communication line does not affect the effect of suppressing the cross current. Therefore, the reliability of the apparatus can be improved.

  In addition, the trial operation does not require high-speed communication compared to the conventional method, and it is not necessary to detect and distribute the load current, so that the cost can be reduced.

  Furthermore, since parameter estimation in the trial run can be performed automatically, manual adjustment is unnecessary and test time can be shortened.

  In addition, two load patterns for estimation are required, but it is sufficient to prepare an appropriate dummy load and operate with no load and dummy load, and perform a test operation regardless of the type of load and power factor. Can do.

  When there is a load that cannot be removed on the main circuit, the parameter can be estimated even if one of the load patterns is not completely unloaded. Therefore, even when there is a load that cannot be removed on the main circuit, a trial run can be performed in a short time.

  Furthermore, the transient cross current when the load fluctuates can be reduced.

[Embodiment 2]
FIG. 7 shows a cross current suppression control block of the inverter INV1 in the second embodiment. This block is a combination of FIGS. 3 and 5 of the first embodiment. The differences from the first embodiment are shown below.

  The active power component Id1 and the reactive power component Iq1 are also input to the subtractors 22a and 22b that calculate the deviation from the output current command values Idref and Iqref and the multipliers 52a to 52d that calculate the product of the impedance differences R1 and X1. To do.

  A signal indicating that communication is normal is input. For communication status detection, for example, it is decided to transmit predetermined data periodically, and if there is an error when receiving the data or if data is not received for a certain period of time, communication error There is a way to judge.

  The switches SW1 and SW2 are provided in front of the amplifiers AMP3 and AMP4 that output the amplitude deviation V1 cmp and the phase deviation θ1 cmp, and the switches SW1 and SW2 are short-circuited when communication is normal.

  A signal indicating that the communication is normal is also input to the estimation block 51b. The amplifiers AMP3 and AMP4 that output the amplitude deviation V1 cmp and the phase deviation θ1 cmp accept the reset signal from the estimation block 51b, and reset the integration elements of the amplifiers AMP3 and AMP4 to zero when the reset signal is input.

  The amplitude command value V1 * that is an input signal of the inverter control block is obtained by subtracting the amplitude difference ΔV1 output from the estimation block 51b from the amplitude shift V1cmp and further adding the voltage drop Vdrop1. The phase command value θ1 * that is the input signal of the inverter control block is obtained by subtracting the phase difference Δθ1 output from the estimation block 51b from the phase shift θ1 cmp of the amplifier AMP4 output, and further adding the phase delay θdrop1 due to the voltage drop. To do.

  FIG. 8 shows the configuration of a parameter estimation block for suppressing cross current in the second embodiment. Changes from the first embodiment will be described below.

  A communication normal signal indicating that communication is normal and an output of the comparator 34 are input to the AND element 56. The AND element 56 outputs a signal of “1” level to the hold device 35 and the AND element 42 when the communication normal signal and the output of the comparator 34 are both “1” level. The AND element 42 outputs a “1” level signal to the hold unit 43 when the outputs of the AND element 56 and the comparator 41 are both “1” level. That is, the operation conditions of the hold devices 35 and 43 include that communication is normal.

  The AND element 46 outputs a reset signal when both of the hold devices 35 and 43 output a “1” level signal, and resets the amplifiers AMP3 and AMP4 of the cross current suppression control block.

  Delay devices 57a to 57d are added after the switch SW in the subsequent stage of the arithmetic unit 45. The delay unit 58 delays the reset signal output from the AND element 42 by one calculation time. The hold units 35 and 43 are configured to input the output of the delay unit 58 and return the output to 0 when a signal is input.

  In the second embodiment, the impedance difference R1, X1, the amplitude difference ΔV1, and the phase difference Δθ1 are repeatedly estimated, and the previous estimation result is added to the obtained estimation result and output.

  Although the parameter estimation procedure is the same as that of the first embodiment, the cross current suppression control block in FIG. 8 simply resets the amplifiers AMP3 and AMP4 when the estimation is completed, and continues to operate the amplifiers AMP3 and AMP4 after the estimation is completed. As a result, it is possible to suppress the cross current generated due to the temperature change / time-dependent change of the cable impedance and the switching element characteristics generated after the estimation is completed.

  At this time, the amplitude difference ΔV1, the phase difference Δθ1, the voltage drop Vdrop1, and the phase delay θdrop1 due to the voltage drop suppress the cross current due to the disturbance before the characteristic change. Therefore, the amplitude deviation V1cmp and the phase deviation θ1cmp generated after the estimation is completed This value is necessary to suppress the cross current due to the fluctuation. When re-estimation is performed using the amplitude deviation V1 cmp and the phase deviation θ1 cmp, the obtained parameter becomes a variation from the previous estimation result.

  Therefore, as shown in FIG. 8, the re-estimation result is integrated with the previous estimation result by the delay units 57a to 57d, so that the variation can be reflected in the parameter. By repeatedly estimating using load fluctuations that occur during actual operation, it is possible to follow temperature changes and changes over time in cable impedance and switching characteristics, and always suppress cross current.

  FIG. 9 shows an example of a time chart of each part signal in FIGS. This represents an operation in which Id1≈Idref (operation to suppress the transient current generated transiently) and an operation to re-estimate and correct the impedance difference R1 after a load change (abrupt change in the current command value Idref).

  In the second embodiment, the trial run can be omitted by setting initial values in advance in the delay units 57a to 57d of the estimation block 51b in FIG. For example, it is possible to cope with the installation in a place where a dummy load cannot be prepared or the case where an additional uninterruptible power supply is added without interrupting the power supply to the actual load. The cross current generated at that time depends on the accuracy of the initial value, but even if the accuracy is low, there is a cross current control block, so the cross current only occurs transiently, and parameter error is canceled by parameter re-estimation. After the re-estimation, the transient cross current can be reduced.

  Here, when communication between different uninterruptible power supply devices is stopped due to a failure or the like, the current command values Idref and Iqref cannot be received. Therefore, it is necessary to stop the amplifiers AMP3 and AMP4 and interrupt parameter estimation. Therefore, a signal indicating that the communication is normal is input, and when the communication is abnormal, the switches SW1 and SW2 at the front stage of the amplifier are opened and the inputs of the amplifiers AMP3 and AMP4 are set to zero, thereby the amplifiers AMP3 and AMP4. To stop.

  The estimation block 51b also includes that the communication conditions are normal in the operating conditions of the internal hold units 35 and 43, so that the parameter estimation is interrupted when the communication is stopped, and the delay unit 52a which is the previous estimation result. The output of -52d is output as it is. Thus, the operation is the same as that of the first embodiment while communication is stopped. However, since the estimation is repeated until immediately before the communication is stopped, the characteristic variation until immediately before the communication is stopped can be reflected in the parameter, and a higher cross current control effect than that of the first embodiment can be obtained.

  In the second embodiment, it is necessary to connect communication lines between different uninterruptible power supply units that are not necessary during the actual operation operation in the first embodiment. However, in Embodiment 2, the parallel operation of the uninterruptible power supply apparatus can be continued while suppressing the cross current by taking the above operation even when the connection line is disconnected or communication is stopped due to an accident or the like.

  The second embodiment also operates by determining one representative uninterruptible power supply. If the representative uninterruptible power supply stops due to an abnormality, etc., another uninterruptible power supply becomes the representative and stops the cross current control and parameter estimation, and the other uninterruptible power supply outputs to the new representative uninterruptible power supply. By operating to match the current, the operation can be continued as it is. For example, in FIG. 6, when the uninterruptible power supply UPS3 stops and the uninterruptible power supply UPS1 becomes a new representative uninterruptible power supply, the uninterruptible power supply UPS1 has an amplitude difference until immediately before the uninterruptible power supply UPS3 stops. Since ΔV1, impedance difference R1, and the like have been estimated, uninterruptible power supply UPS1 outputs a voltage equal to uninterruptible power supply UPS3 in which the influence of disturbance such as amplitude difference ΔV1 and impedance difference R1 has been canceled. Therefore, the uninterruptible power supply UPS2 only needs to output a voltage equal to that of the uninterruptible power supply UPS3 even if the representative uninterruptible power supply is switched, and the operation can be continued without increasing the cross current.

  Further, when the output current command values Idref and Iqref are average values, the operation can be continued as it is if the uninterruptible power supply device that has been stopped when the average is obtained is excluded.

  Also in the second embodiment, it is assumed that the communication for suppressing the cross current (communication for reading the output current command values Idref and Iqref) is performed once every fundamental wave period to several seconds. This is because once the parameter estimation is completed, the cross current can be suppressed without communication, and the cross current suppression by communication is auxiliary for the purpose of following characteristic fluctuations.

  In general, fluctuations in characteristics due to temperature and time do not occur abruptly, so that a sufficient effect can be obtained even at low speed communication. Further, since the period for detecting the magnitude of the cross current in the estimation block is also adapted to the communication, the number of complicated calculations such as square root can be reduced, and the calculation load can be reduced.

  According to the second embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

  Even after the parameter estimation is completed, the communication is enabled and the estimation is repeated, so that the accuracy can be improved, and it is possible to cope with the temperature change and the change with time of the impedance and switching element characteristics.

  It is only necessary that load fluctuations occur in parameter estimation. For example, parameter estimation can be performed even when only the reactive power changes, or even when only the power factor changes without changing the load current amplitude, and the application range can be expanded.

  By inputting manually estimated parameters as the initial value of the integrator, the transient cross current can be reduced from the beginning and the trial run can be omitted. The degree of the effect depends on the estimation accuracy of the initial value, but re-estimation can be performed automatically even if the accuracy is low.

[Embodiment 3]
FIG. 10 shows a cross current suppression control block before parameter estimation of the inverter INV1 in the third embodiment. The changes from FIG. 3 and FIG. 5 in the first embodiment are the portions surrounded by the broken lines in FIG. In the third embodiment, the average current of the d-axis output currents Id1, Id2, and Id3 of the uninterruptible power supply units calculated by the adders 61a and 61b and the dividers 62a and 62b is used as the output current command value Idref. ing. The same applies to the output current command value Iqref. The changes from Embodiment 1 are shown below.

Multipliers 63a and 63b determine the squares of the output current command values Idref and Iqref. Next, the adder 64 adds the outputs of the multipliers 63a and 63b, and the calculator 65 obtains the square root of the output of the adder 64. The obtained value is the fundamental wave amplitude of the output current command value. The comparator 66 outputs 1 when the fundamental wave amplitude of the output current command values Idref and Iqref exceeds the third threshold value Ithc. When the output of the comparator 66 is “1” level and the communication normal signal is “1” level, the AND element 67 outputs a signal of “1” level and short-circuits the switches SW1a and SW1b. The NOT element 68 logically inverts the output of the comparator 66. The AND element 69 outputs a “1” level signal when the output of the comparator 66 is 0 and the communication normal signal is at the “1” level, and short-circuits the switches SW1c and SW1d.

  The output current command value Idref is divided by the fundamental wave amplitude of the output current command value by the divider 70a to calculate the power factor of the output current command value. Further, the output current command value Iqref is divided by the fundamental wave amplitude of the output current command value by the divider 70b.

  In the multipliers 71a to 71d, the product of the outputs of the dividers 70a and 70b and the switches SW1a and SW1b is obtained. The adder 72a adds the outputs of the multipliers 71a and 71c, and the adder 72b subtracts the output of 71d from the output of the multiplier 71b. Processing such as integration is performed based on the outputs of the adders 72a and 72b, and output as impedance differences R1 and X1.

  The cross current suppression control block after parameter estimation in the third embodiment uses the one shown in FIG. 5 as in the first embodiment. However, the amplitude difference ΔV1 and the phase difference Δθ1 output from the estimation block 51a in FIG. 5 are obtained by inverting the signs of the amplitude shift V1 cmp and the phase shift θ1 cmp output from the amplifier AMP in FIG.

  A parameter estimation method according to the third embodiment will be described. In the third embodiment, it is assumed that one of the load patterns becomes no load in the trial operation. When there is no load, since Id = Iq = 0 in the equation (10), the amplitude difference ΔV1 and the phase difference Δθ1 are expressed by the equation (24).

  Also in FIG. 10, if Id = Iq = 0, the amplitude command value V1 * and the phase command value θ1 * are given by equation (25) because equation (1) is established.

  The amplitude deviation V1 cmp and the phase deviation θ1 cmp obtained by the feedback are obtained by inverting the signs of the amplitude difference ΔV1 and the phase difference Δθ1. Therefore, first, a trial run is performed with no load, and the cross current is suppressed using communication. In the block of FIG. 10, the average value of the filter output currents Iups1 to Iups3 is calculated by the formula √ (Idref2 + Iqref2) and output from 65. It is detected that the output of 65 is smaller than a third threshold value Ithc (for example, a value close to zero such as 10%) and recognized as no load, and the switches SW1c and SW1d are short-circuited so that the cross current becomes zero. The amplitude difference ΔV1 and the phase difference Δθ1 are obtained by adjusting the amplitude deviation V1 cmp and the phase deviation θ1 cmp. At this time, the switches SW1a and SW1b are opened, and the impedance differences R1 and X1 remain unchanged from their initial values (usually 0).

  Next, an appropriate load is applied and a test operation is performed to obtain impedance differences R1 and X1. The amplitude deviation V1 cmp and the phase deviation θ1 cmp obtained in the previous test operation with no load are set as the amplitude command value V1A * and the phase command value θ1A *, respectively, and the output current is Id1A = Iq1A = 0. Then, the amplitude command value V1B *, the phase command value θ1B *, and the output current Id1B = Iq1B can be obtained and substituted into the equations (16) and (17).

  However, if the impedance difference R1 is a voltage amplitude adjustment element when the output current Id1 is flowing, and the voltage phase adjustment element is when the output current Iq1 is flowing, the impedance difference R1, X1 is The cross current can be suppressed by directly operating the feedback loop.

  That is, instead of increasing the amplitude deviation V1cmp, the impedance difference R1 is set to be large if there is an output of active power, and the impedance difference X1 is set to be large if there is an output of delayed reactive power, and Vdrop1 is an estimation result of the voltage drop. Can be increased. Instead of advancing the phase shift θ1 cmp, if there is an output of active power, the impedance difference X1 is set small, and if there is a delay reactive power output, the impedance difference R1 is set large to increase the estimation result θdrop1 of the phase delay due to the voltage drop You can do it.

  Thus, the power factor of the load (= active power / √ (active power 2 + reactive power 2) = Idref / √ (Idref2 + Iqref2) is added to the outputs of 24a and 24b, which are signals based on the current deviation (outputs of 22a and 22b). ), The values obtained by multiplying the outputs of the signals 70a and 70b (the outputs of 71a, 71b, 71c, and 71d) based on) are input to the amplifiers AMP1 and AMP2, thereby directly changing the impedance differences R1 and X1 by the feedback loop. Cross current can be suppressed. Since the amplitude difference ΔV1 and the phase difference Δθ1 are obtained in the previous test run without load, the impedance differences R1 and X1 when the cross current becomes zero are adjusted as described above, and the appropriate values are obtained. Based on this concept and the equation (3), a block for estimating the impedance differences R1 and X1 within the dotted line in FIG. 10 is assembled.

  In the block of FIG. 10, it is detected that the average value of the filter output currents Iups1 to Iups3 of each uninterruptible power supply is larger than the third threshold value Ithc, and that there is a load, the switches SW1a and SW1b are turned on, and the impedance difference Switch to the operation of directly operating R1 and X1. At this time, the switches SW1c and SW1d are opened, and the amplifiers AMP3 and AMP4 that output the amplitude shift V1 cmp and the phase shift θ1 cmp stop operating. As the amplitude deviation V1 cmp and the phase deviation θ1 cmp, values immediately before the switches SW1c and SW1d are opened by the integration elements of the amplifiers AMP3 and AMP4 (adjustment results without load) are output.

Then, when the cross current is suppressed to a predetermined value or less, the impedance differences R1 and X1 are considered to have been adjusted to appropriate values, and the trial run is terminated. (Note that the control block for the trial run end process is not shown in FIG. 10. It may be added to FIG. 10, or the tester determines the trial run end by measuring the cross current with a measuring instrument. May be.)
Since the necessary parameter amplitude difference ΔV1, phase difference Δθ1, impedance difference R1, and X1 are obtained as described above, the obtained parameters are set in the control block of FIG. As a result, the same effects as those of the first embodiment can be obtained, and further, the advantage that the control block is simplified, such as the need for the storage bufferer, is obtained as compared with the first embodiment.

  Further, even after the above parameter estimation, by performing actual operation using the control block of FIG. 10, it is possible to follow the temperature change and the change with time of the characteristic as in the second embodiment. In particular, since the impedance difference R1 mainly fluctuates with respect to the temperature change, it is possible to follow the temperature change by directly adjusting the impedance difference R1 with some load.

  When a communication abnormality (abnormal detection of Id2, etc.) occurs in this control method, the communication normal signal in FIG. 10 becomes 0, and the switches SW1a, SW1b, SW1c, SW1d are opened. As a result, the inputs of the four amplifiers AMP1 to AMP4 in FIG. 10 are all 0, so that the outputs of the amplifiers AMP1 to AMP4 having integral elements do not change. Therefore, the parallel operation of the uninterruptible power supply using the parameter estimated value immediately before the occurrence of the abnormality is continued.

  In the third embodiment, the output current command values Idref and Iqref are average values of the filter output currents Iups1 to Iups3 of the uninterruptible power supply devices, but the filter output current Iups of the representative uninterruptible power supply device is the same as in the first embodiment. The output current command value can also be used as it is.

  Note that the filter output current of the third embodiment may be replaced with an inverter output current.

  According to the third embodiment, by limiting one of the load conditions to no load, it is possible to simplify the parameter estimation calculation block such that a storage buffer becomes unnecessary. Thereby, compared with Embodiment 1, size reduction and cost reduction of a control circuit part can be achieved.

  Further, similarly to the second embodiment, it can be made effective during actual operation, and can follow changes in temperature and changes in characteristics of impedance and switching element characteristics.

[Embodiment 4]
FIG. 11 shows an output voltage control block of the inverter INV1 in the fourth embodiment. The blocks added from the first embodiment are shown below.

  The subtractor 73 subtracts the frequency correction value f1 from the rated frequency fstd1 of the uninterruptible power supply UPS1. The integrator 74 integrates the output of the subtractor 73 and further multiplies it by 2π to obtain the phase from the frequency.

  The switch 75 outputs the PLL output at the normal time to the subsequent stage, and outputs the output of the integrator 74 to the subsequent stage when the bypass voltage is abnormal such as a power failure. The adder 76 adds the phase command value θ1 * to the output of the switch 75.

  FIG. 12 shows a cross current suppression control block of the inverter INV1 in the fourth embodiment. The block added from FIG. 5 of Embodiment 1 is shown below.

  Multipliers 77a to 77d calculate the product of the active power component Id1 and reactive power component Iq1 of the output current and the coefficients α and β. An adder 78a adds the outputs of the multipliers 77a and 77c, and an adder 78b subtracts the output of 77d from the output of the multiplier 77b. Multipliers 79a and 79b obtain products of the outputs of the adders 78a and 78b and the gain G0. The subtracters 80a and 80b subtract the outputs of the multipliers 79a and 79b from the voltage drop Vdrop1 and the phase delay θdrop1 due to the voltage drop.

  A multiplier 81 obtains the product of the output of the adder 78b and the gain G1. The output of the multiplier 81 is a frequency correction value f1.

  The fourth embodiment can be operated without synchronizing the output voltage with the bypass voltage as a response to the case where an abnormality occurs in the bypass power source such as a power failure by combining the PQ drooping method which is the existing technology with respect to the first embodiment. This is the method.

  In the output voltage control block of FIG. 11, when the bypass power supply is abnormal, the control circuit of each uninterruptible power supply unit integrates the frequency set instead of the PLL and converts it into a phase to control the output voltage. The frequency of the output voltage is determined not only by the rated frequency fstd1 and frequency correction value f1 of each uninterruptible power supply, but also by the number of operations of the integrating circuit inside the integrator 74 by the control circuit internal oscillator.

  In the cross current suppression control block of FIG. 12, the amplitude and phase of the output voltage are changed by the active power component Id1 and the reactive power component Iq1 of the output current. For example, when α = 1 and β = 0, the output voltage amplitude command value V1 * is decreased when the active power component Id1 of the output current increases. When the delayed reactive power component Iq1 increases, the phase command value θ1 * of the output voltage is advanced, and in the case of operation not synchronized with the bypass, the phase is advanced and the frequency is also increased.

  As a result, when there is another uninterruptible power supply apparatus with a small output current, a decrease in its own output current and an increase in the output current of the other uninterruptible power supply apparatus are promoted. When AC power supplies with different frequencies are connected in parallel, the cross current increases, but by adjusting the frequency according to the output current, the voltage frequency can be made uniform for all uninterruptible power supplies, preventing the expansion of the cross current. be able to.

  When the output currents of the other uninterruptible power supply devices are equal, the frequency of the other uninterruptible power supply devices is changed in the same way as long as the voltage amplitude, phase, and bypass are asynchronous, so the cross current is kept at zero.

  The above functions are the same as those of the conventional PQ drooping method. However, even if an error occurs in the output of the parameter estimation block due to noise or the like, a temperature change or a change over time occurs, the cross current does not have to be repeated. Can be suppressed. Further, since this function acts to suppress the cross current even in the bypass synchronous operation, it can be applied regardless of the bypass synchronous / asynchronous operation.

  Bypass In asynchronous operation, the frequency shift, not the phase shift, is the cause of the cross current, so it is important to make the frequency shift as small as possible. As a method, it is considered to detect the cross current during bypass asynchronous operation by communication and compensate the frequency deviation, or to match the frequency of the internal oscillator at the manufacturing stage of the printed circuit board equipped with the control function of the uninterruptible power supply. It is done.

  However, the former has a problem that there is no means for compensating for the frequency deviation until the bypass asynchronous operation is performed, and it is impossible to cope with a communication stop and a power failure. The latter cannot cope with the temporal change of the internal oscillator.

  An example of this countermeasure is shown in FIG. First, the bypass voltage Vbyp1 is input to the zero cross detector 104, and a zero cross point where the polarity of the bypass voltage Vbyp1 changes from negative to positive is detected. The bypass voltage Vbyp1 is the same system in each uninterruptible power supply, but the detection delay differs depending on the measurement location and the individual difference of detectors. However, since the magnitude of the detection delay does not change suddenly, the detection result of the time between two zero cross points (one cycle of the bypass voltage) has the same value in all uninterruptible power supply devices.

  The counter 105 is operated for one cycle of the bypass voltage by the internal oscillator of the uninterruptible power supply, and the obtained value C1 is output. C1 corresponds to the reciprocal (cycle) of the frequency of the bypass voltage Vbyp1, but is based on the internal oscillator of the uninterruptible power supply UPS1. This is compared with the reference value Cref. Cref may be obtained by obtaining an average of counter outputs of each uninterruptible power supply through communication, or may be one representative uninterruptible power supply determined as a counter output value. A divider 106 is used for the comparison. The multiplier 107 obtains the rated frequency fstd1 from the product of the comparison result and the rated frequency f0 (usually 50 Hz or 60 Hz).

  For example, when the frequency of the internal oscillator of the uninterruptible power supply to be adjusted is higher than that of other uninterruptible power supplies, the integrator 74 in FIG. 11 performs integration internally, but the number of integrations is higher than that of other uninterruptible power supplies. Therefore, the output frequency of the target uninterruptible power supply becomes higher than other uninterruptible power supplies. However, since the counter output also increases from other uninterruptible power supply devices, Cref / C1 becomes smaller than 1 and the rated frequency fstd1 also becomes smaller. Thereby, the excessive number of integrations can be compensated, and a voltage having the same frequency as that of other uninterruptible power supply devices can be output.

  Since the bypass voltage Vbyp = 0 during a power failure, the rated frequency fstd cannot be calculated according to FIG. Therefore, when the bypass voltage Vbyp is in a normal state, the rated frequency fstd is calculated and stored according to FIG. And at the time of a power failure, memorize | stored fstd1 is applied and it applies to the control block of FIG.

  The fourth embodiment can be combined with the second embodiment to further suppress the cross current with respect to the temperature change and the change with time. In the fourth embodiment, a voltage drop due to the PQ droop is newly added, but this voltage drop occurs equally in all uninterruptible power supply devices, and therefore corresponds to the resistance component Rc and reactance component Xc of the impedance in FIG. Since the operation of the estimation block does not depend on the impedance resistance component Rc and reactance component Xc as shown in the equations (16) to (19), it does not cause interference with the estimation block, and the PQ drooping characteristic can be added. .

  However, as a point to be noted when combined with the second embodiment, in the case of bypass asynchronous operation, each uninterruptible power supply device uniquely determines the output frequency according to the magnitude of the cross current, so that the phase shift θ1 cmp (FIG. 7). However, the steady cross current cannot be suppressed. In addition, since the reference phase is not determined, the value of the phase shift θ1 cmp when the cross current becomes zero cannot be used for estimation.

  Therefore, in the bypass asynchronous operation, it is necessary to stop the operation of the amplifier that outputs the phase shift θ1 cmp. That is, the switch SW2 connected to the input of the amplifier AMP4 having the phase shift θ1 cmp in FIG. 7 is opened. Further, the estimation block 51b needs to be stopped. That is, all the switches SW in FIG. 8 are opened. The function of changing the phase based on the voltage drop due to the impedance difference R1, X1 or the PQ drooping characteristic is effective because it is effective in suppressing the transient cross current when the load fluctuates even in the bypass asynchronous operation.

  According to the fourth embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

  The cross current can be reduced even when there is no common synchronization signal when the bypass voltage is abnormal such as a power failure.

  Even if the PQ drooping method is added, it does not interfere with the parameter estimation function.

  The same effect as the PQ drooping method can be obtained. Before the parameter estimation is completed or when an error is included in the parameter estimation result, the cross current can be reduced even when the impedance or the switching element characteristic changes in temperature or changes with time.

  In combination with the second embodiment, the parameter estimation can be repeatedly performed to increase the cross current suppression effect.

  Further, the parameter estimation block can be simplified in combination with the third embodiment.

[Embodiment 5]
FIG. 14 shows an output voltage control block of the inverter INV1 in the fifth embodiment. The blocks added from the first embodiment are shown below.

  Multipliers 81a and 81b multiply the internal phase information ωt + θ1 * of the control circuit by n times. Further, the multiplier 81c multiplies the internal phase information ωt + θ1 * of the control circuit by n−1.

  In the dq converter 82a, the V1 detection signal is converted into a value on the rotation coordinate based on the internal phase information ωt + θ1 * multiplied by n. The low-pass filter LPF removes AC components from the output of the dq converter 82a, and extracts Vdn1 and Vqn1 that are DC components (n-order harmonic components).

  In the dq converter 82b, based on the internal phase information ωt + θ1 * multiplied by n, the detection signal of the filter output current Iups1 is converted into a value on the rotational coordinates. The low-pass filter LPF removes AC components from the output of the dq converter 82b, and extracts Idn1 and Iqn1 that are DC components (n-order harmonic components).

  Multipliers 83a to 83d calculate the product of DC components Idn1 and Iqn1 and impedance difference R1 that is a coefficient output from estimation block 51 and nX1 obtained by multiplying X1 by n. The adder 84a adds the outputs of the multipliers 83a and 83c, and the adder 84b subtracts the output of the 83d from the output of the multiplier 83b. As a result, voltage drops Vdndrop1, Vqndrop1 generated when the n-th harmonic current passes through the estimated cable impedance difference R1, X1 are obtained. These voltage drops Vdndrop1 and Vqndrop1 serve as command values for the nth harmonic of the filter output voltage.

  The multipliers 85a and 85b determine the squares of the DC components Idn1 and Iqn1, and the adder 86 adds the outputs of the multipliers 85a and 85b. The square root of the output of the adder 86 is obtained by the calculator 87 and output as the nth harmonic amplitude (effective value) In1 of the output current.

  A subtractor 88 obtains a deviation between the nth-order harmonic amplitude (effective value) In1 and the harmonic command value Inref. The harmonic command value Inref is determined by determining one representative uninterruptible power supply and inputting the n-th harmonic current amplitude of the representative uninterruptible power supply through communication. Or it is good also as what calculated | required the nth-order amplitude average value of all the filter output currents by communication.

  The switch SW controls opening and closing of the switch according to a communication normal signal. The amplifier AMP inputs the deviation obtained by the subtracter 88 and performs amplifier processing such as integration.

  The subtractors 89a and 89b obtain deviations between the voltage drops Vdndrop1 and Vqndrop1 that are command values and the nth-order harmonic components Vdn1 and Vqn1 that are detection values. Multipliers 90a and 90b determine the product of the deviation output from the subtractors 89a and 89b and the gain as the amplifier AMP output.

  Based on the internal phase information ωt + θ1 * multiplied by n−1, the dq inverse converter 91 converts the outputs of the multipliers 90a and 90b into values on the rotational coordinates. Since the dq converter 82a performs the coordinate conversion of n × (ωt + θ1 *) rotation, the dq inverse converter 91 performs the coordinate conversion of (n−1) × (ωt + θ1 *) reverse rotation, whereby dq inverse The output of the converter 91 performs (ωt + θ1 *) rotation coordinate conversion on the input coordinates of the dq converter 82a. As a result, the coordinate axis becomes the same as the rotation coordinate of the output of the dq converter 11 of the AVR unit within the dotted line in FIG.

  The output of the dq inverse converter 91 is added to the outputs of AMP1 and AMP2, which are voltage command values of the output voltage control block, by the adders 92a and 92b.

  The fifth embodiment is a system in which a harmonic voltage distortion suppressing function and a harmonic current cross current suppressing function are added to the first embodiment.

  First, n-order harmonic components Vdn1 and Vqn1 are extracted from the detection signal of the filter output voltage V1 using dq conversion and a low-pass filter LPF. A deviation from the voltage drops Vdndrop1 and Vqndrop1, which are harmonic voltage command values, is calculated by adding a gain, converted to the same rotational coordinates as the voltage control block, and added to the voltage command value.

  Next, voltage drops Vdndrop1, Vqndrop1 are obtained. The n-order harmonic components Idn1 and Iqn1 are extracted from the detection signal of the filter output current Iups1 using the dq conversion and the low-pass filter LPF. The product of the impedance differences R1 and X1 obtained by the parameter estimation block is taken, and the product of the impedance difference X1 and n that is the order of the harmonic is taken.

  Thereby, the voltage drops Vdndrop1, Vqndrop1 generated when the DC components Idn1, Iqn1 pass through the impedance differences R1, X1 of FIG. 6 can be obtained. By using this voltage drop as the command value of the harmonic voltage, the voltage drop can be compensated and the distortion of the output voltage VL can be reduced.

  Further, since the impedance difference R1, X1 is canceled by compensation for the nth harmonic when viewed from the load, the input impedance of the uninterruptible power supply UPS1 is only the resistance component Rc, the reactance component Xc, and the uninterruptible power supply It can be made equal to the input impedance of UPS3. Therefore, assuming that the load is an n-order harmonic current generation source, the harmonic current flows evenly into uninterruptible power supply devices UPS1 and UPS3. If the same control is applied to the uninterruptible power supply UPS2, the cross current of the nth harmonic can be made zero in all the uninterruptible power supply UPS1 to UPS3 in FIG.

  Further, the cross current is detected by communication and the gain (output of the amplifier AMP in FIG. 14) is adjusted. The amplitude In1 of the nth-order harmonic current and the harmonic command value Inref of the nth-order harmonic current input by communication are compared, and a cross current is detected and input to the amplifier AMP. When its own output current is small, increasing the voltage distortion suppression control gain makes the resistance component Rc and reactance component Xc, which are internal impedances of the inverter, appear to be small, and the output harmonic current can be increased.

  In the gain adjustment function, the harmonic current is handled as amplitude without being divided into d-axis and q-axis. This is because a sufficient suppression effect of the cross current can be obtained only by compensating for the voltage drop, and gain adjustment is used in an auxiliary manner to bring the cross current closer to zero. Further, there is an effect that the burden of communication can be reduced as compared with the case where the d-axis and q-axis current command values are communicated separately. In actual operation, a harmonic load is prepared as a dummy load, and the gain is adjusted during the trial operation. In the actual operation, the gain is fixed. Alternatively, communication may be validated during actual operation and the gain adjustment function may continue to operate.

  If the communication abnormality (inref detection abnormality) occurs when the gain adjustment function is continuously operated, the communication normal signal in FIG. 14 becomes 0 and the switch SW is opened. As a result, the input of the amplifier AMP shown in FIG. 14 becomes 0, so that the output of the amplifier AMP having an integral element does not change. Therefore, the parallel operation of the uninterruptible power supply that suppresses the cross current using the output value of the amplifier AMP immediately before the occurrence of the abnormality is continued.

  The above is the case where the harmonic voltage to be controlled is only the nth order. However, by configuring a plurality of control blocks in parallel, a plurality of harmonic voltages can be controlled simultaneously. Further, by setting n = −1, it is possible to improve the unbalance rate of the output voltage VL when driving an unbalanced load.

[Embodiment 6]
In the sixth embodiment, a harmonic voltage distortion suppressing function and a harmonic current cross current suppressing function are added to the second embodiment. This method can be realized by combining the control block shown in FIG. 14 (Embodiment 5) with the control block shown in FIG. 7 (Embodiment 2) and the parameter estimation block shown in FIG. 8 (Embodiment 2). Similarly to the fifth embodiment, a plurality of control blocks in FIG. 14 are configured in parallel, so that a plurality of harmonic voltages can be controlled simultaneously. Further, by setting n = −1, it is possible to improve the unbalance rate of the output voltage VL when driving an unbalanced load.

[Embodiment 7]
The seventh embodiment is a system in which a harmonic voltage distortion suppressing function and a harmonic current cross current suppressing function are added to the third embodiment. This method can be realized by combining the control block of FIG. 10 (Embodiment 5) with the control block of Embodiment 10 (Embodiment 3). Similarly to the fifth embodiment, a plurality of control blocks in FIG. 14 are configured in parallel, so that a plurality of harmonic voltages can be controlled simultaneously. Further, by setting n = −1, it is possible to improve the unbalance rate of the output voltage VL when driving an unbalanced load.

  Furthermore, the above fifth to seventh embodiments may be combined with the fourth embodiment. This method can be realized by combining the control block of FIG. 14 (Embodiment 5) with the phase ωt + θ1 * generator of the control block of Embodiment 11 (Embodiment 4) and the control block of Embodiment 10 (Embodiment 4).

  In the above embodiment, the uninterruptible power supply device has been described as an example. The application of the present invention is not limited to the uninterruptible power supply. You may apply to the other power converter device which outputs an alternating voltage.

  As described above, according to the fifth to seventh embodiments, the following effects are obtained in addition to the first to third embodiments.

  Even if the cross current is not detected by communication or the like, the harmonic cross current can be suppressed.

  The voltage drop due to the cable impedance can be compensated, and the distortion of the load voltage can be suppressed.

  Even when the parameter estimation is completed or even if the parameter estimation result includes an error, the harmonic cross current can be reduced by the cross current suppression control by communication.

  It can also be combined with the fourth embodiment.

[Embodiment 8]
In the first to seventh embodiments, the inverter of the uninterruptible power supply is considered by separating the voltage source and the internal impedance, the test operation is performed in a state where communication is enabled, and the deviation of the voltage amplitude and the voltage phase output from the voltage source, We proposed a method to suppress the cross current without communication, by estimating the four parameters of impedance component and inductance component and using the estimated parameters during actual operation.

  In the third embodiment, by limiting one of the load patterns of the test run to no load, the deviation of the voltage amplitude and the voltage phase is adjusted at the time of no load, and when the load is turned on, the resistance component and inductance of the internal impedance are directly adjusted by the feedback loop. The method for adjusting the ingredients has been described. This method has an advantage that the operation block is simplified as compared with the other embodiments.

  However, under conditions that do not result in a complete no load, such as when a transformer is connected to the circuit for trial operation and an excitation current flows or a filter capacitor is connected, the following operation occurs and the trial operation takes time. There's a problem.

  FIG. 15 shows the conditions of the main circuit studied in the eighth embodiment. In FIG. 15, for simplification, it is assumed that there is no deviation in the voltage phase of the inverter of each uninterruptible power supply, the inverter internal impedance is only the resistance component Rc, and the load is also connected with three resistors having the same power factor. To do. With this assumption, only the active power component Id flows through the load current, and only the resistance component Rc of voltage amplitude and internal impedance is adjusted. When the switches are opened, if the output voltages VL1, VL2, and VL output by the uninterruptible power supply devices are equal, no cross current will be generated even if the switches are short-circuited. Therefore, it is considered that the characteristics of the output voltage VL1 of the uninterruptible power supply UPS1 are matched with the output voltage VL of the uninterruptible power supply UPS3, which is a reference, in an arbitrary load.

  FIG. 16A shows voltage characteristics of the uninterruptible power supply UPS1 to be adjusted and the reference uninterruptible power supply UPS3. In (a), since the output voltage has a deviation in the initial state, a cross current proportional to the deviation is generated. In this example, the output current of the uninterruptible power supply UPS1 becomes excessive, and the duty of the uninterruptible power supply UPS3 becomes less than that of the uninterruptible power supply UPS1.

  The third embodiment is applied to FIGS. 16B to 16E under the condition that no load is applied, and the voltage characteristics of the uninterruptible power supply UPS1 in FIG. 16A are matched with the voltage characteristics of the uninterruptible power supply UPS3. The operation when

  In application, the third threshold value Ithc is set, and the voltage amplitude is adjusted when the output current of the uninterruptible power supply UPS1 is smaller than the third threshold value Ithc, and the internal impedance is adjusted when it is larger. In FIG. 16B, since the output current of each uninterruptible power supply is IdA and there is a relationship of IdA <Ithc, the intercept (output voltage VL1 when IdA = 0) of the output voltage characteristics of the uninterruptible power supply UPS1. ) Is reduced to reduce the voltage amplitude so that the output voltage VL1 (IdA) at the output current IdA matches the output voltage VL (IdA) of the uninterruptible power supply UPS3.

  Next, consider the case where the load fluctuates and the state (c) is reached. In (c), since the output current is IdB and there is a relationship of IdB> Ithc, the internal impedance of the uninterruptible power supply UPS1 is increased by control. As a result, the slope of the output voltage characteristics of the uninterruptible power supply UPS1 becomes smaller (the sign is minus and the absolute value becomes larger), thereby reducing the voltage amplitude and reducing the output voltage VL1 (IdB) at the output current IdB to the uninterruptible power supply. The output voltage VL (IdB) of the power supply unit UPS3 is made to coincide. However, at this time, there is a difference between the output voltage VL1 (IdA) and the output voltage VL (IdA) in the output current IdA.

  Then, consider a case where a load change occurs and the output current returns to IdA as shown in (d). Since IdA <Ithc, the intercept of the voltage characteristic is increased to make the output voltage VL1 (IdA) and the output voltage VL (IdA) coincide. However, there is a difference between the output voltage VL1 (IdB) and the output voltage VL (IdB). However, the difference between the output voltage VL1 (IdB) and the output voltage VL (IdB) is smaller than that in (b).

  Further, consider the case where the load fluctuates and the output current becomes IdB again as shown in (e). When the output voltage VL1 (IdB) shifted in (d) is adjusted by the inclination, the difference between the output voltage VL1 (IdA) and the output voltage VL (IdA) increases. However, the difference between the output voltage VL1 (IdA) and the output voltage VL (IdA) is smaller than that in (c).

  With the above operation, the characteristics of the output voltage of the uninterruptible power supply UPS1 gradually approach the characteristics of the uninterruptible power supply UPS3 by repeating the load fluctuations of IdA and IdB. It can be seen that it takes more time to repeat the variation.

  It is also possible to apply this method during actual operation to follow the temperature change and aging of the characteristics, but it takes time to suppress the cross current, and for a while after the characteristics change the load fluctuation A cross current will occur between the uninterruptible power supply units each time.

  FIG. 17 shows a cross current suppression control block before parameter estimation of the inverter INV1 in the eighth embodiment.

  This block is different from the third embodiment in the following points.

  A buffer 93 that stores the value of the fundamental wave amplitude of the output current command value obtained by adding the squares of the output current command values Idref and Iqref and calculating the square root is stored one cycle before the cross current control control.

  A comparator 94 is provided for detecting that the fundamental wave amplitude of the stored output current command value before one calculation cycle exceeds the third threshold value Ithc.

  An AND element 95 is provided that outputs 1 when the fundamental wave amplitude of the output current command value one calculation cycle before exceeds the third threshold value Ithc, but the current amplitude falls below the third threshold value Ithc. The output of the AND element 95 is input to the switches SW1e and Sw1f, and when the AND element 95 outputs a “1” level signal, the switches SW1e and Sw1f are short-circuited.

  Similarly to the switches SW1a and Sw1b, the inputs of the switches SW1e and SW1f are obtained by multiplying the deviation between the output current command values Idref and Iqref and the output current detection values Id1 and Iq1 by coefficients α and β, and the output current command values Idref, It is assumed that Iqref is multiplied by the value obtained by dividing the command value amplitude.

A subtractor 96 is provided for subtracting the output current command value amplitude one calculation cycle before from one representing the rated current amplitude. The output of the subtracter 96 is input to a multiplier 97 that takes a product with a preset gain G1. Further, multipliers 98a and 98b that take the product of the multiplier 97 and the switches SW1e and SW1f are provided. The outputs of the multiplier 97 are subtracted by the subtractors 99a and 99b from the outputs of the switches SW1a and Sw1b. The outputs of the subtractors 99a and 99b are respectively input to the amplifier AMP for obtaining the impedance difference R1 and the amplifier AMP for obtaining the impedance difference X1, while the fundamental wave amplitude of the output current command value before one calculation cycle is lower than the third threshold value Ithc. An AND element 100 that outputs a signal of “1” level when the current amplitude exceeds the third threshold value Ithc is provided. The output of the AND element 100 is input to the switches SW1g and SW1h. When the AND element 100 outputs a signal of “1” level, the switches SW1g and SW1h are short-circuited.

  Similarly to the switches SW1c and SW1d, the inputs of the switches SW1g and SW1h are obtained by multiplying the deviation between the output current command values Idref and Iqref and the output current detection values Id1 and Iq1 by coefficients α and β.

  The multiplier 101 takes the product of the output current command value amplitude one calculation cycle before and the gain G2 set in advance. Multipliers 102a and 102b take the product of the outputs of switches SW1g and SW1h and the output of multiplier 101. Subtracters 103a and 103b subtract the outputs of the multipliers 102a and 102b from the output signals of the switches SW1c and SW1d. The output of the subtractor 103a is input to an amplifier AMP that calculates an amplitude shift V1 cmp and a phase shift θ1 cmp.

  The gains G1 and G2 can be set by performing a simulation using the FIG. 1 model and the FIG. 17 model.

  When (b) and (c) in FIG. 16 are compared, when the output voltage becomes excessive due to an increase in load and a cross current is generated, the internal current is increased (the slope is decreased) to suppress the cross current. It can be seen that it is necessary to increase the voltage amplitude (intercept) in order to make the output voltage characteristics uniform. In the eighth embodiment, the above-described points are taken into consideration with respect to the third embodiment so that the characteristics of the output voltage can be adjusted with a small load fluctuation.

  The operation of the eighth embodiment will be described with reference to FIG. Also in FIG. 18, the main circuit conditions are set to FIG. 15 for simplification of description, there is no deviation in the voltage phase of the inverter of each uninterruptible power supply, the inverter internal impedance is only the resistance component Rc, and the load is also a resistor with a power factor of 1 Is considered to match the output voltage VL1 of the uninterruptible power supply UPS1 with the output voltage VL of the uninterruptible power supply UPS3 as a reference.

  First, in FIG. 18A, the output current of each uninterruptible power supply before the load increase is IdA, and VL1 (IdA) = VL (IdA). However, as the load increases, the output current of each uninterruptible power supply becomes IdB, and VL1 (IdB)> VL (IdB). Since the current exceeds the third threshold value Ithc, if the slope is decreased (internal impedance is increased), the output voltage characteristic becomes a broken line in FIG. 18B, and VL1 (IdB) = VL (IdB) and the cross current becomes It is suppressed.

  However, by simultaneously increasing the intercept (increasing the voltage amplitude) here, the output voltage VL1 becomes a solid line in FIG. 18B, and the output voltage for an arbitrary current can be brought close to VL.

  The same applies to the case where VL1 (IdB) <VL (IdB) due to an increase in load. This state is shown in FIG. In this case, the inclination is increased (internal impedance is decreased) to establish VL1 (IdB) = VL (IdB). The output voltage VL1 obtained as a result is the broken line in FIG. At this time, by simultaneously reducing the intercept (decreasing the voltage amplitude), the output voltage VL1 becomes a solid line in FIG. 18D, and can be brought close to the output voltage VL of the uninterruptible power supply UPS3.

  Next, in FIG. 18E, the output current of each uninterruptible power supply before load reduction is IdB, and VL1 (IdB) = VL (IdB), but VL1 (IdA)> VL ( IdA) is shown. Since the output current IdA is smaller than the third threshold value Ithc, the intercept is decreased (the voltage amplitude is decreased), and the output voltage VL1 changes as indicated by a broken line in FIG. 18F, and VL1 (IdA) = VL (IdA) and the cross current is suppressed.

  Here, by simultaneously increasing the slope (decreasing the internal impedance), the output voltage VL1 becomes a solid line in FIG. 18F, and can be brought close to the output voltage VL of the uninterruptible power supply UPS3. As described above, by adjusting the slope (internal impedance) when the load is reduced, the voltage characteristic deviation from the reference uninterruptible power supply can be reduced.

  The same applies to the case where VL1 (IdA) <VTL (IdA) is satisfied due to the load reduction. This state is shown in FIG. In this case, the intercept is increased (voltage amplitude is increased), and the output voltage VL1 has a voltage characteristic as shown by a broken line in FIG. At this time, by simultaneously decreasing the slope (increasing the internal impedance), the voltage output voltage VL1 becomes a solid line in FIG. 18 (h), and can approach the voltage characteristics of the uninterruptible power supply UPS3.

  With the above operation, the eighth embodiment can make the output voltage characteristics after the load change closer to that of the reference uninterruptible power supply as compared with the third embodiment. Therefore, the voltage characteristic deviation when the next load change occurs is reduced, and the cross current generated by the load change can be reduced. In addition, the number of load fluctuations required until the voltage characteristics are uniform can be reduced, and the time required for trial operation can be shortened.

  In the above operation, the relationship between the load size before the change and the necessary adjustment amount will be described. FIG. 19A shows voltage characteristics of the uninterruptible power supply UPS1 when the load increases. The solid line indicates a small load before the increase, and the broken line indicates a state where the load before the increase is large. In order to make the conditions uniform, the voltage difference between UPS1 and UPS3 is zero before the load change, and the voltage difference after the load change is the same as that in FIG.

At this time, compared to the voltage characteristic of the uninterruptible power supply UPS 3 as a reference, the broken line has a larger difference in intercept than the solid line. Therefore, it can be understood that the intercept adjustment amount needs to be increased as the load before the increase increases and the degree of departure from the no-load state increases. If the load before the increase is zero, the intercept can be correctly estimated, and therefore the intercept adjustment at the time of the load increase is unnecessary.

  FIG. 19B shows voltage characteristics of the uninterruptible power supply UPS1 when the load is reduced. The solid line indicates a large load before the decrease, and the broken line indicates a state where the load before the decrease is small. In FIG. 19B as well, the voltage differences after the load change are aligned. At this time, compared with the voltage characteristic of the uninterruptible power supply UPS3 as a reference, the difference in inclination is larger in the broken line than in the solid line. This indicates that when the load decreases, it is necessary to increase the slope adjustment amount as the load before the decrease decreases.

  FIG. 17 is a control block for realizing the above operation. A buffer is provided for storing the value of the previous calculation cycle of the amplitude obtained by the square and square root of the output current command values Idref and Iqref, and the current output current command value amplitude (65 outputs) and the previous calculation cycle Comparison with the third threshold value Ithc is performed using two signals of the output current command value amplitude (output of 93).

  It is determined that the load has increased by detecting that the current command value amplitude is larger than the third threshold value Ithc and the amplitude before one calculation cycle is smaller than the third threshold value Ithc, and the current command value amplitude is determined to be the third threshold value Ithc. It is determined that the load has decreased by detecting that the amplitude is smaller than the third threshold value Ithc and is smaller than the first calculation cycle.

  The intercept (amplitude deviation V1 cmp and phase deviation θ1 cmp) will be described. When the current output current command value amplitude is smaller than the third threshold value Ithc, the switches SW1c and SW1d are short-circuited, and a signal based on the current deviation (outputs of 24a and 24b) is input to the amplifier AMP so that the amplitude deviation V1cmp and the phase deviation θ1cmp are A regulated feedback loop is constructed. The amplifier AMP has a function of integrating a signal based on the input current deviation. When the load increases and the current command value amplitude exceeds the third threshold value Ithc, the switches SW1c and SW1d are opened, the switches SW1g and SW1h are short-circuited for one calculation cycle, and the intercept is corrected. At this time, the multipliers 102a and 102b calculate the product of the signal based on the current deviation and the current command value amplitude one calculation cycle before multiplied by a predetermined gain G2.

  Thereby, the operation | movement which enlarges the adjustment amount of an intercept is implement | achieved, so that the load before increase is large. This operation coincides with the operation described above with reference to FIG.

  Thereafter, the signs are inverted by the subtracters 103a and 103b and input to the amplifier AMP. The reason why the sign is inverted will be described below. FIG. 20 shows the voltage control block of FIG. 17 in which the impedance between the uninterruptible power supply devices is assumed to be α, α = 1, β = 0, and only the cross current suppression control portion is extracted. The subtractor 108 subtracts the output current Id1 from the current command value Idref, and outputs the amplitude deviation V1 cmp to the amplifier AMP. In this block, when the output current Id1 of the uninterruptible power supply UPS1 itself is smaller than the current command value Idref, the amplitude deviation V1 cmp, that is, the intercept of the output voltage characteristic of the uninterruptible power supply UPS1 is increased to promote the increase of the output current Id1.

  FIG. 21 shows the characteristics of the uninterruptible power supply UPS1 and UPS3 before control. Since the current output current average value is IdA and VL1 <VL, the output current Id1 of the uninterruptible power supply UPS1 is smaller than the current command value Idref. At this time, the control block increases the amplitude deviation V1 cmp.

  FIG. 22 shows the characteristics of the uninterruptible power supply UPS1 and UPS3 after control. The intercept of the output voltage VL1 increases, and the output voltage of the uninterruptible power supply UPS1 matches the output voltage of the uninterruptible power supply UPS3 at the output current average value IdA.

  FIG. 23 shows the characteristics when the output current average value of the uninterruptible power supply increases to IdB. At this time, since VL1 <VL and the output current Id1 of the uninterruptible power supply UPS1 is smaller than the command value Idref, the control block attempts to increase the amplitude deviation V1cmp. However, as shown in FIG. 23, the amplitude deviation V1cmp of the uninterruptible power supply UPS1 is larger than the intercept of the uninterruptible power supply UPS3. Therefore, to match the characteristics, it is necessary to reduce the amplitude deviation V1cmp. Therefore, by reversing the sign of the block of the switch SW1g that is temporarily turned on when the load increases, the amplitude deviation V1cmp is reduced when the switch SW1g is short-circuited.

  The above is the reason for inverting the sign. The sign of the switch SW1h block is also inverted for the same reason.

  Next, the inclination (internal impedance) will be described. When the current output current command value amplitude is larger than the third threshold value Ithc, the switches SW1a and SW1b are short-circuited, a current deviation is input to the amplifier AMP, and a feedback loop is formed in which the impedance differences R1 and X1 are adjusted.

  When the load decreases and the current command value amplitude falls below the third threshold value Ithc, the switches SW1a and SW1b are opened, the switches SW1e and SW1f are short-circuited for one calculation cycle, and the inclination is corrected.

  At this time, the current command value amplitude of one calculation cycle before is subtracted from the rated current (input “1” of the subtractor 96 input to the gain G1 in FIG. 17), and the product multiplied by the gain G1 is input. The products of the signals 72a and 72b, which are signals based on the current deviation, are taken by 98a and 98b and input to the amplifier AMP. As a result, an operation of increasing the amount of inclination adjustment as the load before the decrease is realized. The sign is also inverted by a subtracter before being input to the amplifier AMP. This is also the same reason as the intercept adjustment.

  With the above configuration, additional correction of intercept (voltage amplitude) and slope (internal impedance) can be performed at the time of load fluctuation. By this additional correction, the voltage characteristics of the uninterruptible power supply UPS3, which is the reference, can be brought close to the reference in a short time.

  For the sake of simplification, the above operation has been described by taking as an example the case where there is no deviation in the voltage phase of the inverter of each uninterruptible power supply, the inverter internal impedance is only the resistance component Rc, and the load is also a resistor with a power factor of 1. When there is a deviation in the voltage phase of the inverter of each uninterruptible power supply, there is an internal impedance of the reactor component, and even when the load power factor is other than 1, the voltage of each uninterruptible power supply by applying this Embodiment 8 The characteristics can be aligned in a short time.

  This method can also be applied during actual operation. Unlike the third embodiment, the cross current between the uninterruptible power supply devices that occurs every time the load fluctuates can be suppressed, and the follow-up speed with respect to a temperature change or a change with time can be improved.

  According to the eighth embodiment, the following effects can be obtained as compared with the third embodiment.

  By making additional adjustments to the voltage amplitude and voltage phase, the characteristics of the output voltage can be matched with a smaller number of load fluctuations, and the time required for the test run can be shortened.

  When this method is applied during actual operation, the cross current between uninterruptible power supplies that occurs every time the load fluctuates can be suppressed, and the follow-up speed for changes in temperature and changes over time can be improved. .

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

Id, Iq: Output current ΔV1: Amplitude difference Δθ1: Phase difference R1, X1: Impedance difference V1 *: Amplitude command value θ1 *: Phase command value V1 cmp: Amplitude shift θ1 cmp: Phase shift

Claims (8)

A method for controlling a cross current of a power converter that connects a plurality of power converters that output an alternating voltage in parallel and suppresses a cross current that flows between outputs of the power converters,
Detect the filter output current or inverter output current of each power converter in multiple load patterns,
Based on the filter output current or inverter output current of each load pattern, estimate the amplitude difference of the output voltage between each power converter, the phase difference of the output voltage, the impedance difference between each power converter and the load,
Based on the output voltage amplitude difference, the output voltage phase difference, and the impedance difference between each power conversion device and the load, the output voltage amplitude command value and phase command value of each power conversion device. And
A method for suppressing a cross current of a power converter, wherein the amplitude and phase of an output voltage of each power converter are controlled using the amplitude command value and the phase command value. By controlling the amplitude and phase of the output voltage of each power converter in the first load pattern, the effective value of the deviation between the filter output current or inverter output current of each power converter and the output current command value is less than the first threshold value. The output voltage amplitude command value, the output voltage phase command value, the output current command value, the filter output current, or the inverter output current between each power converter when
By controlling the amplitude and phase of the output voltage of each power converter with the second load pattern, the effective value of the deviation between the filter output current or inverter output current of each power converter and the output current command value is greater than or equal to the second threshold value. The output voltage amplitude command value, the output voltage phase command value, the output current command value, the filter output current, or the inverter output current between each power converter when
Based on the values stored in the first load pattern and the second load pattern, the output voltage amplitude difference between the power converters, the output voltage phase difference, the power converter and the load Calculate and store the impedance difference between
The amplitude difference of the output voltage between the stored power converters, the phase difference of the output voltage, and the impedance difference between each power converter and the load are used as fixed values for all load patterns, and each power 2. The method of suppressing a cross current of a power converter according to claim 1, wherein an amplitude command value and a phase command value of the output voltage of the converter are calculated. Detect the filter output current or inverter output current of the power converter in two or more load patterns,
By controlling the amplitude and phase of the output voltage of each power converter with the first load pattern, the effective value of the deviation between the filter output current of each power converter or the inverter output current and the output current command value is less than the first threshold value. The output voltage amplitude command value, the output voltage phase command value, the output current command value or the filter output current or the inverter output current between each power converter when
By controlling the amplitude and phase of the output voltage of each power converter with the second load pattern, the effective value of the deviation between the filter output current or inverter output current of each power converter and the output current command value is greater than the second threshold value. When the effective value of the deviation between the filter output current or the inverter output current and the output current command value is less than the first threshold value, the amplitude command value of the output voltage at that time The output voltage phase command value and the output current command value or filter output current or inverter output current are stored,
The output voltage amplitude command value, the output voltage phase command value, and the output current command value at the two time points are used to determine the output voltage amplitude difference, output voltage phase difference, output voltage phase difference, power conversion device and load. The impedance difference between and is calculated and stored,
In the case where there are three or more load patterns, the amplitude command value of the output voltage between the power converters in the same manner as the first load pattern and the second load pattern in the third and subsequent load patterns, The stored value of the output voltage phase command value and the output current command value or filter output current or inverter output current is updated, and the updated output voltage amplitude command value and output each time these stored values are updated. Based on the voltage phase command value, output current command value, filter output current, or inverter output current, the output voltage amplitude difference, the output voltage phase difference between each power converter, and between each power converter and load Based on the output voltage amplitude difference, the output voltage phase difference, and the impedance difference between each power converter and the load, Cross current suppression method for a power converter according to claim 1, wherein computing the amplitude command and phase command value of the output voltage of the power converter. Limiting one of the load patterns of the test run to no load, adjusting the amplitude deviation and phase deviation so that the impedance difference is zero and the cross current is zero at no load, the amplitude difference and phase difference are obtained,
In the other load pattern, the impedance difference between each power converter and the load is adjusted based on the deviation between the output current command value and the filter output current or the inverter output current and the power factor of the load,
Based on the amplitude difference and phase difference obtained during the no-load pattern and the impedance difference between each power converter and the load adjusted during the other load pattern, the amplitude command value of the output voltage of each power converter The method for suppressing a cross current of a power converter according to any one of claims 1 to 3, wherein a phase command value is calculated. Each power converter comprises a bypass circuit that bypasses the power converter,
When the bypass power supply is abnormal, the correction value is subtracted from the individual rated frequency of each power converter, the result is integrated, and the value obtained by adding 2π to the value obtained by adding the phase command value, the amplitude command value of the output voltage, and the filter output voltage 5. The method for suppressing a cross current of a power converter according to claim 1, wherein the output voltage is controlled based on the detected value.   Detecting the harmonic component of the filter output voltage of each power converter and the harmonic component of the filter output current, and adjusting the amplitude and phase of the output voltage of each power converter using each harmonic component The cross current control method of the power converter according to claim 1. When the effective value of the current output current command value is larger than the third threshold value and the effective value of the output current command value before one calculation cycle is smaller than the third threshold value, the effective value of the output current command value before one calculation cycle Adjust the output voltage phase difference and output voltage amplitude difference according to
When the effective value of the current output current command value is smaller than the third threshold value and the effective value of the output current command value one calculation cycle before is larger than the third threshold value, the active power component of the output current command value is output as the output current command. The value obtained by dividing the reactive power component of the output current command value by the effective value of the output current command value, and the value representing the rated current amplitude, and the output current command value amplitude one calculation cycle before The method for suppressing a cross current of a power converter according to any one of claims 1 to 6, wherein an impedance difference between each power converter and a load is adjusted based on the subtracted value.   The power converter device which performs the cross current control method according to any one of claims 1 to 7.

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