JP2016063165A - Imaging element and solid-state imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging element capable of suppressing the transfer remaining of a signal charge and a solid-state imaging apparatus.SOLUTION: The imaging element includes a storage electrode, a second insulation layer, a semiconductor layer, a collection electrode, a photoelectric conversion layer, and an upper electrode. The storage electrode is formed on a first insulation layer. The second insulation layer is formed on the storage layer. The semiconductor layer is formed so as to cover the storage electrode and the second insulation layer. The collection electrode is formed so as to be in contact with the semiconductor layer and is formed so as to be away from the storage electrode. The photoelectric conversion layer is formed on the semiconductor layer. The upper electrode is formed on the photoelectric conversion layer.SELECTED DRAWING: Figure 3

Description

  Embodiments described herein relate generally to an imaging element and a solid-state imaging device.

  Conventionally, solid-state image sensors such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCDs (Charge Coupled Devices) have been widely used in solid-state image pickup devices. In these solid-state imaging devices, generally, an impurity diffusion region called a floating diffusion region (FD portion) is used to convert a signal charge, which is a charge generated by photoelectric conversion, into a signal voltage.

  The solid-state imaging device resets (initializes) the FD unit to a predetermined potential by the reset transistor every time each frame is imaged. When the FD section is reset by the reset transistor, random thermal noise (kTC noise) is generated. This kTC noise is removed using a correlated double sampling technique.

In recent years, among these solid-state imaging devices, a multilayer imaging device has attracted attention from the viewpoint of improving light utilization efficiency and pixel miniaturization. For example, the multilayer imaging element has a structure in which a photoelectric conversion film such as an organic photoelectric conversion film is stacked on a surface upper layer on a light receiving surface side of a silicon substrate. In such a multilayer imaging device, the photoelectric conversion film formed on the silicon substrate does not have a function of holding signal charges, and therefore kTC noise is removed by post-reset correlated double sampling. However, the post-reset correlated double sampling has a problem that kTC noise is not sufficiently removed.
As a conventional technique for solving such a problem, a multilayer imaging device has been proposed in which signal charges are accumulated in a photoelectric conversion film and kTC noise is removed using correlated double sampling of a pre-reset method.

  However, in such a multilayer imaging device, there are cases where the signal charge is not completely transferred when the signal charge accumulated in the photoelectric conversion film is transferred to the FD portion. That is, there is a case where a signal charge transfer residue occurs in a transfer time with a realistic length.

US Patent Application Publication No. 2013/0093911 US Patent Application Publication No. 2013/0093932

  The problem to be solved by the present invention is to provide an imaging device and a solid-state imaging device that can suppress the remaining transfer of signal charges.

  The imaging device of the embodiment includes a storage electrode, a second insulating layer, a semiconductor layer, a collection electrode, a photoelectric conversion layer, and an upper electrode. The storage electrode is formed on the first insulating layer. The second insulating layer is formed on the storage electrode. The semiconductor layer is formed to cover the storage electrode and the second insulating layer. The collecting electrode is formed so as to be in contact with the semiconductor layer, and is formed so as to be separated from the storage electrode. The photoelectric conversion layer is formed on the semiconductor layer. The upper electrode is formed on the photoelectric conversion layer.

1 is a block diagram showing an example of the overall configuration of a solid-state imaging device 1 according to the present embodiment. FIG. 3 is a diagram illustrating a circuit configuration example of one pixel 10 included in the solid-state imaging device 1 according to the first embodiment. FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure corresponding to one pixel 10 included in the solid-state imaging device 1 according to the first embodiment. FIG. 3 is a diagram illustrating an example of a device structure of a pixel 10 provided in the solid-state imaging device 1 according to the first embodiment. 5 is a flowchart illustrating an example of an operation flow of the solid-state imaging device 1 according to the first embodiment. 4 is a timing chart for explaining the operation of the solid-state imaging device 1 of the first embodiment. FIG. 3 is a diagram illustrating an example of the potential of an internal node of a pixel in each process of the operation of the solid-state imaging device 1 of the first embodiment. The figure which shows the model in the calculation formula of the transfer time of MOS bucket bridge. The figure which shows an example of the result of having estimated the transfer time at the time of using various semiconductor materials for the semiconductor layer 35 of the pixel 10 concerning 1st Embodiment. The table | surface which shows an example of the mobility of various semiconductor materials used for estimation of the transfer time shown in FIG. Diagram showing an example of the estimated result of the transfer time in the solid-state imaging device 1 of the first embodiment to the gap length L _1. FIG. 6 is a cross-sectional view schematically showing a cross-sectional structure corresponding to one pixel 10A included in a solid-state imaging device 1A according to a modification of the first embodiment. Sectional drawing which shows typically the cross-sectional structure corresponding to one pixel 10B with which the solid-state imaging device 1B which concerns on 2nd Embodiment is provided. The figure which shows the manufacturing method of the solid-state imaging device 1B which concerns on 2nd Embodiment. The figure which shows the manufacturing method of the solid-state imaging device 1B which concerns on 2nd Embodiment. The figure which shows the manufacturing method of the solid-state imaging device 1B which concerns on 2nd Embodiment. The figure which shows the manufacturing method of the solid-state imaging device 1B which concerns on 2nd Embodiment. The top view which shows typically the structure corresponding to one pixel 10C with which the solid-state imaging device 1C which concerns on 3rd Embodiment is provided. The top view which shows typically arrangement | positioning of each pixel 10D in the pixel array 2D with which the solid-state imaging device 1D which concerns on 4th Embodiment is provided. The top view which shows typically arrangement | positioning of each pixel 10E in the pixel array 2E with which the solid-state imaging device 1E which concerns on the modification of 4th Embodiment is provided.

Hereinafter, an imaging device and a solid-state imaging device according to embodiments will be described with reference to the drawings.
In the following description, the electrical connection between the components of the solid-state imaging device of the embodiment may be a direct connection or an indirect connection. The direct connection may be performed, for example, by directly connecting members forming the components of the plurality of components. Indirect connection may be performed by, for example, indirectly connecting members forming a plurality of components to each other via any other conductive member.
The drawings in the following description are for explaining the configuration of the solid-state imaging device, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the dimensional relationship of the actual solid-state imaging device.

(First embodiment)
FIG. 1 is a block diagram illustrating an example of the overall configuration of a solid-state imaging device 1 according to the first embodiment.
The solid-state imaging device 1 includes a pixel array 2, a vertical scanning unit 3, a horizontal scanning unit 4, and a control unit 5. The pixel array 2 includes a plurality of pixels 10 arranged in a matrix. The pixel 10 is one example of an image sensor.

  In the row direction of the pixel array 2, a plurality of selection signal lines 3-A1, 3-A2,..., 3-An (n is a natural number) for transmitting the selection signal SEL output from the vertical scanning unit 3 to the pixel 10. ) Is provided. Hereinafter, the selection signal line 3-Ai (i is a natural number satisfying 1 ≦ i ≦ n) indicates one of the plurality of selection signal lines 3-A1, 3-A2,.

  In the row direction of the pixel array 2, a plurality of control signal lines 3-B1, 3-B2,..., 3-Bn for transmitting the reset signal RST output from the vertical scanning unit 3 are selected as described above. The signal lines 3-A1, 3-A2,..., 3-An are provided in parallel. Hereinafter, the control signal line 3-Bi indicates one of the plurality of control signal lines 3-B1, 3-B2,..., 3-Bn.

In the column direction of the pixel array 2, a plurality of pixel signal lines 4-1, 4-2,..., 4-m (m is a natural number) for transmitting the pixel signal output from the pixel 10 to the horizontal scanning unit 4. Is provided. Hereinafter, the pixel signal line 4-j (j is a natural number satisfying 1 ≦ j ≦ m) indicates one of the plurality of pixel signal lines 4-1, 4-2,.
The plurality of pixels 10 constituting the pixel array 2 include a plurality of selection signal lines 3-A1, 3-A2,..., 3-An and a plurality of pixel signal lines 4-1, 4-2,. It is arranged in the intersection area.

  The vertical scanning unit 3 drives the plurality of pixels 10 arranged in the pixel array 2 in units of rows. The vertical scanning unit 3 is configured by a shift register, for example. The vertical scanning unit 3 outputs a selection signal SEL for selecting the pixels 10 constituting the pixel array 2 in units of rows and a reset signal RST for controlling the operation of each pixel 10. That is, the vertical scanning unit 3 selectively scans each pixel 10 in the vertical direction in units of rows, and the selected pixel 10 outputs a pixel signal to the horizontal scanning unit 4 through the pixel signal line 4-j. Here, the pixel signal is a signal based on the signal charge generated by the photoelectric conversion unit of each pixel 10. The photoelectric conversion unit generates a signal charge according to the amount of received light. The photoelectric conversion unit is, for example, a photoelectric conversion film sandwiched between two opposing electrodes.

  The horizontal scanning unit 4 performs signal processing on the pixel signal output from each pixel 10 of the pixel array 2. The horizontal scanning unit 4 includes a column amplifier for amplifying the pixel signal output from each pixel 10 and a signal processing unit for performing signal processing on the amplified pixel signal. The horizontal scanning unit 4 performs signal processing such as correlated double sampling (CDS), signal amplification, AD conversion, and the like for removing the inherent fixed pattern noise of the pixel 10.

  The control unit 5 controls the overall operation of the solid-state imaging device 1. In the present embodiment, the control unit 5 mainly performs control related to driving of the pixels 10. The control unit 5 performs control to read out a pixel signal corresponding to the amount of signal charge generated by the photoelectric conversion unit by exposure after initialization by a circuit unit including a plurality of pixel transistors.

FIG. 2 is a diagram illustrating a circuit configuration example of one pixel 10 included in the solid-state imaging device 1 according to the first embodiment.
In the specific example illustrated in FIG. 2, each pixel 10 includes a photoelectric conversion unit PEC and a pixel circuit unit 21 having a plurality of pixel transistors (so-called MOS transistors). Voltages (VB31, VB33, and VB42) for controlling the potential of the electrodes are applied to each electrode of the photoelectric conversion unit PEC of the pixel 10.
Specifically, the pixel circuit unit 21 of the pixel 10 includes three pixel transistors: a reset transistor RX, an amplification transistor AX, and a selection transistor SX. A predetermined power supply voltage is applied to the drain of the amplification transistor AX. The source of the amplification transistor AX is connected to the drain of the selection transistor SX. The source of the amplification transistor AX is connected to the drain of the selection transistor SX, and the source of the selection transistor SX is connected to the pixel signal line 4-j. A selection signal SEL output from the vertical scanning unit 3 is applied to the gate of the selection transistor SX. A predetermined power supply voltage is applied to the drain of the reset transistor RX, and the source of the reset transistor RX is connected to the gate of the amplification transistor AX. A reset signal RST output from the vertical scanning unit 3 is applied to the gate of the reset transistor RX. The gate of the amplification transistor AX and the source of the reset transistor RX are connected to an FD unit 22 (to be described later) constituting the photoelectric conversion unit PEC. Voltages VB31, VB33, and VB42 are applied to a storage electrode 31, a collection electrode 33, and an upper electrode 42, which will be described later, provided in the photoelectric conversion unit PEC, respectively. Further, the pixel 10 may be configured by four pixel transistors including a transfer transistor.

FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure corresponding to one pixel 10 included in the solid-state imaging device 1 according to the first embodiment. The solid-state imaging device 1 may be a so-called stacked CMOS image sensor.
The pixel 10 includes a semiconductor substrate 20, an interlayer insulating film 30, a storage electrode 31, an insulating film 32, a collecting electrode 33, a contact plug 34, a semiconductor layer 35, a photoelectric conversion layer (photoelectric conversion film) 41, and an upper electrode 42. . The storage electrode 31, the collection electrode 33, and the insulating film 32 are disposed between the interlayer insulating film 30 and the semiconductor layer 35. Among these, the storage electrode 31, the insulating film 32, the collection electrode 33, the semiconductor layer 35, the photoelectric conversion layer 41, and the upper electrode 42 constitute the photoelectric conversion unit PEC shown in FIG.

The pixel 10 may have a plurality of photoelectric conversion units. For example, the pixel 10 may further include a photoelectric conversion unit such as a PD (photodiode) in the semiconductor substrate unit 20 in addition to the photoelectric conversion layer 41. In this case, the photoelectric conversion layer 41 receives light in a specific wavelength range and performs photoelectric conversion, and the photoelectric conversion unit formed in the semiconductor substrate unit 20 receives light in another wavelength range and performs photoelectric conversion. Do.
When the pixel 10 has a plurality of photoelectric conversion units, a so-called pixel sharing structure in which the plurality of photoelectric conversion units share other pixel transistors except the transfer transistor and share a floating diffusion (FD) is adopted. Can do.

  The solid-state imaging device 1 shown in FIG. 3 is a solid-state imaging device using a so-called back-illuminated CMOS image sensor. That is, the upper electrode 42 (upper surface F1 of the upper electrode 42 shown in FIG. 3) formed on the back surface of the semiconductor substrate unit 20 is a light receiving surface that receives light by being incident, and the surface of the semiconductor substrate unit 20 (FIG. 3 is a circuit forming surface on which a circuit including a readout circuit is formed. Note that the solid-state imaging device according to the present embodiment is not limited to a solid-state imaging device using a backside-illuminated CMOS image sensor. The image sensor may be used.

  The semiconductor substrate portion 20 is formed using a silicon substrate capable of forming a pn junction by doping with ion impurities. Examples of the silicon substrate include those made of crystal silicon (cSi), amorphous silicon (aSi), or the like. A pixel circuit unit 21 is formed inside the semiconductor substrate unit 20. The pixel circuit unit 21 includes a pixel transistor and an FD unit 22. The FD portion 22 is a semiconductor region capable of accumulating charges, and its potential can be in a floating state.

The interlayer insulating film 30 is one specific example of the first insulating layer. The interlayer insulating film 30 is formed on the semiconductor substrate unit 20. The interlayer insulating film 30 is, for example, a so-called interlayer insulating film. For the interlayer insulating film 30, an inorganic compound or an organic compound having a high relative dielectric constant can be used. The interlayer insulating film 30 is, for example, SiO ₂ (silicon oxide film).

The storage electrode 31, the insulating film 32, and the collection electrode 33 are patterned for each pixel. The storage electrode 31 is formed on the interlayer insulating film 30.
The material used for the storage electrode 31 is preferably excellent in workability. Examples of materials used for the storage electrode 31 include indium tin oxide (ITO), zinc oxide (ZnO), graphene, and the like.

The insulating film 32 is one specific example of the second insulating layer. The insulating film 32 is formed on the storage electrode 31. The insulating film 32 electrically insulates the semiconductor layer 35 and the storage electrode 31. The insulating film 32 may be formed of the same material as the interlayer insulating film 30 or may be formed of a different material. In order to electrically insulate the semiconductor layer 35 and the storage electrode 31, the thickness of the insulating film 32 is desirably 3 nm or more. The material used for the insulating film 32 is preferably a material with excellent workability.
Examples of the material used for the insulating film 32 include a silicon oxide film, a silicon nitride film, alumina, and an insulating organic compound.

The collecting electrode 33 is formed on the interlayer insulating film 30. The collecting electrode 33 is formed with an interval L ₁ between the collecting electrode 33 and the storage electrode 31. The collection electrode 33 is formed in contact with the semiconductor layer 35.
The material used for the collecting electrode 33 is preferably a material excellent in workability. Examples of the material used for the collecting electrode 33 include indium tin oxide (ITO), zinc oxide (ZnO), graphene, and the like.

It is desirable that the storage electrode 31, the insulating film 32, and the collecting electrode 33 transmit 80% or more of light in a specific wavelength region. The light in the specific wavelength region is, for example, light in the red (R) region (wavelength band in the range of about 590 nm to about 750 nm) and green (G) region (wavelength band in the range of about 500 nm to about 590 nm). Light, light in the blue (B) region (wavelength band in the range of about 400 nm to about 500 nm), light in the visible light region (wavelength band in the range of about 400 nm to about 750 nm), and the like.
When the pixel 10 has a plurality of photoelectric conversion units, if any of the storage electrode 31, the insulating film 32, and the collection electrode 33 absorbs light irradiated at the time of exposure, a photoelectric other than the photoelectric conversion layer 41 is used. The amount of light received by the converter is reduced. Therefore, there is a problem that the apparent sensitivity of the pixel 10 is lowered. In the present embodiment, the storage electrode 31, the insulating film 32, and the collection electrode 33 are formed so as to transmit light, thereby suppressing the occurrence of such a problem.

  The contact plug 34 penetrates the interlayer insulating film 30 and electrically connects the collecting electrode 33 and the FD portion 22 of the pixel circuit portion 21. The contact plug 34 may be formed by embedding a conductive material such as tungsten in a via that penetrates the interlayer insulating film 30. The contact plug 34 can also be formed by a semiconductor layer or the like by ion implantation.

The semiconductor layer 35 is formed so as to cover the entire surface of the storage electrode 31, the insulating film 32, and the collection electrode 33. The thickness of the semiconductor layer 35 is formed to be thicker than the sum of the thickness of the storage electrode 31 and the thickness of the insulating film 32. As a result, the semiconductor layer 35 is formed as a continuous layer from the step between the storage electrode 31 and the collection electrode 33 to the storage electrode 31 or the collection electrode 33. For example, when the thickness of the storage electrode 31 is 20 nm and the thickness of the insulating film 32 is 5 nm, the thickness of the semiconductor layer 35 is desirably 30 nm or more.
The semiconductor layer 35 is patterned for each pixel. As a result, the exchange of charges between the collecting electrodes 33 of the adjacent pixels 10 in the solid-state imaging device 1 is prevented.

  The semiconductor layer 35 accumulates the signal charges generated by the photoelectric conversion layer 41 in the semiconductor layer 35. The semiconductor layer 35 transfers the accumulated signal charge to the collecting electrode 33.

  An inorganic material or an organic semiconductor material may be used for the semiconductor layer 35. The semiconductor layer 35 may be formed, for example, by performing photolithography and etching after forming an inorganic material by sputtering. The semiconductor layer 35 may be formed, for example, by patterning by screen printing using an organic semiconductor material.

The semiconductor layer 35 is preferably formed using a material having high light transmittance. The semiconductor layer 35 desirably transmits 80% or more of light in a specific wavelength region. The light in the specific wavelength region is, for example, red (R) region light, green (G) region light, blue (B) region light, visible light region light, or the like. Further, the material used for the semiconductor layer 35 is preferably a material excellent in workability.
When the pixel 10 includes a plurality of photoelectric conversion units, if the semiconductor layer 35 absorbs light irradiated at the time of exposure, the amount of light received by a photoelectric conversion unit different from the photoelectric conversion layer 41 decreases. Therefore, there is a problem that the apparent sensitivity of the pixel 10 is lowered. In the present embodiment, the occurrence of such a problem is suppressed by configuring the semiconductor layer 35 to transmit light.

Examples of the inorganic material used for the semiconductor layer 35 include silicon carbide, IGZO, diamond, graphene, and carbon nanotube. Examples of the organic semiconductor material used for the semiconductor layer 35 include a condensed polycyclic hydrocarbon compound and a condensed heterocyclic compound. Examples of the condensed polycyclic hydrocarbon compound include pentacene and rubrene. Examples of fused heterocyclic compounds and derivatives thereof include 2,7-dioctyl [1] benzothieno [3,2-b] [1] benzothiophene (C8-BTBT), 3,11-didecyldinaphtho [2,3-d : 2 ′, 3′-d ′] benzo [1,2-b: 4,5-b ′] dithiophene (C10-DNBDT) and the like. Note that a film using C8-BTBT or C10-DNBDT as a material can be formed using the method described in Reference Document 1 below.
Reference 1: Material of the 112th Technical Meeting of the Imaging Society of Japan, 2011, p75

  The photoelectric conversion layer 41 is formed on the semiconductor layer 35. The photoelectric conversion layer 41 is not patterned and is formed on the entire light receiving surface of the pixel 10. The photoelectric conversion layer 41 performs photoelectric conversion according to exposure to generate signal charges. The amount of the generated signal charge depends on the amount of light received by the photoelectric conversion layer 41.

Any photoelectric conversion film can be used for the photoelectric conversion layer 41 as long as it can be stacked on a semiconductor substrate. The photoelectric conversion layer 41 is formed using, for example, an organic photoelectric conversion material.
In the pixel 10 illustrated in FIG. 3, the photoelectric conversion layer 41 is illustrated as a single layer, but the photoelectric conversion layer 41 may include a plurality of layers. The photoelectric conversion layer 41 may be patterned for each pixel.

  The upper electrode 42 is formed on the photoelectric conversion layer 41. The upper electrode 42 may be formed on the entire light receiving surface of the pixel 10 without being patterned, or may be patterned for each pixel. Examples of the material used for the upper electrode 42 include indium tin oxide (ITO), zinc oxide (ZnO), graphene, and the like.

  It is desirable that the upper electrode 42 be formed using a material having high light transmittance. The upper electrode 42 desirably transmits 80% or more of light in a specific wavelength region. The light in the specific wavelength region is, for example, red (R) region light, green (G) region light, blue (B) region light, visible light region light, or the like. Accordingly, the amount of light received by the photoelectric conversion layer 41 is suppressed by the upper electrode 42 absorbing the exposed light. That is, it is suppressed that the apparent sensitivity of the pixel 10 decreases.

  In the pixel 10 shown in FIG. 3, each layer formed on the semiconductor substrate portion 20 can be manufactured using a dry film forming method or a wet film forming method. As the dry film forming method, a vacuum vapor deposition method, a sputtering method, an ion plating method, a physical vapor deposition method such as MBE, or a CVD method such as plasma polymerization can be used. As the wet film formation method, a coating method such as a cast method, a spin coating method, a dipping method, or an LB method can be used. Further, a printing method such as ink jet printing or screen printing, or a transfer method such as thermal transfer or laser transfer may be used.

Next, a method for manufacturing the solid-state imaging device 1 according to the first embodiment will be described.
First, the pixel circuit unit 21 including a plurality of pixel transistors and the FD unit 22 is formed in a region to be each pixel 10 of the semiconductor substrate unit 20. Next, after the interlayer insulating film 30 is stacked on the semiconductor substrate portion 20, a contact plug 34 penetrating the interlayer insulating film 30 is formed. The contact plug 34 is connected to the FD portion 22 described above. Next, the storage electrode 31, the insulating film 32, and the collecting electrode 33 are formed on the interlayer insulating film 30. Collecting electrode 33 is formed so as to open the predetermined interval of the gap length L ₁ minute between the storage electrode 31. The storage electrode 31, the insulating film 32, and the collection electrode 33 may be formed by performing photolithography and etching after being stacked over the entire region to be the pixel 10. Next, the semiconductor layer 35 is formed on the storage electrode 31, the insulating film 32, and the collection electrode 33. Next, after the photoelectric conversion layer 41 is formed on the semiconductor layer 35, the upper electrode 42 is formed on the photoelectric conversion layer 41. Through the steps as described above, the solid-state imaging device 1 can be manufactured.

FIG. 4 is a diagram illustrating an example of a device structure of the pixel 10 provided in the solid-state imaging device 1 according to the first embodiment. In the configuration of the pixel 10 illustrated in FIG. 4, the same components as those illustrated in FIG. 3 are denoted by the same reference numerals. 4 illustrates the device structure of the photoelectric conversion unit PEC and the device structure of the reset transistor RX that configures the pixel circuit unit 21 among the components of the pixel 10 illustrated in FIG. 2 described above. In FIG. 4, the amplification transistor AX and the selection transistor SX constituting the pixel circuit unit 21 are shown outside the frame of the pixel circuit unit 21 for easy understanding, but the amplification transistor AX and the selection transistor SX are The reset transistor RX is formed on the semiconductor substrate portion 20 together with the reset transistor RX.
As described above, the pixel 10 of the semiconductor substrate unit 20 includes the reset transistor RX, the amplification transistor AX, and the selection transistor SX. In the following example, for example, N-channel MOS transistors are used as these transistors, but P-channel MOS transistors may be used, or other transistors may be used.
The gate of the reset transistor RX is the conductive layer 24. The conductive layer 24 is formed on the semiconductor substrate unit 20 via an insulating film (not shown) formed on the semiconductor substrate unit 20 of the pixel 10. A control signal line 3-Bi is connected to the conductive layer 24, and a reset signal RST is applied. The drain of the reset transistor RST is the impurity diffusion region 23 and is connected to the power supply voltage line. The impurity diffusion region 23 is kept at a constant voltage (for example, V ₁ ). The source of the reset transistor RST is connected to the FD unit 22. The reset transistor RX becomes conductive when turned on by the reset signal RST, and resets the FD unit 22 to a predetermined potential.
The gate of the amplification transistor AX is connected to the FD unit 22. The drain of the amplification transistor AX is connected to the power supply voltage line. The source of the amplification transistor AX is connected to the selection transistor SX. The amplification transistor AX functions as a source follower.
A selection signal line 3-Ai is connected to the gate of the selection transistor SX, and a selection signal SEL is applied thereto. The drain of the selection transistor SX is connected to the source of the amplification transistor AX. The source of the selection transistor SX is connected to the pixel signal line 4-j. When the selection transistor SX is turned on by the selection signal SEL output from the vertical scanning unit 3, the selection transistor SX transmits the pixel signal output from the amplification transistor AX to the pixel signal line 4-j. A signal corresponding to the potential of the FD unit 22 is output as a pixel signal output by the amplification transistor AX and the selection transistor SX.

  Next, the operation of the solid-state imaging device 1 of the first embodiment will be described along the flowchart shown in FIG. 5 with reference to FIGS. 6 and 7. FIG. 5 is a flowchart illustrating an example of an operation flow of the solid-state imaging device 1 according to the first embodiment. FIG. 6 is a timing chart for explaining the operation of the solid-state imaging device 1 of the first embodiment. FIG. 7 is a diagram illustrating an example of the potential of the internal node of the pixel in each process of the operation of the solid-state imaging device 1 according to the first embodiment. Here, the operation of the pixel 10 shown in FIG. 3 will be mainly described. Here, as an example, a case where the signal charge generated by the photoelectric conversion layer 41 of the pixel 10 is an electron will be described. Here, a case will be described in which the solid-state imaging device 1 continuously captures a plurality of frames such as moving image shooting.

First, at time t0, exposure is started, and signal charges generated by the photoelectric conversion layer 41 are accumulated in the semiconductor layer 35 (step S1). More specifically, the solid-state imaging device 1, so that the potential phi ₃₁ of the storage electrode 31, the potential phi ₄₂ potential phi ₃₃ and the upper electrode 42 of the collecting electrode 33, satisfies the following equation (1), Voltages VB31, VB33, and VB42 are applied to the storage electrode 31, the collection electrode 33, and the upper electrode. For example, under the control of the control unit 5, the vertical scanning unit 3 applies 0 V as the voltage VB ₃₁ that gives the potential φ ₃₁ to the storage electrode 31 and applies −1 V as the voltage VB ₃₃ that gives the potential φ ₃₃ to the collection electrode 33. and, applying a -5V as a voltage VB42 for applying a potential phi ₄₂ to the upper electrode 42.

At this time, in the photoelectric conversion layer 41, electrons and holes (electron-hole pairs) are generated by photoelectric conversion. The amount of electron-hole pairs generated corresponds to the exposure dose. More specifically, for example, when the photoelectric conversion layer 41 is formed of an organic photoelectric conversion film, excitons generated in the organic photoelectric conversion film by exposure are generated by an electric field generated in the photoelectric conversion layer 41. The carrier is separated. The electric field generated in the photoelectric conversion layer 41 is an electric field generated by a potential difference between the upper electrode 42 and the storage electrode 31 or an electric field generated by a potential difference between the upper electrode 42 and the collection electrode 33.
When the signal charge is an electron, most of the electrons in the electron-hole pair move toward the storage electrode 31 side. At this time, holes in the electron-hole pair move toward the upper electrode 42 and are further discharged out of the photoelectric conversion layer 41 via the upper electrode 42.
There is an insulating film 32 between the storage electrode 31 and the semiconductor layer 35. Therefore, electrons that have moved from the photoelectric conversion layer 41 toward the storage electrode 31 cannot exceed the potential barrier due to the insulating film 32, and the vicinity of the upper portion of the storage electrode 31 and the insulating film 32 in the semiconductor layer 35 ( Hereinafter, it is stored in a “signal charge storage area”). That is, the signal charge (electrons) is accumulated in the inner region of the semiconductor layer 35 and in the region near the interface with the second insulating layer. At this time, since the potential of the storage electrode 31 is equal to or higher than the potential of the collection electrode 33, the signal charge accumulated in the signal charge accumulation area does not move toward the collection electrode 33 and enters the signal charge accumulation area. It remains accumulated.

Next, at time t1, the solid-state imaging device 1 resets the FD unit 22 of the pixel 10 (step S2). More specifically, under the control of the control unit 5, the vertical scanning unit 3 sets the selection signal SEL and the reset signal RST to a high level. At this time, the voltage V _RST of the reset signal RST applied to the conductive layer 24 is higher than the voltage V ₁ applied to the impurity diffusion region 23. Therefore, the potential of the conductive layer 24 to which the voltage V _RST is applied, is lower than the potential phi ₁ of the impurity diffusion region 23, reset transistor RX is turned on. When the reset transistor RX is turned on, charge is exchanged between the FD portion 22 and the impurity diffusion region 23. Therefore, FD unit 22, the same potential phi ₁ and the impurity diffusion region 23 is reset (see first row in FIG. 7).

Subsequently, at time t2, under the control of the control unit 5, the vertical scanning unit 3 sets the reset signal RST to a low level. As a result, the reset transistor RX is turned off, and the FD portion 22 is electrically disconnected from the impurity diffusion region 23. That is, the FD unit 22 is in a floating state. Thermal noise (kTC noise) is generated when the reset transistor RX is turned off. Therefore, the potential of the FD portion 22 becomes a potential φ ₂ different from φ ₁ . The kTC noise is a noise that is randomly generated every time the reset transistor RX is turned off.

Subsequently, at time t3, under the control of the control unit 5, the horizontal scanning unit 4 reads the voltage VSIG indicating the voltage of the FD unit 22, and detects the voltage value of the voltage VSIG as a reset level (step S3). Specifically, the voltage of the FD unit 22 is output from the pixel 10 through the amplification transistor AX as the pixel signal VSIG. At this time, the voltage VSIG read from the FD portion 22 is a voltage corresponding to the potential phi _2, the reset transistor RX at time t2 contains a kTC noise generated when it is in the OFF state (FIG. 7 (See the second row of The pixel signal VSIG output from the pixel 10 is supplied to the horizontal scanning unit 4 through the pixel signal line 4-j. The horizontal scanning unit 4 amplifies the pixel signal VSIG and outputs a voltage _Vout . A signal processing unit (not shown) of the horizontal scanning unit 4 samples and holds the voltage _Vout as a reset level.

Subsequently, at time t4, the solid-state imaging device 1 transfers the signal charge to the FD unit 22 (step S4). In addition, at time t4, the solid-state imaging device 1 ends (completes) the exposure and signal charge accumulation performed from time t0.
More specifically, the solid-state imaging device 1, the potential phi ₃₁ of the storage electrode 31, so that the potential phi ₄₂ potential phi ₃₃ and the upper electrode 42 of the collecting electrode 33, satisfies the formula (2) shown below, A voltage is applied to the storage electrode 31, the collection electrode 33 and the upper electrode 42. For example, under the control of the control unit 5, the vertical scanning unit 3 applies −1 V as the voltage VB ₃₁ that applies the potential φ ₃₁ to the storage electrode 31, and applies 0 V as the voltage VB ₃₃ that applies the potential φ ₃₃ to the collection electrode 33. and, applying a -5V as a voltage VB42 for applying a potential phi ₄₂ to the upper electrode 42.

At this time, a fringe electric field is generated between the vicinity of the edge of the storage electrode 31 on the collection electrode 33 side and the collection electrode 33. The fringe electric field is generated by a potential difference between the storage electrode 31 and the collection electrode 33, and is near the center of the signal charge storage area (that is, near the center of the upper portion of the storage electrode 31 in the semiconductor layer 35). Does not occur. By this fringe electric field, the signal charge accumulated near the edge on the collection electrode 33 side of the signal charge accumulation area is transferred to the collection electrode 33. As a result, the signal charge density in the vicinity of the edge on the collection electrode 33 side of the signal charge accumulation area is lowered, and a signal charge concentration gradient is generated in the signal charge accumulation area. Due to the concentration gradient of the signal charge, the signal charge accumulated in the signal charge accumulation area moves by diffusion from the vicinity of the center of the signal charge accumulation area toward the edge of the signal charge accumulation area on the collecting electrode 33 side. .
Thus, even when the fringe electric field due to the potential difference between the storage electrode 31 and the collection electrode 33 does not occur near the center of the signal charge storage area, the signal charge stored near the center of the signal charge storage area. Is also transferred to the collecting electrode 33. The signal charge transferred to the collection electrode 33 is transferred to the FD unit 22 via the contact plug 34. Potential of the FD unit 22 by the signal charge is transferred from the signal charge storage area, the potential phi ₃ (see third stage of FIG. 7).
In general, the movement speed of charges due to diffusion is slower than the movement speed of charges due to electric field drift. Therefore, the time for the signal charge to move in the signal charge storage area by diffusion is longer than the time for the signal charge to move by the fringe electric field between the storage electrode 31 and the collection electrode 33. However, as will be described later, when the semiconductor layer 35 is formed of a material having sufficiently high mobility, signal charges can be transferred from the storage electrode 31 to the collection electrode 33 within a realistic time. .
The solid-state imaging device 1 captures a plurality of frames by repeatedly executing the above steps S1 to S4. The solid-state imaging device 1 executes step S5 and step S6 described below after step S4 each time the above-described steps S1 to S4 are repeatedly executed.

After step S4 described above, at time t5, under the control of the control unit 5, the horizontal scanning unit 4 detects a voltage VSIG indicating the voltage of the FD unit 22 as a pixel signal (step S5). Specifically, the voltage of the FD unit 22 is output from the pixel 10 through the amplification transistor AX and the selection transistor SX as the pixel signal VSIG. At this time, the voltage of the pixel signal VSIG is a voltage corresponding to the potential phi ₃ (see the fourth stage of FIG. 7).
After the FD unit 22 is reset at time t1, the kTC noise remains held in the FD unit 22. Therefore, the pixel signal VSIG includes the same kTC noise as the kTC noise included in the voltage VSIG detected at time t3.
The pixel signal VSIG output from the pixel 10 is supplied to the horizontal scanning unit 4 through the pixel signal line 4-j. The horizontal scanning unit 4 amplifies the pixel signal VSIG and outputs a voltage _Vout . A signal processing unit (not shown) of the horizontal scanning unit 4 samples and holds the voltage _Vout .

Subsequently, at time t6, under the control of the control unit 5, the signal processing unit of the horizontal scanning unit 4 calculates the signal voltage VS from the voltage _Vout obtained by the above sampling (step S6). Specifically, the signal processing unit of the horizontal scanning unit 4 is based on the sampling value of the voltage V _out (reset level) based on the voltage VSIG of the FD unit 22 at time t3 and the voltage VSIG of the FD unit 22 at time t6. The difference between the voltage _{Vout and} the sampling value is calculated, and the calculation result is output as the signal voltage VS. The signal voltage VS represents a signal component corresponding to the amount of charge generated by the photoelectric conversion layer 41 by exposure.
Thus, according to the solid-state imaging device 1, it is possible to obtain a signal voltage from which kTC noise has been removed by using the CDS process of the previous reset method.

Next, estimation of the time required for signal charges accumulated in the signal charge accumulation area to be transferred from the signal charge accumulation area to the collecting electrode 33 by diffusion will be described. The estimation of the time required for the signal charge accumulated in the signal charge accumulation area to move by diffusion was performed using the transfer time of the MOS bucket bridge described in Reference Document 2 below.
Reference 2: MGCollet and LJMEsser, Festkorperprobleme XIII, 1973, p337

FIG. 8 is a diagram illustrating a model in the calculation formula of the transfer time of the MOS bucket bridge. In the model shown in FIG. 8, MOS (Metal Oxide Semiconductor) structures (hereinafter referred to as “MOS”) that are adjacent to each other and are continuous are formed. The MOS in FIG. 8 includes a semiconductor substrate J1, a gate oxide film J2, and a gate electrode J3. The semiconductor substrate J1 is formed using p-type silicon. A channel portion J4 is formed in the semiconductor substrate J1 using n-type silicon. The gate oxide film J2 is formed of SiO ₂ on the semiconductor substrate J1. The gate electrode J3 is formed on the gate oxide film J2.
In the MOS bucket bridge configured as described above, the charges accumulated in the channel portion J4 immediately below the gate electrode J3 are transferred to the adjacent MOS. In the MOS bucket bridge, the charge transfer process includes a drift process due to a fringe electric field in the edge portion J5 and a diffusion process in the channel portion J4.
In the MOS bucket bridge, it is assumed that the doping concentration of the channel portion J4 is sufficiently high and there is no potential gradient of the channel portion J4 except for the vicinity of the edge portion J5 (the potential gradient can be regarded as flat). In the potential block region J6, it is assumed that the current during charge transfer is continuous.
The relationship between the transfer time and the accumulated charge amount in the MOS bucket bridge is expressed by the following equations (3) and (4) in consideration of the charge diffusion process.

Here, t is the time when the charge transfer start time is t = 0. Qs (0) is the amount of charge accumulated in the channel portion J2 at the start of charge transfer (t = 0), and Qs (t) is accumulated in the channel portion J4 at time t from the start of transfer. The amount of charge. Further, C _ox is the capacitance of the channel portion J4 per unit area, L _B is the distance between the gate electrodes of adjacent MOSs, and L _C is the gate electrode length of the MOSs. Further, μ _n is the mobility of the silicon layer (semiconductor substrate J1), q is the elementary charge, and n ₀ is the initial number of electrons per unit area (the number of electrons at t = 0).

Comparing the MOS bucket bridge model shown in FIG. 8 with the pixel 10 shown in FIG. 3, the semiconductor substrate J1 can be regarded as the semiconductor layer 35 in the pixel 10. Further, the gate oxide film J2 can be regarded as the insulating film 32 in the pixel 10. Further, the gate electrode J3 can be regarded as the storage electrode 31 in the pixel 10. Further, the adjacent MOS gate electrode to which the charge is transferred can be regarded as the collecting electrode 33 in the pixel 10.
That is, μ _n can be regarded as the mobility of the semiconductor layer 35. The distance _{L B} between the adjacent MOS gate electrode may be considered as the gap length _{L 1} between the storage electrode 31 and the collecting electrode 33, the gate electrode length _{L C} of the MOS, the storage electrode 31 it can be regarded as a minimum dimension L ₂ between the edges. Further, the capacitance C _ox of the channel portion J4 per unit area can be regarded as the capacitance per unit area of the capacitor formed by the semiconductor layer 35, the insulating film 32, and the storage electrode 31.

In order to perform high-speed reading equivalent to an existing 4-transistor CMOS image sensor (hereinafter referred to as “existing CMOS sensor”), the solid-state imaging device 1 performs an operation of reading a signal from each pixel (hereinafter referred to as “signal”). Read operation ”) must be performed within 1 / (f × Line) seconds. Here, f is a frame frequency, and Line is the number of rows of the pixel array 2 (sensor array). The signal reading operation includes an operation of reading a signal voltage from each pixel and an operation of resetting the FD unit 22. The operation of resetting the FD unit 22 takes about 2 μsec, for example.
From the above-described conditions regarding the time of the signal readout operation, and the equations (3) and (4), the solid-state imaging device 1 needs to be configured to satisfy the following equation (5). .

Here, S _C is the area of the storage electrode 31 per one pixel 10, Q, after the read operation of the signal charge (i.e., 1 / (f × Line) seconds) to the signal charge storage area This is the number of remaining signal charges (number of remaining signal charges).
In order for the solid-state imaging device 1 to operate with readout noise equivalent to that of an existing CMOS sensor, the number Q of remaining signal charges needs to be less than or equal to that of an existing sensor. In order for the solid-state imaging device 1 to operate with, for example, readout noise equivalent to the dark current noise of an embedded silicon photodiode, the number of remaining signal charges Q needs to be about 0.5 electrons or less. In addition, the solid-state imaging device 1 is equivalent to readout noise of an organic stacked CMOS image sensor (hereinafter referred to as “feedback reset organic CMOS sensor”) to which, for example, feedback reset described in Reference Document 3 below is applied. In order to operate with read noise, the number of remaining signal charges Q needs to be about 2.3 electrons or less.
Reference 3: M.Ishii, S.Kasuga, K.Yazawa, Y.Sakata, T.Okino, Y.Sato, J.Hirase, Y.Hirose, T.Tamaki, Y.Matsunaga, and Y.Kato, “ An ultra-low noise photoconductive film image sensor with a high speed column feed back amplifer noise canceller ”2013 Symposium on VLSI Circuits Digest of Technical Papers, C8
For example, in order to perform high-speed readout equivalent to that of an existing CMOS sensor and to operate with readout noise equivalent to that of a feedback reset organic CMOS sensor, the solid-state imaging device 1 satisfies the following formula (6). It needs to be formed.

  Next, the signal charge transfer time when various semiconductor materials are used for the semiconductor layer 35 of the solid-state imaging device 1 will be described with reference to FIGS. 9 and 10. FIG. 9 is a diagram illustrating an example of a result of estimating a transfer time when various semiconductor materials are used for the semiconductor layer 35 of the pixel 10 according to the first embodiment. FIG. 10 is a table showing an example of the mobility of various semiconductor materials used for estimating the transfer time shown in FIG.

In the graph shown in FIG. 9, the vertical axis represents the band gap of various semiconductor materials, and the horizontal axis represents the transfer time when various semiconductor materials are used for the semiconductor layer 35 of the solid-state imaging device 1 of the first embodiment. Indicates.
Transfer times shown in FIG. 9, the shape in plan view of the storage electrode 31 of the pixel 10 is a square with a side length of 1 [mu] m, with the gap length L ₁ between the storage electrode 31 and the collecting electrode 33 is 50nm It is an estimate for a certain case. That is, in equation (6), the _{L 1} and 50 nm, and the _{L 2} and 1 [mu] m. Furthermore, since μ _n in equation (6) can be regarded as the mobility of the semiconductor layer 35, the transfer values shown in FIG. 9 are substituted by substituting the mobility values corresponding to the various semiconductor materials shown in the table of FIG. Time can be calculated.
The transfer time (8.6 μsec) indicated by the broken line in FIG. 9 is the maximum time that the solid-state imaging device 1 can perform for the signal readout operation from each pixel in order to perform high-speed readout equivalent to that of the existing CMOS sensor. Value. This transfer time (8.6 μsec) was estimated on the assumption that the solid-state imaging device 1 is Full-HD (pixel size 1920 × 1080) and the frame frequency f is 60 Hz. When the solid-state imaging device 1 is Full-HD, the number of lines Line of the pixel array 2 is 1920.

In the specific example of the estimation of the transfer time shown in FIG. 9, the transfer time of the solid-state imaging device 1 when IGZO is used for the semiconductor layer 35 is 2.87 μsec. That is, when IGZO is used for the semiconductor layer 35, the solid-state imaging device 1 performs the signal reading operation from each pixel including the operation (for example, 2 μsec) for resetting the FD unit 22 within the above-described 8.6 μsec. be able to.
On the other hand, in the configuration described in Patent Document 1 above, the signal charge accumulated in the organic photoelectric conversion film moves in the organic photoelectric conversion film and is transferred to the collecting electrode, and the transfer time is 6 msec. It is estimated that this is necessary. In this transfer time estimation, the organic photoelectric conversion film was assumed to be C60, and the mobility of the organic photoelectric conversion film was assumed to be 0.000001 [m ² / V / sec].

  From the viewpoint of signal charge transfer time, it is desirable that the material used for the semiconductor layer 35 has high mobility. It is desirable that the material used for the semiconductor layer 35 further transmits 80% or more of light in a wavelength band including visible light. As such a semiconductor material, graphene, IGZO, silicon carbide (SiC), a diamond thin film, a condensed polycyclic hydrocarbon compound, and a condensed heterocyclic compound can be used for the semiconductor layer 35. Examples of the condensed polycyclic hydrocarbon compound include pentacene and rubrene. Examples of fused heterocyclic compounds include 2,7-dioctyl [1] benzothieno [3,2-b] [1] benzothiophene (C8-BTBT), 3,11-didecyldinaphtho [2,3-d: 2 ′, 3′-d ′] benzo [1,2-b: 4,5-b ′] dithiophene (C10-DNBDT) and the like.

  In order to suppress noise due to carriers excited by thermal energy at room temperature, the band gap of the semiconductor material used for the semiconductor layer 35 is larger than the band gap of silicon (Si) used in existing photodiodes. It is desirable. By adopting such a configuration, the solid-state imaging device 1 is configured such that in the semiconductor layer 35, carriers excited by thermal energy at room temperature are mixed with signal charges accumulated in the semiconductor layer 35 and become noise. Can be suppressed.

Next, a description will be given of the relationship between the transfer time of the gap length L ₁ and the signal charges between the storage electrode 31 and the collecting electrode 33. Figure 11 is a diagram showing an example of the estimated result of the transfer time in the solid-state imaging device 1 of the first embodiment to the gap length L _1. Transfer times shown in FIG. 11 is a minimum dimension _{L 2} is 1μm between the edges of the storage electrode 31 of the solid-state imaging device 1, the semiconductor layer 35 is formed using IGZO, mobility 15cm in the semiconductor layer 35 ² / (V · sec) was estimated.

In the case where the solid-state imaging device 1 is, for example, Full-HD (pixel size 1920 × 1080) and the frame frequency f is 60 Hz, the solid-state imaging device 1 can perform high-speed reading equivalent to an existing CMOS sensor. The operation of reading the signal voltage from each pixel and the operation of resetting the FD section must be performed within 8.6 microseconds. When the time required for the reset operation of the FD unit 22 is 2 microseconds, the solid-state imaging device 1 needs to perform an operation of reading a signal voltage from each pixel within 6.6 microseconds (= 8.6-2). is there.
In the specific example shown in FIG. 11, for the transfer time to read out the signal voltage from the pixel is less than 6.6 microseconds, the gap length L ₁ between the storage electrode 31 and the collecting electrode 33 is equal to or less than 115nm Need to be formed.

According to the first embodiment described above, the solid-state imaging device 1 has the semiconductor layer 35 that is formed so as to cover the storage electrode 31 and the insulating film 32 and transfers the stored signal charge to the collection electrode 33. As a result, it is possible to suppress the remaining transfer of signal charges.
In particular, even when the fringe electric field due to the potential difference between the storage electrode 31 and the collection electrode 33 is not generated in the central portion on the storage electrode 31 in the semiconductor layer 35, the signal charge diffusion in the semiconductor layer 35 is used to By transferring the signal charge accumulated in the charge accumulation area to the collecting electrode 33, it is possible to perform high-speed reading equivalent to that of the existing CMOS sensor.
In addition, according to the first embodiment, in the semiconductor layer 35, signal charges generated by photoelectric conversion in the photoelectric conversion layer 41 can be accumulated and held. Therefore, the solid-state imaging device 1 can remove the kTC noise more accurately by using the pre-reset type CDS process than in the case of performing the post-reset type CDS process.

Next, a modification of the first embodiment will be described. FIG. 12 is a cross-sectional view schematically showing a cross-sectional structure corresponding to one pixel 10A included in the solid-state imaging device 1A according to the modification of the first embodiment.
The pixel 10A according to the modification of the first embodiment shown in FIG. 12 is different from the pixel 10A in that the collecting electrode 33a is provided in place of the collecting electrode 33 and the contact plug 34a is provided in place of the contact plug 34. The configuration can be the same as that of the pixel 10 according to the first embodiment. Therefore, among the components of the pixel 10A shown in FIG. 12, the same parts as those of the pixel 10 shown in FIG. 3 are assigned the same reference numerals as those in FIG.

  The collecting electrode 33 a is the same as the collecting electrode 33 in the solid-state imaging device 1 except that the collecting electrode 33 a is formed so as to surround the storage electrode 31.

  The contact plug 34 a is the same as the contact plug 34 in the solid-state imaging device 1 except that a plurality of contact plugs penetrate the interlayer insulating film 30.

Comparing the MOS bucket bridge model shown in FIG. 8 with the pixel 10A shown in FIG. 12, the distance L _B between adjacent MOS gate electrodes in the above equation (4) is the same as the storage electrode 31 and the collection electrode. It can be regarded as the gap length L ₁ between the electrode 33 (FIG. 12). Furthermore, the gate electrode length L _C of the MOS in the above equation (4) can be regarded as half the minimum dimension between the edges of the storage electrode 31. That is, when the shape of the pixel 10 </ _b > A in the plane of the storage electrode 31 is a square, L ₂ in the above equation (5) corresponds to half of one side of the storage electrode 31. Therefore, the solid-state imaging device 1 </ b> A can perform high-speed reading equivalent to that of the existing CMOS sensor using the storage electrode 31 having a size larger than that of the solid-state imaging device 1.
The in-plane of the pixel 10 is a plane perpendicular to the stacking direction of the pixels 10. Further, the stacking direction of the pixels 10 is a direction in which the layers of the pixels 10 are stacked. That is, the stacking direction of the pixels 10 is a direction perpendicular to the surface of the semiconductor substrate unit 20.

Next, a manufacturing method of the solid-state imaging device 1A will be described. The manufacturing method of the solid-state imaging device 1A may be the same as the manufacturing method of the solid-state imaging device 1 of the first embodiment except that the collecting electrode 33a is formed and the contact plug 34a is formed. Therefore, the description of the manufacturing method of the solid-state imaging device 1A is omitted for the same components as the manufacturing method of the solid-state imaging device 1 of the first embodiment.
The contact plugs 34 a are formed as a plurality of contact plugs 34 a that penetrate the interlayer insulating film 30 after the interlayer insulating film 30 is stacked.
The collection electrode 33a is formed on the interlayer insulating film 30 by the same method as the collection electrode 33 of the solid-state imaging device 1 of the first embodiment except that the collection electrode 33a has a shape surrounding the storage electrode 31. The Through the steps as described above, the solid-state imaging device 1A can be manufactured.

According to the modification of the first embodiment described above, it is possible to suppress the remaining transfer of signal charges as in the first embodiment. Furthermore, according to the modification of the first embodiment, the solid-state imaging device 1 </ b> A is formed between the storage electrode 31 and the collection electrode 33 a by forming the collection electrode 33 a so as to surround the storage electrode 31. The area where the fringe electric field is generated can be made larger than that of the solid-state imaging device 1. Therefore, the solid-state imaging device 1A can transfer the signal charge accumulated in the signal charge accumulation area to the collection electrode 33a more efficiently.
That is, the solid-state imaging device 1A can transfer more signal charges to the collection electrode 33a within the same transfer time. Therefore, the solid-state imaging device 1A can accumulate more signal charges in the signal charge accumulation area, and can have a wider dynamic range. Further, L ₂ in the above equation (5) can be regarded as half of the minimum dimension between the edges of the storage electrode 31 of the solid-state imaging device 1A. Therefore, the solid-state imaging device 1A increases the size of the storage electrode 31 more. It becomes possible to take large.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 13 is a cross-sectional view schematically showing a cross-sectional structure corresponding to one pixel 10B included in the solid-state imaging device 1B according to the second embodiment.

The pixel 10B according to the second embodiment may have the same configuration as the pixel 10 according to the first embodiment, except for the following two points. The first point is that the pixel 10B has a storage electrode 31a, an insulating film 32a, a collection electrode 33b, and a contact plug 34b in place of the storage electrode 31, the insulating film 32, the collection electrode 33, the contact plug 34, and the semiconductor layer 35. And a semiconductor layer 35a. The second point is that the pixel 10 </ b> B further includes a barrier film 36.
Of the constituent elements of the pixel 10B shown in FIG. 13, the same portions as those of the pixel 10 shown in FIG. 3 are denoted by the same reference numerals as those in FIG.

  As shown in FIG. 13, in the pixel 10B of the solid-state imaging device 1B, the storage electrode 31a and the insulating film 32a are disposed between the interlayer insulating film 30 and the semiconductor layer 35a, and the collecting electrode 33b is formed of the semiconductor layer 35a. Placed on top.

  The storage electrode 31a and the insulating film 32a are patterned for each pixel. The storage electrode 31 a is formed on the interlayer insulating film 30. As shown in FIG. 13, the storage electrode 31a may be formed up to the end portion of the light receiving surface of the pixel 10B in plan view.

  The insulating film 32a is formed on the storage electrode 31a. As shown in FIG. 13, the insulating film 32a may be formed up to the end of the light receiving surface of the pixel 10B in plan view.

The collection electrode 33b is formed on the semiconductor layer 35a. That is, the collection electrode 33b is formed closer to the light receiving surface side (upper electrode 42 side) of the pixel 10B than the storage electrode 31a.
A part of the collection electrode 33b and a part of the storage electrode 31a are configured to be stacked with the semiconductor layer 35a interposed therebetween. That is, a part of the collecting electrode 33b and a part of the storage electrode 31a are configured to face each other with the semiconductor layer 35a interposed therebetween.
It is desirable that a part of the collecting electrode 33b and a part of the storage electrode 31a are formed so as to partially overlap in plan view. By adopting such a configuration, compared to a case where a part of the collection electrode 33b and a part of the storage electrode 31a do not overlap in the plan view between the collection electrode 33b and the storage electrode 31a. A strong fringe electric field can be generated.

  The contact plug 34 b penetrates the interlayer insulating film 30 and the semiconductor layer 35 a and electrically connects the collecting electrode 33 b and the FD portion 22 of the pixel circuit portion 21.

The semiconductor layer 35a is formed so as to cover the entire surface of the storage electrode 31a and the insulating film 32a. A part of the semiconductor layer 35a is disposed so as to be in contact with a part of the collecting electrode 33b.
The thickness of the semiconductor layer 35a is formed to be larger than the sum of the thickness of the storage electrode 31a and the thickness of the insulating film 32a. As a result, the semiconductor layer 35a is formed as a continuous layer even at the step portion at the end of the storage electrode 31a.

The semiconductor layer 35a may be patterned for each pixel. In this case, the semiconductor layer 35a may be formed by performing photolithography and etching after sputtering an inorganic material. The semiconductor layer 35a may be formed by patterning by screen printing using an organic semiconductor material. This prevents charge exchange between the collecting electrodes 33b of the adjacent pixels 10B in the solid-state imaging device 1B.
The semiconductor layer 35a may be formed on the entire surface of the pixel array 2 of the solid-state imaging device 1B (that is, the entire surface of the sensor array surface). In this case, the semiconductor layer 35a may be formed by sputtering an inorganic material. The semiconductor layer 35a may be formed by applying an organic semiconductor material by a meniscus method. When signal charges are accumulated, a potential well is formed in the signal charge accumulation area by a bias voltage applied to the accumulation electrode 31. Therefore, even when the semiconductor layer 35a is formed on the entire surface of the pixel array 2 of the solid-state imaging device 1B, it is possible to suppress exchange of signal charges accumulated via the semiconductor layer 35a between adjacent pixels 10B. Is done.

The barrier film 36 is one specific example of the third insulating layer. The barrier film 36 is formed on the collecting electrode 33b. The barrier film 36 suppresses the occurrence of charge exchange between the collection electrode 33b and the photoelectric conversion layer 41. The exchange of charges is, for example, that charges are directly injected from the photoelectric conversion layer 41 to the collecting electrode 33b. The barrier film 36 is a so-called barrier film in the case where the photoelectric conversion layer 41 is formed of an organic semiconductor, for example.
The material used for the barrier film 36 is preferably a material excellent in workability. Further, the barrier film 36 may be formed of a dielectric material having high insulation. The barrier film 36 desirably transmits 80% or more of light in a specific wavelength region. The light in the specific wavelength region is, for example, red (R) region light, green (G) region light, blue (B) region light, visible light region light, or the like. When the pixel 10 includes a plurality of photoelectric conversion units, if the barrier film 36 absorbs light irradiated at the time of exposure, the amount of light received by a photoelectric conversion unit other than the photoelectric conversion layer 41 decreases. Therefore, there is a problem that the apparent sensitivity of the pixel 10 is lowered. In the present embodiment, the barrier film 36 is configured to transmit light, so that the occurrence of such a problem is suppressed.
When the photoelectric conversion layer 41 is formed of an organic semiconductor, the barrier film 36 is formed by using a Schottky barrier formed at the contact interface between the organic semiconductor of the photoelectric conversion layer 41 and the collection electrode 33b. Also good.
Note that the storage electrode 31a, the insulating film 32a, the collection electrode 33b, and the semiconductor layer 35a desirably transmit 80% or more of light in a specific wavelength region, as in the first embodiment. Other components may be the same as those of the pixel 10 of the first embodiment shown in FIG.

It is desirable that the pixel 10B is configured to satisfy the relationship of the above-described formula (5). In the configuration pixel 10B as described above, L _B in the above equation (3) and (4) corresponds to the spacing of the collecting electrode 33b and the storage electrode 31a, corresponding to the thickness of the semiconductor layer 35a . That is, L ₁ in the above formulas (5) and (6) corresponds to the thickness of the semiconductor layer 35a.
When the pixel size is Full-HD and the frame frequency f is 60 Hz, in order to perform high-speed reading equivalent to that of the existing CMOS sensor, the solid-state imaging device 1B performs signal reading operation from each pixel 8.6. Must be done within microseconds. Minimum dimension _{L 2} between the edges of the storage electrode 31a of each pixel 10B is 1 [mu] m, the semiconductor layer 35a is formed using IGZO, if the mobility of the semiconductor layer 35a is ^{15cm 2 / (V · sec)} , The thickness of the semiconductor layer 35a is desirably 115 nm or less.

  Next, a method for manufacturing the solid-state imaging device 1B according to the second embodiment will be described with reference to FIGS. 14-17 is a figure which shows the manufacturing method of the solid-state imaging device 1B which concerns on 2nd Embodiment. In the manufacturing method of the solid-state imaging device 1B of the second embodiment, the configuration of the formation process of the storage electrode 31a, the insulating film 32a, the collecting electrode 33b, the contact plug 34b, the semiconductor layer 35a, and the barrier film 36 is the first implementation. This is different from the manufacturing method of the solid-state imaging device 1 according to the embodiment, and other configurations are the same as those of the first embodiment. Accordingly, in the manufacturing method of the solid-state imaging device 1B of the second embodiment, the same components as those of the manufacturing method of the solid-state imaging device 1 of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  First, as illustrated in FIG. 14, the semiconductor substrate unit 20, the pixel circuit unit 21, and the interlayer insulating film 30 are formed in the same manner as the formation process of the solid-state imaging device 1 of the first embodiment described above. Next, the storage electrode 31 a and the insulating film 32 a are formed on the interlayer insulating film 30. The storage electrode 31a and the insulating film 32a may be formed by performing photolithography and etching after being stacked over the entire region to be the pixel 10. Next, the semiconductor layer 35a is formed on the storage electrode 31a and the insulating film 32a. Next, a contact plug 34b penetrating the interlayer insulating film 30 and the semiconductor layer 35a is formed. The contact plug 34b is connected to the FD portion 22 described above.

  Next, as shown in FIG. 15, the collecting electrode 33b and the barrier film 36 are formed on the semiconductor layer 35a. The collection electrode 33 b and the barrier film 36 may be formed by performing photolithography and etching after being stacked over the entire region to be the pixel 10. As shown in FIG. 16, a part of the collecting electrode 33b and a part of the storage electrode 31a are stacked so as to sandwich the semiconductor layer 35a.

  Next, as illustrated in FIG. 17, the photoelectric conversion layer 41 is formed on the collection electrode 33 b, the barrier film 36, and the semiconductor layer 35 a, and then the upper electrode 42 is formed on the photoelectric conversion layer 41. Through the steps as described above, the solid-state imaging device 1B can be manufactured.

According to the second embodiment described above, signal transfer residuals can be suppressed as in the first embodiment. Furthermore, according to the second embodiment, L ₁ in the above equation (5) corresponds to the distance between the collection electrode 33b and the storage electrode 31a, and corresponds to the thickness of the semiconductor layer 35a. Therefore, the solid-state imaging device 1B can adjust the distance between the collection electrode 33b and the storage electrode 31a (L ₁ in the above formula (5)) by adjusting the thickness of the semiconductor layer 35a. Therefore, the solid-state imaging device 1B can more easily adjust the interval between the collection electrode 33b and the storage electrode 31a than when the collection electrode and the storage electrode are formed in the same plane using lithography or the like. It becomes possible.
In the solid-state imaging device 1B of the second embodiment, the distance between the collection electrode 33b and the storage electrode 31a is not in the plane of the pixel 10B but in the thickness direction (stacking direction of the pixels 10B). The area can be further reduced. That is, the solid-state imaging device 1B can improve the integration degree of elements.

Next, a modification of the second embodiment will be described. In the solid-state imaging device 1B of the second embodiment, the collection electrode 33b is formed to face one end portion of the storage electrode 31a. However, the collection electrode 33b is a storage electrode in plan view. It may be formed so as to surround the periphery of 31a. As a result, an area where a fringe electric field is generated between the storage electrode 31a and the collection electrode 33b can be made larger. Therefore, the solid-state imaging device 1B can more efficiently transfer the signal charge accumulated in the signal charge accumulation area to the collection electrode 33b.
That is, the solid-state imaging device 1B can transfer more signal charges to the collection electrode 33b within the same transfer time. Therefore, the solid-state imaging device 1B can accumulate more signal charges in the signal charge accumulation area, and can have a wider dynamic range.

(Third embodiment)
Next, a third embodiment will be described. FIG. 18 is a plan view schematically showing a structure corresponding to one pixel 10C included in the solid-state imaging device 1C according to the third embodiment.

The pixel 10C according to the third embodiment is the first implementation except that the storage electrode 31b, the insulating film 32b, and the collection electrode 33c are replaced with the storage electrode 31, the insulation film 32, and the collection electrode 33. The same configuration as that of the pixel 10 according to the embodiment may be used.
Of the constituent elements of the pixel 10C shown in FIG. 18, the same portions as those of the pixel 10 shown in FIG. 3 are denoted by the same reference numerals as those in FIG.

The storage electrode 31 b is formed between the interlayer insulating film 30 and the semiconductor layer 35. The storage electrode 31b is configured to have a plurality of substantially rectangular portions in one pixel 10C. The plurality of substantially rectangular portions of the storage electrode 31b may be configured to be parallel to each other. The storage electrode 31b may be configured to have a so-called comb shape. As a result, the solid-state imaging device 1C can have a larger peripheral length of the storage electrode 31b than when the storage electrode 31b has a rectangular shape. That is, the solid-state imaging device 1C can increase the area where the storage electrode 31b and the collection electrode 33c face each other.
The insulating film 32b is formed on the storage electrode 31b. The insulating film 32b is formed so as to cover the entire surface of the storage electrode 31b. The semiconductor layer 35 and the storage electrode 31b are electrically insulated by the insulating film 32b.
The collecting electrode 33 c is formed between the interlayer insulating film 30 and the semiconductor layer 35. A part of the collecting electrode 33 c is formed in contact with the semiconductor layer 35. The collection electrode 33c is configured to have a plurality of substantially rectangular portions in one pixel 10C. The plurality of substantially rectangular portions of the collecting electrode 33c may be configured to be parallel to each other. Further, the plurality of substantially rectangular portions of the collecting electrode 33c may be connected by the rectangular portions so as to form a continuous surface in the same plane. The collection electrode 33c may be configured to have a so-called comb shape.

The plurality of substantially rectangular portions of the storage electrode 31b and the plurality of substantially rectangular portions of the collecting electrode 33c are arranged to face each other with the semiconductor layer 35 interposed therebetween.
Note that the storage electrode 31b, the insulating film 32b, and the collection electrode 33c desirably transmit 80% or more of light in a specific wavelength region, as in the first embodiment.
Other components may be the same as those of the pixel 10 of the first embodiment shown in FIG.

  According to the third embodiment described above, signal charge transfer residue can be suppressed as in the first embodiment. Furthermore, according to the third embodiment, the solid-state imaging device 1C can take a larger area in which a fringe electric field is generated between the storage electrode 31a and the collection electrode 33b. Therefore, the solid-state imaging device 1C can more efficiently transfer the signal charge accumulated in the signal charge accumulation area to the collection electrode 33c. That is, the solid-state imaging device 1C can transfer more signal charges to the collecting electrode 33c within the same transfer time. Therefore, the solid-state imaging device 1C can accumulate more signal charges in the signal charge accumulation area, and can have a wider dynamic range.

Next, a modification of the third embodiment will be described. In the solid-state imaging device 1C of the third embodiment, the collection electrode 33c is formed between the interlayer insulating film 30 and the semiconductor layer 35. However, the collection electrode 33c is formed on the semiconductor layer 35. May be.
In this case, a barrier film 36 may be further formed on the collecting electrode 33c. The barrier film 36 suppresses the occurrence of charge exchange between the collection electrode 33c and the photoelectric conversion layer 41. The barrier film 36 may be formed of a highly insulating dielectric material. When the photoelectric conversion layer 41 is formed of an organic semiconductor, the barrier film 36 is formed by using a Schottky barrier formed at the contact interface between the organic semiconductor of the photoelectric conversion layer 41 and the collection electrode 33b. May be.

According to the modification of the third embodiment configured as described above, L ₁ in the above equation (5) corresponds to the interval between the collection electrode 33 c and the storage electrode 31 b, and is equal to the thickness of the semiconductor layer 35. Correspond. Therefore, the solid-state imaging device 1 </ b> C configured as described above adjusts the distance between the collection electrode 33 c and the storage electrode 31 b (L ₁ in the above formula (5)) by adjusting the thickness of the semiconductor layer 35. It is possible. Therefore, the distance between the collection electrode 33c and the storage electrode 31b can be adjusted more easily than when the collection electrode 33c and the storage electrode 31b are formed in the same plane using lithography or the like. .

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 19 is a plan view schematically showing the arrangement of the pixels 10D in the pixel array 2D included in the solid-state imaging device 1D according to the fourth embodiment.

The solid-state imaging device 1D according to the fourth embodiment is the same as the solid-state imaging device 1 according to the first embodiment, except that the collection electrode 33d is shared by the plurality of pixels 10D of the pixel array 2D. The structure of may be sufficient.
In the specific example shown in FIG. 19, the collection electrode 33d is shared by four pixels 10D adjacent to each other in the column direction in the pixel array 2D. The number of the plurality of pixels 10D sharing the collection electrode 33d is not limited to four.
Further, in the solid-state imaging device 1D, a plurality of pixels 10D sharing the collection electrode 33d may share one contact plug 34 and one FD portion 22.
The semiconductor layer 35 is patterned for each pixel. A photoelectric conversion layer 41 is formed between the semiconductor layers 35 of the pixels 10D adjacent to each other. Accordingly, the exchange of signal charges between the adjacent pixels 10D via the semiconductor layer 35 between the plurality of pixels 10D sharing the collection electrode 33d is suppressed.
In the pixel array 2D, the distance between the storage electrodes 31 of the two pixels 10D adjacent to each other in the row direction is larger than the distance between the storage electrode 31 and the collection electrode 33d in one pixel 10D. It may be configured.
Other components may be the same as those of the solid-state imaging device 1 according to the first embodiment shown in FIGS.

  According to the fourth embodiment described above, signal charge transfer residue can be suppressed as in the first embodiment. Furthermore, according to the fourth embodiment, the solid-state imaging device 1D reduces the area of the collection electrode 33d in each pixel 10D by adopting a configuration in which a plurality of adjacent pixels 10D share the collection electrode 33d. can do. Therefore, the area ratio of the collection electrode 33d in the pixel 10D can be reduced, and the area ratio of the storage electrode 31 can be increased. Therefore, the number of signal charges that can be generated by photoelectric conversion can be increased for the same pixel size. Further, it is possible to increase the number of signal charges that can be accumulated for the same pixel size. That is, more signal charges can be read out for the same pixel size. That is, the efficiency of the pixel can be improved.

  In the solid-state imaging device 1D, when a plurality of pixels 10D that share the collection electrode 33d share one contact plug 34 and one FD portion 22, the number of contact plugs 34 and FD portions 22 that are configured is reduced. Can do. Therefore, the solid-state imaging device 1D can save the area of the contact plug 34 and the FD portion 22 whose configurations are omitted, and can increase the degree of integration.

Next, a modification of the fourth embodiment will be described.
FIG. 20 is a plan view schematically showing the arrangement of the pixels 10E in the pixel array 2E provided in the solid-state imaging device 1E according to the modification of the fourth embodiment.
A solid-state imaging device 1E according to a modification of the fourth embodiment shown in FIG. 20 is similar to the solid-state imaging device 1D according to the fourth embodiment, except that a collecting electrode 33e is provided instead of the collecting electrode 33d. It can be set as the same structure. Therefore, among the components of the solid-state imaging device 1E shown in FIG. 20, the same components as those of the solid-state imaging device 1D shown in FIG. 19 are denoted by the same reference numerals as those in FIG.

The collection electrode 33e is the same as the collection electrode 33d in the solid-state imaging device 1D except that the collection electrode 33e is formed so as to surround the storage electrode 31.
The collection electrode 33e only needs to be electrically connected to the collection electrodes 33e of the plurality of pixels 10E adjacent to each other in the column direction. The collection electrode 33e is not limited to the shape shown in the specific example of FIG.

  The collection electrode 33d may be formed on the semiconductor layer 35 similarly to the collection electrode 33b of the pixel 10B shown in FIG. At this time, a part of the collecting electrode 33d and a part of the storage electrode 31 may be stacked with the semiconductor layer 35 interposed therebetween. Furthermore, it is desirable that a part of the collecting electrode 33d and a part of the storage electrode 31 are formed so as to partially overlap in plan view.

  According to the modification of the fourth embodiment configured as described above, the solid-state imaging device 1E has a larger area in which a fringe electric field is generated between the storage electrode 31 and the collecting electrode 33e than the solid-state imaging device 1D. It is possible to take. Therefore, the solid-state imaging device 1E is accumulated in the signal charge accumulation area as compared with the solid-state imaging device 1D having the same configuration except that the shape of the collecting electrode 33e is a shape surrounding the storage electrode 31. It becomes possible to transfer the signal charge to the collecting electrode 33e more efficiently. That is, the solid-state imaging device 1E can transfer more signal charges to the collection electrode 33e within the same transfer time. Therefore, the solid-state imaging device 1E can accumulate more signal charges in the signal charge accumulation area, and can have a wider dynamic range.

  In each of the above embodiments, the solid-state imaging device is a CMOS image sensor, but may be a CCD image sensor.

  According to at least one embodiment described above, the semiconductor layer is formed so as to cover the entire surface of the storage electrode and the second insulating layer. The semiconductor layer accumulates and holds the signal charge generated by the photoelectric conversion layer, and transfers the accumulated signal charge to the collecting electrode. For this reason, it is possible to suppress the remaining transfer of signal charges.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1, 1A, 1B, 1D, 1E ... Solid-state imaging device, 2 ... Pixel array, 3 ... Vertical scanning part, 4 ... Horizontal scanning part, 5 ... Control part, 3-A1-3-An ... Selection signal line, 3- B1-3-Bn ... control signal lines, 4-1-4-m ... pixel signal lines, 10, 10A, 10B, 10C, 10D, 10E ... pixels, 20 ... semiconductor substrate part, 21 ... pixel circuit part, 22 ... FD portion, 23 ... impurity diffusion region, 24 ... conductive layer, 30 ... interlayer insulating film, 31, 31a, 31b ... storage electrode, 32, 32a ... insulating film, 33, 33a, 33b, 33c, 33d, 33e ... collecting Electrode, 34, 34a, 34b ... contact plug, 35, 35a ... semiconductor layer, 36 ... barrier film, 41 ... photoelectric conversion layer, 42 ... upper electrode

Claims (10)

A storage electrode formed on the first insulating layer;
A second insulating layer formed on the storage electrode;
A semiconductor layer formed to cover the storage electrode and the second insulating layer;
A collecting electrode formed in contact with the semiconductor layer and formed away from the storage electrode;
A photoelectric conversion layer formed on the semiconductor layer;
An upper electrode formed on the photoelectric conversion layer;
An imaging device comprising: And the mobility mu _n the semiconductor layer, an area of the storage electrode and S _C, the minimum dimension between the edges of the storage electrode and L _2, the distance between the collecting electrode and the storage electrode and L ₁ The capacitance per unit area of the capacitor formed by the semiconductor layer, the second insulating layer, and the storage electrode is C _ox , the frame frequency of the image sensor is f, and the number of rows of the sensor array is Line. When the number of remaining signal charges is Q and the elementary charge is q,

The imaging device according to claim 1, wherein the relationship is satisfied. In the collecting electrode, a part of the collecting electrode and a part of the storage electrode are stacked with the semiconductor layer interposed therebetween,
The imaging device according to claim 1 or 2. The collection electrode has a shape surrounding the storage electrode.
The imaging device according to any one of claims 1 to 3. The collection electrode has a plurality of substantially rectangular portions, and the plurality of substantially rectangular portions of the collection electrode are arranged to be parallel to each other,
The storage electrode has a plurality of substantially rectangular portions, and the plurality of substantially rectangular portions of the storage electrode are arranged in parallel to each other,
The plurality of substantially rectangular portions of the collection electrode and the plurality of substantially rectangular portions of the storage electrode are arranged to face each other with the semiconductor layer interposed therebetween,
The imaging device according to any one of claims 1 to 4. The semiconductor layer is formed of a semiconductor containing at least one of silicon carbide, IGZO, diamond, graphene, carbon nanotubes, a condensed polycyclic hydrocarbon compound, and a condensed heterocyclic compound;
The imaging device according to any one of claims 1 to 5. The collection electrode is a film containing any one of ZnO, ITO (Indium-Tin-Oxide) and graphene,
The imaging device according to any one of claims 1 to 6. The storage electrode is a film containing any one of ZnO, ITO, and graphene;
The imaging device according to any one of claims 1 to 7. The semiconductor layer transmits 80% or more of light having a wavelength of 400 nm to 750 nm;
The imaging device according to any one of claims 1 to 8.   A solid-state imaging device including the imaging device according to claim 1.

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