JP2016062985A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which inhibits poor connection with laminated another semiconductor device and simplifies a constitution of a mold for forming an encapsulation resin layer.SOLUTION: A semiconductor device manufacturing method comprises: a process of preparing a wiring board 2 which has a first surface, a second surface opposite to the first surface and a plurality of lands 8b, 9b formed on the second surface; a process of mounting a first semiconductor chip 12 on the first surface of the wiring board 2; a process of forming a first encapsulation resin layer 16 on the first surface of the wiring board 2 so as to cover the first semiconductor chip 12; a process of mounting a second semiconductor chip 18 on the second surface of the wiring board after the process of forming the first encapsulation resin layer 16; and a process of forming a second encapsulation resin layer 23 on the second surface of the wiring board 2 so as to cover the second semiconductor chip 18.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In order to increase the density and functionality of a semiconductor device, there is a semiconductor device having a PoP (Package on Package) structure in which a plurality of semiconductor packages are stacked and mounted. For example, FIG. 1 of Patent Document 1 includes a lower package in which a controller chip is mounted on a wiring board and an upper package in which two semiconductor chips are stacked and mounted on another wiring board. Discloses a semiconductor device having a PoP structure in which upper packages are stacked and mounted via solder balls. Since the upper package in the semiconductor device described in Patent Document 1 has a configuration in which only the upper surface on which two semiconductor chips in another wiring substrate are stacked and mounted is covered with the sealing body, the sealing body is cured. It warps so as to be convex on the lower surface side by shrinkage. For this reason, in the semiconductor device described in Patent Document 1, there is a possibility of causing a connection failure such that the solder balls connected to the upper package are not partially connected to the lower package.

  Further, in Patent Document 2, in order to suppress warpage of the semiconductor device, the upper and lower surfaces of the wiring board on which the semiconductor chip is mounted on both sides or one side are covered with a sealing body, and the sealing body on one side of the wiring board is penetrated. A semiconductor device in which solder balls are arranged via a conductor layer is disclosed. In Patent Document 2, the sealing bodies on the upper and lower sides of the wiring board are formed simultaneously.

JP 2013-125765 A JP 2010-103348 A

  The following analysis is given by the inventor.

  However, in Patent Document 2, since the amount of the sealing body on the semiconductor chip side is larger than that on the conductor layer side of the wiring substrate, the sealing body on the semiconductor chip side is harder than the sealing body on the conductor layer side. There is a possibility that the shrinkage becomes large and warps so as to protrude toward the conductor layer side of the semiconductor device, resulting in a connection failure such that the solder balls connected to the conductor layer are not partially connected to the lower package. Further, in Patent Document 2, when forming a sealing body, in order to inject a sealing resin for the sealing body into the respective cavities of the upper mold and the lower mold for sandwiching the wiring substrate, There is a possibility that the structure of the mold is complicated, for example, it is necessary to arrange a plunger in each cavity of the lower mold.

  A method of manufacturing a semiconductor device according to one aspect includes a step of preparing a wiring board having a first surface, a second surface facing the first surface, and a plurality of lands formed on the second surface; Mounting a first semiconductor chip on the first surface of the wiring board; forming a first sealing resin layer on the first surface of the wiring board so as to cover the first semiconductor chip; After the step of forming the first sealing resin layer, a step of mounting a second semiconductor chip on the second surface of the wiring substrate; and the first of the wiring substrate so as to cover the second semiconductor chip Forming a second sealing resin layer on the two surfaces.

  According to the one aspect, the warping direction of the wiring board can be warped to be convex toward the first surface side, connection failure with other semiconductor devices to be stacked can be suppressed, and the sealing resin layer is formed The configuration of the mold can be simplified.

1 is a plan view schematically showing a configuration of a semiconductor device according to Embodiment 1. FIG. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1 schematically showing the configuration of the semiconductor device according to the first embodiment. 1 is a cross-sectional view schematically showing a configuration of a stacked semiconductor device including a semiconductor device according to Embodiment 1. FIG. FIG. 5 is a process cross-sectional view schematically showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5 is a process cross-sectional view following FIG. 4 schematically showing the method for manufacturing the semiconductor device according to the first embodiment. 5 is a process cross-sectional view schematically showing a molding process in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 7 is a process cross-sectional view following FIG. 6 schematically showing a molding process in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view schematically showing a configuration of a semiconductor device according to a second embodiment. FIG. 10 is a process cross-sectional view schematically showing the manufacturing method of the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view following FIG. 9 schematically illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 11 is a process cross-sectional view following FIG. 10 schematically showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view schematically showing a molding process in the method for manufacturing a semiconductor device according to Embodiment 2. FIG. 13 is a process cross-sectional view following FIG. 12 schematically illustrating a molding process in the method for manufacturing a semiconductor device according to the second embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. Note that, in the present application, where reference numerals are attached to the drawings, these are only for the purpose of helping understanding, and are not intended to be limited to the illustrated embodiments.

[Embodiment 1]
A semiconductor device according to Embodiment 1 will be described with reference to the drawings. FIG. 1 is a plan view schematically showing the configuration of the semiconductor device according to the first embodiment. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1 schematically showing the configuration of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view schematically showing the configuration of the stacked semiconductor device including the semiconductor device according to the first embodiment.

  The semiconductor device 1 according to the first embodiment is an upper package stacked on a semiconductor device 26 serving as a lower package (see FIG. 3). In the semiconductor device 1, the first semiconductor chip 12 is mounted on the upper surface of the wiring substrate 2 (the surface opposite to the conductor posts 10 and 11; the upper surface in FIG. 2), and the lower surface (conductor post) of the wiring substrate 2. The second semiconductor chip 18 is mounted on a surface on the 10, 11 side; a lower surface in FIG. The semiconductor device 1 includes a wiring board 2, a first conductor post 10, a second conductor post 11, a first semiconductor chip 12, a bump electrode 13, a solder layer 14, a resin filling member 15, a first sealing member. It has a stop resin layer 16, a second semiconductor chip 18, a bump electrode 19, a solder layer 20, a resin filling member 21, a second sealing resin layer 23, and solder balls 24 and 25.

  The wiring board 2 is a board in which wiring patterns 8 and 9 are formed on both surfaces of the insulating base 3. For the wiring board 2, for example, a substantially rectangular plate having a thickness of about 90 μm can be used. The wiring board 2 is formed from the upper surface (surface opposite to the conductor posts 10 and 11 side; the upper surface in FIG. 2) to the lower surface (conductor post 10 and 11 side surface) of the insulating base 3 (for example, glass epoxy substrate). A plurality of second wiring patterns 9 (having a plurality of first wiring patterns 8 (conductors such as Cu) formed over the lower surface in FIG. 2) and formed on the lower surface of the insulating substrate 3; A conductor such as Cu).

  The first wiring pattern 8 includes a first connection pad 8 a disposed on the upper surface of the insulating substrate 3 and a first land 8 b disposed on the lower surface of the insulating substrate 3. The first connection pad 8 a is electrically connected to the electrode pad 12 a of the first semiconductor chip 12 through the bump electrode 13 and the solder layer 14. The first land 8 b is connected to the first conductor post 10. The first wiring pattern 8 electrically connects the corresponding electrode pad 12 a and the first conductor post 10. The first land 8b is disposed outside the second land 9b along the four sides of the wiring substrate 2, for example, in a region outside the region where the second semiconductor chip 18 is disposed. Ni / Au plating (not shown) may be formed on the surfaces of the first connection pads 8a and the first lands 8b.

  The second wiring pattern 9 includes a second connection pad 9 a disposed on the lower surface of the insulating substrate 3 and a second land 9 b disposed on the lower surface of the insulating substrate 3. The second connection pad 9 a is electrically connected to the electrode pad 18 a of the second semiconductor chip 18 through the bump electrode 19 and the solder layer 20. The second land 9 b is connected to the second conductor post 11. The second wiring pattern 9 electrically connects the corresponding electrode pad 18 a and the second conductor post 11. The second land 9b is disposed in the region outside the region where the second semiconductor chip 18 is disposed, for example, along the four sides of the wiring substrate 2 and inside the first land 8b. Ni / Au plating (not shown) may be formed on the surfaces of the second connection pads 9a and the second lands 9b.

  The solder resist film 4 is an insulating film that protects the first wiring pattern 8 disposed at a predetermined position on the upper surface of the insulating base 3. The solder resist film 4 covers part of the insulating base material 3 and the first wiring pattern 8 on the upper surface of the insulating base material 3. The solder resist film 4 has an opening 4 a in the central region of the wiring board 2. A plurality of first connection pads 8a are arranged in the opening 4a.

  The solder resist film 5 is an insulating film that protects the first wiring pattern 8 and the second wiring pattern 9 disposed at predetermined positions on the lower surface of the insulating base material 3. The solder resist film 5 covers a part of each of the insulating base material 3, the first wiring pattern 8, and the second wiring pattern 9 on the lower surface of the insulating base material 3. The solder resist film 5 has an opening 5 a in a region near the center of the wiring board 2. A plurality of second connection pads 9a are arranged in the opening 5a.

  It should be noted that the solder resist films 4 and 5 are formed so that the thickness thereof is thinner than the surrounding parts at the part arranged in the region overlapping with the semiconductor chips 12 and 18 instead of forming the openings 4a and 5a. It may be formed.

  The first semiconductor chip 12 is a chip having an electronic circuit made of a semiconductor. For example, a DRAM (Dynamic Random Access Memory) memory chip can be used as the first semiconductor chip 12. The first semiconductor chip 12 is arranged in the central region of the upper surface of the wiring board 2 (the surface opposite to the conductor posts 10 and 11 side; the upper surface in FIG. 2). For example, the first semiconductor chip 12 is electrically connected to a predetermined memory circuit (not shown) built in the first semiconductor chip 12 on one surface of the substantially rectangular silicon substrate (surface on the wiring substrate 2 side). A plurality of electrode pads 12a are formed. The plurality of electrode pads 12 a are arranged and arranged along two opposing short sides of the first semiconductor chip 12. On each electrode pad 12a, a bump electrode 13 is formed so as to protrude from one surface of the first semiconductor chip 12 (surface on the wiring board 2 side). As the bump electrode 13, for example, a pillar made of Cu can be used. Each bump electrode 13 is bonded to and electrically connected to the corresponding first connection pad 8a through the solder layer.

  The resin filling member 15 is a member made of resin filled in a gap between the first semiconductor chip 12 and the wiring substrate 2. For the resin filling member 15, for example, UF (Underfill), NCF (Non-Conductive Film), or NCP (Non-conductive Paste) can be used.

  The first sealing resin layer 16 seals the first semiconductor chip 12 by covering one surface (the upper surface, the surface on the first semiconductor chip 12 side, the first surface) of the wiring substrate 2 including the first semiconductor chip 12. Resin. For the first sealing resin layer 16, for example, a thermosetting epoxy resin or the like can be used.

  The second semiconductor chip 18 is a chip having an electronic circuit composed of a semiconductor. As the second semiconductor chip 18, for example, a DRAM memory chip can be used, and the same memory chip as the first semiconductor chip 12 can be used. The second semiconductor chip 18 is disposed in the central region of the lower surface of the wiring board 2 (the surface on the conductor posts 10 and 11 side; the lower surface in FIG. 2). As shown in FIG. 1, the second semiconductor chip 18 is arranged in a state of being rotated by approximately 90 ° with respect to the first semiconductor chip 12. For example, the second semiconductor chip 18 is electrically connected to a predetermined memory circuit (not shown) built in the second semiconductor chip 18 on one surface of the substantially rectangular silicon substrate (surface on the wiring substrate 2 side). A plurality of electrode pads 18a are formed. The plurality of electrode pads 18a are arranged along each of two opposing short sides. On each electrode pad 18a, a bump electrode 19 is formed so as to protrude from one surface of the second semiconductor chip 18 (surface on the wiring board 2 side). For example, a pillar made of Cu can be used as the bump electrode 19. Each bump electrode 19 is bonded to and electrically connected to the corresponding second connection pad 9a through the solder layer 20.

  The resin filling member 21 is a member made of resin filled in a gap between the second semiconductor chip 18 and the wiring board 2. For the resin filling member 21, for example, UF, NCF, or NCP can be used.

  The conductor posts 10 and 11 are post-like conductors (on the lands 8b and 9b arranged on the peripheral region of the other surface (the lower surface, the surface on the second semiconductor chip 18 side, the second surface) of the wiring board 2). For example, a member made of Cu). The conductor posts 10 and 11 are formed higher than the mounting height of the second semiconductor chip 18 from the other surface of the wiring board 2.

  The second sealing resin layer 23 seals the first semiconductor chip 12 by covering the other surface (the lower surface, the surface on the second semiconductor chip 18 side, the second surface) of the wiring board 2 including the second semiconductor chip 18. Resin that stops. The second sealing resin layer 23 is formed so as to cover the side surfaces of the conductor posts 10 and 11 and to expose the front end surfaces of the conductor posts 10 and 11. For the second sealing resin layer 23, for example, a thermosetting epoxy resin or the like can be used.

  The solder balls 24 and 25 are external electrodes mounted on the exposed surfaces of the conductor posts 10 and 11.

  The semiconductor device 26 serving as the lower package is mounted with the semiconductor device 1 serving as the upper package. The semiconductor device 26 includes a wiring board 27, solder balls 34, 35, 36, a third semiconductor chip 37, a bump electrode 38, and a resin filling member 39.

  The wiring board 27 is a board in which wiring patterns 31, 32, and 33 are formed on both surfaces of the insulating base material 28. As the wiring board 27, for example, a substantially rectangular plate-shaped substrate can be used. The wiring board 27 is formed from an upper surface (surface on the semiconductor device 1 side; upper surface in FIG. 3) to a lower surface (surface opposite to the semiconductor device 1 side) of the insulating base material 28 (for example, glass epoxy substrate); 3 has a plurality of wiring patterns 31, 32, and 33 (conductors such as Cu).

  The wiring pattern 31 includes connection pads 31 a disposed on the upper surface of the insulating base material 28 and lands 31 b disposed on the lower surface of the insulating base material 28. The connection pad 31a is electrically connected to the electrode pad 37a of the third semiconductor chip 37 via the bump electrode 38. The land 31 b is connected to the solder ball 34. The wiring pattern 31 electrically connects the corresponding electrode pad 37 a and the solder ball 34. The wiring patterns 32 and 33 include lands 32 a and 33 a disposed on the upper surface of the insulating base material 28, and lands 32 b and 33 b disposed on the lower surface of the insulating base material 28. The land 32 a is connected to the solder ball 24. The land 32 b is connected to the solder ball 35. The wiring pattern 32 electrically connects the corresponding solder ball 24 and the solder ball 35. The land 33 a is connected to the solder ball 25. The land 33 b is connected to the solder ball 36. The wiring pattern 33 electrically connects the corresponding solder ball 25 and the solder ball 36.

  The solder resist film 29 is an insulating film that protects the wiring patterns 31, 32, 33 disposed at predetermined positions on the upper surface of the insulating base 28. The solder resist film 29 covers a part of the insulating base material 28 and the wiring patterns 31, 32, 33 on the upper surface of the insulating base material 28. The solder resist film 29 has an opening 29 a in the central region of the wiring board 27. A plurality of connection pads 31a are arranged in the opening 29a. The solder resist film 30 is an insulating film that protects the wiring patterns 31, 32, and 33 disposed at predetermined positions on the lower surface of the insulating base material 28. The solder resist film 30 covers a part of each of the insulating base material 28 and the wiring patterns 31, 32, 33 on the lower surface of the insulating base material 28.

  The third semiconductor chip 37 is a chip having an electronic circuit made of a semiconductor. As the third semiconductor chip 37, for example, a logic chip can be used. The third semiconductor chip 37 is disposed in the central region on the upper surface of the wiring board 27. For example, the third semiconductor chip 37 is electrically connected to a predetermined memory circuit (not shown) built in the third semiconductor chip 37 on one surface (surface on the wiring substrate 2 side) of a substantially rectangular silicon substrate. A plurality of electrode pads 37a are formed. Each electrode pad 37a is joined to and electrically connected to the corresponding connection pad 31a via the bump electrode 38.

  The resin filling member 39 is a member made of resin filled in the gap between the third semiconductor chip 37 and the wiring board 27. For the resin filling member 39, for example, UF, NCF, or NCP can be used.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. 4 and 5 are process cross-sectional views schematically showing the method for manufacturing the semiconductor device according to the first embodiment. 6 and 7 are process cross-sectional views schematically showing a molding process in the method for manufacturing a semiconductor device according to the first embodiment.

  First, a wiring mother board 40 having a plurality of product regions 40a is prepared, and then conductor posts 10 and 11 are formed on the lands 8b and 9b of the wiring mother board 40 (step A1; see FIG. 4A).

  Here, the plurality of product regions 40a are portions to be the wiring substrate 2 shown in FIGS. 1 and 2, and the configuration of each product region 40a is the same as that of the wiring substrate 2 of FIGS. The plurality of product regions 40a of the wiring motherboard 40 are arranged in a matrix, and each of the plurality of product regions 40a is partitioned by a plurality of dicing lines 40b. Further, a frame portion 40 c is formed outside the plurality of product regions 40 a of the wiring mother board 40.

  Next, the first semiconductor chip 12 is placed on the upper surface (surface opposite to the conductor posts 10 and 11 side; the upper surface in FIG. 4) of each product region (40a in FIG. 4A) of the wiring mother board 40. Mounting is performed by flip chip mounting (step A2; see FIG. 4B).

  Here, in step A2 (flip chip mounting process), a first semiconductor chip 12 in which bump electrodes 13 are formed on a plurality of electrode pads 12a is prepared. Step A2 can be performed using a flip chip bonding apparatus (not shown). In addition, a resin filling member 15 (for example, NCF) formed in advance on one surface of the first semiconductor chip 12 (surface on the bump electrode 13 side) can be used. In this case, the conductor posts 10 and 11 of the wiring mother board 40 are disposed in the relief grooves formed on the stage in the flip chip bonding apparatus, so that the other surface (the lower surface, the conductor posts 10, 11 side surface, second surface). Thereafter, the back surface of the first semiconductor chip 12 is held by a bonding tool in a flip chip bonding apparatus, heated to a temperature of about 240 ° C. and a load is applied, and the bump electrodes 13 of the first semiconductor chip 12 are soldered (see FIG. 2, 14; omitted in FIG. 4), the first semiconductor chip 12 is mounted on the product region 40 a of the wiring motherboard 40 by bonding to the first connection pads 8 a of the product region 40 a. At this time, the resin filling member 15 formed on one surface (the surface on the bump electrode 13 side) of the first semiconductor chip 12 is melted, and is formed in the gap between the product region 40 a of the wiring mother board 40 and the first semiconductor chip 12. The resin filling member 15 is filled. Thereafter, the resin filling member 15 is cured by curing at a predetermined temperature (for example, about 150 ° C.).

  The resin-filled member 15 has a wiring mother board 40 and a first wiring after flip chip mounting of the first semiconductor chip 12 instead of NCF formed in advance on one surface of the first semiconductor chip 12 (surface on the bump electrode 13 side). 1 A UF that fills a gap between the semiconductor chip 12 and the semiconductor chip 12 can be used. Further, NCP supplied in advance to the product region 40a of the wiring mother board 40 can be used for the resin filling member 15 instead of NCF, and the NCP and the product region 40a of the wiring mother board 40 are connected to each other by flip chip mounting. The gap between the semiconductor chip 12 and the semiconductor chip 12 may be filled.

  Further, in step A2, the wiring mother board 40 is heated, and the wiring mother board 40 having a higher thermal expansion coefficient than the first semiconductor chip 12 is larger in thermal expansion than the first semiconductor chip 12, and the flip chip mounting is performed. Thereafter, the wiring mother board 40 contracts more than the first semiconductor chip 12 when the temperature returns to room temperature. Since the contraction of the portion of the wiring mother board 40 where the first semiconductor chip 12 is mounted is limited, the wiring mother board 40 protrudes upward (on the first semiconductor chip 12 side) as shown in FIG. Warpage occurs.

  Next, a plurality of product regions 40a mounted on each product region 40a on one surface (upper surface, surface on the first semiconductor chip 12 side, first surface) of each product region (40a in FIG. 4A) of the wiring motherboard 40. A first sealing resin layer 16 that collectively covers the first semiconductor chip 12 is formed (step A3; see FIG. 4C).

  Here, step A3 (molding process) can be performed using a transfer molding apparatus (not shown). The transfer mold apparatus has, for example, a mold die 45 composed of an upper die 43 and a lower die 44 as shown in FIG. A cavity 43 a is formed in the upper mold 43, and a recess 44 a for mounting the wiring mother board 40 is formed in the lower mold 44. Further, in the recess 44 a of the lower mold 44, relief grooves 44 b corresponding to the plurality of conductor posts 10 and 11 are formed. The mold 45 is configured such that a cull (not shown) is formed on the upper mold 43 and molten sealing resin is injected from the cull through the gate 49 into the cavity 43a.

  When using such a transfer mold apparatus, first, the wiring mother board 40 on which the first semiconductor chip 12 is mounted is set in the recess 44a of the lower mold 44 (step B1; see FIG. 6A). At this time, the wiring mother board 40 is disposed in the recess 44a of the lower mold 44 so that the plurality of conductor posts 10 and 11 are accommodated in the escape grooves 44b. Further, since the wiring mother board 40 is thermally expanded by being heated by the mold 45, there is no warping.

  After step B1, the wiring mother board 40 is closed with the upper mold 43 and the lower mold 44, whereby a predetermined amount is provided above one surface (the upper surface, the first semiconductor chip 12 side surface, the first surface) of the wiring mother substrate 40. The cavity 43a, the gate 49, and the air vent 50 are formed (step B2; see FIG. 6B).

  After Step B2, the resin tablet is supplied to the pot (not shown) of the lower mold 44, and the mold resin 45 is heated with a heater (not shown), so that the sealing resin that melts the resin tablet in the pot is obtained. Then, the cavity 43a is filled by injecting into the cavity 43a from the gate 49 through a cull with a plunger (not shown), and then molded at a predetermined temperature (for example, 175 ° C.) to thermally cure the sealing resin. Thus, the semi-cured first sealing resin layer 16 filled with the sealing resin in the cavity 43a is formed (step B3; see FIG. 6C). Thereafter, the mold closing with the mold die 45 is released, the wiring mother board 40 is taken out from the mold die 45, and then the first sealing resin layer 16 is broken with the gate 49, and the wiring mother board 40 with the gate 49 is removed. Then, the first sealing resin layer 16 located on the cull (not shown) is removed.

  After Step B3, the wiring mother board 40 is placed in a baking furnace (not shown), and after curing at a predetermined temperature (for example, 175 ° C.) for a predetermined time, the first sealing resin layer 16 is completely cured. (Step B4). In addition, after molding, the wiring mother board 40, the first semiconductor chip 12, and the first sealing resin layer 16 in a thermally expanded state contract by returning to room temperature, and as shown in FIG. Warps in a convex manner on the upper side (first semiconductor chip 12 side).

  Next, the other surface (lower surface, conductor post) of each product region (40a in FIG. 4A) of the wiring mother board 40 (including the first semiconductor chip 12, the resin filling member 15, and the first sealing resin layer 16). The second semiconductor chip 18 is mounted on the 10, 11 side surface, the second surface) by flip chip mounting (step A4; see FIG. 4D).

  Here, in step A4 (flip chip mounting process), a second semiconductor chip 18 having the same configuration as the first semiconductor chip 12 is prepared. Step A4 can be performed using a flip chip bonding apparatus (not shown). In addition, a resin-filled member 21 (for example, NCF) formed in advance on one surface of the second semiconductor chip 18 (surface on the bump electrode 19 side) can be used. In this case, one surface (the upper surface, the surface on the first semiconductor chip 12 side, the first surface) of the wiring mother board 40 is held on the stage in the flip chip bonding apparatus. Thereafter, the back surface of the second semiconductor chip 18 is held by a bonding tool in a flip chip bonding apparatus, heated to a temperature of about 240 ° C. and a load is applied, and the bump electrodes 19 of the second semiconductor chip 18 are soldered (see FIG. 2, which is omitted in FIG. 4, is bonded to the second connection pad 9 a of the product region 40 a, so that the other surface (the lower surface, the surface on the conductor posts 10, 11 side) of the product region 40 a of the wiring mother board 40 The second semiconductor chip 18 is mounted on the second surface. At this time, the warp of the wiring mother board 40 is eliminated by heating. In addition, the resin filling member 21 formed on one surface of the second semiconductor chip 18 (surface on the bump electrode 19 side) is melted, and the gap between the product region 40a of the wiring mother board 40 and the second semiconductor chip 18 is filled with resin. The member 21 is filled. Thereafter, the resin-filled member 21 is cured by curing at a predetermined temperature (for example, about 150 ° C.). At this time, the wiring mother board 40 that has been thermally expanded at the time of flip chip mounting contracts when the temperature returns to room temperature after the flip chip mounting. At this time, since the first semiconductor chip 12 is first mounted and the warp shape on the side where the first sealing resin layer 16 is formed is dominant, the wiring mother board 40 is placed on the upper side as shown in FIG. Warpage occurs so as to protrude toward the first semiconductor chip 12 side.

  Next, each second semiconductor chip 18 and each of the conductor posts 10 and 11 are collectively attached to the other surface (the lower surface, the surface on the side of the conductor posts 10 and 11, the second surface) of each product region 40 a of the wiring mother board 40. A covering second sealing resin layer 23 is formed (step A5; see FIG. 5A).

  Here, step A5 (molding process) can be performed using a transfer molding apparatus (not shown). The transfer mold apparatus has, for example, a mold die 45 composed of an upper die 43 and a lower die 46 as shown in FIG. A cavity 43 a is formed in the upper mold 43, and a recess 46 a for mounting the wiring mother board 40 is formed in the lower mold 46. The mold 45 is configured such that a cull (not shown) is formed on the upper mold 43 and molten sealing resin is injected from the cull through the gate 49 into the cavity 43a.

  When using such a transfer molding apparatus, first, the wiring mother board 40 on which the first semiconductor chip 12 and the second semiconductor chip 18 are mounted is set in the recess 46a of the lower mold 46 (step C1; FIG. 7 ( a)). At this time, the wiring mother board 40 is set with the surface on the first semiconductor chip 12 side facing the concave portion 46 a side of the lower mold 46. Further, since the wiring mother board 40 is thermally expanded by being heated by the mold, warping of the wiring mother board is eliminated.

  After step C1, the wiring mother board 40 is closed with the upper mold 43 and the lower mold 46, so that the other surface of the wiring mother board 40 (the lower surface, the surface on the side of the conductor posts 10, 11 and the second surface) is located above. A cavity 43a, a gate 49, and an air vent 50 having a predetermined size are formed (step C2; see FIG. 7B).

  After Step C2, the resin tablet is supplied to the pot (not shown) of the lower mold 46, and the mold resin 45 is heated with a heater (not shown) to melt the sealing resin that melts the resin tablet in the pot. Then, the cavity 43a is filled by injecting into the cavity 43a from the gate 49 through a cull with a plunger (not shown), and then molded at a predetermined temperature (for example, 175 ° C.) to thermally cure the sealing resin. Thus, the semi-cured second sealing resin layer 23 is formed (step C3; see FIG. 7C). Thereafter, the mold closing in the mold die 45 is released, the wiring mother board 40 is taken out from the mold die 45, and then the second sealing resin layer 23 is broken by the gate 49, and from the wiring mother board 40 to the gate 49 Then, the second sealing resin layer 23 located on the cull (not shown) is removed.

  After Step C3, the wiring mother board 40 is placed in a baking furnace (not shown), and after-curing at a predetermined temperature (for example, 175 ° C.) for a predetermined time, the second sealing resin layer 23 is completely formed. Curing is performed (step C4). In addition, after molding, the wiring motherboard 40, the semiconductor chips 12 and 18, and the sealing resin layers 15 and 21 in a thermally expanded state contract by returning to room temperature. At that time, since the first semiconductor chip 12 is first mounted and the warp shape on the side where the first sealing resin layer 16 is formed is dominant, the wiring mother board 40 is placed on the upper side as shown in FIG. A convex warp is generated on the first semiconductor chip 12 side.

  As described above, the first semiconductor chip 12 is mounted on the one surface (the upper surface, the surface opposite to the conductor posts 10 and 11 side, the first surface) side of the wiring mother board 40, and the wiring is performed so as to cover the first semiconductor chip 12. After forming the first sealing resin layer 16 on one surface of the mother board 40, the second semiconductor chip 18 is placed on the other surface (the lower surface, the surface on the conductor posts 10, 11 side, the second surface) side of the wiring mother substrate 40. By mounting the second sealing resin layer 23 on the other surface of the wiring mother board 40 so as to cover the second semiconductor chip 18 and the plurality of conductor posts 10, 11, the warping direction of the wiring mother board 40 can be changed. The warp can be convex upward (on the first semiconductor chip 12 side). Also, by molding one side at a time, it can be created with an existing molding device by changing the mold without significantly changing the molding device.

  Next, a predetermined amount of the second sealing resin layer 23 on the other surface (the lower surface, the surface on the side of the conductor posts 10 and 11, the second surface) of the wiring mother board 40 is ground by a grindstone of a polishing apparatus (not shown). Then, the tips of the conductor posts 10 and 11 are exposed (step A6; see FIG. 5B). At this time, the second sealing resin layer 23 is left on the second semiconductor chip 18 on the other surface of the wiring mother board 40. In this way, when the second sealing resin layer 23 is ground and the tip portions of the conductor posts 10 and 11 are exposed, the back surface of the second semiconductor chip 18 is made of scraps of the conductor posts 10 and 11 during grinding. It is possible to suppress contamination.

  In step A6, the conductor post 10, the second sealing resin layer 23 formed on the other surface (the lower surface, the surface on the conductor posts 10, 11 side, the second surface) of the wiring mother board 40 is ground. 11, the second sealing resin layer 23 is formed in a state where the film is in close contact with the tip portions of the conductor posts 10, 11 when molding, and the plurality of conductor posts 10, 11 are formed. You may form the 2nd sealing resin layer 23 so that a front-end | tip part may not be covered.

  Next, solder balls 24 and 25 serving as external electrodes are formed on the tips of the plurality of conductor posts 10 and 11 exposed from the second sealing resin layer 23 of the wiring mother board 40 (step A7; FIG. 5 ( c)).

  Here, in step A7 (ball mounting process), using a mounting tool (not shown) in which a plurality of suction holes are formed in accordance with the arrangement of the plurality of conductor posts 10 and 11 of the wiring motherboard 40, for example, Solder balls 24 and 25 made of solder or the like are held in the suction holes of the mounting tool, a flux is transferred and formed on the held solder balls 24 and 25, and the solder balls 24 and 25 are mounted on the plurality of conductor posts 10 and 11 of the wiring mother board 40 at a time. . After mounting the solder balls 24, 25 on all the conductor posts 10, 11, the wiring mother board 40 is reflowed at a predetermined temperature, whereby the solder balls 24 serving as external electrodes on the conductor posts 10, 11 of the wiring mother board 40. 25 are formed.

  Finally, along the dicing line (40b in FIG. 5C) of the wiring mother board 40 on which the solder balls 24 and 25 are formed, the product area (40a in FIG. 5A) is cut and separated ( Step A8; see FIG. 5 (d)).

  Here, in step A8 (substrate dividing step), for example, the first sealing resin layer 16 formed on the wiring mother board 40 is fastened to a dicing tape and fastened by a dicing apparatus (not shown). By rotating and grinding with a rotating dicing blade, full cutting is performed along the dicing line, and then the product area 40a separated from the dicing tape is picked up so that the upper side as shown in FIGS. A warped semiconductor device 1 (upper package) that protrudes toward the first semiconductor chip 12 is obtained.

  The first sealing resin layer 16 that seals one surface (the upper surface, the surface on the first semiconductor chip 12 side, the first surface) of the wiring substrate 2 and the other surface (the lower surface, the second semiconductor chip 18). The amount of warpage can also be adjusted by changing the filler content and the like with the second sealing resin layer 23 that seals the side surface, the second surface), and using resins having different thermal expansion coefficients. For example, the second sealing resin layer 23 formed on the other surface of the wiring substrate 2 has a larger linear expansion coefficient or contraction rate than the first sealing resin layer 16 formed on one surface of the wiring substrate 2. Thus, the amount of warpage can be adjusted in the plus warping direction (the warping direction convex toward the upper side (first semiconductor chip 12 side)).

  According to the first embodiment, in the manufacture of the semiconductor device 1 to be the upper package of PoP, the first semiconductor chip is provided on the one surface (the upper surface, the surface opposite to the conductor posts 10 and 11 side, the first surface) side of the wiring substrate 2. 12 and the first sealing resin layer 16 is formed on one surface of the wiring substrate 2 so as to cover the first semiconductor chip 12, and then the other surface (the lower surface, the surface on the side of the conductor posts 10, 11). The second semiconductor chip 18 is mounted on the (second surface) side, and the second sealing resin layer 23 is formed on the other surface of the wiring board 2 so as to cover the second semiconductor chip 18 and the plurality of conductor posts 10 and 11. Thus, as shown in FIG. 2, the warping direction of the wiring board 2 can be warped to be convex toward one side (the first semiconductor chip 12 side). As a result, as shown in FIG. 3, it becomes possible to match the warping direction of the semiconductor device 26 that is the lower package of PoP, and the solder balls 24 and 25 of the semiconductor device 1 that is the upper package are the semiconductors that are the lower package. Good connection to the lands 32a, 33a of the device 26 is possible. Thereby, the reliability of the stacked semiconductor device can be improved.

  In addition, according to the first embodiment, the semiconductor device 1 serving as the upper package has the semiconductor posts 12 and 18 flip-chip mounted on both surfaces of the wiring board 2 and the conductor posts 10 and 11 penetrating the second sealing resin layer 23. By mounting the solder balls 24 and 25 on the top, it is possible to increase the capacity and reduce the thickness, and to secure a standoff.

  Further, according to the first embodiment, the semiconductor substrate 12 and 18 are electrically connected to both surfaces of the wiring substrate 2 by flip chip mounting, and the wiring substrate 2 and the semiconductor chips 12 and 18 are electrically connected to each other by the bonding wire. Compared with the case where the semiconductor chips 12 and 18 are electrically connected, the wiring length can be shortened, the electrical characteristics of a memory chip such as a DRAM can be improved, and the semiconductor device 1 can be speeded up.

  Further, according to the first embodiment, the semiconductor chips 12 and 18 having substantially the same configuration in which a plurality of bump electrodes 13 and 19 are arranged along two opposing short sides are formed on the wiring board 1. The flip electrodes are mounted on both surfaces of the semiconductor chip 12 by flip chip mounting so that the bump electrodes 13 and 19 formed on the short sides of the semiconductor chips 12 and 18 are arranged along the corresponding sides. Wiring can be performed on the arranged lands 8a and 9a, and it is possible to make the two semiconductor chips 12 and 18 have the same length wiring while avoiding concentration of part of the wiring.

  Furthermore, according to the first embodiment, by avoiding dense wiring in the wiring board 2, the manufacturing yield of the wiring board 2 can be improved and the manufacturing cost of the semiconductor device 1 can be reduced.

  In the upper package of the PoP structure, there is a demand for an increase in capacity and thickness, and a semiconductor chip is flip-chip mounted on both sides of the wiring board, and a sealing resin layer that covers the semiconductor chip is formed on both sides of the wiring board. A DSFC (Double Side Flip Chip) structure provided with a plurality of conductor posts penetrating the sealing resin layer on the lower surface side is employed. In the PoP adopting the DSFC structure for the upper package, the initial warpage is slightly convex upward (plus warpage; about +50 μm) in consideration of mounting of the upper package and the lower package, and the heat generation is convex downward The target warpage (minus warp; thermal warpage bathtub curve) is designed. Since the DSFC structure is balanced in structure, it is considered that warpage can be easily adjusted.

  However, in the upper package adopting the DSFC structure, since a plurality of conductor posts are arranged on the lower side of the wiring board, the upper sealing resin layer of the wiring board has a resin amount higher than that of the lower sealing resin layer. Become more. For this reason, the upper sealing resin layer of the wiring board is more hardened and contracted than the lower sealing resin layer, and a warp (minus warp) that protrudes downward occurs. Further, even if the shrinkage ratio between the upper sealing resin layer and the lower sealing resin layer of the wiring board is greatly changed to 0.35% and 0.45%, the wiring board is projected to be −118 μm and downward. Became a warp (minus warp).

  Further, when the semiconductor chip is flip-chip mounted and resin-sealed in order from the lower side to the upper side of the wiring board, the wiring board is warped (minus warpage) to protrude downward. Further, when the semiconductor chip is flip-chip mounted and sealed on the lower side of the wiring board where the post is located, the wiring board is warped to be convex downward (minus warpage) only at the stage of flip chip mounting. From this, it can be considered that the warp shape (direction) on the side to be flip-chip mounted and sealed first is dominant even after the completion later.

  Since the lower package of the PoP often warps upward, if the upper package warps downward, the warp direction with the lower package is reversed and the upper package is good for the lower package. There is a possibility that it cannot be laminated.

[Embodiment 2]
A semiconductor device according to Embodiment 2 will be described with reference to the drawings. FIG. 8 is a cross-sectional view schematically showing the configuration of the semiconductor device according to the second embodiment. 8 is a cross-sectional view corresponding to the section AA ′ in FIG.

  The second embodiment is a modification of the first embodiment, and uses solder bumps 51 and 52 instead of columnar conductor posts (10 and 11 in FIG. 2). The solder bumps 51 and 52 are spherical conductors (for example, disposed on the lands 8b and 9b disposed in the peripheral region of the other surface (the lower surface, the surface on the second semiconductor chip 18 side, the second surface) of the wiring board 2. , Solder). The solder bumps 51 and 52 are formed higher than the mounting height of the second semiconductor chip 18 from the other surface of the wiring board 2. Other configurations are the same as those of the first embodiment.

  Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to the drawings. 9 to 11 are process cross-sectional views schematically showing the method for manufacturing a semiconductor device according to the second embodiment. 12 and 13 are process cross-sectional views schematically showing a molding process in the semiconductor device manufacturing method according to the second embodiment.

  In the second embodiment, instead of starting from a wiring mother board (40 in FIG. 4A) on which conductor posts (10 and 11 in FIG. 4A) are formed in advance as in the first embodiment, a wiring mother board is used. Starting from the state of only 40, after the first sealing resin layer 16 is formed, the solder bumps 51 and 52 are mounted on the lands 8b and 9b. Other steps are the same as those in the first embodiment. Details are as follows.

  First, a wiring mother board 40 having a plurality of product regions 40a is prepared (step D1; see FIG. 9A). At this stage, solder bumps (51 and 52 in FIG. 8) are not formed on the lands 8b and 9b.

  Next, similarly to step A2 of Embodiment 1 (see FIG. 4B), the upper surface (upper surface in FIG. 9, first surface) of each product region (40a in FIG. 9A) of the wiring motherboard 40 The first semiconductor chip 12 is mounted on the connection pad 8a side by flip-chip mounting (step D2; see FIG. 9B).

  Next, similarly to Step A3 and Steps B1 to B4 (see FIG. 4C and FIGS. 6A to 6C) of the first embodiment, each product region (FIG. The first sealing resin that collectively covers the plurality of first semiconductor chips 12 mounted in each product region 40a on one surface (upper surface, surface on the first semiconductor chip 12 side, first surface) of 40a) of a). The layer 16 is formed (step D3; see FIGS. 9C and 12A to 12C). At this stage, solder bumps (51 and 52 in FIG. 8) are not formed on the lands 8b and 9b. Therefore, the recess 44a of the lower mold 44 in FIG. 12 has a relief groove (corresponding to 44b in FIG. 6). ) Is not formed. Thereby, the structure of the lower mold | type 44 can be simplified and the manufacturing cost of the semiconductor device 1 can be reduced.

  Next, each product of the wiring mother board 40 (including the first semiconductor chip 12, the resin filling member 15, and the first sealing resin layer 16) is the same as in step A4 of Embodiment 1 (see FIG. 4D). The second semiconductor chip 18 is mounted on the other surface of the region 40a (the lower surface, the surface on the second connection pad 9a side, the second surface) by flip chip mounting (step D4; see FIG. 10A).

  Next, solder bumps 51 and 52 are formed on the lands 8b and 9b (step D5; see FIG. 10B).

  Next, similarly to Step A5 and Steps C1 to C4 of Embodiment 1 (see FIGS. 5A and 7A to 7C), each product region (FIG. The second sealing resin layer that collectively covers each second semiconductor chip 18 and each solder bump 51, 52 on the other surface (the lower surface, the surface on the solder bump 51, 52 side, the second surface) of 40 a) of a). 23 (step D6; see FIG. 10C).

  Next, in the same manner as in Step A6 (see FIG. 5B) of the first embodiment, the other surface (the lower surface, the surface on the solder bumps 51 and 52 side) of the wiring mother board 40 is obtained by a grindstone of a polishing apparatus (not shown). The second sealing resin layer 23 on the second surface) is ground by a predetermined amount to expose the tip portions of the solder bumps 51 and 52 (step D7; see FIG. 11A).

  Next, in the same manner as in step A7 (see FIG. 5C) of the first embodiment, the outer surfaces of the solder bumps 51 and 52 exposed from the second sealing resin layer 23 of the wiring motherboard 40 are externally connected. Solder balls 24 and 25 to be electrodes are formed (step D8; see FIG. 11B).

  Finally, similarly to Step A8 of Embodiment 1 (see FIG. 5D), along the dicing line (40b in FIG. 11B) of the wiring mother board 40 on which the solder balls 24 and 25 are formed, Each product area (40a in FIG. 11A) is cut and separated (step D9; see FIG. 11C). As described above, the warped semiconductor device 1 (upper package) that protrudes upward (on the first semiconductor chip 12 side) as shown in FIG. 8 is obtained.

  According to the second embodiment, the first semiconductor chip 12 is mounted on one surface (the upper surface in FIG. 8, the surface on the first connection pad 8a side) of the wiring motherboard 40 so as to cover the first semiconductor chip 12. After the first sealing resin layer 16 is formed on one surface of the wiring mother board 40, the second semiconductor is formed on the other surface of the wiring mother board 40 (the lower surface in FIG. 8, the surface on the second connection pad 9a side). By mounting the chip 18 and forming the second sealing resin layer 23 so as to cover the second semiconductor chip and the plurality of conductor posts 11, 12, the warping direction of the semiconductor device 1 is set to the upper side as shown in FIG. The first semiconductor chip 12 side) can be warped convexly, and the same effect as in the first embodiment can be obtained.

  In addition, according to the second embodiment, the first semiconductor chip 12 is mounted and the first sealing is performed by using solder bumps 51 and 52 instead of the conductor posts (10 and 11 in FIG. 2) of the first embodiment. Since the solder bumps 51 and 52 can be formed after the resin layer 16 is formed, it is not necessary to provide a relief groove in the lower mold of the mold when the first sealing resin layer 16 is formed, and the lower mold can be shared. It becomes possible.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to the said embodiment, and can be variously changed in the range which does not deviate from the summary.

  For example, in the present embodiment, the case where a rigid wiring substrate such as a glass epoxy substrate is used has been described. However, a flexible wiring substrate using a polyimide substrate or the like may be used.

  In this embodiment, the case where two memory chips having the same configuration are mounted on the upper and lower surfaces of the wiring board has been described. However, two different configuration semiconductor chips, such as a memory chip of a DRAM and a flash memory, are connected to the wiring board. You may apply when mounting on upper and lower surfaces.

  Furthermore, in the present embodiment, the case where the memory chips mounted on the upper and lower surfaces of the wiring board are arranged so as to intersect with each other is described, but the upper and lower memory chips may be arranged in the same direction.

(Appendix)
A method of manufacturing a semiconductor device according to one aspect includes a step of preparing a wiring board having a first surface, a second surface facing the first surface, and a plurality of lands formed on the second surface; Mounting a first semiconductor chip on the first surface of the wiring board; forming a first sealing resin layer on the first surface of the wiring board so as to cover the first semiconductor chip; After the step of forming the first sealing resin layer, a step of mounting a second semiconductor chip on the second surface of the wiring substrate; and the first of the wiring substrate so as to cover the second semiconductor chip Forming a second sealing resin layer on the two surfaces.

  In the method for manufacturing a semiconductor device, a step of disposing a plurality of conductors protruding from the second surface on the plurality of lands of the wiring board before the step of forming the second sealing resin layer. In the step of forming the second sealing resin layer, the second sealing resin layer is formed on the second surface of the wiring board so as to cover the second semiconductor chip and the plurality of conductors. The step of exposing the plurality of conductors from the second sealing resin layer may be included after the step of forming the second sealing resin layer.

  In the method for manufacturing a semiconductor device, the plurality of conductors can be disposed on the plurality of lands after the step of preparing the wiring board and before the step of mounting the first semiconductor chip.

  In the semiconductor device manufacturing method, the conductor may be a columnar conductor post.

  In the method of manufacturing the semiconductor device, in the step of disposing the plurality of conductors, after the step of forming the first sealing resin layer and before the step of forming the second sealing resin layer, The plurality of conductors can be disposed on the plurality of lands.

  In the semiconductor device manufacturing method, the conductor may be a solder bump.

  In the method of manufacturing the semiconductor device, in the step of mounting the first semiconductor chip, the first semiconductor chip is mounted on the first surface of the wiring board by flip chip mounting, and the wiring board and the first semiconductor are mounted. In the step of filling the first resin filling member between the chip and mounting the second semiconductor chip, the second semiconductor chip is mounted on the second surface of the wiring board by flip chip mounting, and the wiring A second resin filling member can be filled between the substrate and the second semiconductor chip.

  In the method for manufacturing a semiconductor device, the first semiconductor chip and the second semiconductor chip have a rectangular plate shape, and have the same configuration in which a plurality of bump electrodes are arranged along two opposing short sides. In addition, the first semiconductor chip and the second semiconductor chip may be flip-chip mounted in a state in which the first semiconductor chip and the second semiconductor chip are rotated by 90 °.

  The method for manufacturing a semiconductor device may include a step of exposing the tip of the conductor by grinding the second sealing resin layer after the step of forming the second sealing resin layer.

  In the manufacturing method of the semiconductor device, after the step of exposing the tip of the conductor, a solder ball can be formed on the tip of the conductor.

  It should be noted that the embodiments or examples can be changed or adjusted within the scope of the entire disclosure (including claims and drawings) of the present invention and based on the basic technical concept. In addition, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible within the scope of the entire disclosure of the present invention. It is. That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea. Further, regarding numerical values and numerical ranges described in the present application, it is considered that any intermediate value, lower numerical value, and small range are described even if not specified.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Wiring board 3 Insulating base material 4, 5 Solder resist film 4a, 5a Opening 8 First wiring pattern 8a First connection pad 8b First land 9 Second wiring pattern 9a Second connection pad 9b Second land 10 First conductor post (conductor)
11 Second conductor post (conductor)
12 First Semiconductor Chip 12a Electrode Pad 13 Bump Electrode 14 Solder Layer 15 Resin Filling Member (First Resin Filling Member)
16 First sealing resin layer 18 Second semiconductor chip 18a Electrode pad 19 Bump electrode 20 Solder layer 21 Resin filling member (second resin filling member)
23 Second sealing resin layer 24, 25 Solder ball 26 Semiconductor device 27 Wiring substrate 28 Insulating base material 29, 30 Solder resist film 29a Opening 31 Wiring pattern 31a Connection pad 31b Land 32, 33 Wiring pattern 32a, 32b, 33a, 33b Land 34, 35, 36 Solder ball 37 Third semiconductor chip 37a Electrode pad 38 Bump electrode 39 Resin filling member 40 Wiring mother board 40a Product region 40b Dicing line 40c Frame portion 43 Upper die 43a Cavity 44 Lower die 44a Recess 44b Escape groove 45 Mold 46 Lower mold 46a Recess 49 Gate 50 Air vent 51 First solder bump (conductor)
52 Second solder bump (conductor)
60 Stacked semiconductor devices

Claims (10)

Preparing a wiring board having a first surface, a second surface facing the first surface, and a plurality of lands formed on the second surface;
Mounting a first semiconductor chip on the first surface of the wiring board;
Forming a first sealing resin layer on the first surface of the wiring substrate so as to cover the first semiconductor chip;
After the step of forming the first sealing resin layer, a step of mounting a second semiconductor chip on the second surface of the wiring board;
Forming a second sealing resin layer on the second surface of the wiring substrate so as to cover the second semiconductor chip;
A method of manufacturing a semiconductor device including: Before the step of forming the second sealing resin layer, including a step of disposing a plurality of conductors protruding from the second surface on the plurality of lands of the wiring board;
In the step of forming the second sealing resin layer, the second sealing resin layer is formed on the second surface of the wiring board so as to cover the second semiconductor chip and the plurality of conductors,
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of exposing the plurality of conductors from the second sealing resin layer after the step of forming the second sealing resin layer.   The method of manufacturing a semiconductor device according to claim 2, wherein the plurality of conductors are arranged on the plurality of lands after the step of preparing the wiring board and before the step of mounting the first semiconductor chip.   The method of manufacturing a semiconductor device according to claim 3, wherein the conductor is a columnar conductor post.   In the step of disposing the plurality of conductors, after the step of forming the first sealing resin layer and before the step of forming the second sealing resin layer, the plurality of conductors on the plurality of lands. The method for manufacturing a semiconductor device according to claim 2, wherein the conductor is disposed.   The method of manufacturing a semiconductor device according to claim 5, wherein the conductor is a solder bump. In the step of mounting the first semiconductor chip, the first semiconductor chip is mounted on the first surface of the wiring board by flip chip mounting, and a first resin is provided between the wiring board and the first semiconductor chip. Filling the filling member,
In the step of mounting the second semiconductor chip, the second semiconductor chip is mounted on the second surface of the wiring board by flip chip mounting, and a second resin is interposed between the wiring board and the second semiconductor chip. The method for manufacturing a semiconductor device according to claim 1, wherein the filling member is filled. The first semiconductor chip and the second semiconductor chip have a rectangular plate shape and the same configuration in which a plurality of bump electrodes are arranged along two opposing short sides,
The method of manufacturing a semiconductor device according to claim 7, wherein the first semiconductor chip and the second semiconductor chip are flip-chip mounted in a state where they are arranged to be rotated by 90 °.   The semiconductor according to any one of claims 1 to 7, further comprising a step of exposing a tip of the conductor by grinding the second sealing resin layer after the step of forming the second sealing resin layer. Device manufacturing method.   The method for manufacturing a semiconductor device according to claim 9, wherein a solder ball is formed on the tip portion of the conductor after the step of exposing the tip portion of the conductor.

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