JP2016058659A - Silicon carbide semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a silicon carbide semiconductor device having high channel mobility while minimizing deterioration in productivity.SOLUTION: In a silicon carbide semiconductor device, an interface state density of an interface between a silicon carbide semiconductor and a gate oxide film on the silicon carbide semiconductor at an average of not less than 0.2 eV and not more than 0.3 eV is equal to or less than 1.8×10/cm/eV. When manufacturing such silicon carbide semiconductor device, in a process of performing an oxidation treatment to provide the gate oxide film on the silicon carbide semiconductor or in a process of performing POA (Post Oxidation Anneal) treatment after providing the gate oxide film, a heat treat furnace is cooled and a silicon carbide semiconductor is removed from the heat treat furnace at a furnace removal temperature of not less than 200°C and less than 400°C.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

  As semiconductor devices using silicon carbide as a material such as a silicon carbide (SiC) single crystal substrate, Schottky barrier diodes and planar vertical MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) are products. It has become. In the conventional silicon carbide MOSFET, since the interface state density at the interface between the gate oxide film and silicon carbide is large, the channel mobility is small and the element resistance is large.

When manufacturing a silicon carbide MOSFET, it is known that the channel mobility is improved by performing a POA (Post Oxidation Annealing) process using water vapor after a gate oxidation process using dry oxygen. For example, the channel mobility when the POA treatment is not performed after the gate oxidation treatment with dry oxygen is 6 cm ² / V / s, whereas the channel mobility when the POA treatment with water vapor is performed after the gate oxidation treatment. Is known to improve to about 25 cm ² / V / s (see Non-Patent Document 1, for example).

  Further, in a silicon carbide MOSFET, since the gate oxide film is thick, the POA process may be performed at a high temperature of 1100 ° C. or higher. In order to shorten the time required for the POA process, the temperature when the wafer is put into the heat treatment furnace or the temperature when the wafer is taken out from the heat treatment furnace is set high, and the temperature rise time to the set temperature and the temperature drop time from the set temperature are set. It is desirable to shorten it. For this reason, the temperature of the heat treatment furnace when the wafer is taken in and out is often about 700 ° C., for example. On the other hand, a method of taking out a wafer from a heat treatment furnace after cooling the furnace temperature to room temperature has been reported (for example, see Non-Patent Document 2).

Kazuo Arai, 1 other, “Basics and Applications of SiC Devices”, Ohmsha, March 26, 203 Yoji Yano and four others, “Fluctuations in 4H-SiC MOSFET characteristics caused by traps with long time constants”, 18th lecture meeting on SiC and related wide gap semiconductors Kobe International Conference Hall P-92

  However, if the temperature at the time of removing the wafer from the heat treatment furnace is high, an unintended oxidation reaction may occur due to dry oxygen in the atmosphere around the wafer boat when the wafer is removed from the furnace. When this unintended oxidation reaction occurs, the interface state density at the interface between the silicon carbide semiconductor and the gate oxide film is increased, resulting in a problem that the channel mobility is decreased. On the other hand, when the wafer is taken out after being cooled to room temperature, even if the rate of temperature decrease is set to 5 ° C. per minute, it becomes about 3 ° C. per minute when it is about 400 ° C. or less, and every minute when it is about 200 ° C. or less. Since it becomes about 1.5 ° C., for example, it takes more than half a day to cool from 1100 ° C. to room temperature. As a result, the total time required for the gate oxidation process is, for example, about 6 hours when the wafer unloading temperature is 700 ° C., but increases to about 18 hours when the wafer is taken out at room temperature. Therefore, there is a problem that productivity is reduced to 1/3.

  An object of the present invention is to provide a silicon carbide semiconductor device having a high channel mobility and a method for manufacturing the same while minimizing a decrease in productivity in order to eliminate the above-described problems caused by the prior art.

In order to solve the above-described problems and achieve the object, a silicon carbide semiconductor device according to the present invention has a silicon carbide semiconductor and the silicon carbide semiconductor, where Ec is a conductor energy level and E is a measured energy level. The average value of the interface state density at 0.2 eV ≦ Ec−E ≦ 0.3 eV at the interface with the upper gate oxide film is 1.8 × 10 ¹¹ / cm ² / eV or less. .

  According to the present invention, since the interface state density is sufficiently low, high channel mobility is realized.

  The silicon carbide semiconductor device according to the present invention is the first conductivity type silicon carbide substrate provided on the front surface of the first conductivity type silicon carbide substrate and the first conductivity type silicon carbide substrate in the above-described invention. A first conductivity type silicon carbide layer having an impurity concentration lower than that of the silicon carbide substrate; a first second conductivity type region provided in a part of a surface region of the first conductivity type silicon carbide layer; Impurity concentration of the first conductivity type source region provided in the surface region of the second conductivity type region and the first second conductivity type region provided in the surface region of the first second conductivity type region. A second conductive type region having a high height, a source electrode electrically connected to the first conductive type source region and the second second conductive type region, and the first second conductive type region, On the surface of the region sandwiched between the first conductivity type silicon carbide layer and the first conductivity type source region Wherein a gate oxide film provided, characterized in that it comprises a gate electrode provided on the gate oxide film, and a drain electrode provided on the back surface of the first conductivity type silicon carbide substrate.

  According to the present invention, a vertical silicon carbide MOS (Metal Oxide Semiconductor) semiconductor device having high channel mobility can be obtained.

  Also, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, an oxidation treatment is performed in a heat treatment furnace to provide a gate oxide film on the silicon carbide semiconductor, and then the heat treatment furnace is cooled to 200 ° C. or higher and lower than 400 ° C. The silicon carbide semiconductor is removed from the heat treatment furnace at a furnace discharge temperature of

  According to the present invention, since the furnace discharge temperature is 200 ° C. or higher, it is not necessary to perform cooling from 200 ° C. to room temperature, which takes about 3 to 4 hours, for example, so that a reduction in productivity can be suppressed. When the furnace discharge temperature is lower than 400 ° C., it is possible to prevent unintended oxidation from proceeding when the silicon carbide semiconductor device is removed from the furnace, so that the interface state density is prevented from increasing, and high channel movement is achieved. can get.

  According to another aspect of the present invention, there is provided a method for manufacturing a silicon carbide semiconductor device comprising: performing oxidation treatment in a heat treatment furnace to provide a gate oxide film on a silicon carbide semiconductor; performing POA (Post Oxidation Annealing) treatment; The heat treatment furnace is cooled, and the silicon carbide semiconductor is removed from the heat treatment furnace at a furnace temperature of 200 ° C. or higher and lower than 400 ° C.

  According to the present invention, since the furnace discharge temperature is 200 ° C. or higher, it is not necessary to perform cooling from 200 ° C. to room temperature, which takes about 3 to 4 hours, for example, so that a reduction in productivity can be suppressed. When the furnace discharge temperature is lower than 400 ° C., it is possible to prevent unintended oxidation from proceeding when the silicon carbide semiconductor device is removed from the furnace, so that the interface state density is prevented from increasing, and high channel movement is achieved. can get.

  According to the silicon carbide semiconductor device and the method for manufacturing the same according to the present invention, a silicon carbide semiconductor device having high channel mobility can be obtained while minimizing the decrease in productivity.

It is sectional drawing which shows an example of the silicon carbide semiconductor device concerning embodiment of this invention. It is a temperature profile figure which shows an example of the furnace temperature change in the gate oxidation process of the manufacturing method of the silicon carbide semiconductor device concerning embodiment of this invention. It is a temperature profile figure which shows an example of the temperature change in a furnace in the POA process of the manufacturing method of the silicon carbide semiconductor device concerning embodiment of this invention. It is a characteristic view which shows the example of a measurement of an interface state density. It is sectional drawing which shows another example of the silicon carbide semiconductor device concerning embodiment of this invention.

  Exemplary embodiments of a silicon carbide semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached thereto. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

FIG. 1 is a cross-sectional view illustrating an example of a silicon carbide semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the silicon carbide semiconductor device includes an n silicon carbide substrate 1 made of N type silicon carbide and an n ⁻ silicon carbide layer 2 made of N type silicon carbide. The n silicon carbide substrate 1 may be, for example, a silicon carbide single crystal substrate in which silicon carbide is doped with an N-type impurity. The n silicon carbide substrate 1 becomes a drain region, for example.

N ⁻ silicon carbide layer 2 is provided on the front surface of n silicon carbide substrate 1. The impurity concentration of n ⁻ silicon carbide layer 2 is lower than that of n silicon carbide substrate 1. The n ⁻ silicon carbide layer 2 may be a semiconductor layer in which silicon carbide is doped with an N-type impurity, for example. The n ⁻ silicon carbide layer 2 is, for example, an N-type drift layer.

The silicon carbide semiconductor device has, for example, a p region 3, an n source region 4, a p ⁺ region 5, a gate oxide film 6, a gate electrode 7, and a source electrode 8 on the front surface side of the n silicon carbide substrate 1. It has. The silicon carbide semiconductor device includes, for example, a drain electrode 9 on the back surface side of the n silicon carbide substrate 1.

P region 3 is provided in part of the surface region of n ⁻ silicon carbide layer 2. P region 3 is provided so as to sandwich another part of the surface region of n ⁻ silicon carbide layer 2. The p region 3 may be a semiconductor region in which silicon carbide is doped with a P-type impurity, for example. The p region 3 is an example of a first second conductivity type region.

The n source region 4 is provided in the surface region of the p region 3. N source region 4 is provided apart from the surface region of n ⁻ silicon carbide layer 2 sandwiched between adjacent p region 3 and p region 3. The impurity concentration of n source region 4 is higher than that of n ⁻ silicon carbide layer 2.

p ⁺ region 5 is provided on the opposite side of the surface region of n ⁻ silicon carbide layer 2 between adjacent p region 3 and p region 3 with n source region 4 sandwiched in the surface region of p region 3. It has been. The p ⁺ region 5 is in contact with the p region 3 and the n source region 4. The impurity concentration of p ⁺ region 5 is higher than that of p region 3. The p ⁺ region 5 is an example of a second second conductivity type region.

Gate oxide film 6 is provided on the surface of p region 3 of n ⁻ silicon carbide layer 2 sandwiched between p region 3 and n source region 4. Here, the conductor energy level is Ec, and the measured energy level is E. The average value of the interface state density at 0.2 eV ≦ Ec−E ≦ 0.3 eV at the interface between the p region 3 and the gate oxide film 6 is 1.8 × 10 ¹¹ / cm ² / eV or less.

  The gate electrode 7 is provided on the surface of the gate oxide film 6.

Source electrode 8 is provided in contact with n source region 4 and p ⁺ region 5. The source electrode 8 is electrically connected to the n source region 4 and the p ⁺ region 5. The source electrode 8 is insulated from the gate electrode 7 by an interlayer insulating film (not shown).

  Drain electrode 9 is provided on the back surface of n silicon carbide substrate 1. Drain electrode 9 is in ohmic contact with n silicon carbide substrate 1.

Example of Manufacturing Procedure of Silicon Carbide Semiconductor Device Shown in FIG. 1 First, an n silicon carbide substrate 1 made of N-type silicon carbide is prepared. An n ⁻ silicon carbide layer 2 made of silicon carbide, for example, is epitaxially grown on the front surface of the n silicon carbide substrate 1 while doping an N-type impurity, for example.

Next, a P-type impurity is ion-implanted into a region to be the p region 3 in the surface region of the n ⁻ silicon carbide layer 2 by a photolithography technique and an ion implantation method. Next, an N-type impurity is ion-implanted into a region to be the n source region 4 in the ion implantation region to be the p region 3 by a photolithography technique and an ion implantation method.

Next, a P-type impurity is ion-implanted into the region to be the p ⁺ region 5 in the ion implantation region to be the p region 3 by photolithography and ion implantation. Note that the order of ion implantation for providing the p region 3, ion implantation for providing the n source region 4, and ion implantation for providing the p ⁺ region 5 is not limited to the order described above, and can be variously changed. .

Next, heat treatment (annealing) is performed to activate each ion implantation region that becomes, for example, the p region 3, the n source region 4, and the p ⁺ region 5. Thereby, the p region 3, the n source region 4 and the p ⁺ region 5 are formed. As described above, the respective ion implantation regions may be activated collectively by one heat treatment, or may be activated by performing heat treatment every time ion implantation is performed.

Next, the surface on which the p region 3, the n source region 4 and the p ⁺ region 5 are provided is thermally oxidized, and a gate oxide film 6 is provided on the entire surface. A POA process may be performed after the gate oxidation process. By performing the POA process, the film quality of the gate oxide film 6 is improved. In the gate oxidation process and the POA process, a batch type vertical diffusion furnace that simultaneously processes about 100 to 150 wafers may be used. In a vertical diffusion furnace, wafers placed on a jig called a wafer boat slowly rise in a diffusion furnace maintained at about 700 ° C., for example. When the increase is completed, the temperature is increased, the gas valve is switched, the gas flow rate is changed, and the temperature is decreased based on a preset program. When the process is complete, the wafer boat slowly descends and is removed from the furnace. The temperature change in the heat treatment furnace in the gate oxidation process and the POA process will be described later.

Next, a gate electrode 7 is provided on the gate oxide film 6. Next, a source electrode 8 is provided so as to be in contact with the n source region 4 and the p ⁺ region 5. Next, the drain electrode 9 is provided on the back surface of the n silicon carbide substrate 1. Then, heat treatment is performed to make ohmic contact between n-silicon carbide substrate 1 and drain electrode 9. As described above, the silicon carbide semiconductor device shown in FIG. 1 is completed.

-Example of furnace temperature change in gate oxidation process FIG. 2: is a temperature profile figure which shows an example of the furnace temperature change in the gate oxidation process of the manufacturing method of the silicon carbide semiconductor device concerning embodiment of this invention. FIG. 2 shows an example of a gate oxidation process using NO gas at a furnace temperature of 700 ° C., for example.

As shown in FIG. 2, the temperature is raised from 700 ° C. to 1300 ° C., for example, in a nitrogen (N ₂ ) atmosphere. Subsequently, the atmosphere is switched to NO, and gate oxidation is performed at 1300 ° C., for example. Subsequently, the temperature is switched to a nitrogen atmosphere, and the temperature is lowered by setting the rate of temperature decrease to, for example, 5 ° C. per minute up to a furnace temperature of 200 ° C. to 400 ° C., for example, 300 ° C. Originally, if the temperature can be decreased from 1300 ° C. to 300 ° C. at −5 ° C./min, it reaches 300 ° C. in 200 minutes as shown by the broken line.

  However, it is considered that as the furnace temperature decreases, it becomes impossible to follow the temperature decrease rate of −5 ° C./min as indicated by the solid line. Therefore, it is necessary to confirm that the in-furnace temperature is a predetermined furnace discharge temperature, for example, 300 ° C., and to start descent of the wafer boat without managing the elapsed time after the temperature lowering is started.

  In order to realize this function, a program that does not proceed to the next step unless the predetermined furnace discharge temperature is reached may be established. When there is no such function, for example, the temperature drop rate from 1100 ° C. to 800 ° C. is −5 ° C./min, the temperature drop rate from 800 ° C. to 600 ° C. is −3 ° C./min, and the temperature drop is 600 ° C. to 300 ° C. The rate of temperature decrease may be changed in a temperature range such as a rate of −1.5 ° C./min.

-Example of furnace temperature change in POA process FIG. 3: is a temperature profile figure which shows an example of the furnace temperature change in the POA process of the manufacturing method of the silicon carbide semiconductor device concerning embodiment of this invention. FIG. 3 shows an example of POA treatment with steam (H ₂ O) at a furnace temperature of 700 ° C., for example.

  As shown in FIG. 3, the temperature is raised from 700 ° C. to 1100 ° C., for example, in a nitrogen atmosphere. Subsequently, the atmosphere is switched to water vapor, and a POA treatment is performed at 1100 ° C., for example. Subsequently, the temperature is switched to a nitrogen atmosphere, and the temperature is lowered by setting the rate of temperature decrease to, for example, 5 ° C. per minute up to a furnace temperature of 200 ° C. to 400 ° C., for example, 300 ° C. Originally, if the temperature can be decreased from 1100 ° C. to 300 ° C. at −5 ° C./min, the temperature reaches 300 ° C. in 160 minutes as shown by the broken line.

  However, it is considered that as the furnace temperature decreases, it becomes impossible to follow the temperature decrease rate of −5 ° C./min as indicated by the solid line. Therefore, it is necessary to confirm that the in-furnace temperature is a predetermined furnace discharge temperature, for example, 300 ° C., and to start descent of the wafer boat without managing the elapsed time after the temperature lowering is started.

  In order to realize this function, a program that does not proceed to the next step unless the predetermined furnace discharge temperature is reached may be established. When there is no such function, for example, the temperature drop rate from 1100 ° C. to 800 ° C. is −5 ° C./min, the temperature drop rate from 800 ° C. to 600 ° C. is −3 ° C./min, and the temperature drop is 600 ° C. to 300 ° C. The rate of temperature decrease may be changed in a temperature range such as a rate of −1.5 ° C./min.

Measurement Example of Interface State Density FIG. 4 is a characteristic diagram showing an example of measurement of interface state density. In FIG. 4, the vertical axis represents the interface state density Dit, and the unit is / cm ² / eV. The horizontal axis represents the difference Ec−E between the conductor energy level Ec and the measured energy level E, and the unit is eV. The plot of “Dry oxidation only” is for a sample that was subjected to gate oxidation in an N ₂ O gas atmosphere at 1300 ° C., then exited at 700 ° C. and not subjected to POA treatment. The plot of “700 ° C. Furnace” shows a sample of a sample that was gate-oxidized in an N ₂ O gas atmosphere at 1300 ° C., then POA-treated in a steam atmosphere at 1100 ° C. Is. The plot of “300 ° C. Furnace” shows a sample of the sample that was gate-oxidized in a N ₂ O gas atmosphere at 1300 ° C., then POA-treated in a steam atmosphere at 1100 ° C., and then vented at 300 ° C. Is. The “300 ° C. furnace discharge” sample is a sample according to the embodiment.

The average value of the interface state density at the interface between the p region 3 and the gate oxide film 6 at 0.2 eV ≦ Ec−E ≦ 0.3 eV is 8 × 10 ¹² / cm ² / It is about eV, and is about 5 × 10 ¹¹ / cm ² / eV in the sample of “700 ° C. furnace exit”. On the other hand, the average value of the interface state density at 0.2 eV ≦ Ec−E ≦ 0.3 eV of the “300 ° C. furnace discharge” sample is 1.8 × 10 ¹¹ / cm ² / eV, and “700 It is less than half of the value of the sample “Centigrade Furnace”.

  In the “dry oxidation only” sample, a large number of dangling bonds such as dangling bonds exist at the interface between the p region 3 and the gate oxide film 6, and these dangling bonds serve as carrier capture sources. Therefore, the channel mobility does not increase. On the other hand, when the POA process using water vapor is performed after the gate oxidation process, the dangling bonds are terminated by a hydroxyl group (—OH) or the like, so that the interface state density is reduced and carriers are hardly captured. Therefore, channel mobility increases. However, if the temperature at the furnace is higher than 400 ° C., an unintended oxidation reaction occurs at the time of the furnace, and the interface terminated with a hydroxyl group by POA treatment becomes dangling bonds again, and the interface state density increases. it is conceivable that. Therefore, performing the furnace discharge at a temperature higher than 400 ° C. is considered to be one of the causes for the channel mobility to decrease.

  According to the embodiment, since the interface state density is sufficiently low, high channel mobility can be realized. Moreover, since it is not necessary to perform cooling from the furnace temperature to room temperature, it is possible to suppress a decrease in productivity. In addition, since unintended oxidation can be prevented from proceeding when leaving the furnace, it is possible to prevent the interface state density from increasing. Thereby, high channel movement can be realized. Therefore, a silicon carbide semiconductor device having high channel mobility can be obtained while minimizing the decrease in productivity.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the temperatures and gas types described in the embodiments are examples, and the present invention is not limited to them. In each embodiment, the first conductivity type is N-type and the second conductivity type is P-type. However, in the present invention, the first conductivity type is P-type and the second conductivity type is N-type. It holds. Further, for example, as shown in FIG. 5, the same applies to a silicon carbide semiconductor device having an epitaxial layer of a conductivity type different from that of the silicon carbide substrate on the front surface side of the silicon carbide substrate.

-Another example of a silicon carbide semiconductor device FIG. 5: is sectional drawing which shows another example of the silicon carbide semiconductor device concerning embodiment of this invention. As shown in FIG. 5, the silicon carbide semiconductor device includes an n silicon carbide substrate 1 and an n ⁻ silicon carbide layer 2. n silicon carbide substrate 1 and the n ^- For the silicon carbide layer 2, is similar to the example shown in FIG. 1, and overlapping description will be omitted.

The silicon carbide semiconductor device has, for example, a p region 3, an n source region 4, a p ⁺ region 5, a gate oxide film 6, a gate electrode 7, and a source electrode 8 on the front surface side of the n silicon carbide substrate 1. , P base region 10, p silicon carbide layer 11, and n ⁻ region 12. The silicon carbide semiconductor device includes, for example, a drain electrode 9 on the back surface side of the n silicon carbide substrate 1.

P base region 10 is provided in part of the surface region of n ⁻ silicon carbide layer 2. P base region 10 is provided so as to sandwich another part of the surface region of n ⁻ silicon carbide layer 2. The p base region 10 may be a semiconductor region in which silicon carbide is doped with a P-type impurity, for example.

p silicon carbide layer 11 is provided on the surface of n ⁻ silicon carbide layer 2. The p silicon carbide layer 11 may be, for example, a semiconductor layer obtained by doping silicon carbide with a P-type impurity.

N ⁻ region 12 is provided on the surface of the region between adjacent p base regions 10 and 10 of n ⁻ silicon carbide layer 2. N ⁻ region 12 penetrates p silicon carbide layer 11 and is in contact with the region between adjacent p base region 10 and p base region 10 of n ⁻ silicon carbide layer 2. The impurity concentration of n ⁻ region 12 is lower than that of n silicon carbide substrate 1. For example, n ⁻ region 12 may be a region obtained by inverting the conductivity type of a part of p silicon carbide layer 11 by ion implantation of N-type impurities and heat treatment. For example, n ⁻ region 12 becomes an n-type drift region together with n ⁻ silicon carbide layer 2.

P region 3 is a part of p silicon carbide layer 11 and is provided on the surface of p base region 10. The p region 3 is provided so as to sandwich the n ⁻ region 12.

The n source region 4 is provided in the surface region of the p region 3 on the p base region 10. N source region 4 is provided apart from n ⁻ region 12. The impurity concentration of n source region 4 is higher than that of n ⁻ region 12.

p ⁺ region 5 penetrates through p silicon carbide layer 11 and contacts p base region 10 in p silicon carbide layer 11. p ⁺ region 5, n ^- and away from the region 12, across the n source region 4 n ^- is provided on the opposite side of the region 12. The p ⁺ region 5 is in contact with the p region 3 and the n source region 4. The impurity concentration of p ⁺ region 5 is higher than that of p silicon carbide layer 11.

Gate oxide film 6 is provided on the surface of p silicon carbide layer 11 in a region sandwiched between n ⁻ region 12 and n source region 4 in p region 3. The average value of the interface state density at 0.2 eV ≦ Ec−E ≦ 0.3 eV at the interface between the p region 3 and the gate oxide film 6 is 1.8 × 10 ¹¹ / cm ² / eV or less.

  About the gate electrode 7, the source electrode 8, and the drain electrode 9, since it is the same as that of the example shown in FIG. 1, the overlapping description is abbreviate | omitted.

  As described above, the silicon carbide semiconductor device and the method for manufacturing the same according to the present invention are useful for, for example, a silicon carbide semiconductor device that can be used as a switching device formed on a silicon carbide substrate. It is suitable for semiconductor devices such as vertical MOSFETs.

1 n silicon carbide substrate 2 n ^- SiC layer 3 p region 4 n source region 5 p ⁺ region 6 gate oxide film 7 gate electrode 8 source electrode 9 drain electrode

Claims (4)

When the conductor energy level is Ec and the measured energy level is E, the interface at 0.2 eV ≦ Ec−E ≦ 0.3 eV at the interface between the silicon carbide semiconductor and the gate oxide film on the silicon carbide semiconductor. An average value of level density is 1.8 × 10 ¹¹ / cm ² / eV or less. A first conductivity type silicon carbide substrate;
A first conductivity type silicon carbide layer having an impurity concentration lower than that of the first conductivity type silicon carbide substrate provided on the front surface of the first conductivity type silicon carbide substrate;
A first second conductivity type region provided in a part of a surface region of the first conductivity type silicon carbide layer;
A first conductivity type source region provided in a surface region of the first second conductivity type region;
A second second conductivity type region having a higher impurity concentration than the first second conductivity type region, provided in a surface region of the first second conductivity type region;
A source electrode electrically connected to the first conductivity type source region and the second second conductivity type region;
The gate oxide film provided on the surface of the region of the first second conductivity type region sandwiched between the first conductivity type silicon carbide layer and the first conductivity type source region;
A gate electrode provided on the gate oxide film;
A drain electrode provided on the back surface of the first conductivity type silicon carbide substrate;
The silicon carbide semiconductor device according to claim 1, comprising:   An oxidation treatment is performed in a heat treatment furnace to provide a gate oxide film on the silicon carbide semiconductor, and then the heat treatment furnace is cooled to take out the silicon carbide semiconductor from the heat treatment furnace at a furnace temperature of 200 ° C. or higher and lower than 400 ° C. A method for manufacturing a silicon carbide semiconductor device.   An oxidation treatment is performed in a heat treatment furnace to provide a gate oxide film on the silicon carbide semiconductor, and then a POA treatment is performed. After the POA treatment, the heat treatment furnace is cooled, and the heat treatment is performed at a furnace discharge temperature of 200 ° C. or more and less than 400 ° C. A method of manufacturing a silicon carbide semiconductor device, wherein the silicon carbide semiconductor is removed from a furnace.

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