JP2011165941A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device using SiC and having a low on-resistance and excellent reliability, and a method of fabricating the same. <P>SOLUTION: The semiconductor device is characterized by comprising a silicon carbide layer, a gate insulating film formed on the silicon carbide layer with silicon, oxygen, and nitrogen as principal components and the minimum concentration of nitrogen of ≥1×10<SP>20</SP>atoms/cm<SP>3</SP>, and a gate electrode formed on the gate insulating film. The method of fabricating the semiconductor device is characterized by comprising a step of forming an oxide film or oxynitride film on the surface (000-1) or (11-20) of the silicon carbide layer, a step of forming the gate insulating film by heat treatment in an atmosphere containing ammonia gas after the oxide film or oxynitride film has been formed, and a step of forming the gate electrode on the gate insulating film. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device using silicon carbide (SiC).

  Silicon carbide (hereinafter also referred to as SiC) is expected as a next-generation power semiconductor device material. Compared with Si, SiC has excellent physical properties such as a band gap of 3 times, a breakdown electric field strength of about 10 times, and a thermal conductivity of about 3 times. By utilizing this characteristic, it is possible to realize a power semiconductor device capable of operating at a low temperature and operating at a high temperature.

  Examples of such a high breakdown voltage semiconductor device utilizing the characteristics of SiC include a vertical MISFET and an IGBT. MISFETs and IGBTs are required to increase channel mobility and achieve low on-resistance for higher device performance.

  However, interface states are likely to be formed at the interface between the gate insulating film and SiC formed on SiC, particularly at the interface with the thermal oxide film. For this reason, there exists a problem that the mobility of a channel falls.

  Patent Document 1 describes a semiconductor device having a nitrogen concentration peak near the interface between SiC and a gate insulating film.

JP 2006-210818 A

  In order to improve the performance of the device, it is necessary to further improve the mobility of the channel. At the same time, improvement in the reliability of the gate insulating film is also required.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device using SiC and having a low on-resistance and excellent reliability and a method for manufacturing the semiconductor device. There is.

A semiconductor device according to a first aspect of the present invention is formed on a silicon carbide layer and the silicon carbide layer, and contains silicon, oxygen, and nitrogen as main components, and the minimum concentration of nitrogen is 1 × 10 ²⁰ atoms / cm ³ or more. And a gate electrode formed on the gate insulating film.

  In the semiconductor device of the above aspect, it is preferable that the gate insulating film is formed on a (000-1) plane or a (0001) plane of the silicon carbide layer.

  In the semiconductor device of the above aspect, it is preferable that the gate insulating film is formed on a (11-20) surface of a side surface of the groove formed in the silicon carbide layer.

  In the semiconductor device of the above aspect, it is desirable that the gate insulating film is a gate insulating film of MISFET or IGBT.

  In the semiconductor device according to the above aspect, the gate insulating film preferably has a thickness of 30 nm to 100 nm.

  A method for manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming an oxide film or an oxynitride film on a (000-1) plane or a (11-20) plane of a silicon carbide layer, and the oxidation After the formation of the material film or the oxynitride film, the method includes a step of heat-treating in an atmosphere containing ammonia gas to form a gate insulating film, and a step of forming a gate electrode on the gate insulating film.

  In the method of manufacturing a semiconductor device according to the second aspect, it is preferable that the oxide film is formed by dry oxidation and wet oxidation after the dry oxidation.

  In the method of manufacturing a semiconductor device according to the second aspect, it is preferable that the oxynitride film is formed by dry oxidation and oxynitridation with a nitrogen oxide gas after the dry oxidation.

  A method for manufacturing a semiconductor device according to a third aspect of the present invention includes a step of forming an oxynitride film on a (0001) surface of a silicon carbide layer by dry oxidation and oxynitridation with a nitrogen oxide gas after the dry oxidation. And a step of forming a gate insulating film by heat treatment in an atmosphere containing ammonia gas after forming the oxynitride film, and a step of forming a gate electrode on the gate insulating film.

  In the semiconductor device manufacturing method of the second or third aspect, it is preferable that the heat treatment is performed at a temperature of 800 ° C. or higher and 1350 ° C. or lower.

  According to the present invention, it is possible to provide a semiconductor device using SiC and having a low on-resistance and excellent reliability and a method for manufacturing the semiconductor device.

It is sectional drawing which shows the structure of MISFET which is the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. It is a SIMS analysis result of the nitrogen concentration of the gate insulating film of the semiconductor device of the first embodiment. It is a SIMS analysis result of the nitrogen concentration of the gate insulating film when POA is performed in an N ₂ O gas atmosphere. It is a figure which shows the interface state reduction effect of 1st Embodiment. It is a figure which shows the interface state reduction effect of 1st Embodiment. It is a figure which shows the interface state reduction effect of 1st Embodiment. It is a figure which shows the MISFET characteristic of 1st Embodiment. It is a figure which shows the effective dielectric constant of the gate insulating film in 1st Embodiment. It is a figure which shows the TDDB characteristic of the gate insulating film of 1st Embodiment. It is a SIMS analysis result of the nitrogen concentration of the gate insulating film of the semiconductor device of 2nd Embodiment. It is a SIMS analysis result of the nitrogen concentration of the gate insulating film of the semiconductor device of 2nd Embodiment. It is a SIMS analysis result of the nitrogen concentration of the gate insulating film when POA is not performed. It is a figure which shows the MISFET characteristic of 2nd Embodiment. It is a figure which shows the TDDB characteristic of the gate insulating film of 2nd Embodiment. It is sectional drawing which shows the structure of MISFET which is a semiconductor device of 3rd Embodiment. It is sectional drawing which shows the structure of IGBT which is a semiconductor device of 4th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this specification, the same or similar components are denoted by the same reference numerals.

  Note that in this specification, a gate insulating film containing silicon, oxygen, and nitrogen as main components means a gate insulating film in which the amount of elements other than silicon, oxygen, and nitrogen in the film is smaller than that of silicon, oxygen, and nitrogen. Means.

  In this specification, dry oxidation means a process in which a semiconductor layer or the like is thermally oxidized by diluting only oxygen gas or oxygen gas with an inert gas or the like. In addition, wet oxidation means a process of thermal oxidation in an atmosphere containing at least oxygen gas and water vapor. For example, a pyrogenic oxidation method is given as a specific example.

  In this specification, the (000-1) plane, the (0001) plane, and the (11-20) plane are concepts that include all planes equivalent to these in crystallography.

  Further, in this specification, the minimum concentration in a film is defined as the lowest concentration among the concentrations at the boundary between two regions when a certain film is equally divided into 10 regions in the film thickness direction. That is, it is defined as the lowest concentration among the nine boundary concentrations specified for a certain film. Further, the average concentration of a certain film is appropriately determined by the average value of the concentrations of the nine boundary portions.

(First embodiment)
The semiconductor device of the present embodiment is formed on a silicon carbide layer and a silicon carbide layer, and has silicon (Si), oxygen (O), and nitrogen (N) as main components, and the minimum concentration of nitrogen is 1 × 10 ^20. It has a gate insulating film of atoms / cm ³ or more and a gate electrode formed on the gate insulating film.

  Here, a vertical MISFET will be described as an example. With the above structure, the interface state between the gate insulating film and the SiC layer is reduced, and the carrier mobility is improved. Therefore, a MISFET with low on-resistance and high driving power is realized. Further, the reliability of the gate insulating film is improved, and a highly reliable MISFET is realized.

FIG. 1 is a cross-sectional view showing a configuration of a MISFET which is a semiconductor device of the present embodiment. The MISFET 100 includes an SiC substrate 12 having first and second main surfaces. In FIG. 1, the first main surface is the upper surface of the drawing, and the second main surface is the lower surface of the drawing. The SiC substrate 12 is a hexagonal 4H—SiC substrate (n ⁺ substrate) having an impurity concentration of about 5 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ^{−3 and} containing, for example, nitrogen (N) as an n-type impurity.

This SiC substrate 12 has a (000-1) plane as a first main surface. An n-type n ⁻ layer 14 having an n-type impurity impurity concentration of about 5 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ⁻³ is formed on the first main surface. The film thickness of the n ⁻ layer 14 is, for example, about 5 to 10 μm.

A p-type p-well region 16 having a p-type impurity concentration of about 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ is formed on a partial surface of the n ⁻ layer 14. The depth of the p well region 16 is, for example, about 0.6 μm.

An n-type source region 18 having an n-type impurity impurity concentration of about 1 × 10 ²⁰ is formed on a partial surface of the p-well region 16. The depth of the source region 18 is shallower than the depth of the p-well region 16 and is, for example, about 0.3 μm.

Further, a p-type p-well having a p-type impurity concentration of about 1 × 10 ¹⁹ to 1 × 10 ²⁰ cm ^{−3 on} a partial surface of the p-well region 16 and on the side of the n-type source region 18. A contact region 20 is formed. The depth of the p well contact region 20 is shallower than the depth of the p well region 16 and is, for example, about 0.3 μm.

Furthermore, the gate insulating film 28 is formed on the surface of the p well region 16 and the n ⁻ layer 14 so as to straddle these regions and layers. That is, the gate insulating film 28 is formed on the (000-1) plane of the SiC layer 14.

The gate insulating film 28 is a film mainly composed of silicon, oxygen, and nitrogen, and the minimum concentration of nitrogen in the film is 1 × 10 ²⁰ atoms / cm ³ or more. From the viewpoint of increasing the relative dielectric constant and improving the reliability, it is more desirable that the minimum concentration of nitrogen in the film is 1 × 10 ²¹ atoms / cm ³ or more.

  The film thickness of the gate insulating film 28 is desirably 30 nm or more and 100 nm or less. If it is less than 30 nm, the initial withstand voltage and reliability of the gate insulating film may be deteriorated. If it is larger than 100 nm, the driving force of the MISFET may be deteriorated.

  A gate electrode 30 is formed on the gate insulating film 28. For example, polysilicon or the like can be applied to the gate electrode 30. On the gate electrode 30, an interlayer insulating film 32 made of, for example, a silicon oxide film is formed.

  A source / p well common electrode 24 electrically connected to the source region 18 and the p well contact region 20 is provided. The source / p-well common electrode 24 includes, for example, a Ni barrier metal layer 24a and an Al metal layer 24b on the barrier metal layer 24a. The Ni barrier metal layer 24a and the Al metal layer 24b may form an alloy by reaction. A drain electrode 36 is formed on the second main surface of SiC substrate 12.

  In the present embodiment, the n-type impurity is preferably nitrogen (N), for example, but phosphorus (P), arsenic (As), or the like can also be applied. For example, aluminum (Al) is preferable as the p-type impurity, but boron (B) or the like can also be applied.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described. 2 to 4 are process cross-sectional views illustrating the method of manufacturing the semiconductor device according to the present embodiment.

First, a low-resistance 4H—SiC substrate 12 containing phosphorus or nitrogen as an n-type impurity at an impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ and having a thickness of, for example, 300 μm and having a hexagonal crystal lattice is prepared. Then, for example, nitrogen is included as an n-type impurity on the (000-1) plane which is one main surface of the SiC substrate 12 by an epitaxial growth method, and the thickness is about 10 × 10 ¹⁵ cm ⁻³ . A high resistance SiC layer 14 is grown.

  Next, aluminum, which is a p-type impurity, is ion-implanted into the SiC layer 14 using an appropriate mask material to form a p-well region 16. Next, phosphorus, which is an n-type impurity, is ion-implanted into the SiC layer 14 using an appropriate mask material to form the source region 18. Thereafter, aluminum, which is a p-type impurity, is ion-implanted into the SiC layer 14 using an appropriate mask material to form the p-well contact region 20. Thereafter, the ion-implanted impurities are activated by, for example, heat treatment at about 1600 ° C.

  Next, as illustrated in FIG. 2, an oxide film 28 a is formed on the (000-1) plane of the SiC layer 14 by dry oxidation at 1250 ° C. The film thickness of the oxide film 28a to be formed is 40 nm, for example.

Next, as shown in FIG. 3, as so-called POA (Post Oxidation Annealing), for example, heat treatment (ammonia annealing or NH ₃ annealing) is performed in an atmosphere containing ammonia gas at a temperature of 1200 ° C., and ammonia thermal nitridation is performed. . By this heat treatment, the oxide film 28a is nitrided to form the gate insulating film 28. At this time, it is desirable to perform POA in a 100% ammonia gas atmosphere from the viewpoint of increasing the nitriding efficiency of the oxide film.

  The temperature of the heat treatment is desirably 800 ° C. or higher and 1350 ° C. or lower. If it is less than 800 ° C., there is a possibility that sufficient thermal nitriding effect may not be obtained. At a temperature higher than 1350 ° C., there is a concern that the film quality is deteriorated due to excessive thermal nitriding. The temperature of the heat treatment is more preferably 1000 ° C. or higher and 1200 ° C. or lower from the viewpoint of obtaining a high effective relative dielectric constant and high reliability.

Also, from the viewpoint of improving the characteristics of the MISFET, it is desirable to oxynitride the oxide film 28a with a nitrogen oxide gas, for example, N ₂ O gas, before the thermal ammonia nitridation to form an oxynitride film. Further, it is desirable from the viewpoint of improving the characteristics of the MISFET that the oxide film 28a is additionally oxidized by wet oxidation before the thermal nitridation of ammonia.

  Next, as shown in FIG. 4, polysilicon is deposited on the gate insulating film 28, and the polysilicon is patterned using an appropriate mask material to form the gate electrode 30.

  Thereafter, the interlayer insulating film 32, the source / p-well common electrode 24, and the drain electrode 36 are formed by a known semiconductor process, and the vertical MISFET shown in FIG. 1 is manufactured.

According to the manufacturing method of the present embodiment, a gate insulating film having silicon, oxygen, and nitrogen as main components and a minimum nitrogen concentration of 1 × 10 ²⁰ atoms / cm ³ or more is formed. Therefore, a MISFET with low on-resistance and high driving power is realized. Further, the reliability of the gate insulating film is improved, and a highly reliable MISFET is realized.

  FIG. 5 shows the SIMS analysis result of the nitrogen concentration of the gate insulating film of the semiconductor device of this embodiment. The horizontal axis represents the depth from the surface of the gate insulating film, and the vertical axis represents the nitrogen concentration. This shows the result of performing POA on an oxide film formed by dry oxidation at 1250 ° C. at a temperature of 800 ° C., 1000 ° C., and 1200 ° C. in a 100% ammonia gas atmosphere. At the same time, the result when POA is not performed is also shown.

When POA is performed, the minimum concentration of nitrogen in the film is 1 × 10 ²⁰ atoms / cm ³ or more. In addition, the nitrogen concentration distribution is relatively uniform in the depth direction of the film. In particular, when the temperature is 1000 ° C. or higher, the minimum concentration of nitrogen in the film is 1 × 10 ²¹ atoms / cm ³ or higher.

The average concentration of nitrogen in the film is in the range of 1 × 10 ²¹ atoms / cm ^{3 to} 1 × 10 ²² atoms / cm ^{3 at} both 1000 ° C. and 1200 ° C.

FIG. 6 shows SIMS analysis results of the nitrogen concentration of the gate insulating film when POA is performed in an N ₂ O gas atmosphere. The figure shows the results of N ₂ O oxynitridation as POA at 1250 ° C. for an oxide film formed by dry oxidation at 1250 ° C. In this case, unlike the case of POA in an ammonia gas atmosphere, there is a nitrogen concentration peak near the interface between the gate insulating film and the SiC layer. And only in this peak portion, the concentration of nitrogen is 1 × 10 ²⁰ atoms / cm ³ or more.

7, 8, and 9 are diagrams showing the interface state reduction effect of the present embodiment. The horizontal axis represents the interface state depth represented by Ec-E, and the vertical axis represents the interface state density. FIG. 7 shows the case where POA is in a 100% ammonia gas atmosphere (NH ₃ annealing). FIG. 8 shows a case where POA is performed in a 100% ammonia gas atmosphere after a 100% N ₂ O gas atmosphere (N ₂ O annealing + NH ₃ annealing). FIG. 9 shows a case where wet oxidation at 900 ° C. is performed after dry oxidation, and then POA is performed in a 100% ammonia gas atmosphere (wet oxidation + NH ₃ annealing).

  In either case, the interface state density is lowered by POA in an ammonia gas atmosphere. In particular, when the POA is performed at a high temperature, the interface state density is significantly reduced.

FIG. 10 is a diagram showing the MISFET characteristics of the present embodiment. Figure 10 (a) is inverted channel mobility NH ₃ annealing temperature dependence of, and FIG. 10 (b) is NH ₃ annealing temperature dependency of the drain current. Data are shown for cases where the POA after dry oxidation is NH ₃ annealing, the POA after dry oxidation is N ₂ O annealing + NH ₃ annealing, and wet oxidation + NH ₃ annealing is performed after dry oxidation.

In particular, when POA is N ₂ O annealing + NH ₃ annealing and when wet oxidation + NH ₃ annealing is performed, an increase in inversion channel mobility and an increase in drain current are remarkable. Thus, N ₂ O annealing or wet oxidation is preferably performed between dry oxidation and NH ₃ annealing from the viewpoint of improving the characteristics of the MISFET.

Even when N ₂ O annealing or wet oxidation is performed between dry oxidation and NH ₃ annealing, the minimum concentration of nitrogen in the gate insulating film is 1 × 10 ²⁰ atoms / cm ³ or more. That is, the same nitrogen concentration distribution as shown in FIG. 5 is realized.

FIG. 11 is a diagram showing the effective relative dielectric constant of the gate insulating film in the present embodiment. The data shows the case where the POA after dry oxidation is NH ₃ annealing, the POA after dry oxidation is N ₂ O annealing + NH ₃ annealing, and the case where wet oxidation + NH ₃ annealing is performed after dry oxidation.

In either case, the effective relative permittivity increases as the NH ₃ annealing temperature increases. As described above, since the effective relative permittivity is increased, the driving capability of the MISFET can be improved. Alternatively, it is possible to improve the reliability of the gate insulating film by increasing the thickness of the gate insulating film while maintaining the drive capability of the MISFET.

As is clear from FIG. 11, the effective relative permittivity rises remarkably when wet oxidation + NH ₃ annealing is performed after dry oxidation. Therefore, from the viewpoint of improving the effective relative dielectric constant, it is desirable to perform wet oxidation + NH ₃ annealing after dry oxidation.

FIG. 12 is a diagram showing TDDB characteristics of the gate insulating film of the present embodiment. 12A shows a case where the POA after dry oxidation is 1200 ° C. and 100% NH ₃ annealing, and FIG. 12B shows a case where 900 ° C. wet oxidation + 1200 ° C. and 100% NH ₃ annealing is performed after dry oxidation. . For comparison, a case where NH ₃ annealing is not performed is also shown.

All are the results of constant current TDDB (Time Dependent Dielectric Breakdown) measurement at room temperature. The stress current density is evaluated as 7 mA / cm ² . Al is used for the gate electrode. In either case, the Weibull distribution curve is distributed on the high Qbd side as compared with the case where NH ₃ annealing is not performed. Therefore, it can be seen that NH ₃ annealing improves the reliability of the gate insulating film.

  As described above, a gate insulating film in which nitrogen is uniformly distributed at a high concentration is realized by POA using ammonia gas not containing oxygen atoms. Therefore, a MISFET having a low on-resistance and excellent reliability is realized.

  In addition, when 100% ammonia gas is used, for example, there is an advantage that there is less risk of explosion and safety and industrial productivity are superior compared to annealing in which oxygen gas and ammonia gas are mixed.

In addition, if the temperature at which the ammonia gas is purged is appropriately controlled during the NH ₃ annealing, hydrogen in the ammonia gas may cause unbonded species present in the interface between the gate insulating film and the SiC layer and in the gate insulating film. It becomes possible to control the degree of hydrogen termination. That is, if the purge is performed at a low temperature, the amount of termination increases, and if the purge is performed at a high temperature, the termination amount decreases. Therefore, there is an advantage that the flat band shift amount can be made variable and the Vth of the MISFET can be controlled.

(Second Embodiment)
In the semiconductor device of the present embodiment, the gate insulating film is formed on the (000-1) plane of the SiC layer in the first embodiment, whereas the gate insulating film is formed on the (0001) plane of the SiC layer. The difference is that a film is formed. Except this point, the second embodiment is the same as the first embodiment. Accordingly, the description overlapping with the first embodiment is omitted.

  The semiconductor device of the present embodiment can be manufactured by the same method as that of the first embodiment except that the SiC layer is epitaxially grown on the (0001) plane of the SiC substrate.

13 and 14 show the SIMS analysis results of the nitrogen concentration of the gate insulating film of the semiconductor device of this embodiment. 13 shows the case where the POA after 1350 ° C. dry oxidation is 900 ° C. and 100% NH ₃ annealing, and FIG. 14 shows the case where the POA after 1350 ° C. dry oxidation is 1200 ° C. and 100% NH ₃ annealing. FIG. 15 shows the SIMS analysis result of the nitrogen concentration of the gate insulating film when POA is not performed.

When the POA is 900 ° C. or 1200 ° C., the minimum concentration of nitrogen in the film is 1 × 10 ²⁰ atoms / cm ³ or more. In addition, the nitrogen concentration distribution is relatively uniform in the depth direction of the film. In particular, in the case of 1200 ° C. or higher, the minimum concentration of nitrogen in the film is 1 × 10 ²¹ atoms / cm ³ or higher. The average concentration of nitrogen in the film is in the range of 1 × 10 ²¹ atoms / cm ^{3 to} 1 × 10 ²² atoms / cm ³ in any case.

FIG. 16 is a diagram showing the MISFET characteristics of the present embodiment. The gate insulating film of FIGS. 13 and 14 is used. As apparent from FIG. 16, the inversion channel mobility is improved by NH ₃ annealing.

FIG. 17 is a diagram showing TDDB characteristics of the gate insulating film of this embodiment. POA is 1200 ° C. after dry oxidation, compared to the case of 100% NH ₃ anneal, the POA 1350 ° C. after dry oxidation, after 100% _{N 2} O gas atmosphere, 1200 ° C., the case of the 100% NH ₃ annealing is doing.

Each film thickness is about 40 nm. It is a result of constant current TDDB (Time Dependent Dielectric Breakdown) measurement at room temperature. The stress current density is evaluated as 7 mA / cm ² . Al is used for the gate electrode.

In either case, a high Qbd value can be obtained, but the improvement in the reliability of the gate insulating film is particularly remarkable when POA is N ₂ O annealing + NH ₃ annealing. Therefore, when forming a gate insulating film on the (0001) plane of the SiC layer, an oxynitride film is formed by dry oxidation and N ₂ O oxynitridation after dry oxidation, and then contains ammonia gas. It is desirable to perform heat treatment in an atmosphere. Although not shown in FIG. 17, Qbd when POA is not performed is about two orders of magnitude lower than when POA is 1200 ° C. and 100% NH ₃ annealing.

(Third embodiment)
The semiconductor device according to the present embodiment is a vertical MISFET in which the gate insulating film and the gate electrode are provided on the (11-20) surface on the side surface of the trench (trench) formed in the SiC layer. The form is different. Except for this point, the second embodiment is the same as the first embodiment. Accordingly, the description overlapping with the first embodiment is omitted.

  FIG. 18 is a cross-sectional view showing a configuration of a MISFET which is a semiconductor device of the present embodiment. As shown in the figure, the gate insulating film 28 of the MISFET 200 is provided on the side surface of the trench provided in the SiC layer 14. The trench side surface is the (11-20) plane. A gate electrode 30 is formed on the gate insulating film 28 so as to be embedded in the trench.

Also in the MISFET 200, the interface state between the gate insulating film and the SiC layer can be reduced by setting the minimum concentration of nitrogen in the gate insulating film mainly containing silicon, oxygen, and nitrogen to 1 × 10 ²⁰ atoms / cm ³ or more. And the mobility of the carrier is improved. Therefore, a MISFET with low on-resistance and high driving power is realized. Further, the reliability of the gate insulating film is improved, and a highly reliable MISFET is realized. Further, by providing the channel region on the side surface of the trench, the MISFET can be miniaturized.

The gate insulating film 28 having a minimum nitrogen concentration of 1 × 10 ²⁰ atoms / cm ³ or more can be formed by the manufacturing method described in the first or second embodiment.

(Fourth embodiment)
In the first or second embodiment, the semiconductor device of the present embodiment is a p-type in contrast to the n-type SiC substrate, and constitutes an IGBT (Insulated Gate Bipolar Transistor). Since it is the same as that of 1st or 2nd Embodiment except the point from which the impurity type of a SiC substrate differs, the overlapping description is abbreviate | omitted.

FIG. 19 is a cross-sectional view showing a configuration of an IGBT which is a semiconductor device of the present embodiment. The IGBT 300 includes a SiC substrate 52 having first and second main surfaces. In FIG. 19, the first main surface is the upper surface of the drawing, and the second main surface is the lower surface of the drawing. The SiC substrate 52 is a hexagonal 4H—SiC substrate (p ⁺ substrate) having an impurity concentration of about 5 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ^{−3 and} containing, for example, Al as a p-type impurity.

Further, in the method of manufacturing the semiconductor device according to the present embodiment, the SiC substrate to be prepared is first or second except that the prepared SiC substrate is, for example, a hexagonal 4H—SiC substrate (p ⁺ substrate) containing Al as a p-type impurity. This is the same as the embodiment. Therefore, according to the semiconductor device of the present embodiment, an IGBT with low on-resistance and high driving power is realized. Further, the reliability of the gate insulating film is improved, and a highly reliable IGBT is realized. An IGBT having a low on-resistance and excellent reliability can be manufactured.

  The embodiments of the present invention have been described above with reference to specific examples. The above embodiment is merely given as an example, and does not limit the present invention. In the description of the embodiment, the description of the semiconductor device, the method for manufacturing the semiconductor device, etc., which is not directly necessary for the description of the present invention is omitted. Elements relating to the manufacturing method and the like can be appropriately selected and used.

For example, in the embodiment, the annealing in a 100% ammonia gas atmosphere has been described as an example, but the annealing may be performed by diluting the ammonia gas with, for example, N ₂ gas.

In the embodiment, the case where N ₂ O gas is used as the nitrogen oxide gas has been described as an example. However, NO gas, NO ₂ gas, or the like can also be used.

In addition, the oxide film before the ammonia annealing is not limited to the formation by dry oxidation or wet oxidation by a pyrological method, but can be formed by, for example, a wet oxidation method by bubbling H ₂ O, a CVD method, a sputtering method, an ALD method, or the like. It does not matter. Further, the oxynitride film before the ammonia annealing is not limited to the formation by dry oxidation and oxynitridation with nitrogen oxide gas, but may be formed by CVD, sputtering, ALD, or the like.

  In the embodiment, the n-type MOSFET and the n-type IGBT using electrons as carriers have been described. However, the present invention can also be applied to a p-type MOSFET and p-type IGBT using holes as carriers.

  In addition, although the case where polysilicon is used as a material for the gate electrode has been described as an example, a stacked structure of other semiconductors, metals, metal silicides, or materials selected from these can be applied.

  In addition, the scope of the present invention includes all semiconductor devices that include the elements of the present invention and that can be appropriately modified by those skilled in the art and methods for manufacturing the semiconductor devices. The scope of the present invention is defined by the appended claims and equivalents thereof.

12 Silicon carbide substrate 14 n ⁻ layer 16 p well region 18 source region 20 p well contact region 24 source / p well common electrode 28 gate insulating film 28a oxide film 30 gate electrode 32 interlayer insulating film 36 drain electrode 100 MISFET
200 MISFET
300 IGBT

Claims (10)

A silicon carbide layer;
A gate insulating film formed on the silicon carbide layer, the main component of which is silicon, oxygen, and nitrogen, and the minimum concentration of nitrogen is 1 × 10 ²⁰ atoms / cm ³ or more;
A semiconductor device comprising a gate electrode formed on the gate insulating film.   2. The semiconductor device according to claim 1, wherein the gate insulating film is formed on a (000-1) plane or a (0001) plane of the silicon carbide layer.   The semiconductor device according to claim 1, wherein the gate insulating film is formed on a (11-20) surface of a groove side surface formed in the silicon carbide layer.   The semiconductor device according to claim 1, wherein the gate insulating film is a gate insulating film of MISFET or IGBT.   5. The semiconductor device according to claim 1, wherein the gate insulating film has a thickness of 30 nm to 100 nm. Forming an oxide film or an oxynitride film on the (000-1) or (11-20) plane of the silicon carbide layer;
Forming a gate insulating film by heat treatment in an atmosphere containing ammonia gas after forming the oxide film or the oxynitride film;
A method for manufacturing a semiconductor device, comprising: forming a gate electrode on the gate insulating film.   The method of manufacturing a semiconductor device according to claim 6, wherein the oxide film is formed by dry oxidation and wet oxidation after the dry oxidation.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the formation of the oxynitride film is performed by dry oxidation and oxynitridation with a nitrogen oxide gas after the dry oxidation. Forming an oxynitride film on the (0001) surface of the silicon carbide layer by dry oxidation and oxynitridation with nitrogen oxide gas after the dry oxidation;
After the formation of the oxynitride film, heat treatment in an atmosphere containing ammonia gas to form a gate insulating film;
A method for manufacturing a semiconductor device, comprising: forming a gate electrode on the gate insulating film. The method for manufacturing a semiconductor device according to claim 6, wherein the heat treatment is performed at a temperature of 800 ° C. or higher and 1350 ° C. or lower.