JP2016181672A - Semiconductor device, semiconductor device manufacturing method, inverter circuit, driving device, vehicle and lift - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which an interface state on a SiC surface is reduced.SOLUTION: A semiconductor device of an embodiment comprises: a SiC layer having a first surface; an insulation layer; and a region between the first surface of the SiC layer and the insulation, which contains at least one element of a group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium) and Ba (barium), and a full width at half maximum of a concentration peak of the element is 1 nm or less, and when assuming that a surface density on the first surface of Si (silicon) and C (carbon) which have a bond not to be coupled with Si (silicon) or C (carbon) in the SiC layer is defined as a first surface density, a second surface density which is a surface density of the element is equal to or less than half the first surface density.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a conductor device, a method for manufacturing a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator.

  SiC (silicon carbide) is expected as a material for next-generation semiconductor devices. Compared with Si (silicon), SiC has excellent physical properties such as a band gap of 3 times, a breakdown electric field strength of about 10 times, and a thermal conductivity of about 3 times. By utilizing this characteristic, it is possible to realize a semiconductor device capable of operating at high temperature with low loss.

  However, for example, when a MIS (Metal Insulator Semiconductor) structure is formed using SiC, the density of interface states existing between the semiconductor and the insulating layer is larger than that of Si. For this reason, there is a problem that the mobility of charges is lowered, and the on-resistance of MISFET (Metal Insulator Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) is increased.

  Further, for example, when an SBD (Schottky Barrier Diode) is manufactured by providing a metal electrode on SiC, Fermi level pinning occurs due to an interface state existing between SiC and the metal electrode. For this reason, there exists a problem that a desired characteristic cannot be implement | achieved as SBD.

Special table 2014-523131 gazette

  The problem to be solved by the present invention is to provide a semiconductor device, a semiconductor device manufacturing method, an inverter circuit, a driving device, a vehicle, and an elevator in which the interface state on the SiC surface is reduced.

  The semiconductor device according to the embodiment includes at least one member selected from the group consisting of a SiC layer having a first surface, an insulating layer, Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium). Si having a bond that contains two elements, the full width at half maximum of the concentration peak of the element is 1 nm or less, and does not bond to either Si (silicon) or C (carbon) in the SiC layer on the first surface. When the surface density of silicon and C (carbon) is the first surface density, the second surface density, which is the surface density of the element, is less than or equal to ½ of the first surface density. A region between the first surface of the layer and the insulating layer.

1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment. It is a figure which shows the crystal structure of the SiC semiconductor of 1st Embodiment. In the manufacturing method of the semiconductor device of a 4th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 4th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 4th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 4th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 4th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 4th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 5th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 5th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 5th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 6th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 6th embodiment, it is a schematic cross section showing a semiconductor device in the middle of manufacture. It is a schematic cross section which shows the semiconductor device of 7th Embodiment. It is a schematic cross section which shows the semiconductor device of 8th Embodiment. It is a schematic cross section which shows the semiconductor device of 9th Embodiment. It is a schematic cross section showing a semiconductor device of a 10th embodiment. It is a schematic cross section which shows the semiconductor device of 11th Embodiment. It is a schematic cross section which shows the semiconductor device of 12th Embodiment. It is a schematic cross section which shows the semiconductor device of 13th Embodiment. It is a schematic cross section which shows the semiconductor device of the modification of 13th Embodiment. It is a schematic cross section which shows the semiconductor device of 14th Embodiment. It is a schematic cross section which shows the semiconductor device of the modification of 14th Embodiment. It is a schematic cross section which shows the semiconductor device of 15th Embodiment. It is a schematic diagram of the drive device of 16th Embodiment. It is a schematic diagram of the vehicle of 17th Embodiment. It is a schematic diagram of the vehicle of 18th Embodiment. It is a schematic diagram of the elevator of 19th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same members and the like are denoted by the same reference numerals, and the description of the members and the like once described is omitted as appropriate.

In the following description, the notations n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ represent the relative level of impurity concentration in each conductivity type. That is, n ⁺ indicates that the n-type impurity concentration is relatively higher than n, and n ⁻ indicates that the n-type impurity concentration is relatively lower than n. Further, p ⁺ indicates that the p-type impurity concentration is relatively higher than p, and p ⁻ indicates that the p-type impurity concentration is relatively lower than p. In some cases, n ⁺ type and n ⁻ type are simply referred to as n type, p ⁺ type and p ⁻ type as simply p type.

(First embodiment)
The semiconductor device of the present embodiment is provided between a SiC layer having a first surface, an insulating layer, and the first surface of the SiC layer and the insulating layer, and includes Be (beryllium), Mg (magnesium), and Ca. (Calcium), Sr (strontium), Ba (barium) at least one element selected from the group, the full width at half maximum of the concentration peak of the element is 1 nm or less, Si (silicon) in the first surface Alternatively, when the surface density of Si (silicon) and C (carbon) not bonded to any of C (carbon) is the first surface density, the second surface density that is the surface density of the element is the first surface density. And a region that is less than or equal to ½ of.

  Hereinafter, for convenience, the region is referred to as an interface region. For convenience, the element contained in the interface region is referred to as a termination element.

  FIG. 1 is a schematic cross-sectional view showing the configuration of a MISFET that is a semiconductor device of the present embodiment. The MISFET 100 is a Double Implantation MOSFET (DIMOSFET) in which a p-well and a source region are formed by ion implantation.

The MISFET 100 includes an n ⁺ type SiC substrate 12. In this specification, the upper surface in FIG. 1 is referred to as the front surface, and the lower surface in FIG.

The SiC substrate 12 is, for example, a 4H—SiC SiC substrate having an impurity concentration of 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²⁰ cm ^{−3 and} containing, for example, N (nitrogen) as an n-type impurity.

  FIG. 2 is a diagram showing a crystal structure of the SiC semiconductor. A typical crystal structure of the SiC semiconductor is a hexagonal system such as 4H—SiC. One of the surfaces (the top surface of the hexagonal column) whose normal is the c-axis along the axial direction of the hexagonal column is the (0001) surface. A plane equivalent to the (0001) plane is referred to as a silicon plane and expressed as a {0001} plane. Si (silicon) is arranged on the silicon surface.

  The other side of the surface (the top surface of the hexagonal column) having the c-axis along the axial direction of the hexagonal column as a normal is the (000-1) plane. A plane equivalent to the (000-1) plane is referred to as a carbon plane and expressed as a {000-1} plane. C (carbon) is arranged on the carbon surface

  On the other hand, the side surface (column surface) of the hexagonal column is an m-plane that is a plane equivalent to the (1-100) plane, that is, the {1-100} plane. A plane passing through a pair of ridge lines that are not adjacent to each other is an a plane that is equivalent to the (11-20) plane, that is, a {11-20} plane. Both Si (silicon) and C (carbon) are arranged on the m-plane and the a-plane.

  Hereinafter, the case where the surface of SiC substrate 12 is a surface inclined by 0 ° or more and 30 ° or less with respect to the silicon surface and the back surface is a surface inclined by 0 ° or more and 30 ° or less with respect to the carbon surface will be described as an example.

On the surface of the SiC substrate 12, for example, an n ⁻ type drift layer (SiC layer) 14 having an n type impurity concentration of 5 × 10 ^{15 to} 2 × 10 ¹⁶ cm ⁻³ is formed. The drift layer 14 is, for example, a SiC epitaxial growth layer formed on the SiC substrate 12 by epitaxial growth.

  The surface (first surface) of the drift layer 14 is also a surface inclined at 0 ° or more and 30 ° or less with respect to the silicon surface. The thickness of the drift layer 14 is, for example, not less than 5 μm and not more than 100 μm.

For example, a p-type p-well region (SiC layer) 16 having a p-type impurity impurity concentration of 5 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less is formed on a partial surface of the drift layer 14. Yes. The depth of the p well region 16 is, for example, about 0.6 μm. The p well region 16 functions as a channel region of the MISFET 100.

An n ⁺ -type source region 18 having an n-type impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ cm ⁻³ or less, for example, is formed on a partial surface of the p-well region 16. . The depth of the source region 18 is shallower than the depth of the p-well region 16 and is, for example, about 0.3 μm.

Further, on the surface of a part of the p-well region 16 and on the side of the source region 18, for example, a p ⁺ -type impurity having a p-type impurity impurity concentration of 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²² cm ^−3. P well contact region 20 is formed. The depth of the p well contact region 20 is shallower than the depth of the p well region 16 and is, for example, about 0.3 μm.

  A gate insulating layer (insulating layer) 28 is formed on the surface (first surface) of the drift layer 14 and the p-well region 16 so as to straddle these layers and regions. For the gate insulating layer 28, for example, a silicon oxide film, a silicon oxynitride film, or a high-k insulating film can be applied. From the viewpoint of suppressing the leakage current of the gate insulating layer 28, it is desirable to apply a silicon oxide film having a larger band gap as compared with the high-k insulating film.

Further, if C (carbon) is excessively present in the gate insulating layer 28, the density of trap levels that adversely affect device characteristics may increase. Therefore, it is desirable that the concentration of C (carbon) in the gate insulating layer 28 is 1 × 10 ¹⁸ cm ⁻³ or less.

  A gate electrode 30 is formed on the gate insulating layer 28. For example, doped polysilicon or the like can be applied to the gate electrode 30. On the gate electrode 30, an interlayer insulating film 32 made of, for example, a silicon oxide film is formed.

  A p-well region 16 sandwiched between the source region 18 and the drift layer 14 under the gate electrode 30 functions as a channel region of the MISFET 100.

  The gate insulating layer 28 is provided between the gate electrode 30 and the drift layer 14. An interface region 40 is provided between the drift layer 14 and the gate insulating layer 28.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  The termination element is segregated at the interface between the drift layer 14 and the gate insulating layer 28. The full width at half maximum of the concentration peak of the terminal element is 1 nm or less. The full width at half maximum of the concentration peak is desirably 0.5 nm or less, and more desirably less than 0.2 nm.

  The interface region 40 is preferably a monoatomic layer.

  The surface density of Si (silicon) and C (carbon) that does not bond to either Si (silicon) or C (carbon) on the surface (first surface) of the drift layer (SiC layer) 14 is defined as the first surface density. . Further, the surface density of the termination element is set to the second surface density. The second surface density is ½ or less of the first surface density.

  It is desirable that the second surface density is 1/120 or less of the first surface density. Further, it is desirable that the second surface density is 1/12000 or more of the first surface density.

The peak of the concentration of the termination element in the interface region 40 is desirably 5 × 10 ¹⁸ cm ⁻³ or more. Moreover, it is more desirable that it is 1 × 10 ¹⁹ cm ⁻³ or more.

The concentration of the termination element in the gate insulating layer (insulating layer) 28 is desirably 1 × 10 ¹⁸ cm ⁻³ or less. Although the concentration of the termination element in the insulating layer can be confirmed by SIMS, it is more preferably below the detection limit of each termination element (approximately 1 × 10 ¹⁷ cm ⁻³ or less). The concentration of the termination element in the gate insulating layer 28 is, for example, a concentration at a position away from the peak of the termination element concentration in the interface region 40 by 1 nm or more.

  The MISFET 100 includes a conductive source electrode 34 that is electrically connected to the source region 18 and the p-well contact region 20. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16.

  The source electrode 34 is constituted by, for example, a laminate of a Ni (nickel) barrier metal layer and an Al (aluminum) metal layer on the barrier metal layer. The Ni barrier metal layer and the Al metal layer may form an alloy by reaction.

  In addition, a conductive drain electrode 36 is formed on the side opposite to the drift layer 14 of the SiC substrate 12, that is, on the back surface side. The drain electrode 36 is, for example, Ni (nickel).

  In this embodiment, the n-type impurity is preferably N (nitrogen) or P (phosphorus), for example, but As (arsenic) or Sb (antimony) can also be applied. For example, Al (aluminum) is preferable as the p-type impurity, but B (boron), Ga (gallium), In (indium), or the like can also be applied.

  Hereinafter, the operation and effect of the semiconductor device of this embodiment will be described.

  One of the reasons why high mobility cannot be realized in the SiC MIS structure is considered to be that interface Si (silicon) or C (carbon) dangling bonds are not terminated and interface states are formed. . As a result of the first-principles calculation by the inventors, an element selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium), which are alkaline earth metals ( It was revealed that the dangling bonds on the surface of the SiC layer can be stably terminated by the termination element.

  More specifically, for example, when the element is present in a laminated structure of an SiC layer and a silicon oxide film, the element is present in the SiC layer rather than being present in the SiC layer or the silicon oxide film. It has been found that it is more energetically stable to bond to the surface of the SiC layer with the exchange of electrons with Si (silicon) or C (carbon) on the surface. Since one of the above elements is divalent, it is bonded to the SiC layer surface by exchanging electrons with two Si or C adjacent on the SiC layer surface. However, in order to create a structure in which the termination element is segregated only at the laminated interface between the SiC layer and the silicon oxide film, it is necessary to devise processes as described later.

  The bonding state between the element and Si or C can be confirmed by XPS (X-ray Photoelectron Spectroscopy) measurement or the like.

  In the present embodiment, the surface of the SiC layer is terminated with at least one element selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium). Accordingly, the interface state at the interface of the MIS structure is reduced, and high mobility can be obtained in the channel portion. Therefore, a MISFET having a low on-resistance can be realized.

  FIG. 3 is a diagram illustrating an example of a band diagram of the semiconductor device of the present embodiment. A band diagram when the silicon surface of the SiC semiconductor is terminated with Sr (strontium) is obtained by the first principle calculation.

  As shown in FIG. 3, when Sr is bonded to Si, the dangling bond of Si is terminated, and the interface state caused by the dangling bond in the mid gap between the valence band and the conduction band is eliminated. . And the band gap energy has recovered the band gap energy of bulk 4H-SiC.

  Further, according to the first principle calculation, the termination element of this embodiment has a termination structure that is more stable in terms of energy than, for example, H (hydrogen) or N (nitrogen), which are known to terminate dangling bonds. It has been found that it can be formed. Therefore, for example, even if a high-temperature process is performed during manufacturing, generation of dangling bonds due to the dissociation of the termination element is unlikely to occur.

  When oxidizing the surface of the SiC layer, oxygen attacks the Si back bond, resulting in roughness of the interface between the SiC and the oxide film, which may reduce the reliability of the gate insulating layer. Further, C (carbon) may diffuse into the oxide film during oxidation, which may increase leakage current and decrease reliability. In addition, C (carbon) vacancies are generated in the SiC layer during oxidation to form trap levels, which may reduce the mobility of the MISFET.

  According to the present embodiment, the outermost surface of the SiC layer is terminated by the above termination element, and the stable interface region 40 is formed. When the stable interface region 40 exists, further oxidation of the SiC layer is suppressed even when exposed to an oxidizing atmosphere. Therefore, the roughness of the interface and the diffusion of C (carbon) into the oxide film are suppressed. Therefore, an increase in leakage current of the gate insulating layer and a decrease in reliability are suppressed. Further, the formation of C (carbon) vacancies is also suppressed, and the decrease in mobility of the MISFET is also suppressed.

  On the other hand, if there is an excessive termination element that does not bond to the surface of the SiC layer, the termination element diffuses into the insulating layer. For example, when the insulating layer is a silicon oxide film, a silicate or oxide of a termination element is formed in the silicon oxide film. Since the silicate of the termination element and the oxide of the termination element in the insulating layer have a small band offset, a trap level may be formed and the reliability of the insulating layer may be reduced.

  Therefore, it is not desirable that the termination element is present in an amount larger than the amount bonded to the SiC layer at the interface between the SiC layer and the insulating layer because the device characteristics are deteriorated.

  As described above, the termination element of the present embodiment is bonded to the surface of the SiC layer by exchanging electrons between two Si or C. For this reason, on the surface of the SiC layer, the termination element cannot bond more than half of the number of Si or C that can be provided with dangling bonds.

  Therefore, it is desirable that the second surface density of the termination element is ½ or less of the first surface density from the viewpoint of preventing an excessive termination element from being present. In other words, it is desirable that the second surface density of the termination element is not greater than ½ of the first surface density. Here, the first surface density is the surface density of Si (silicon) and C (carbon) that do not bond to either Si (silicon) or C (carbon) on the surface (first surface) of the SiC layer. In other words, it is the surface density of Si or C that can have dangling bonds on the surface (first surface) of the SiC layer.

For example, consider a case where the surface (first surface) of the drift layer 14 is a silicon surface. The surface density of Si (silicon) or C (carbon) appearing on the surface of the silicon surface is 2.4 × 10 ¹⁵ cm ⁻² . On the silicon surface, C (carbon) on the surface is all bonded to Si (silicon). Therefore, in the case of the silicon surface, since only Si does not bond to either Si or C, the first surface density is halved to 1.2 × 10 ¹⁵ cm ⁻² . Therefore, it is desirable that the second surface density is 0.6 × 10 ¹⁵ cm ⁻² or less, that is, 6 × 10 ¹⁴ cm ⁻² or less.

If the thickness of the interface region is 0.2 nm, the surface density of 6 × 10 ¹⁴ cm ⁻² corresponds to 3 × 10 ²² cm ⁻³ in volume density. Therefore, the peak concentration of the termination element is desirably 3 × 10 ²² cm ⁻³ or less.

The interface state density on the surface of the SiC layer is about 1 × 10 ¹⁴ cm ⁻² or less. In this case, if one terminal element terminates one interface state, the upper limit of the terminal element is 1 × 10 ¹⁴ cm ⁻² . This is 1/12 of 1.2 × 10 ¹⁵ cm ⁻² that is the first surface density of the silicon surface. Therefore, it is desirable that the second surface density is 1/12 or less of the first surface density. Moreover, it is desirable that the second surface density is 1 × 10 ¹⁴ cm ⁻² or less.

If the thickness of the interface region is 0.2 nm, the surface density of 1 × 10 ¹⁴ cm ⁻² corresponds to 5 × 10 ²¹ cm ⁻³ in volume density. Therefore, the peak concentration of the termination element is preferably 5 × 10 ²¹ cm ⁻³ or less.

In general, the interface state density on the surface of the SiC layer is about 1 × 10 ¹³ cm ⁻² . In this case, if one terminal element terminates one interface state, the upper limit of the terminal element is 1 × 10 ¹³ cm ⁻² . This is 1/120 of 1.2 × 10 ¹⁵ cm ⁻² which is the first surface density of the silicon surface. Therefore, it is desirable that the second surface density is 1/120 or less of the first surface density. Moreover, it is desirable that the second surface density is 1 × 10 ¹³ cm ⁻² or less.

If the thickness of the interface region is 0.2 nm, the surface density of 1 × 10 ¹³ cm ⁻² corresponds to 5 × 10 ²⁰ cm ⁻³ in volume density. Therefore, the peak concentration of the termination element is desirably 5 × 10 ²⁰ cm ⁻³ or less.

Further, in order to realize the termination effect by the above elements, it is sufficient that at least one of ten interface states considered to be present can be terminated by the above termination element. Therefore, it is desirable that the second surface density is 1/1200 or more of the first surface density. Further, it is desirable that the second surface density is 1 × 10 ¹² cm ⁻² or more.

If the thickness of the interface region is 0.2 nm, the surface density of 1 × 10 ¹² cm ⁻² corresponds to 5 × 10 ¹⁹ cm ⁻³ in volume density. Therefore, the peak concentration of the termination element is desirably 5 × 10 ¹⁹ cm ⁻³ or more.

Further, in order to realize the termination effect by the above elements, it is desirable that at least one of 100 interface states considered to be present be terminated by the above termination element. Therefore, it is desirable that the second surface density is 1/12000 or more of the first surface density. The second surface density is desirably 1 × 10 ¹¹ cm ⁻² or more.

If the thickness of the interface region is 0.2 nm, the surface density of 1 × 10 ¹¹ cm ⁻² corresponds to 5 × 10 ¹⁸ cm ⁻³ in volume density. Therefore, the peak concentration of the termination element is preferably 5 × 10 ¹⁸ cm ⁻³ or more.

  The first surface density can be calculated geometrically if the surface orientation of the surface (first surface) of the SiC layer is determined. The second surface density can be obtained by, for example, SIMS (Secondary Ion Mass Spectrometry). For example, the second areal density is a value obtained by dividing the amount of the termination element in the interface region counted by SIMS (Secondary Ion Mass Spectrometry) by the beam area of incident ions.

In addition, from the viewpoint of suppressing the presence of a termination element in the insulating layer and deteriorating device characteristics, the concentration of the termination element in the insulating layer is desirably 1 × 10 ¹⁸ cm ⁻³ or less. Although the concentration of the termination element in the insulating layer can be confirmed by SIMS, it is more preferably below the detection limit of each termination element (approximately 1 × 10 ¹⁷ cm ⁻³ or less).

  In addition, the interface region 40 is preferably a monoatomic layer from the viewpoint of suppressing the deterioration of device characteristics due to the presence of the termination element in the insulating layer.

  The monoatomic layer means a state in which the terminal element has only one atomic layer on the SiC surface. When the interface region 40 is a monoatomic layer, the physical film thickness of the interface region 40 is one atom or less. Specifically, it is less than 0.2 nm.

  When the interface region 40 is a monoatomic layer, the number of termination elements matches the number of Si (silicon) and C (carbon) that are not bonded to either Si (silicon) or C (carbon) on the surface of the SiC layer. That is, when the first surface density and the second surface density are equal, the interface region 40 is defined as one monolayer (1ML). When the interface region 40 is a monoatomic layer, the second surface density is half of the first surface density, so the interface region 40 is ½ monolayer or less. The interface region 40 is desirably 1/120 monolayer or less. The interface region 40 is preferably 1/12000 monolayer or more.

  Note that an interface state that is not terminated with a termination element may be terminated with H (hydrogen), N (nitrogen), or F (fluorine). Therefore, the interface region 40 may contain H (hydrogen), N (nitrogen), or F (fluorine).

  Of the terminal elements, the element with the larger atomic radius is more stably bonded to the SiC layer surface. Therefore, from the viewpoint of realizing a stable termination structure, it is desirable that the termination element is Ba (barium) or Sr (strontium). On the other hand, from the viewpoint of reducing the manufacturing cost of the semiconductor device, it is desirable that the terminal elements are Mg (magnesium) and Ca (calcium), which are inexpensive elements.

  Note that the surface (first surface) of the drift layer 14 is desirably a surface that is inclined at 0 ° or more and 8 ° or less with respect to the silicon surface.

  As described above, according to the present embodiment, the interface state between the SiC layer and the gate insulating layer is reduced, and a MISFET having high mobility is realized. And the roughness between the interfaces between the SiC layer and the gate insulating layer is reduced. Further, the concentration of the termination element in the gate insulating layer is suppressed. Therefore, the leakage current of the gate insulating layer is reduced and the reliability of the gate insulating layer is improved. Therefore, the MISFET 100 having high operating performance and high reliability is realized.

(Second Embodiment)
In the semiconductor device of this embodiment, the surface (first surface) of the drift layer (SiC layer) is a surface inclined at 0 ° or more and 30 ° or less with respect to the carbon surface ((000-1) surface). This is different from the first embodiment. The description overlapping with that of the first embodiment is omitted.

  The configuration of the MISFET of this embodiment is the same as that shown in FIG. Hereinafter, the MISFET of this embodiment will be described with reference to FIG.

  In the MISFET of this embodiment, the surface of the SiC substrate 12 and the surface (first surface) of the drift layer (SiC layer) 14 are inclined by 0 ° or more and 30 ° or less with respect to the carbon surface ((000-1) surface). It is.

  An interface region 40 is provided at the interface between the drift layer (SiC layer) 14 and the gate insulating layer (insulating layer) 28. The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  On the carbon surface, the surface Si (silicon) is all bonded to C (carbon). Therefore, in the case of a carbon surface, only C does not bond to either Si or C. Therefore, only C can form a dangling bond.

  From the first-principles calculation by the inventor, it has been found that the termination element is more stable to bond with C than to Si. Therefore, according to the present embodiment, a MISFET including the interface region 40 that is more stable than the first embodiment is realized.

  Note that the surface of the drift layer 14 is desirably a surface inclined by 0 ° or more and 8 ° or less with respect to the carbon surface from the viewpoint of realizing a more stable interface region 40.

(Third embodiment)
The semiconductor device of this embodiment differs from that of the first embodiment in that the surface (first surface) of the drift layer (SiC layer) is a surface inclined at 0 ° or more and 30 ° or less with respect to the <0001> direction. ing. The description overlapping with that of the first embodiment is omitted.

  In the MISFET of the present embodiment, the surface of the SiC substrate 12 and the surface (first surface) of the drift layer (SiC layer) 14 are surfaces that are inclined at 0 degree or more and 30 degrees or less with respect to the <0001> direction. For example, the surface of the drift layer 14 is an a plane or an m plane. Note that the <0001> direction includes the [0001] direction and the [000-1] direction.

  An interface region 40 is provided at the interface between the drift layer 14 and the gate insulating layer (insulating layer) 28. The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  On the surface inclined at 0 ° or more and 30 ° or less with respect to the <0001> direction, both Si (silicon) and C (carbon) can form dangling bonds.

  As described in the second embodiment, it has been found that the termination element is more stable when bonded to C than to Si. On the other hand, for example, when the gate insulating layer 28 is an oxide film, Si is more strongly bonded to oxygen than C.

  Therefore, according to the present embodiment, the termination element is bonded to C, so that an interface region 40 that is more stable than that of the first embodiment is realized, and the bonding between the SiC layer and the gate oxide film 28 is also Si. It is stabilized by the combination of oxygen. Therefore, a MISFET with stable device characteristics is realized.

  Note that the surface of the drift layer 14 is desirably a surface inclined at 0 ° or more and 8 ° or less with respect to the <0001> direction.

(Fourth embodiment)
The manufacturing method of the semiconductor device of the present embodiment has at least one selected from the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium) on the first surface of the SiC layer. Ions of one element are implanted, a thermal oxide film is formed on the first surface of the SiC layer, the thermal oxide film is peeled off, and a first insulating layer is formed on the first surface of the SiC layer. The manufacturing method of the semiconductor device of this embodiment is an example of the manufacturing method of the semiconductor device shown in the first embodiment.

  4 to 8 are schematic cross-sectional views showing the semiconductor device being manufactured in the method for manufacturing the semiconductor device of the present embodiment.

First, an n ⁺ type SiC substrate 12 having a front surface that is a silicon surface and a rear surface that is a carbon surface is prepared. Next, an n ⁻ type drift layer (SiC layer) 14 is formed on the surface of SiC substrate 12 by an epitaxial growth method.

Next, a p-type p well region 16, an n ⁺ type source region 18 and a p ⁺ type p well contact region 20 are formed by a known photolithography method and ion implantation method.

  Next, at least one element selected from the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium) from the surface (first surface) of the drift layer 14 ( Ions are implanted into the drift layer 14 (FIG. 4). Hereinafter, Sr (strontium) will be described as an example of the termination element.

  Prior to the Sr ion implantation, for example, a cap film (second insulating layer) of an insulating film such as a silicon oxide film may be provided on the surface of the drift layer 14. By ion-implanting Sr through the cap film, it becomes easy to distribute Sr in the drift layer 14 after ion implantation near the surface of the drift layer 14.

  Next, a thermal oxide film 42 is formed on the drift layer 14 (FIG. 5). When the thermal oxide film 42 is formed, Sr introduced into the drift layer 14 by ion implantation segregates at the energetically stable interface between the drift layer 14 and the thermal oxide film 42 to form an interface region 40. More specifically, Sr is bonded to Si at the interface between the drift layer 14 and the thermal oxide film 42 and distributed at a high concentration at the interface.

  At this time, it is desirable to perform thermal oxidation so that almost all of Sr implanted into the drift layer 14 moves to the interface region 40 or the thermal oxide film 42. That is, it is desirable to change the entire region where Sr is implanted into the interface region 40 or the thermal oxide film 42 by thermal oxidation.

  The thermal oxidation is performed at a temperature of 900 ° C. or higher and 1100 ° C. or lower by dry oxidation, for example.

  Next, the thermal oxide film 42 is entirely removed by, for example, a known wet etching method (FIG. 6). The remaining interface region 40 is less than 0.2 nm.

  Next, a gate insulating layer (first insulating layer) 28 is formed on the interface region 40 on the surface side of the drift layer 14. The gate insulating layer 28 is a silicon oxide film formed by a deposition method such as LPCVD (Low Pressure Chemical Vapor Deposition).

  After forming the gate insulating layer 28, annealing for densification of the gate insulating layer 28 may be performed. Annealing is performed at a temperature of 1200 ° C. or higher and 1300 ° C. or lower in an inert gas atmosphere such as nitrogen or argon.

  Next, a gate electrode 30 is formed on the gate insulating layer 28 by a known method (FIG. 8). The gate electrode 30 is, for example, doped polysilicon formed by LPCVD.

  Thereafter, the interlayer insulating film 32, the source electrode 34, and the drain electrode 36 are formed by a known process, and the MISFET 100 of this embodiment shown in FIG. 1 is manufactured.

  In the manufacturing method according to the present embodiment, the thermal oxide film 42 is completely removed to remove carbon diffused in the thermal oxide film 42 and excess termination elements, and the trap level in the gate insulating layer 28 is reduced.

  By the manufacturing method of this embodiment, a MISFET having high operating performance and high reliability is realized.

(Fifth embodiment)
The manufacturing method of the semiconductor device of the present embodiment has at least one selected from the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium) on the first surface of the SiC layer. A first film containing one element is formed, and a first insulating layer is formed on the first surface of the SiC layer. The manufacturing method of the semiconductor device of this embodiment is an example of the manufacturing method of the semiconductor device shown in the first embodiment.

  9 to 11 are schematic cross-sectional views showing the semiconductor device being manufactured in the method for manufacturing the semiconductor device of the present embodiment.

First, an n ⁺ type SiC substrate 12 having a front surface that is a silicon surface and a rear surface that is a carbon surface is prepared. Next, n ⁻ type drift layer (SiC layer) 14 is formed on the first surface of SiC substrate 12 by epitaxial growth.

After forming drift layer 14 on SiC substrate 12, p-type p-well region 16, n ⁺ -type source region 18 and p ⁺ -type p-well contact region are formed by a known photolithography method and ion implantation method. 20 is formed. The steps up to this step are the same as in the fourth embodiment.

  Next, at least one element selected from the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium) is formed on the surface (first surface) of the drift layer 14. A termination element-containing film (first film) 44 including a termination element is formed (FIG. 9). The termination element-containing film 44 is, for example, a single film of the termination element. The single film is, for example, a metal film. Hereinafter, Sr (strontium) will be described as an example of the termination element.

  A single Sr film (Sr film) is formed as a termination element-containing film 44 on the surface of the drift layer 14. The Sr film is formed by, for example, a known sputtering method. The Sr film may be formed by vapor deposition or MBE (Molecular Beam Epitaxy).

  Next, the surface of the drift layer 14 is thermally oxidized to form a thermal oxide film 46 (FIG. 10). When the thermal oxide film 46 is formed, the Sr of the termination element-containing film 44 segregates at the interface between the energetically stable drift layer 14 and the thermal oxide film 46 to form the interface region 40. More specifically, Sr is combined with Si at the interface between the drift layer 14 and the thermal oxide film 46 and distributed at a high concentration at the interface.

  Next, the thermal oxide film 46 is completely removed by, for example, a known wet etching method (FIG. 11). The remaining interface region 40 is less than 0.2 nm.

  Next, as in the fourth embodiment, a gate insulating layer (first insulating layer) 28 is formed on the interface region 40 on the surface side of the drift layer 14. Further, the gate electrode 30 is formed on the gate insulating layer 28.

  Thereafter, the interlayer insulating film 32, the source electrode 34, and the drain electrode 36 are formed by a known process, and the MISFET 100 of this embodiment shown in FIG. 1 is manufactured.

  Instead of the thermal oxide film, a thermal oxynitride film may be formed by thermal oxynitridation.

  In the manufacturing method of this embodiment, the thermal oxide film 46 is completely removed to remove carbon diffused in the thermal oxide film 46 and excess termination elements, and the trap level in the gate insulating layer (insulating layer) 28 is removed. Reduce.

  In addition, the amount of Sr can be controlled by, for example, the MBE method so as not to generate an excessive termination element. For example, when the surface density of Si (silicon) and C (carbon) that do not bond to either Si (silicon) or C (carbon) on the first surface is the first surface density, the surface density of Sr. The amount of Sr is controlled so that the surface density of 2 is ½ or less of the first surface density. According to this method, the formation of a thermal oxide film or a thermal oxynitride film can be omitted.

  By the manufacturing method of this embodiment, a MISFET having high operating performance and high reliability is realized.

(Sixth embodiment)
The manufacturing method of the semiconductor device of this embodiment is different from that of the fifth embodiment in that the termination element-containing film 44 is a silicate film and that the SiC layer is not thermally oxidized. The manufacturing method of the semiconductor device of this embodiment is an example of the manufacturing method of the semiconductor device shown in the first embodiment.

  12 and 13 are schematic cross-sectional views showing a semiconductor device being manufactured in the method for manufacturing a semiconductor device of the present embodiment.

First, an n ⁺ type SiC substrate 12 having a front surface that is a silicon surface and a rear surface that is a carbon surface is prepared. Next, n ⁻ type drift layer (SiC layer) 14 is formed on the first surface of SiC substrate 12 by epitaxial growth.

After forming an n ⁻ type drift layer (SiC layer) 14 on the SiC substrate 12, a p type p well region 16, an n ⁺ type source region 18, and p are formed by a known photolithography method and ion implantation method. ^{A +} -type p-well contact region 20 is formed. The steps up to this step are the same as in the fifth embodiment.

  Next, at least one element selected from the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium) is formed on the surface (first surface) of the drift layer 14. A termination element-containing film (first film) 44 including a termination element is formed (FIG. 12). The film containing the termination element is a silicate film of the termination element. Hereinafter, Sr (strontium) will be described as an example of the termination element.

  A Sr silicate film (SrSiO film) is formed as a termination element-containing film 44 on the surface of the drift layer 14. The SrSiO film is formed by, for example, a known sputtering method.

  Next, the termination element-containing film 44 is removed by etching (FIG. 13). Etching is performed by a known dry etching method.

  When the termination element-containing film 44 is etched, Sr of the termination element-containing film 44 segregates on the surface of the drift layer 14 that is stable in terms of energy to form the interface region 40. More specifically, Sc is combined with Si on the surface of the drift layer 14 and distributed at a high concentration at the interface.

  The interface termination structure by the termination element is extremely stable in terms of energy. Accordingly, when Sr can move freely by etching of the termination element-containing film 44, the surface of the drift layer 14 is moved so as to form an interface termination structure. And Sr couple | bonds with a dangling bond and the state segregated to the interface is formed.

  Next, as in the fifth embodiment, a gate insulating layer (first insulating layer) 28 is formed on the interface region 40 on the surface side of the drift layer 14. Further, the gate electrode 30 is formed on the gate insulating layer 28.

  Thereafter, the interlayer insulating film 32, the source electrode 34, and the drain electrode 36 are formed by a known process, and the MISFET 100 of this embodiment shown in FIG. 1 is manufactured.

  By the manufacturing method of this embodiment, a MISFET having high operating performance and high reliability is realized.

(Seventh embodiment)
The semiconductor device of this embodiment is the same as that of the first embodiment except that it is a trench gate type MISFET. Therefore, description of the contents overlapping with those of the first embodiment is omitted.

  FIG. 14 is a schematic cross-sectional view showing the configuration of a MISFET that is a semiconductor device of the present embodiment. The MISFET 200 is a trench gate type MISFET in which a gate insulating layer and a gate electrode are provided in a trench.

The MISFET 200 includes an n ⁺ type SiC substrate 12 having a front surface and a back surface. In FIG. 14, the front surface is the upper surface of the drawing, and the back surface is the lower surface of the drawing. The surface of SiC substrate 12 is a surface inclined at an angle of 0 ° to 8 ° with respect to the silicon surface.

  The SiC substrate 12 is, for example, a 4H—SiC SiC substrate.

An n ⁻ type drift layer (SiC layer) 14 is formed on the surface of SiC substrate 12. The drift layer 14 is an epitaxial growth layer formed on the SiC substrate 12 by epitaxial growth, for example. The surface of the drift layer 14 is also a plane inclined at 0 ° or more and 8 ° or less with respect to the silicon surface.

  A p-type p-well region (SiC layer) 16 is formed on a partial surface of the drift layer 14. The p well region 16 functions as a channel region of the MISFET 200.

An n ⁺ type source region 18 is formed on a partial surface of the p well region 16. A p ⁺ -type p-well contact region 20 is formed on a partial surface of the p-well region 16 and on the side of the source region 18.

  Trench 50 is provided in the direction from the surface of drift layer 14 toward SiC substrate 12. The inner wall surface of the trench 50 is, for example, an m-plane or a-plane.

  A gate insulating layer (insulating layer) 28 formed so as to straddle these layers and regions continuously on the surface (first surface) of the drift layer 14, the p-well region 16 and the source region 18 in the trench 50. Have.

  A gate electrode 30 is formed on the gate insulating layer 28. The p-well region 16 sandwiched between the source region 18 and the drift layer 14 on the side surface of the trench 50 functions as a channel region of the MISFET 200.

  The gate insulating layer 28 is provided between the gate electrode 30 and the drift layer 14. An interface region 40 is provided at the interface between the drift layer 14 and the gate insulating layer 28. The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  A conductive source electrode 34 that is electrically connected to the source region 18 and the p-well contact region 20 is provided. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16. A conductive drain electrode 36 is formed on the side of the SiC substrate 12 opposite to the drift layer 14, that is, on the second surface side.

  According to the present embodiment, the presence of the interface region 40 can provide the same effect as that of the first embodiment. Furthermore, by adopting the trench gate structure, it is possible to improve the integration degree of MISFET and to reduce the conductive loss by eliminating the JFET region.

(Eighth embodiment)
The semiconductor device of this embodiment is the same as that of the first embodiment except that it is not a MISFET but an IGBT. Therefore, description of the contents overlapping with those of the first embodiment is omitted.

  FIG. 15 is a schematic cross-sectional view showing the configuration of the IGBT that is the semiconductor device of the present embodiment.

The IGBT 300 includes a p ⁺ type SiC substrate 112 having a front surface and a back surface. In FIG. 15, the front surface is the upper surface of the drawing, and the back surface is the lower surface of the drawing. The surface of SiC substrate 112 is a surface inclined at an angle of 0 ° to 8 ° with respect to the silicon surface.

An n ⁻ type drift layer (SiC layer) 14 is formed on the surface of SiC substrate 112. The drift layer 14 is, for example, an epitaxial growth layer formed by epitaxial growth on the SiC substrate 112. The surface (first surface) of the drift layer 14 is also a surface inclined at 0 ° or more and 8 ° or less with respect to the silicon surface.

  A p-type p-well region (SiC layer) 16 is formed on a partial surface of the drift layer 14. The p well region 16 functions as a channel region of the IGBT 300.

An n ⁺ -type emitter region 118 is formed on a partial surface of the p-well region 16.
A p ⁺ -type p-well contact region 20 is formed on a partial surface of the p-well region 16 and on the side of the emitter region 118.

  A gate insulating layer (insulating layer) 28 is formed on the surface of the drift layer 14 and the p-well region 16 so as to straddle these layers and regions.

  A gate electrode 30 is formed on the gate insulating layer 28. On the gate electrode 30, an interlayer insulating film 32 made of, for example, a silicon oxide film is formed.

  A p-well region 16 sandwiched between the source region 18 and the drift layer 14 under the gate electrode 30 functions as a channel region of the MISFET 100.

  The gate insulating layer 28 is provided between the gate electrode 30 and the drift layer 14. An interface region 40 is provided at the interface between the drift layer 14 and the gate insulating layer 28. The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  A conductive emitter electrode 134 that is electrically connected to the emitter region 118 and the p-well contact region 20 is provided. The emitter electrode 134 also functions as a p-well electrode that applies a potential to the p-well region 16.

  In addition, a conductive collector electrode 136 is formed on the side of the SiC substrate 112 opposite to the drift layer 14, that is, on the second surface side.

  According to the present embodiment, the presence of the interface region 40 makes it possible to obtain the same operations and effects as in the first embodiment. Therefore, the IGBT 300 having high operation performance and high reliability is realized.

(Ninth embodiment)
The semiconductor device of this embodiment is different from that of the first embodiment in that an interface region is provided in the termination region of the MISFET. The description overlapping with that of the first embodiment is omitted.

  FIG. 16 is a schematic cross-sectional view showing the configuration of a MISFET that is a semiconductor device of the present embodiment. The MISFET 400 includes an element region and a termination region provided around the element region. The termination region has a function of improving the breakdown voltage of the MISFET 400.

  In the element region, for example, the MISFET 100 of the first embodiment is arranged as a unit cell.

The termination region includes a p-type RESURF region (SiC layer) 60, a p ⁺ -type contact region 62, a p-type guard ring region (SiC layer) 64, a field oxide film (insulating layer) 33, and an interface region 40. The interface region 40 is provided between the surface (first surface) of the p-type RESURF region 60 and the p-type guard ring region 64 and the field oxide film 33.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

The field oxide film 33 is, for example, a silicon oxide film. The concentration of the termination element in the field oxide film 33 is desirably 1 × 10 ¹⁸ cm ⁻³ or less. The concentration of the termination element in the field oxide film 33 can be confirmed by SIMS, but it is more preferably below the detection limit of each termination element (approximately 1 × 10 ¹⁷ cm ⁻³ or less). The concentration of the termination element in the field oxide film 33 is, for example, a concentration at a position away from the peak of the concentration of the termination element in the interface region 40 by 1 nm or more.

  When the MISFET 400 is turned off, a depletion layer is formed in the drift layer 14 between the RESURF region 60, the guard ring region 64, and the guard ring region 64, whereby the breakdown voltage of the MISFET 400 is improved.

  However, if an interface state exists at the interface between the RESURF region 60 and the guard ring region 64 and the field oxide film 33, charges are trapped in the interface state. There is a possibility that a desired depletion layer may not be formed due to the electric field of the trapped charge. In this case, the breakdown voltage of the MISFET 400 is deteriorated.

  According to this embodiment, the interface state is terminated by providing the interface region 40. Therefore, a desired depletion layer is formed and a MISFET with a stable breakdown voltage is realized.

(Tenth embodiment)
The semiconductor device of this embodiment is different from that of the first embodiment in that an interface region is provided in the termination region of the SiC PIN diode. The description overlapping with that of the first embodiment is omitted.

  FIG. 17 is a schematic cross-sectional view showing a configuration of a PIN diode that is a semiconductor device of the present embodiment.

The PIN diode 500 includes an n ⁺ type cathode region 70, an n ⁻ type drift layer (SiC layer) 72, a p ⁺ type anode region 74, a p type guard ring (SiC layer) 76, an interface region 40, and a protective film. (Insulating layer) 78, an anode electrode 80, and a cathode electrode 82 are provided.

  The interface region 40 is provided between the guard ring 76 and the drift layer 72 and the protective film 78.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

The protective film 78 is, for example, a silicon oxide film. The concentration of the termination element in the protective film 78 is desirably 1 × 10 ¹⁸ cm ⁻³ or less. Although the concentration of the termination element in the protective film 78 can be confirmed by SIMS, it is more preferably below the detection limit of each termination element (approximately 1 × 10 ¹⁷ cm ⁻³ or less). The concentration of the termination element in the protective film 78 is, for example, a concentration at a position away from the peak of the termination element concentration in the interface region 40 by 1 nm or more.

  When the PIN diode 500 is turned off, a depletion layer is formed in the guard ring 76 and the drift layer 72, whereby the breakdown voltage of the PIN diode 500 is improved.

  However, if an interface state exists at the interface between the guard ring 76 and the drift layer 72 and the protective film 78, charges are trapped in the interface state. There is a possibility that a desired depletion layer may not be formed due to the electric field of the trapped charge. In this case, the breakdown voltage of the PIN diode 500 is deteriorated.

  According to this embodiment, the interface state is terminated by providing the interface region 40. Therefore, a PIN diode having a desired breakdown voltage and a stable withstand voltage is realized.

(Eleventh embodiment)
The semiconductor device of this embodiment is different from that of the first embodiment in that an interface region is provided in a termination region of a SiC SBD (Schottky Barrier Diode). The description overlapping with that of the first embodiment is omitted.

  FIG. 18 is a schematic cross-sectional view showing the configuration of the SBD that is the semiconductor device of the present embodiment.

The SBD 600 includes an n ⁺ type cathode region 70, an n ⁻ type drift layer (SiC layer) 72, a p type guard ring (SiC layer) 76, an interface region 40, a protective film (insulating layer) 78, an anode electrode 80, A cathode electrode 82 is provided.

  The interface region 40 is provided between the guard ring 76 and the drift layer 72 and the protective film 78.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

The protective film 78 is, for example, a silicon oxide film. The concentration of the termination element in the protective film 78 is desirably 1 × 10 ¹⁸ cm ⁻³ or less. Although the concentration of the termination element in the protective film 78 can be confirmed by SIMS, it is more preferably below the detection limit of each termination element (approximately 1 × 10 ¹⁷ cm ⁻³ or less). The concentration of the termination element in the protective film 78 is, for example, a concentration at a position away from the peak of the termination element concentration in the interface region 40 by 1 nm or more.

  When the SBD 600 is turned off, a depletion layer is formed in the guard ring 76 and the drift layer 72, whereby the breakdown voltage of the SBD 600 is improved.

  However, if an interface state exists at the interface between the guard ring 76 and the drift layer 72 and the protective film 78, charges are trapped in the interface state. There is a possibility that a desired depletion layer may not be formed due to the electric field of the trapped charge. In this case, the breakdown voltage of the SBD 600 is deteriorated.

  According to this embodiment, the interface state is terminated by providing the interface region 40. Therefore, a desired depletion layer is formed and an SBD with stable breakdown voltage is realized.

(Twelfth embodiment)
The semiconductor device of the present embodiment is provided between the SiC layer having the first surface, the metal electrode, and the first surface of the SiC layer and the metal electrode, and includes Be (beryllium), Mg (magnesium), and Ca. (Calcium), Sr (strontium), Ba (barium) at least one element selected from the group, the full width at half maximum of the concentration peak of the element is 1 nm or less, Si (silicon) in the first surface Alternatively, when the surface density of Si (silicon) and C (carbon) not bonded to any of C (carbon) is the first surface density, the second surface density that is the surface density of the element is the first surface density. And a region that is less than or equal to ½ of.

  The semiconductor device of the present embodiment is different from the eleventh embodiment in that an interface region is also provided between the anode electrode and the drift layer. The description overlapping with the eleventh embodiment is omitted.

  FIG. 19 is a schematic cross-sectional view showing the configuration of the SBD that is the semiconductor device of this embodiment.

The SBD 600 includes an n ⁺ type cathode region 70, an n ⁻ type drift layer (SiC layer) 72, a p type guard ring (SiC layer) 76, an interface region 40, a protective film (insulating layer) 78, an anode electrode (metal) Electrode) 80 and a cathode electrode 82.

  The interface region 40 is provided between the guard ring 76 and the drift layer 72 and the protective film 78. The interface region 40 is also provided between the drift layer 72 and the anode electrode 80.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  The termination element is segregated at the interface between the drift layer 72 and the anode electrode 80. The full width at half maximum of the concentration peak of the terminal element is 1 nm or less. The full width at half maximum of the concentration peak is desirably 0.5 nm or less, and more desirably less than 0.2 nm.

  The interface region 40 is preferably a monoatomic layer.

  The surface density of Si (silicon) and C (carbon) that is not bonded to either Si (silicon) or C (carbon) on the surface (first surface) of the drift layer 72 is defined as the first surface density. Further, the surface density of the termination element is set to the second surface density. The second surface density is ½ or less of the first surface density.

  It is desirable that the second surface density is 1/120 or less of the first surface density. Further, it is desirable that the second surface density is 1/12000 or more of the first surface density.

The peak of the concentration of the termination element in the interface region 40 is desirably 5 × 10 ¹⁸ cm ⁻³ or more. Moreover, it is more desirable that it is 1 × 10 ¹⁹ cm ⁻³ or more.

  The protective film 78 is, for example, a silicon oxide film.

  If an interface state exists at the interface between the drift layer 72 and the anode electrode 80, Fermi level pinning occurs. For this reason, a desired Schottky barrier may not be realized between the drift layer 72 and the anode electrode 80.

  According to this embodiment, the interface state is terminated by providing the interface region 40. Therefore, an SBD having a desired Schottky barrier determined by the work function of the anode electrode 80 is realized.

(13th Embodiment)
The semiconductor device of this embodiment is provided between a diamond layer having a first surface, an insulating layer, and the first surface of the diamond layer and the insulating layer, and includes Be (beryllium), Mg (magnesium), and Ca. (Calcium), Sr (strontium), Ba (barium) at least one element selected from the group, the full width at half maximum of the concentration peak of the element is 1 nm or less, C (carbon) in the first surface When the surface density of C (carbon) not bonded to the first surface density is the first surface density, a region where the second surface density, which is the surface density of the element, is ½ or less of the first surface density, Prepare.

  The same as the eleventh embodiment, except that diamond is used as the semiconductor material instead of SiC. Therefore, the description overlapping with the eleventh embodiment is omitted.

  FIG. 20 is a schematic cross-sectional view showing the configuration of the SBD that is the semiconductor device of this embodiment.

The SBD 800 includes an n ⁺ type cathode region 90, an n ⁻ type drift layer (diamond layer) 92, a p type guard ring (diamond layer) 96, an interface region 40, a protective film (insulating layer) 78, an anode electrode 80, A cathode electrode 82 is provided.

The interface region 40 is provided between the p-type guard ring 96 and the n ⁻ -type drift layer 92 and the protective film 78.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  The termination element is segregated at the interface between the drift layer 92 and the protective film (insulating layer) 78. The full width at half maximum of the concentration peak of the terminal element is 1 nm or less. The full width at half maximum of the concentration peak is desirably 0.5 nm or less, and more desirably less than 0.2 nm.

  The interface region 40 is preferably a monoatomic layer.

  The surface density of C (carbon) that is not bonded to C (carbon) on the surface (first surface) of the drift layer 92 is defined as the first surface density. Further, the surface density of the termination element is set to the second surface density. The second surface density is ½ or less of the first surface density.

  It is desirable that the second surface density is 1/120 or less of the first surface density. Further, it is desirable that the second surface density is 1/12000 or more of the first surface density.

The peak of the concentration of the termination element in the interface region 40 is desirably 5 × 10 ¹⁸ cm ⁻³ or more. Moreover, it is more desirable that it is 1 × 10 ¹⁹ cm ⁻³ or more.

The protective film 78 is, for example, a silicon oxide film. The concentration of the termination element in the protective film 78 is desirably 1 × 10 ¹⁸ cm ⁻³ or less. Although the concentration of the termination element in the protective film 78 can be confirmed by SIMS, it is more preferably below the detection limit of each termination element (approximately 1 × 10 ¹⁷ cm ⁻³ or less). The concentration of the termination element in the protective film 78 is, for example, a concentration at a position away from the peak of the termination element concentration in the interface region 40 by 1 nm or more.

  When the SBD 800 is turned off, a depletion layer is formed in the guard ring 96 and the drift layer 92, whereby the breakdown voltage of the SBD 800 is improved.

  However, if an interface state exists at the interface between the guard ring 96 and the drift layer 92 and the protective film 78, charges are trapped in the interface state. There is a possibility that a desired depletion layer may not be formed due to the electric field of the trapped charge. In this case, the breakdown voltage of the SBD 800 deteriorates.

  The surface of the diamond layer also has carbon dangling bonds, for example, like the SiC layer on the carbon surface. The termination element terminates the dangling bond by bonding with C (carbon).

  According to this embodiment, the interface state is terminated by providing the interface region 40. Therefore, a desired depletion layer is formed and an SBD with stable breakdown voltage is realized.

  Furthermore, as described above, it has been found that the termination element is more stable to bond with C than to Si. When diamond is used as a semiconductor material, all the terminal elements in the interface region 40 are bonded to C. Therefore, an SBD having an extremely stable interface region 40 is realized.

(Modification)
FIG. 21 is a schematic cross-sectional view showing a configuration of an SBD that is a semiconductor device according to a modification of the present embodiment.

The modified SBD includes a p ⁺ type cathode region 190, a p ⁻ type drift layer (diamond layer) 192, an n type guard ring (diamond layer) 196, an interface region 40, a protective film (insulating layer) 78, an anode An electrode 80 and a cathode electrode 82 are provided.

The interface region 40 is provided between the n-type guard ring 196 and the p ⁻ -type drift layer 192 and the protective film 78.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  The SBD of this modification is different from the SBD of this embodiment in that the n-type and the p-type are inverted. According to this modification, the interface state is terminated by providing the interface region 40. Therefore, a desired depletion layer is formed and an SBD with stable breakdown voltage is realized.

(Fourteenth embodiment)
The semiconductor device of the present embodiment is provided between a diamond layer having a first surface, a metal electrode, and the first surface of the diamond layer and the metal electrode, and includes Be (beryllium), Mg (magnesium), and Ca. (Calcium), Sr (strontium), Ba (barium) at least one element selected from the group, the full width at half maximum of the concentration peak of the element is 1 nm or less, C (carbon) in the first surface When the surface density of C (carbon) that is not bonded to the first surface density is the first surface density, a second surface density that is the surface density of the element is ½ or less of the first surface density;
Is provided.

  The semiconductor device of this embodiment is different from the thirteenth embodiment in that an interface region is also provided between the anode electrode and the drift layer. The description overlapping with the thirteenth embodiment is omitted.

  FIG. 22 is a schematic cross-sectional view showing the configuration of the SBD that is the semiconductor device of the present embodiment.

The SBD 900 includes an n ⁺ -type cathode region 90, an n ⁻ -type drift layer (diamond layer) 92, a p-type guard ring (diamond layer) 96, an interface region 40, a protective film (insulating layer) 78, an anode electrode (metal) Electrode) 80 and a cathode electrode 82.

  The interface region 40 is provided between the guard ring 96 and the drift layer 92 and the protective film 78. The interface region 40 is also provided between the drift layer 92 and the anode electrode 80.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  The termination element is segregated at the interface between the drift layer 92 and the anode electrode 80. The full width at half maximum of the concentration peak of the terminal element is 1 nm or less. The full width at half maximum of the concentration peak is desirably 0.5 nm or less, and more desirably less than 0.2 nm.

  The interface region 40 is preferably a monoatomic layer.

  The surface density of Si (silicon) and C (carbon) that do not bond to either Si (silicon) or C (carbon) on the surface of the drift layer 72 is defined as a first surface density. Further, the surface density of the termination element is set to the second surface density. The second surface density is ½ or less of the first surface density.

  It is desirable that the second surface density is 1/120 or less of the first surface density. Further, it is desirable that the second surface density is 1/12000 or more of the first surface density.

The peak of the concentration of the termination element in the interface region 40 is desirably 5 × 10 ¹⁸ cm ⁻³ or more. Moreover, it is more desirable that it is 1 × 10 ¹⁹ cm ⁻³ or more.

  The protective film 78 is, for example, a silicon oxide film.

  If an interface state exists at the interface between the drift layer 92 and the anode electrode 80, Fermi level pinning occurs. For this reason, a desired Schottky barrier may not be realized between the drift layer 92 and the anode electrode 80.

  According to this embodiment, the interface state is terminated by providing the interface region 40. Therefore, an SBD having a desired Schottky barrier determined by the work function of the anode electrode 80 is realized.

  Furthermore, as described above, it has been found that the termination element is more stable to bond with C than to Si. When diamond is used as a semiconductor material, all the terminal elements in the interface region 40 are bonded to C. Therefore, an SBD having an extremely stable interface region 40 is realized.

(Modification)
FIG. 23 is a schematic cross-sectional view showing a configuration of an SBD that is a semiconductor device according to a modification of the present embodiment.

The modified SBD includes a p ⁺ type cathode region 190, a p ⁻ type drift layer (diamond layer) 192, an n type guard ring (diamond layer) 196, an interface region 40, a protective film (insulating layer) 78, an anode An electrode 80 and a cathode electrode 82 are provided.

The interface region 40 is provided between the n-type guard ring 196 and the p ⁻ -type drift layer 192 and the protective film 78.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  The SBD of this modification is different from the SBD of this embodiment in that the n-type and the p-type are inverted. According to this modification, the interface state is terminated by providing the interface region 40. Therefore, an SBD having a desired Schottky barrier determined by the work function of the anode electrode 80 is realized.

(Fifteenth embodiment)
The semiconductor device of this embodiment is provided between a diamond layer having a first surface, an insulating layer, and the first surface of the diamond layer and the insulating layer, and includes Be (beryllium), Mg (magnesium), and Ca. (Calcium), Sr (strontium), Ba (barium) at least one element selected from the group, the full width at half maximum of the concentration peak of the element is 1 nm or less, C (carbon) in the first surface When the surface density of C (carbon) not bonded to the first surface density is the first surface density, a region where the second surface density, which is the surface density of the element, is ½ or less of the first surface density, Prepare.

  The same as the tenth embodiment, except that diamond is used as the semiconductor material instead of SiC and the n-type and p-type are inverted. Therefore, the description overlapping with the tenth embodiment is omitted.

  FIG. 24 is a schematic cross-sectional view showing a configuration of a PIN diode which is a semiconductor device of the present embodiment.

The PIN diode 1000 includes a p ⁺ type cathode region 170, a p ⁻ type drift layer (SiC layer) 172, an n ⁺ type anode region 174, an n type guard ring (SiC layer) 176, an interface region 40, a protective film. (Insulating layer) 78, an anode electrode 80, and a cathode electrode 82 are provided.

  The interface region 40 is provided between the guard ring 76 and the drift layer 72 and the protective film 78.

  The interface region 40 contains at least one element (terminal element) selected from the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium).

  According to this embodiment, the interface state is terminated by providing the interface region 40. Therefore, a PIN diode having a desired breakdown voltage and a stable withstand voltage is realized.

  Furthermore, as described above, it has been found that the termination element is more stable to bond with C than to Si. When diamond is used as a semiconductor material, all the terminal elements in the interface region 40 are bonded to C. Therefore, an SBD having an extremely stable interface region 40 is realized.

(Sixteenth embodiment)
The inverter circuit and the drive device of this embodiment are drive devices provided with the semiconductor device of the first embodiment.

  FIG. 25 is a schematic diagram of the drive device of the present embodiment. The driving device 1100 includes a motor 140 and an inverter circuit 150.

  The inverter circuit 50 includes three semiconductor modules 100a, 100b, and 100c that use the MISFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 100a, 100b, and 100c in parallel, a three-phase inverter circuit 150 including three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

  According to the present embodiment, the operation of the inverter circuit 150 and the driving device 1100 is stabilized by including the MISFET 100 having a reduced interface state.

(Seventeenth embodiment)
The vehicle according to the present embodiment is a vehicle including the semiconductor device according to the first embodiment.

  FIG. 26 is a schematic diagram of a vehicle according to the present embodiment. The vehicle 1200 according to this embodiment is a railway vehicle. The vehicle 1200 includes a motor 140 and an inverter circuit 150.

  The inverter circuit 50 includes three semiconductor modules 100a, 100b, and 100c that use the MISFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 100a, 100b, and 100c in parallel, a three-phase inverter circuit 150 including three AC voltage output terminals U, V, and W is realized.

  The motor 140 is driven by the AC voltage output from the inverter circuit 150. Wheels 1290 of vehicle 1200 are rotated by motor 140.

  According to the present embodiment, the operation of the vehicle 1200 is stabilized by including the MISFET 100 having a reduced interface state.

(Eighteenth embodiment)
The vehicle according to the present embodiment is a vehicle including the semiconductor device according to the first embodiment.

  FIG. 27 is a schematic diagram of a vehicle according to the present embodiment. The vehicle 1300 of this embodiment is an automobile. The vehicle 1300 includes a motor 140 and an inverter circuit 150.

  The inverter circuit 150 includes three semiconductor modules 100a, 100b, and 100c that use the MISFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 100a, 100b, and 100c in parallel, a three-phase inverter circuit 150 including three AC voltage output terminals U, V, and W is realized.

  The motor 140 is driven by the AC voltage output from the inverter circuit 150. The wheel 140 of the vehicle 1000 is rotated by the motor 140.

  According to this embodiment, the reliability of the vehicle 1300 is improved by including the MISFET having a high threshold.

(Nineteenth embodiment)
The elevator according to the present embodiment is an elevator including the semiconductor device according to the first embodiment.

  FIG. 28 is a schematic diagram of an elevator (elevator) according to the present embodiment. The elevator 1400 of this embodiment includes a car 1010, a counterweight 1012, a wire rope 1014, a hoisting machine 1016, a motor 140, and an inverter circuit 150.

  The inverter circuit 150 includes three semiconductor modules 100a, 100b, and 100c that use the MISFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 100a, 100b, and 100c in parallel, a three-phase inverter circuit 150 including three AC voltage output terminals U, V, and W is realized.

  The motor 140 is driven by the AC voltage output from the inverter circuit 150. The hoisting machine 1016 is rotated by the motor 140 and the car 1010 is moved up and down.

  According to this embodiment, the reliability of the elevator 1400 is improved by providing the MISFET having a high threshold.

  In the first to twelfth embodiments, the characteristics of the device having a structure in which the n-type and the p-type are interchanged can also be improved.

  As described above, in the embodiment, the case of 4H—SiC is described as an example of the crystal structure of silicon carbide, but the present invention can also be applied to silicon carbide having other crystal structures such as 6H—SiC, 3C—SiC, and the like. is there.

  In the seventeenth to nineteenth embodiments, the case where the semiconductor device of the present invention is applied to a vehicle or an elevator has been described as an example. However, the semiconductor device of the present invention is applied to, for example, a power conditioner of a solar power generation system. It is also possible to do.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, a component in one embodiment may be replaced or changed with a component in another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

14 Drift layer (SiC layer)
16 p-well region (SiC layer)
28 Gate insulation layer (insulation layer)
30 Gate electrode 33 Field oxide film (insulating layer)
40 Interface area
60 RESURF region (SiC layer)
64 Guard ring region 72 Drift layer (SiC layer)
76 Guard ring (SiC layer)
78 Protective film (insulating layer)
80 Anode electrode (metal electrode)
92 Drift layer (Diamond layer)
96 Guard ring (diamond layer)
100 MISFET (semiconductor device)
140 Motor 150 Inverter circuit 200 MISFET (semiconductor device)
300 IGBT (semiconductor device)
400 MISFET (semiconductor device)
500 PIN diode (semiconductor device)
600 SBD (semiconductor device)
700 SBD (semiconductor device)
800 SBD (semiconductor device)
900 SBD (semiconductor device)
1000 PIN diode (semiconductor device)
1100 Driving device 1200 Vehicle 1300 Vehicle 1400 Elevator

Claims (27)

A SiC layer comprising a first surface;
An insulating layer;
Containing at least one element of the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), the full width at half maximum of the concentration peak of the element being 1 nm or less, When the surface density of Si (silicon) and C (carbon) having a bond that does not bond to either Si (silicon) or C (carbon) in the SiC layer on the first surface is the first surface density, A region between the first surface of the SiC layer and the insulating layer, wherein a second surface density, which is a surface density of the element, is ½ or less of the first surface density;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the second surface density is 1/120 or less of the first surface density.   The semiconductor device according to claim 1, wherein the second area density is 1/12000 or more of the first area density. 4. The semiconductor device according to claim 1, wherein the concentration of the element at the peak is 5 × 10 ¹⁸ cm ⁻³ or more. 5. The semiconductor device according to claim 1, wherein the concentration of the element in the insulating layer is 1 × 10 ¹⁸ cm ⁻³ or less.   6. The semiconductor device according to claim 1, wherein the region is a monoatomic layer of the element.   The semiconductor device according to any one of claims 1 to 6, wherein the first surface is a surface inclined at an angle of 0 degrees to 30 degrees with respect to a <0001> direction.   7. The semiconductor device according to claim 1, wherein the first surface is a surface inclined at an angle of 0 degrees to 30 degrees with respect to the (000-1) plane.   The semiconductor device according to claim 1, further comprising a gate electrode on the insulating layer.   10. The second surface density is a value obtained by dividing the amount of the element in the region counted by SIMS (Secondary Ion Mass Spectrometry) by the beam area of incident ions. The semiconductor device described. A diamond layer comprising a first surface;
An insulating layer;
Containing at least one element of the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), the full width at half maximum of the concentration peak of the element being 1 nm or less, When the surface density of C (carbon) having a bond that does not bond to C (carbon) of the diamond layer on the first surface is the first surface density, the second surface density that is the surface density of the element A region between the first surface of the diamond layer and the insulating layer, wherein is a half or less of the first surface density;
A semiconductor device comprising: A SiC layer comprising a first surface;
A metal electrode;
Containing at least one element of the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), the full width at half maximum of the concentration peak of the element being 1 nm or less, When the surface density of Si (silicon) and C (carbon) having a bond that does not bond to either Si (silicon) or C (carbon) in the SiC layer on the first surface is the first surface density, A region between the first surface of the SiC layer and the metal electrode, wherein a second surface density, which is a surface density of the element, is ½ or less of the first surface density;
A semiconductor device comprising:   The semiconductor device according to claim 12, wherein the second surface density is 1/120 or less of the first surface density.   The semiconductor device according to claim 12 or 13, wherein the second surface density is 1/12000 or more of the first surface density. The semiconductor device according to claim 12, wherein the concentration of the element at the peak is 5 × 10 ¹⁸ cm ⁻³ or more. A diamond layer comprising a first surface;
A metal electrode;
Containing at least one element of the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), the full width at half maximum of the concentration peak of the element being 1 nm or less, When the surface density of C (carbon) having a bond that does not bond to C (carbon) in the diamond layer on the first surface is the first surface density, the second surface is the surface density of the element. A region between the first surface of the diamond layer and the metal electrode, the density being ½ or less of the first surface density;
A semiconductor device comprising: A SiC layer comprising a first surface;
An insulating layer;
Containing at least one element of the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), the full width at half maximum of the peak of the concentration of the element being 1 nm or less, A region between the first surface of the SiC layer and the insulating layer;
A semiconductor device in which the element is divalent.   An inverter circuit comprising the semiconductor device according to claim 1.   A driving device comprising the semiconductor device according to claim 1.   A vehicle comprising the semiconductor device according to any one of claims 1 to 17.   An elevator comprising the semiconductor device according to claim 1. From the first surface of the SiC layer, ions of at least one element of the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium) are ion-implanted,
Forming a thermal oxide film on the first surface of the SiC layer;
Peeling off the thermal oxide film,
A method of manufacturing a semiconductor device, wherein a first insulating layer is formed on the first surface of the SiC layer.   23. The method of manufacturing a semiconductor device according to claim 22, wherein a second insulating layer is formed on the first surface of the SiC layer before the ion implantation.   24. The method for manufacturing a semiconductor device according to claim 22, wherein a gate electrode is formed on the first insulating layer. Forming a first film containing at least one element of the group of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium) on the first surface of the SiC layer;
A method of manufacturing a semiconductor device, wherein a first insulating layer is formed on the first surface of the SiC layer. After forming the first film and before forming the first insulating layer, a thermal oxide film is formed on the first surface,
26. The method of manufacturing a semiconductor device according to claim 25, wherein the thermal oxide film is removed before forming the first insulating layer. The first film is a silicate film of the element or an oxide film of the element;
26. The method of manufacturing a semiconductor device according to claim 25, wherein the silicate film or the oxide film is peeled off before forming the first insulating layer.

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