JP7005847B2 - Semiconductor devices, manufacturing methods for semiconductor devices, inverter circuits, drives, vehicles, and elevators - Google Patents

Description

Embodiments of the present invention relate to semiconductor devices, methods for manufacturing semiconductor devices, inverter circuits, drive devices, vehicles, and elevators.

Silicon carbide (SiC) is expected as a material for next-generation semiconductor devices. Silicon carbide has excellent physical properties such as a bandgap of 3 times, a breaking electric field strength of about 10 times, and a thermal conductivity of about 3 times that of silicon (Si). By utilizing this characteristic, a semiconductor device capable of low loss and high temperature operation can be realized.

However, for example, when a MOSFET (Meat Oxide Semiconductor Field Effect Transistor) is formed using silicon carbide, there is a problem that the carrier mobility is deteriorated.

JP-A-2017-216305

An object to be solved by the present invention is to provide a semiconductor device capable of improving carrier mobility.

The semiconductor device of the embodiment is a semiconductor layer of silicon carbide or diamond, a first carbon located on the semiconductor layer, a first atom bonded to the first carbon, and the first carbon. The first atom has a second atom bonded to the first carbon, a first terminal group bonded to the first carbon, and a second terminal group bonded to the first carbon. It is one atom selected from the group consisting of silicon (Si), carbon (C), oxygen (O), nitrogen (N), and aluminum (Al), and the second atom is silicon (Si), It is one atom selected from the group consisting of carbon (C), oxygen (O), nitrogen (N), and aluminum (Al), and the first terminal group is a hydroxyl group (OH) and fluorine (F). , Hydrogen (H), and deuterium (D), one of which is a terminal group selected from the group consisting of hydrogen (H), hydrogen (H), and hydrogen (D). , An insulating layer which is one terminating group selected from the group consisting of heavy hydrogen (D).

The schematic sectional view of the semiconductor device of 1st Embodiment. Explanatory drawing of the 1st coupling structure of 1st Embodiment. The figure which illustrates the 1st binding structure of 1st Embodiment. The enlarged schematic diagram of the gate insulating layer of 1st Embodiment. Explanatory drawing of the 2nd bond structure of 1st Embodiment. The process flow diagram of the manufacturing method of the semiconductor device of 1st Embodiment. The explanatory view of the operation and effect of the semiconductor device of 1st Embodiment. The schematic sectional view of the semiconductor device of 2nd Embodiment. The figure which shows the concentration distribution of the terminal element of 2nd Embodiment. The process flow diagram of the manufacturing method of the semiconductor device of 2nd Embodiment. The schematic sectional view of the semiconductor device of 3rd Embodiment. The schematic diagram of the drive device of 4th Embodiment. The schematic diagram of the vehicle of the 5th Embodiment. The schematic diagram of the vehicle of 6th Embodiment. The schematic diagram of the elevator of 7th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members will be designated by the same reference numerals, and the description of the members and the like once described will be omitted as appropriate.

Further, in the following description, when there are notations of n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ , they indicate the relative high and low of the impurity concentration in each conductive type. That is, n ⁺ indicates that the concentration of n-type impurities is relatively higher than that of n, and n ⁻ indicates that the concentration of n-type impurities is relatively lower than that of n. Further, p ⁺ indicates that the concentration of p-type impurities is relatively higher than that of p, and p ⁻ indicates that the concentration of p-type impurities is relatively lower than that of p. In some cases, n ⁺ type and n ^- type are simply referred to as n-type, p ⁺ -type and p ^- type are simply referred to as p-type.

(First Embodiment)
The semiconductor device of the first embodiment is located on a semiconductor layer of silicon carbide or diamond, a first carbon, a first atom bonded to the first carbon, and a first carbon. It has a second atom bonded to, a first terminal group bonded to the first carbon, and a second terminal group bonded to the first carbon, and the first atom is silicon (Si). ), Carbon (C), oxygen (O), nitrogen (N), and aluminum (Al). The second atom is silicon (Si) and carbon (C). ), Oxygen (O), nitrogen (N), and aluminum (Al), and the first terminal group is a hydroxyl group (OH), fluorine (F), and hydrogen (H). ) And one terminal group selected from the group consisting of heavy hydrogen (D), and the second terminal group is a hydroxyl group (OH), fluorine (F), hydrogen (H), and heavy hydrogen (D). ) Is provided with an insulating layer which is one terminal group selected from the group consisting of).

Hereinafter, a case where the semiconductor layer is silicon carbide and the insulating layer is silicon oxide will be described as an example.

FIG. 1 is a schematic cross-sectional view of the semiconductor device of the first embodiment. The semiconductor device of the first embodiment is a MOSFET 100. MOSFET 100 is a Double Implantation MOSFET (DI MOSFET) that forms a p-well and a source region by ion implantation. Further, the MOSFET 100 is an n-channel MOSFET having electrons as carriers.

The MOSFET 100 includes a silicon carbide substrate 12, a drift layer 14 (semiconductor layer), a p-well region 16 (semiconductor layer), a source region 18, a p-well contact region 20, a gate insulating layer 28 (insulating layer), a gate electrode 30, and layers. It includes an insulating film 32, a source electrode 34, and a drain electrode 36. The gate insulating layer 28 has a first region 28a and a second region 28b.

The silicon carbide substrate 12 is, for example, an n ⁺ type 4H—SiC substrate. The silicon carbide substrate 12 contains, for example, nitrogen (N) as an n-type impurity. The impurity concentration of the n-type impurities in the silicon carbide substrate 12 is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less.

The surface of the silicon carbide substrate 12 is, for example, a surface inclined at 0 degrees or more and 8 degrees or less with respect to the (0001) plane. The (0001) plane is referred to as a silicon plane. The back surface of the silicon carbide substrate 12 is, for example, a surface inclined at 0 degrees or more and 8 degrees or less with respect to the (000-1) surface. The (000-1) surface is referred to as a carbon surface.

The drift layer 14 is provided on the surface of the silicon carbide substrate 12. The drift layer 14 is an n ^- type silicon carbide layer. The drift layer 14 contains, for example, nitrogen as an n-type impurity.

The impurity concentration of the n-type impurities in the drift layer 14 is, for example, 5 × 10 ¹⁵ cm ^-3 or more and 2 × 10 ¹⁶ cm ^-3 or less. The drift layer 14 is, for example, an epitaxial growth layer of SiC formed on the silicon carbide substrate 12 by epitaxial growth.

The surface of the drift layer 14 is also a surface inclined by 0 degrees or more and 8 degrees or less with respect to the silicon surface. The thickness of the drift layer 14 is, for example, 5 μm or more and 100 μm or less.

The p-well region 16 is provided on a partial surface of the drift layer 14. The p-well region 16 is a p-type silicon carbide region. The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The impurity concentration of the p-type impurity in the p-well region 16 is, for example, 5 × 10 ¹⁵ cm ^-3 or more and 1 × 10 ¹⁷ cm ^-3 or less.

The depth of the p-well region 16 is, for example, 0.4 μm or more and 0.8 μm or less. The p-well region 16 functions as a channel region of the MOSFET 100.

The surface of the p-well region 16 is also a surface inclined at 0 degrees or more and 8 degrees or less with respect to the silicon surface.

The source region 18 is provided on a partial surface of the p-well region 16. The source region 18 is an n ⁺ type silicon carbide layer. The source region 18 contains, for example, phosphorus (P) as an n-type impurity. The impurity concentration of the n-type impurity in the source region 18 is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²² cm ^-3 cm or less.

The depth of the source region 18 is shallower than the depth of the p-well region 16. The depth of the source region 18 is, for example, 0.2 μm or more and 0.4 μm or less.

The p-well contact region 20 is provided on a partial surface of the p-well region 16. The p-well contact region 20 is provided on the side of the source region 18. The p-well contact region 20 is a p ⁺ type silicon carbide region.

The p-well contact region 20 contains, for example, aluminum as a p-type impurity. The impurity concentration of the p-type impurity in the p-well contact region 20 is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²² cm ^-3 or less.

The depth of the p-well contact region 20 is shallower than the depth of the p-well region 16. The depth of the p-well contact region 20 is, for example, 0.2 μm or more and 0.4 μm or less.

The gate insulating layer 28 is provided between the p-well region 16 and the gate electrode 30. The gate insulating layer 28 is provided on the drift layer 14 and the p-well region 16. The gate insulating layer 28 is continuously formed on the surfaces of the drift layer 14 and the p-well region 16.

The gate insulating layer 28 is silicon oxide. The gate insulating layer 28 may be, for example, an oxide other than silicon oxide or a nitride oxide. The gate insulating layer 28 may be, for example, aluminum oxide, silicon oxynitride, or the like.

The thickness of the gate insulating layer 28 is, for example, 30 nm or more and 100 nm or less. The gate insulating layer 28 functions as the gate insulating layer of the MOSFET 100.

Carbon is contained in the gate insulating layer 28. The carbon concentration in the gate insulating layer 28 is, for example, 2 × 10 ¹⁶ cm ^-3 or more and 2 × 10 ²² cm ^-3 or less.

The concentration of carbon in the gate insulating layer 28 can be measured, for example, by secondary ion mass spectrometry (SIMS).

FIG. 2 is an explanatory diagram of the first coupling structure of the first embodiment. The gate insulating layer 28 has a first bonding structure.

The first bond structure consists of a first carbon (C), a first atom (A1) bonded to the first carbon (C), and a second atom bonded to the first carbon (C) ( It has A2), a first terminal group (T1) bonded to the first carbon (C), and a second terminal group (T2) bonded to the first carbon (C). The first atom (A1) is one atom selected from the group consisting of silicon (Si), carbon (C), oxygen (O), nitrogen (N), and aluminum (Al), and is the second atom. The atom (A2) is one atom selected from the group consisting of silicon (Si), carbon (C), oxygen (O), nitrogen (N), and aluminum (Al), and is a first terminal group (1st terminal group). T1) is one terminal group selected from the group consisting of hydroxyl group (OH), fluorine (F), hydrogen (H), and deuterium (D), and the second terminal group (T2) is a hydroxyl group. It is one terminal group selected from the group consisting of (OH), fluorine (F), hydrogen (H), and deuterium (D).

FIG. 3 is a diagram illustrating the first coupling structure of the first embodiment. FIG. 3 shows a case where the first terminal group (T1) and the second terminal group (T2) are of the same type. 3 (a), 3 (b), 3 (c), and 3 (d) show the case where the first terminal group (T1) and the second terminal group (T2) are hydroxyl groups (OH). be. 3 (e), 3 (f), 3 (g), and 3 (h) show the case where the first terminal group (T1) and the second terminal group (T2) are fluorine (F). be.

FIG. 3 shows a case where the gate insulating layer 28 is silicon oxide, and the first atom (A1) and the second atom (A2) are silicon (Si), carbon (C), or oxygen (O). Become. For example, when the gate insulating layer 28 is aluminum oxide, the first atom (A1) and the second atom (A2) may be aluminum (Al). Further, for example, when the gate insulating layer 28 is silicon nitride, the first atom (A1) and the second atom (A2) may be nitrogen (N).

In the first bond structure, the coordination number of the first carbon (C) is 4. The first carbon (C), the first atom (A1), the second atom (A2), the first termination group (T1), and the second termination group (T2) are formed by sp ³ orbitals. It is combined.

FIG. 4 is an enlarged schematic view of the gate insulating layer of the first embodiment. The gate insulating layer 28 has a first region 28a and a second region 28b. The second region 28b sandwiches the first region 28a with the drift layer 14.

The first carbon (C) in the first region 28a is more than the first carbon (C) in the second region 28b. The density of the first carbon (C) in the first region 28a is higher than the density of the first carbon (C) in the second region 28b. In other words, the first binding structure of the first region 28a is larger than the first binding structure of the second region 28b. In other words, the density of the first bond structure in the first region 28a is higher than the density of the first bond structure in the second region 28b.

FIG. 5 is an explanatory diagram of the second coupling structure of the first embodiment. The gate insulating layer 28 may have a second coupling structure.

The second bond structure has a second carbon (C) and oxygen (O) that is double bonded to the second carbon (C). For example, two silicons (Si) are bonded to the second carbon (C) as shown in FIG. 5 (a). Further, for example, as shown in FIG. 5B, two carbons (C) are bonded to the second carbon (C). Further, for example, as shown in FIG. 5 (c), silicon (Si) and carbon (C) are bonded to the second carbon (C) one by one.

In the second bond structure, the coordination number of the second carbon (C) is 3. The ^second carbon (C) and oxygen (O) are bonded by the sp2 orbital.

The first carbon (C) in the gate insulating layer 28 is, for example, more than the second carbon (C). The density of the first carbon (C) in the gate insulating layer 28 is higher than the density of the second carbon (C). In other words, the density of the first bonded structure in the gate insulating layer 28 is higher than the density of the second bonded structure.

The presence or absence of the first coupling structure and the second coupling structure in the gate insulating layer 28 can be determined by, for example, X-ray Photoelectron Spectroscopy (XPS). Further, the difference in the amount and density of the first bonded structure between the first region 28a and the second region 28b, and the quantity and density of the first bonded structure and the second bonded structure in the gate insulating layer 28. The difference between the two can also be determined by XPS.

The gate electrode 30 is provided on the gate insulating layer 28. The gate electrode 30 sandwiches the gate insulating layer 28 with the drift layer 14.

For example, polycrystalline silicon containing an n-type impurity or a p-type impurity can be applied to the gate electrode 30.

The interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is, for example, a silicon oxide film.

The source electrode 34 is electrically connected to the source region 18 and the p-well contact region 20. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16.

The source electrode 34 is composed of, for example, a laminate of a Ni (nickel) barrier metal layer and an aluminum metal layer on the barrier metal layer. The barrier metal layer of nickel and the silicon carbide layer may react to form nickel silicide (NiSi, _Ni2Si , etc.). The nickel barrier metal layer and the aluminum metal layer may form an alloy by reaction.

The drain electrode 36 is provided on the side opposite to the drift layer 14 of the silicon carbide substrate 12, that is, on the back surface side. The drain electrode 36 is, for example, nickel. Nickel may react with the silicon carbide substrate 12 to form nickel silicide (NiSi, _Ni2Si , etc.).

In the first embodiment, the n-type impurities are, for example, nitrogen and phosphorus. It is also possible to apply arsenic (As) or antimony (Sb) as an n-type impurity.

Further, in the first embodiment, the p-type impurity is, for example, aluminum. Boron (B), gallium (Ga), and indium (In) can also be applied as p-type impurities.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.

In the method for manufacturing a semiconductor device according to the first embodiment, an insulating film is formed on a semiconductor layer of silicon carbide, and the insulating film is irradiated with microwaves in an atmosphere containing water.

FIG. 6 is a process flow chart of the method for manufacturing a semiconductor device according to the first embodiment.

As shown in FIG. 6, the manufacturing method of the semiconductor device includes drift layer formation (step S100), p-type impurity ion injection (step S102), n-type impurity ion injection (step S104), and p-type impurity ion injection (step S106). ), First silicon oxide film formation (step S108), microwave irradiation (step S110), second silicon oxide film formation (step S112), first annealing (step S114), gate electrode formation (step S116). , An interlayer insulating film formation (step S118), a source electrode formation (step S120), a drain electrode formation (step S122), and a second annealing (step S124).

First, an n ⁺ type silicon carbide substrate 12 is prepared. The silicon carbide substrate 12 is, for example, 4H-SiC. The silicon carbide substrate 12 is, for example, a silicon carbide wafer W.

The silicon carbide substrate 12 contains nitrogen as an n-type impurity. The impurity concentration of the n-type impurities in the silicon carbide substrate 12 is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. The thickness of the silicon carbide substrate 12 is, for example, 350 μm. The silicon carbide substrate 12 may be thinned to about 90 μm before forming the drain electrode 36 on the back surface.

In step S100, the drift layer 14 is formed on the silicon surface of the silicon carbide substrate 12 by the epitaxial growth method. The drift layer 14 is 4H-SiC.

The drift layer 14 contains nitrogen as an n-type impurity. The impurity concentration of the n-type impurities in the drift layer 14 is, for example, 5 × 10 ¹⁵ cm ^-3 or more and 2 × 10 ¹⁶ cm ^-3 or less. The thickness of the drift layer 14 is, for example, 5 μm or more and 100 μm or less.

In step S102, first, a first mask material is formed by patterning by photolithography and etching. Then, using the first mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift layer 14. The p-well region 16 is formed by ion implantation.

In step S104, first, a second mask material is formed by patterning by photolithography and etching. Then, using the second mask material as an ion implantation mask, nitrogen, which is an n-type impurity, is ion-implanted into the drift layer 14 to form the source region 18.

In step S106, a third mask material is formed by patterning by photolithography and etching. Using the third mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift layer 14 to form the p-well contact region 20.

In step S108, the drift layer 14 and the p-well region 16 are thermally oxidized to form a first silicon oxide film on the drift layer 14 and the p-well region 16. The first silicon oxide film becomes a part of the gate insulating layer 28.

Thermal oxidation is performed, for example, in a dry oxygen atmosphere. The temperature of thermal oxidation is, for example, 1000 ° C. or higher and 1250 ° C. or lower. The thickness of the first silicon oxide film is, for example, 1 nm or more and 10 nm or less.

Excess carbon generated by thermal oxidation of the drift layer 14 and the p-well region 16 is incorporated into the first silicon oxide film. Then, the carbon incorporated into the first silicon oxide film forms a double bond between carbon and oxygen in the first silicon oxide film to stabilize it. In other words, the carbon incorporated into the first silicon oxide film forms and stabilizes a second bonded structure in the first silicon oxide film.

In step S110, the first silicon oxide film is irradiated with microwaves in an atmosphere containing water. The supply of water into the atmosphere is performed, for example, by bubbling with nitrogen gas.

The temperature at the time of irradiating the microwave is, for example, 300 ° C. or higher and 600 ° C. or lower. The first silicon oxide film is heated to, for example, 300 ° C. or higher and 600 ° C. or lower. The frequency of the microwave is, for example, 1 GHz or more and 5 GHz or less.

By irradiating the first silicon oxide film with microwaves in an atmosphere containing water, the double bond between carbon and oxygen is broken, and a structure in which carbon is bonded to two hydroxyl groups (OH) is formed. .. In other words, the second bonding structure is converted into a first bonding structure in which the first terminal group (T1) and the second terminal group (T2) are hydroxyl groups (OH).

In step S112, a second silicon oxide film is formed on the first silicon oxide film. The second silicon oxide film becomes a part of the gate insulating layer 28.

The second silicon oxide film is a deposited film formed by, for example, a CVD method (Chemical Vapor Deposition) or a PVD method (Physical Vapor Deposition). The thickness of the second silicon oxide film is, for example, 20 nm or more and 100 nm or less.

The second silicon oxide film is, for example, a silicon oxide film formed by a CVD method using tetraethyl orthosilicate (TEOS) as a source gas.

In step S114, the first annealing is performed. The first annealing is performed, for example, in a non-oxidizing atmosphere. The temperature of the first annealing is, for example, 900 ° C. or higher and 1300 ° C. or lower. By the first annealing, the first silicon oxide film and the second silicon oxide film become a dense film.

In step S116, the gate electrode 30 is formed on the second silicon oxide film. The gate electrode 30 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

In step S118, the interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is, for example, a silicon oxide film.

In step S120, the source electrode 34 is formed. The source electrode 34 is formed on the source region 18 and the p-well contact region 20. The source electrode 34 is formed, for example, by sputtering nickel (Ni) and aluminum (Al).

In step S122, the drain electrode 36 is formed. The drain electrode 36 is formed on the back surface side of the silicon carbide substrate 12. The drain electrode 36 is formed, for example, by sputtering nickel.

In step S124, the second annealing is performed. The second annealing is performed, for example, in an argon gas atmosphere at 400 ° C. or higher and 1000 ° C. or lower. The second annealing reduces the contact resistance between the source electrode 34 and the drain electrode 36.

The MOSFET 100 shown in FIG. 1 is formed by the above manufacturing method.

Next, the operation and effect of the first embodiment will be described.

When a MOSFET is formed using silicon carbide, there is a problem that the mobility of carriers deteriorates. It is considered that the interface state between the silicon carbide layer and the gate insulating layer and the energy level existing in the band gap of the gate insulating layer cause deterioration of carrier mobility.

Further, when a MOSFET is formed using silicon carbide, there is a problem that the threshold voltage fluctuates. It is considered that the energy level existing in the band gap of the gate insulating layer causes the fluctuation of the threshold voltage.

Further, there is a problem that the leakage current of the gate insulating film increases. It is considered that the energy level existing in the band gap of the gate insulating layer causes the leakage current of the gate insulating film.

In the MOSFE 100 of the first embodiment, the double bond of carbon and oxygen forming an energy level in the gate insulating layer is reduced. Therefore, deterioration of carrier mobility, fluctuation of threshold voltage, and increase of leakage current of the gate insulating film are suppressed. Therefore, a MOSFET with improved characteristics is realized. The details will be described below.

The first-principles calculation by the inventors revealed that when silicon carbide is thermally oxidized to form a silicon oxide film, a large amount of carbon double-bonded with oxygen is generated in the silicon oxide film. That is, it was clarified that the second bonding structure shown in FIG. 5 was generated in a large amount in the silicon oxide film.

Excess carbon is generated by oxidizing silicon carbide. This surplus carbon forms carbon clusters in the silicon oxide film near the interface between the silicon carbide layer and the silicon oxide film, for example. For example, a second bond structure is generated at the end of this carbon cluster. Further, for example, excess carbon enters the oxygen position in the silicon oxide film, so that a second bonded structure is generated.

FIG. 7 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. 7 (a) and 7 (b) are band diagrams in the case where the silicon oxide film has a second bonding structure. FIG. 7C is a band diagram when the silicon oxide film has a first bonding structure. FIG. 7 is based on the inventor's first principle calculation.

When there is a double bond of carbon and oxygen in the silicon oxide film, that is, when there is a second bond structure, for example, as shown in FIGS. 7 (a) and 7 (b), the silicon oxide film has a double bond. An energy level containing no electrons (white circle in FIG. 7) and an energy level filled with electrons (black circle in FIG. 7) are generated.

In the case of FIG. 7A, the energy level containing no electrons is located near the lower end of the conduction band of 4H-SiC. In the case of FIG. 7B, the energy level containing no electrons is located slightly below the lower end of the conduction band of silicon oxide.

In the second bond structure, the degree of interaction between the carbon and oxygen that are double bonded varies depending on the surrounding structure. As the degree of interaction changes, the level of energy level in the silicon oxide film changes. The change in energy level level is at any level between the levels shown in FIGS. 7 (a) and 7 (b).

For example, in the case of FIG. 7A, the energy level containing no electrons is near the lower end of the conduction band of 4H-SiC. Therefore, the second bonding structure tends to cause deterioration of carrier mobility. Further, for example, in the case of FIG. 7B, the energy level containing no electrons is located slightly below the lower end of the conduction band of silicon oxide. Therefore, the second coupling structure tends to cause fluctuations in the threshold voltage and an increase in the leakage current of the gate insulating film.

On the other hand, as shown in FIG. 7 (c), in the case of the first bonded structure in the silicon oxide film, there are only levels filled with electrons in the silicon oxide film. The level containing no electrons is shallower than the lower end of the conduction band of the silicon oxide film. In other words, there are no electron trapping levels in the bandgap of the silicon oxide film.

Therefore, the first coupling structure does not cause deterioration of carrier mobility, fluctuation of threshold voltage, and increase of leakage current of the gate insulating film.

In the MOSFET 100 of the first embodiment, the second bonded structure in the silicon oxide film is converted into the first bonded structure. Therefore, the harmful energy level in the silicon oxide film caused by the second bonding structure disappears. Therefore, the deterioration of the carrier mobility of the MOSFET 100, the fluctuation of the threshold voltage, and the increase of the leakage current of the gate insulating film are suppressed.

In the method for manufacturing MOSFE100 of the first embodiment, the drift layer 14 and the p-well region 16 are thermally oxidized in step S108 to form a first silicon oxide film (insulating film) of silicon oxide. At this time, a large amount of the second bonded structure is formed in the first silicon oxide film.

In step S110, the first silicon oxide film is irradiated with microwaves in an atmosphere containing water. The energy of the microwave breaks the carbon-oxygen double bond in the second bond structure. Then, two OH groups derived from water in the atmosphere are bonded to carbon to form a first bonded structure.

In step S112, a second silicon oxide film is formed on the first silicon oxide film. The second silicon oxide film is formed of a sedimentary film rather than a thermal oxide film. Therefore, there is little excess carbon in the second silicon oxide film, and it is difficult to form the second bonded structure.

When the gate insulating layer 28 is formed by the first silicon oxide film of the thermal oxide film and the second silicon oxide film of the deposited film, the density of the first bonded structure of the first region 28a is increased. It is higher than the density of the first bonded structure in the second region 28b.

After forming the first bonded structure by microwave irradiation, the first terminal group (T1) and the second terminal group (T2) are subjected to plasma treatment with fluorine (F) to form a hydroxyl group (OH). Can be replaced with fluorine (F). Further, for example, by performing plasma treatment of hydrogen (H) or deuterium (D), the first terminal group (T1) and the second terminal group (T2) can be hydrogenated from the hydroxyl group (OH). It can be replaced with H) or deuterium (D).

It is preferable that the amount of the first carbon (C) in the gate insulating layer 28 is larger than that of the second carbon (C). In other words, it is preferable that the first bonding structure in the gate insulating layer 28 is larger than the second bonding structure. By reducing the amount of the second coupling structure in the gate insulating layer 28, the characteristics of the MOSFET are improved.

The temperature at the time of irradiating the microwave is preferably 300 ° C. or higher and 600 ° C. or lower. If it is below the above range, water may not be sufficiently diffused into the first silicon oxide film. If it exceeds the above range, oxidation of the silicon carbide layer may proceed.

The thickness of the first silicon oxide film is preferably 10 nm or less. If it exceeds the above range, the amount of the second bonded structure may become too large.

As described above, according to the first embodiment, the deterioration of the mobility of the carrier of the MOSFET is suppressed. In addition, the threshold fluctuation of the MOSFET is suppressed. In addition, an increase in the leakage current of the MOSFET is suppressed. Therefore, a MOSFET with improved characteristics is realized.

(Second embodiment)
The semiconductor device of the second embodiment is located between the semiconductor layer and the insulating layer, and has nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and scandium (Sc). ), Yttrium (Y), and at least one selected from the group consisting of lanthanoids (La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). It differs from the first embodiment in that it further includes a region containing an element. Hereinafter, some descriptions of the contents overlapping with the first embodiment will be omitted.

FIG. 8 is a schematic cross-sectional view of the semiconductor device of the second embodiment. The semiconductor device of the second embodiment is a MOSFET 200. The MOSFET 200 is a DI MOSFET. Further, the MOSFET 200 is an n-channel MOSFET having electrons as carriers.

The MOSFET 200 includes a silicon carbide substrate 12, a drift layer 14 (semiconductor layer), a p-well region 16 (semiconductor layer), a source region 18, a p-well contact region 20, a gate insulating layer 28 (insulating layer), a gate electrode 30, and interlayer insulation. A film 32, a source electrode 34, a drain electrode 36, and an interface region 40 (region) are provided. The gate insulating layer 28 has a first region 28a and a second region 28b.

The interface region 40 is located between the drift layer 14 and the p-well region 16 and the gate insulating layer 28. The interface region 40 includes nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), scandium (Sc), yttrium (Y), and lanthanoids (La, Ce, Pr, It contains at least one element (terminating element) of the group Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu).

FIG. 9 is a diagram showing the concentration distribution of the terminal element of the second embodiment.

The terminal element is segregated at the interface between the drift layer 14 and the p-well region 16 and the gate insulating layer 28. The peak of the concentration distribution of the terminal element is in the interface region 40.

The full width at half maximum with respect to the peak of the concentration distribution of the terminal element is, for example, 1 nm or less. Further, the full width at half maximum with respect to the peak of the concentration distribution is preferably, for example, 0.25 nm or less, and more preferably less than 0.2 nm.

The terminal element replaces the silicon atom or carbon atom in the uppermost layer of the drift layer 14 and the p-well region 16. Since the atom in the uppermost layer is substituted, the terminal element is tricoordinated with the silicon carbide layer. In other words, the terminal element is at the position of the silicon atom or carbon atom in the crystal lattice of silicon carbide. That is, the terminal element is tri-coordinated with the carbon atom of the silicon carbide layer or tri-coordinated with the silicon atom of the silicon carbide layer.

The peak value of the concentration distribution of the terminal element in the interface region 40 is, for example, 4 × 10 ¹⁶ cm ^-3 or more and 4 × 10 ²⁰ cm ^-3 or less.

The concentration and distribution of the terminal elements in the interface region 40 can be measured, for example, by secondary ion mass spectrometry (SIMS). Further, regarding the concentration and distribution of the terminal element, for example, the electronic state and its spatial distribution can be specified by XPS, TEM-EDX, Atom Probe, HR-RBS and the like. Infrared spectroscopy and Raman spectroscopy also observe a vibration mode based on a structure tricoordinated to the silicon carbide layer.

The concentration of the terminal element in the gate insulating layer 28 and the silicon carbide layer is, for example, 2 × 10 ¹⁶ cm ^-3 or less.

Next, a method of manufacturing the semiconductor device of the second embodiment will be described.

In the method for manufacturing a semiconductor device according to the second embodiment, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and scandium (Sc) are used before irradiation with microwaves. , Yttrium (Y), and at least one element selected from the group consisting of lanthanoids (La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). It differs from the production method of the first embodiment in that the heat treatment is performed in an atmosphere containing.

FIG. 10 is a process flow chart of a method for manufacturing a semiconductor device according to the second embodiment.

As shown in FIG. 10, the manufacturing method of the semiconductor device includes drift layer formation (step S100), p-type impurity ion injection (step S102), n-type impurity ion injection (step S104), and p-type impurity ion injection (step S106). ), First silicon oxide film formation (step S108), interfacial termination heat treatment (step S109), microwave irradiation (step S110), second silicon oxide film formation (step S112), first annealing (step S114). , Gate electrode formation (step S116), interlayer insulating film formation (step S118), source electrode formation (step S120), drain electrode formation (step S122), and second annealing (step S124).

In step S109, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismus (Bi), scandium (Sc), yttrium (Y), and lanthanoids (La, Ce, Pr, Nd). , Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) The heat treatment is performed in an atmosphere containing at least one element (terminating element). The temperature of the heat treatment is, for example, 300 ° C. or higher and 900 ° C. or lower.

The interface region 40 is formed by step S109.

After the interface region 40 is formed, in step S110, the first silicon oxide film is irradiated with microwaves in an atmosphere containing water. By irradiating the first silicon oxide film with microwaves in an atmosphere containing water, the double bond between carbon and oxygen is broken, and a structure in which carbon is bonded to two hydroxyl groups (OH) is formed. .. In other words, the second bonding structure is converted into a first bonding structure in which the first terminal group (T1) and the second terminal group (T2) are hydroxyl groups (OH).

Immediately after the formation of the first silicon oxide film and before the interface termination heat treatment, a third annealing equivalent to the first annealing may be performed. The third annealing makes it difficult for the terminal element during the interface termination treatment to be distributed in the insulating film, and makes it easy for the terminal element to pile up on the interface of the substrate.

Next, the operation and effect of the second embodiment will be described.

When a MOSFET is formed using silicon carbide, there is a problem that the mobility of carriers deteriorates. It is considered that the interface state between the silicon carbide layer and the gate insulating layer and the energy level in the gate insulating layer cause deterioration of carrier mobility.

The interface state between the silicon carbide layer and the gate insulating layer is considered to be caused by dangling bonds of silicon atoms or carbon atoms in the uppermost layer of the silicon carbide layer.

In the MOSFET 200 of the second embodiment, the amount of the interface state between the silicon carbide layer and the gate insulating layer 28 is reduced by forming the interface region 40. In the MOSFET 200, the silicon atom having a dangling bond or the carbon atom having a dangling bond in the uppermost layer of the drift layer 14 and the p-well region 16 is replaced by a terminal element. Therefore, dangling bonds are reduced. Therefore, in the MOSFET 200, deterioration of carrier mobility is further suppressed.

In the method for manufacturing the MOSFET 200 of the second embodiment, the interface region 40 is formed before the first silicon oxide film is irradiated with microwaves. The presence of the interface region 40 suppresses the oxidation of the silicon carbide layer when the first silicon oxide film is irradiated with microwaves. Therefore, it is suppressed that a second bond structure is newly formed by thermal oxidation.

As described above, according to the second embodiment, the deterioration of the mobility of the carrier of the MOSFET is suppressed. In addition, the threshold fluctuation of the MOSFET is suppressed. In addition, an increase in the leakage current of the MOSFET is suppressed. Therefore, a MOSFET with improved characteristics is realized.

(Third embodiment)
The semiconductor device of the third embodiment is different from the first embodiment in that the first coupling structure is present in the gate insulating layer in the terminal region of the MOSFET. Some descriptions will be omitted for the contents that overlap with the first embodiment.

FIG. 11 is a schematic cross-sectional view of the semiconductor device of the third embodiment. The semiconductor device of the third embodiment is a MOSFET 250. The MOSFET 250 includes an element region and a termination region provided around the element region. The termination region has a function of improving the withstand voltage of the MOSFET 250.

In the element region, for example, the MOSFET 100 of the first embodiment is arranged as a unit cell.

The terminal region includes a p-type resurf region 60 (semiconductor layer), a p ⁺ type contact region 62, a p-type guard ring region 64 (semiconductor layer), a gate insulating layer 28 (insulating layer), and a field oxide film 33. ..

The configuration of the gate insulating layer 28 is the same as that of the semiconductor device of the first embodiment.

The field oxide film 33 is, for example, a silicon oxide film.

When the MOSFET 250 is turned off, the depletion layer is formed in the drift layer 14 between the resurf region 60, the guard ring region 64, and the guard ring region 64, so that the withstand voltage of the MOSFET 250 is improved.

However, if an energy level is present in the gate insulating layer 28, the charge is trapped in the energy level. The electric field of the trapped charge may prevent the formation of the desired depletion layer. In this case, the withstand voltage of the MOSFET 250 deteriorates.

According to the third embodiment, the second bonding structure of the gate insulating layer 28 is converted into the first bonding structure. Therefore, the energy level in the gate insulating layer 28 is reduced. Therefore, a desired depletion layer is formed and a MOSFET with a stable withstand voltage is realized.

(Fourth Embodiment)
The inverter circuit and drive device of the fourth embodiment are drive devices including the semiconductor device of the first embodiment.

FIG. 12 is a schematic view of the drive device of the fourth embodiment. The drive device 300 includes a motor 140 and an inverter circuit 150.

The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c having the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

According to the fourth embodiment, the characteristics of the inverter circuit 150 and the drive device 300 are improved by providing the MOSFET 100 with improved characteristics.

(Fifth Embodiment)
The vehicle of the fifth embodiment is a vehicle provided with the semiconductor device of the first embodiment.

FIG. 13 is a schematic view of the vehicle of the fifth embodiment. The vehicle 400 of the fifth embodiment is a railroad vehicle. The vehicle 400 includes a motor 140 and an inverter circuit 150.

The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the wheels 90 of the vehicle 400.

According to the fifth embodiment, the characteristics of the vehicle 400 are improved by providing the MOSFET 100 with improved characteristics.

(Sixth Embodiment)
The vehicle of the sixth embodiment is a vehicle provided with the semiconductor device of the first embodiment.

FIG. 14 is a schematic view of the vehicle of the sixth embodiment. The vehicle 500 of the sixth embodiment is an automobile. The vehicle 500 includes a motor 140 and an inverter circuit 150.

The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the wheels 90 of the vehicle 500.

According to the sixth embodiment, the characteristics of the vehicle 500 are improved by providing the MOSFET 100 with improved characteristics.

(7th Embodiment)
The elevator of the seventh embodiment is an elevator provided with the semiconductor device of the first embodiment.

FIG. 15 is a schematic diagram of the elevator of the seventh embodiment. The elevator 600 of the seventh embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoisting machine 616, a motor 140, and an inverter circuit 150.

The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

The motor 140 is driven by the AC voltage output from the inverter circuit 150. The hoisting machine 616 is rotated by the motor 140, and the car 610 is moved up and down.

According to the seventh embodiment, the characteristics of the elevator 600 are improved by providing the MOSFET 100 with improved characteristics.

As described above, in the first to third embodiments, the case of 4H-SiC as the crystal structure of silicon carbide has been described as an example, but the present invention can be applied to silicon carbide having other crystal structures such as 6H-SiC and 3C-SiC. It is also possible to apply.

Further, in the first to third embodiments, the case where the gate insulating layer 28 is provided on the silicon surface of the silicon carbide has been described as an example, but other surfaces of the silicon carbide, for example, the carbon surface, the a surface, and the m surface, have been described. The present invention can also be applied when the gate insulating layer 28 is provided on the (0-33-8) plane or the like.

Further, in the first to third embodiments, the case where the semiconductor layer is silicon carbide has been described as an example, but the semiconductor layer may be diamond.

Further, in the first to third embodiments, the n-channel type planar MOSFET has been described as an example, but the present invention can also be applied to the n-channel type trench type MOSFET. Typical orientations of the trench side surface are a-plane, m-plane, (0-33-8) plane, and the like. The a-plane and the m-plane are planes perpendicular to the Si-plane and the C-plane. The (0-33-8) plane is a plane tilted by 54.7 ° in the <1-100> direction with respect to the (0001) plane. This crystal plane orientation is the crystal plane corresponding to Si (001) in the Si crystal.

The present invention can also be applied to an n-channel type IGBT (Insulated Gate Bipolar Transistor).

Further, the present invention can be applied not only to the n-channel type but also to the p-channel type MOSFET or IGBT.

Further, in the fourth to seventh embodiments, the case where the semiconductor device of the present invention is applied to a vehicle or an elevator has been described as an example, but the semiconductor device of the present invention is applied to, for example, a power conditioner of a photovoltaic power generation system. It is also possible to do.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or modified with the components of another embodiment. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

14 Drift layer (semiconductor layer)
16 p-well region (semiconductor layer)
28 Gate insulating layer (insulating layer)
28a First region 28b Second region 30 Gate electrode 40 Interface region (region)
60 Resurf region (semiconductor layer)
64 Guard ring area (semiconductor layer)
100 MOSFET (semiconductor device)
150 Inverter circuit 200 MOSFET (semiconductor device)
250 MOSFET (semiconductor device)
300 Drive 400 Vehicle 500 Vehicle 600 Elevator

Claims (19)

With a semiconductor layer of silicon carbide or diamond,
Located on the semiconductor layer, it is bonded to the first carbon, the first atom bonded to the first carbon, the second atom bonded to the first carbon, and the first carbon. The first atom has silicon (Si), carbon (C), oxygen (O), and nitrogen. It is one atom selected from the group consisting of (N) and aluminum (Al), and the second atom is silicon (Si), carbon (C), oxygen (O), nitrogen (N), and , Aluminum (Al), and the first terminal group is a group consisting of a hydroxyl group (OH), a fluorine (F), a hydrogen (H), and a deuterium (D). The second terminal group is one terminal group selected from the group consisting of a hydroxyl group (OH), a fluorine (F), a hydrogen (H), and a deuterium (D). With an insulating layer that is
A semiconductor device equipped with. The semiconductor device according to claim 1, wherein the insulating layer is an oxide or an oxynitride. The semiconductor device according to claim 1 or 2, wherein the insulating layer is silicon oxide. The semiconductor device according to any one of claims 1 to 3, wherein the insulating layer has a second carbon that double bonds with oxygen, and the first carbon is more than the second carbon. Located between the semiconductor layer and the insulating layer, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismus (Bi), scandium (Sc), yttrium (Y), and , Further comprising a region containing at least one element selected from the group consisting of lanthanoids (La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). The semiconductor device according to any one of claims 1 to 4. The semiconductor device according to any one of claims 1 to 5, wherein the first terminal group and the second terminal group are of the same type. The insulating layer has a first region and a second region sandwiching the first region between the semiconductor layer, and the first carbon in the first region is the second region. The semiconductor device according to any one of claims 1 to 6, which has more than the first carbon in the region. The semiconductor device according to any one of claims 1 to 7, further comprising a gate electrode that sandwiches the insulating layer between the semiconductor layer and the semiconductor layer. The semiconductor device according to any one of claims 1 to 8, wherein the thickness of the insulating layer is 30 nm or more and 100 nm or less. The inverter circuit including the semiconductor device according to any one of claims 1 to 9. A drive device including the semiconductor device according to any one of claims 1 to 9. A vehicle including the semiconductor device according to any one of claims 1 to 9. An elevator comprising the semiconductor device according to any one of claims 1 to 9. An insulating film is formed on the semiconductor layer of silicon carbide or diamond, and the insulating film is formed.
A method for manufacturing a semiconductor device that irradiates the insulating film with microwaves in an atmosphere containing water. The method for manufacturing a semiconductor device according to claim 14, wherein the insulating film is formed by thermal oxidation. The method for manufacturing a semiconductor device according to claim 14 or 15, wherein the temperature at the time of irradiating the microwave is 300 ° C. or higher and 600 ° C. or lower. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein the thickness of the insulating film is 10 nm or less. The method for manufacturing a semiconductor device according to any one of claims 14 to 17, wherein plasma treatment of fluorine (F), hydrogen (H), or deuterium (D) is performed after irradiation with the microwave. Before irradiating with the microwave, nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismus (Bi), scandium (Sc), yttrium (Y), and lanthanoid (La, 14 to claim 14 to perform heat treatment in an atmosphere containing at least one element selected from the group consisting of Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). 18. The method for manufacturing a semiconductor device according to any one of claims 18.

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