JP2016058500A - Semiconductor element formation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a formation method of a semiconductor element which has atomic-order flatness on an interface between a semiconductor region for channel formation and a gate oxide film.SOLUTION: A semiconductor element formation method includes the step of arranging in an inert gas atmosphere, a Si semiconductor substrate where an element isolation pattern is formed on a surface and performing annealing at a temperature of 900°C or less for a predetermined time. The semiconductor element formation method includes the step of performing a heat treatment before the annealing, at a temperature lower than an annealing temperature in the annealing.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a method for forming a semiconductor element constituting a semiconductor device such as an IC or LSI.

  The history of semiconductor devices such as ICs and LSIs is also the history of miniaturization of semiconductor elements (transistors and the like) constituting high integration. A typical semiconductor element is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the MOSFET, a source region is formed on one side, a drain region is formed on the other side, and a semiconductor region (active region) in which a channel region is formed is formed therebetween. In general, a gate oxide film is provided on the semiconductor region. A gate electrode is provided on the gate oxide film. The channel region is formed immediately below the gate oxide film when the element is driven, and the element is turned on and off by controlling the amount of charge moving through the channel region. That is, an ON-OFF signal is applied to the gate electrode to turn on and off the current flowing through the channel region (current drive).

1A, 1B, and 1C schematically show a structure of a typical MOSFET.
A MOSFET 100 shown in FIG. 1A includes a source region 102 and a drain region 103 formed on a single crystal silicon (Si) semiconductor substrate (silicon wafer) 101, and a semiconductor region (active region) 104 between which a channel region is formed. Has been.
A gate oxide film 105 and a gate electrode 106 can be provided on the semiconductor region 104. 1A and 1B schematically show the interface (I) between the semiconductor region 104 and the gate oxide film 105 in an enlarged manner. FIG. 1B partially exaggerates the case where the interface (I) is uneven and FIG. 1C shows the case where the interface (I) is smooth. When the MOSFET 100 is not so fine, the influence of the unevenness of the interface (I) shown in FIG. 1B can be ignored for a large amount of charges (electrons, holes) moving in the channel region. As the element size becomes smaller, the influence of this unevenness on the movement of charges becomes larger. Therefore, as shown in FIG. 1C, the smoothness of the interface (I) is required to be even to the atomic order level as the element size is reduced. That is, as the MOSFET element itself becomes smaller due to the demand for miniaturization, the current driving capability (current driving capability) becomes more influenced by the flatness of the interface (I) between the gate oxide film and the semiconductor region. . That is, as shown in FIG. 1C, when the smoothness of the interface (I) is excellent, the charge goes straight from the source region 102 toward the drain region 103 as shown by the arrow B, whereas in FIG. If the interface (I) is uneven as shown in FIG. 5B, the electric charge moves to the drain region 103 depending on the unevenness in the direction of movement as shown by the arrow A.

As a result, when the flatness of the interface (I) is poor, the current driving capability is lowered and unsuitable for high-speed operation of the device. Therefore, the surface of the single crystal silicon (Si) semiconductor substrate (silicon wafer) is made as flat as possible. (Non-Patent Document 1). For this reason, conventionally, planarization treatment in atomic order has been performed in advance on the surface of a single crystal silicon (Si) semiconductor substrate (silicon wafer) on which MOSFETs are highly integrated (for example, Non-Patent Document 2 and Patent Document 1). 2).
However, in practice, various processes (ion implantation, well formation, element isolation, etching, cleaning, rinsing, etc.) are applied to the Si semiconductor substrate immediately before forming the gate oxide film on the semiconductor region. It is extremely difficult to maintain the initial atomic order flatness of the surface of the semiconductor region even after the gate oxide film is formed.
As one of the solutions, alkali-free cleaning that is performed at room temperature with light and air completely blocked is used for cleaning, and radical oxidation is used for gate oxide film formation. This is a method (conventional method A).

T. Ohmi, K. Kotani, A. Teramoto, and M. Miyashita, IEEE Elec. Dev. Lett., 12, 652 (1991). L. Zhong, A. Hojo, Y. Matsushita, Y. Aiba, K. Hayashi, R. Takeda, H. Shirai, and H. Saito, Phy. Rev. B. 54, 2304 (1996).

International publication WO2011 / 096417A1 International Publication WO2013 / 150636A1

However, in the conventional method A, since alkali cleaning cannot be employed, it is difficult to completely remove particles remaining on the surface to be processed of the semiconductor substrate.
Furthermore, since it is necessary to completely block light and air, a manufacturing apparatus for that purpose must be prepared, and an increase in manufacturing cost is inevitable. For this reason, the operating profit of the semiconductor device to be manufactured is pressed.
Therefore, it is conceivable to perform an annealing process for conventional atomic order flattening after the element isolation pattern is formed. However, since the principle of flattening is due to migration of silicon (Si), the SiO2 surface coexists in addition to the Si surface. Then, if the film quality of the SiO2 film is not high quality (satisfying the stoichiometric relationship), if even a slight amount of oxygen or moisture is present in the process atmosphere, silicon (Si) reacts with oxygen or moisture, There is a concern that it becomes SiO or SiH4 and leaves the film.
Therefore, it is necessary to exclude oxygen and moisture as much as possible in the processing atmosphere during the element manufacturing process.
Furthermore, if the film quality of the SiO2 film is not high, the SiO2 film tends to take oxygen and moisture from the processing atmosphere into the film during the manufacturing process, and also tends to adsorb moisture on the surface. is there.
Therefore, when annealing treatment is performed on the SiO2 film, oxygen and moisture are released from the film during the treatment process, and the released oxygen and moisture react with Si in the Si film to be separated from the film as SiO or SiH4. There is a concern.
On the other hand, a high-quality SiO2 film cannot be obtained unless it is a thermal oxide film, but a thermal oxide film as a high-quality SiO2 film cannot be easily obtained unless the temperature is higher than 1000 ° C. There is.
However, until now, in the formation of MOSFETs, when such a high temperature process is applied, the element region is also oxidized. Therefore, an element isolation film and a gate oxide film are formed by a sputtering method or a CVD method. In such a method, it is said that a high quality film such as a thermal oxide film cannot be obtained.
In addition, the surface of the Si layer is hydrogen-terminated in the state after cleaning with hydrofluoric acid, but the hydrogen desorbs from the surface of the Si layer in the region of 380 ° C. to 450 ° C. as the temperature is increased. When the terminal hydrogen disappears, the surface of the Si layer is very easily oxidized, and a silicon oxide film is often formed. When this silicon oxide film is formed, the subsequent planarization process is hindered.

The present invention has been made in view of the above problems, and one of its purposes is to form a semiconductor region for channel formation (without forming an atomic order planarization surface treatment in advance on a silicon wafer before device formation). (Hereinafter referred to as “semiconductor region (Ch)”) and an interface (I) between the gate oxide film and a method for forming a semiconductor element capable of forming a semiconductor element having flatness on the atomic order. It is.
Another object of the present invention is that the flatness of the interface (I) of the formed element can be formed at the atomic order level even when the element is miniaturized, and further high-speed operation and high functionality can be achieved. It is to provide a method for forming a semiconductor device

One aspect of the present invention includes a step of providing a Si semiconductor substrate having an element isolation pattern formed on the surface thereof in an inert gas atmosphere and annealing at 900 ° C. or lower for a predetermined time in the FET formation process. A method for forming a semiconductor element is provided.
Another aspect of the present invention lies in a method for forming a semiconductor element, including a step of performing a heat treatment at a temperature lower than the annealing temperature of the annealing treatment before the annealing treatment.
Still another aspect of the present invention lies in a method for forming a semiconductor element, including a step of performing radical oxidation treatment by plasma excitation before the annealing treatment.

  According to the present invention, the interface (I) between the semiconductor region for channel formation and the gate oxide film can be provided with atomic order flatness, and a semiconductor device capable of further high-speed operation and high functionality can be provided.

The typical structure explanatory view for explaining that the movement state of the electric charge which moves the channel region in MOSFET of a typical structural example depends on the flatness of the interface just under the gate insulating film. FIG. 1B is an enlarged view in a circle indicated by a dotted line in FIG. 1A, showing an example of a structure in which an interface (I) is uneven. FIG. 1B is an enlarged view in a circle indicated by a dotted line in FIG. 1A and shows an example of a structure in which an interface (I) is smooth. The typical structure explanatory view showing typically the structure of the typical example of MOSFET concerning the present invention. The figure which shows a suitable example of the manufacturing process of the manufacturing method in connection with this invention. Sectional drawing which shows each process of FIG. 3 typically. FIG. 4B is a cross-sectional view schematically showing each process following FIG. 4A. The graph which shows an example of the measurement result of the sample created in connection with this invention. The graph which shows the other example of the measurement result of the sample produced in connection with this invention. The graph which shows the temperature sequence (annealing conditions (i)) in the case of sample preparation in this invention. The graph which shows another temperature sequence (annealing condition (ii)) in the case of sample preparation in this invention.

  Here, a method of forming the MOSFET according to the present embodiment will be described with reference to FIGS.

FIG. 2 is a schematic structural explanatory view schematically showing the structure of a typical example of a MOSFET according to the present invention.
A MOSFET 900 shown in FIG. 2 has a structure in which each element (MOSFET) is isolated by an STI (Shallow Trench Isolation) element isolation method.
MOSFET 900 includes a semiconductor substrate 901, field insulating films (buried oxide films) 902a and 902b, source region 906, drain region 907, gate insulating film 904, gate electrode 905, silicide films 903a, 903b and 903c, interlayer insulating film 908a, 908b, a gate extraction electrode 909, a source extraction electrode 910, a drain extraction electrode 911, and a sidewall 912.

3, 4A and 4B are schematic manufacturing process explanatory diagrams for explaining a preferable example of a part of the manufacturing process according to the present invention.
Each process shown in FIG. 3 is as follows.
Step (A): Pad oxide film (SiO 2 film) 301, CVD nitride film forming step (B): Nitride film (Si 3 N 4) 302, oxide film (SiO 2) 301, (Si) semiconductor substrate 901 Step of forming shallow groove 303 by etching and forming trench oxide film (SiO 2) 304 (C)... Forming field insulating film (SiO 2 film) 902 and the upper portion thereof, and removing trench oxide film 303 by CMP Step (D) ... Natural oxide film / nitride film 302 removal step (E) ... Pad oxide film 301 removal step (F) ... Step of forming oxide film 305 by wet oxidation before ion implantation ( G) ... Well formation (ion implantation)
Step (H) ... Removal step of oxide film 305 before ion implantation (I) ... Planarization process of atomic order (J) ... Formation step of gate insulating film (oxide film) 904 by radical oxidation (K) ) ... Formation of gate electrode 905

First, the surface of the semiconductor substrate 901 (silicon wafer, silicon semiconductor substrate) is cleaned by a cleaning method using an alkaline solution and rinsed with pure water.
Next, in order to define an element formation region, a pad SiO2 film 301 and a Si3N4 film 302 are formed on the surface of the semiconductor substrate 901, and then a predetermined portion of the semiconductor substrate 901 is etched to form a shallow isolation groove 303 (303a). , 303b).
After the inner wall of the groove 303 is thermally oxidized to form the trench oxide film 304, a channel stopper impurity is introduced into the groove bottom surface and the groove side surface as necessary.
Thereafter, a sufficient amount of SiO2 is deposited so as to fill the trench 303 with SiO2 by CVD to form field insulating films 902 (902a, 902b).
At this time, the nitride film 302 is exposed by flattening an excess region formed of CVD-SiO 2 using a planarization technique such as CMP (Chemical Mechanical Polishing).
Finally, the nitride film 302 is removed to complete the element isolation structure (“Step (D)”).
Next, the pad oxide film 301 is removed (“Step (E)”).
Then, before the ion implantation, wet oxidation is performed (“step (F)”), and then ion implantation is performed in a predetermined region to form a well, thereby providing a source region 906 and a drain region 907 (“step (G) ) ").
Next, the oxide film formed by the oxidation treatment in the step (F) is removed (“Step (H)”).
Next, an atomic order flattening process according to the present invention is performed (“Step (I)”).
Thereafter, radical oxidation treatment is performed to form a gate insulating film 904 (“step (J)”).
A polysilicon (Poly-Si) film is deposited on the gate insulating film 904 to form a gate electrode 905 (“Step (K)”).
Thereafter, sidewalls 912 (912a, 912b) are formed with a silicon nitride film or the like as necessary.
Next, as a preferred mode, it is desirable to perform silicide processing on the surface of the gate electrode 905, the surface of the source region 906, and the surface of the drain region 907 to provide silicide films 903 (903a, 903b, 903c) made of CoSi or the like.
After that, an interlayer insulating film 908 is provided, a contact hole is formed at a predetermined position of the interlayer insulating film 908, and then the contact hole is filled with a desired metal to obtain a gate extraction metal electrode 909, a source extraction metal electrode 910, A drain extraction metal electrode 911 is formed.
As described above, a MOSFET having a structure as shown in FIG. 2 is formed.

In addition, when a large number of transistors are formed on the same semiconductor substrate, the element isolation method between the transistors is as described in FIGS. 2, 3, 4A and 4B. In addition to STI (Shallow trench Isolation) embedded in trenches, LOCOS (Local
Oxidation of Silicon (Oxidation of Silicon) element isolation method, mesa isolation method, trench isolation method, etc. employed when forming a MOSFET in SOI (Silicon on Insulator) are used.
In miniaturization, STI is advantageous, and in the case of SOI, trench isolation, particularly trench isolation that partially leaves the Si layer is preferably employed.
Furthermore, those skilled in the art can easily conceive that the present invention can be applied to multi-channel FETs such as FIN-FETs.

In the method for forming a semiconductor element of the present invention, in the MOSFET formation process, the semiconductor substrate having an element isolation pattern formed on the surface is annealed at 900 ° C. or lower for a predetermined time in an inert gas atmosphere such as argon (Ar). The process of carrying out is included.
By performing this process, the surface of the activated region where the gate insulating film is formed becomes smooth (flatness) at the atomic order level. If a gate insulating film is formed on the surface of the activated region having smoothness, a MOSFET can be formed with the smoothness maintained at the contact interface between the activated region and the gate insulating film.
As the inert gas, helium (He), neon (Ne), krypton (Kr), xenon (Xe), nitrogen (N2), and the like can be used in addition to Ar gas.
In the present invention, since the surface to be processed of the semiconductor substrate is not only the Si surface but also the silicon oxide (SiO 2) surface immediately after the formation of the element isolation pattern, the quality of the SiO 2 film is high (stoichiometric). If there is even a small amount of oxygen or hydrogen in the process atmosphere, silicon (Si) reacts with oxygen or hydrogen to become SiO or SiH4 and is detached from the film. Therefore, oxygen and moisture are excluded as much as possible from the processing atmosphere during the device manufacturing process.
In the present invention, the oxygen / water concentration in the inert gas introduced into the processing atmosphere forming space for forming the processing atmosphere is preferably 100 ppb or less, preferably 30 ppb or less, more preferably 10 ppb or less.
In addition, before performing the planarization treatment in the present invention, it is preferable to perform pre-annealing treatment on the semiconductor substrate on which the element isolation pattern is formed to remove oxygen and moisture from the semiconductor substrate in advance. .
At this time, if the oxygen / moisture volatilized at the time of removal reacts with Si of the silicon film to form a silicon oxide film, the subsequent planarization may be hindered. Therefore, it is preferable to perform the pre-annealing process at a low temperature. .
Furthermore, when the atomic order is flattened, the surface of the Si film is terminated with hydrogen in a state after cleaning with hydrofluoric acid. However, when the temperature is increased, the hydrogen is removed from the Si film in a temperature range of 380 ° C. to 450 ° C. break away. Therefore, if the terminal hydrogen disappears from the Si film surface, the Si film surface is very easily oxidized.
Considering the above points in total, it is desirable to perform the oxygen / water removal treatment at 380 ° C. or lower. If the temperature is too low, the effect of removing oxygen and moisture becomes small, and it is more preferable to carry out in a temperature range of 300 ° C to 380 ° C.
The pre-annealing atmosphere need not be the same as the planarizing atmosphere, but preferably the pre-annealing atmosphere and the planarizing atmosphere should be the same to avoid complications. preferable.
The pre-annealing treatment for removing oxygen / moisture is performed until the oxygen / water concentration in the exhausted inert gas is preferably 100 ppb or less, more preferably 30 ppb or less, and even more preferably 10 ppb or less. Is desirable.

Hereinafter, the present invention will be described in more detail based on examples.
“Preparation of sample 1”
First, a silicon wafer (Si semiconductor substrate) having a diameter of 200 mmφ and a surface of (100) orientation was prepared, and the surface of the silicon wafer (semiconductor substrate) was cleaned by the following procedure.

That is, the surface of the silicon wafer was washed with ozone (O 3) water for 10 minutes, washed with diluted HF (0.5 wt%) for 1 minute, and finally rinsed with ultrapure water for 3 minutes.
Using the semiconductor substrate (1) whose surface has been cleaned in this manner, shallow trench isolation (STI) is performed by a well-known MOS device fabrication process, and P and N wells are formed by ion implantation, and gate insulation is performed. A film is formed by wet thermal oxidation at 850 ° C., and then gate electrode formation, source / drain region formation, interlayer insulation film formation, contact hole formation, metal contact formation, etc. are performed, and NMOSTr (gate length: 0.410 μm) was formed in 131072 pieces on the semiconductor substrate (1).
The semiconductor substrate in which the NMOS Tr is formed as described above is subjected to dilute hydrofluoric acid (0.5%) treatment for 1 minute immediately before forming the gate oxide film by radical oxidation (radical oxidation by Kr / O2 plasma). The natural oxide film was removed.
Next, immediately after rinsing with pure water for 10 minutes, it was set at a predetermined position of the annealing treatment apparatus and subjected to annealing treatment (planarization treatment in the present invention). The annealing conditions at this time are the annealing conditions (i) of the temperature sequence shown in FIG. 7 (Sample 1-1).
The procedure and conditions were the same as those of Sample 1-1, except that the gate length L was 0.28 μm (Sample 1-2), 0.25 μm (Sample 1-3), and 0.22 μm (Sample 1-4). In this case, 131072 NMOS transistors were formed on each semiconductor substrate.

“Preparation of Sample A (Comparative Example A)”
First, a silicon wafer (“semiconductor substrate (2)”) having a diameter of 200 mmφ and a surface of (100) orientation was prepared, and cleaning and rinsing of the surface of the semiconductor substrate (2) were performed in the same manner as the sample 1.

Using this semiconductor substrate (2), in the same manner as Sample 1, shallow trench isolation (STI) is performed by a known CMOS device manufacturing process, P well and N well are formed by ion implantation, and a gate insulating film is formed by 850. Formed by wet thermal oxidation at 0 ° C., followed by gate electrode formation, source / drain formation, interlayer insulating film formation, contact hole formation, metal contact formation, etc., to produce NMOSTr (gate length L 0.40 μm) (sample) A).
The number of NMOS Trs built in the semiconductor substrate (2) is 131,072.

“Preparation of Sample B (Comparative Example B)”
As will be described later in detail, a silicon wafer having a diameter of 200 mmφ and a surface of (100) orientation (“semiconductor substrate (3)”)) is prepared, and the surface of the semiconductor substrate (3) is cleaned and rinsed. The semiconductor substrate (3) thus cleaned was annealed at 850 ° C. for 300 minutes (“step (5)”) in accordance with the temperature sequence shown in FIG. The argon (Ar) flow rate during heating was 28 L / min.
First, a semiconductor substrate (3) having a diameter of 200 mmφ and a (100) -oriented surface is prepared.

The surface of the semiconductor substrate (3) was washed with ozone (O3) water for 10 minutes, then washed with dilute HF (0.5 wt%) for 1 minute, and finally ultrapure water rinse was performed for 3 minutes. .
Thereafter, the semiconductor substrate (3) subjected to the cleaning and rinsing treatment as described above was placed in a heat treatment apparatus. Next, an argon (Ar) gas having a moisture content of 0.2 ppb or less and oxygen (O 2) of 0.1 ppb or less flows in the heat treatment space in the heat treatment apparatus at a heat treatment temperature of 850 ° C. and a heat treatment time of 300 minutes. Under the conditions, the semiconductor substrate (3) was heat-treated.
The temperature sequence of the heat treatment at this time is shown in FIG.
That is, first, the temperature of the silicon wafer was maintained at 30 ° C. for 60 minutes (“Step (1)”). Thereafter, the temperature of the silicon wafer was increased to 200 ° C. at a temperature increase rate of 5 ° C./min, and held at 200 ° C. for 120 minutes (“step (2)”).
Next, the temperature of the silicon wafer was increased to 600 ° C. at a rate of temperature increase of 4 ° C./min, and held at 600 ° C. for 20 minutes (“Step (3)”).
Subsequently, the temperature of the silicon wafer was increased at a temperature increase rate of 3 ° C./min until the temperature of the silicon wafer reached 800 ° C., and held at 800 ° C. for 20 minutes (“Step (4)”).
Next, the temperature of the silicon wafer was increased to 850 ° C. at a temperature increase rate of 1.5 ° C./min, and held at 850 ° C. for 300 minutes (“Step (5)”).
Thereafter, the temperature was lowered until the temperature of the silicon wafer reached 30 ° C. in the temperature sequence shown in FIG.

That is, after the step (5), the temperature of the silicon wafer was lowered at a temperature drop rate of 1 ° C./min until the temperature of the silicon wafer reached 800 ° C. and held at 800 ° C. for 20 minutes (“step (6)”).
Thereafter, the temperature of the silicon wafer was lowered to 30 ° C. at a temperature lowering speed of 1.5 ° C./min. Thereafter, the heater of the heat treatment apparatus was turned off.
131072 NMOS transistors (Tr) were formed in the semiconductor substrate (3) thus prepared as follows.
First, T. Ohmi, “Total room temperature wet cleaning Si substrate
surface, ”J. Electrochem. Soc., Vol. 143, No. 9,
pp.2957-2964, Sep. 1996. Washing was performed by a washing method not using an alkaline solution.

Next, the field oxide film 902 was formed on the semiconductor substrate (3) subjected to the above-described processing by applying the element isolation method by STI according to the procedure described in FIGS.
Then, according to the procedures and conditions described in FIGS. 2 and 3, and not shown in FIGS. 2 and 3, as shown in FIG. 2, using other known methods that can be easily implemented by those skilled in the art. 131072 NMOS transistors having a structure were formed on the semiconductor substrate (3).
In each of Samples 1-1 to 1-4 and Samples A and B, the gate oxide film was formed by radical oxidation using Kr / O2 plasma without roughening the atomic order flat surface.

"Evaluation of each sample"
In Sample 1-1, Sample A, and B, the noise voltage (fluctuation of gate-source voltage) of 131072 NMOSTr at the drain current of 5 μA was evaluated, and the noise voltage of the NMOSTr having a cumulative frequency probability of 99% was evaluated. As a result of the evaluation, the result shown in FIG. 5 was obtained.
From this result, it can be seen that both Sample 1-1 and Sample B achieve noise reduction compared to Sample A.
However, in the case of Sample B, after the planarization annealing, alkali cleaning cannot be used to maintain the atomic order flat surface (the flat surface tends to be roughened by alkali cleaning). It was necessary to remove particles by sonic cleaning or the like. For this reason, the removal efficiency is poor, long time washing is required, and the production efficiency is remarkably lowered. Further, in order not to roughen the formed flat surface, it is necessary to completely shield the light during wet cleaning, and the process steps become complicated.
From the above, it was shown that the method for forming a semiconductor element according to the present invention performed on Sample 1-1 is remarkably excellent.

Example 2
“Preparation of Samples 2-1 to 2-3”
Samples 2-1 to 2-3 were created in the same procedure and conditions as Samples 1-2 to 1-4 except that the annealing conditions were the annealing conditions (i) of the temperature sequence shown in FIG.

Sample 2-1: Gate length L: 0.28 μm
Sample 2-2: Gate length L: 0.25 μm
Sample 2-3: Gate length L: 0.22 μm

The temperature sequence shown in FIG. 8 is essentially the same as the temperature sequence shown in FIG. 7 except that step (c) is added.
In this embodiment, the reason for introducing this step (c) is that the moisture concentration in the Ar exhaust gas is measured immediately after the temperature is raised to 350 ° C. when the planarization annealing process is performed in the temperature sequence shown in FIG. Then, since about 1 ppm was observed depending on the sample, this is to avoid the influence of moisture as much as possible.
The reason is that the observed moisture is considered to be water adhering to the SiO2 film for element isolation on the Si semiconductor substrate during rinsing with pure water, and when the temperature is further raised in this state, the water and the Si surface react to become flat. This is because it is assumed that there is a possibility of inhibiting the transformation.
As shown in FIG. 8, when the step (c) for heating and maintaining at 350 ° C. for 300 minutes is provided, the moisture concentration in the Ar exhaust gas in the steps after the step (c) can be lowered to 10 ppb or less. It was.
Thereby, even if it raised to 850 degreeC after that, the planarization process was able to be completed, releasing almost no water | moisture content.
The same evaluation as that of Sample 1-1 was applied to Samples 1-2 to 1-4 and Samples 2-1 to 2-3.
Then, as the gate length L of the transistor is shortened, as shown in the graph C of FIG. 6, according to the element manufacturing method of the sample 1, the noise voltage reduction effect decreases as the miniaturization progresses. It came to be seen.
On the other hand, in the case of Samples 2-1 to 2-3, as shown in the graph E of FIG. 6, the noise voltage reduction effect is not reduced as the miniaturization progresses. It was.
Examining the cause, it was presumed that in Samples 1-2 to 1-4, there was a problem with the edge of the element isolation pattern, and that the effect would become effective as the miniaturization of the element progressed.

Example 3
“Preparation of Samples 3-1 to 3-3”
The procedure and conditions are the same as those of Samples 1-2 to 1-4 except that a treatment step for radical oxidation is performed by plasma excited by microwaves (Kr / O2 plasma) at 2.45 GHz before the planarization annealing treatment. Samples 3-1 to 3-3 were prepared.
The conditions for radical oxidation at this time were as follows.

・ Semiconductor substrate: 200 mm wafer ・ Gas flow rate: Krypton (Kr): 1000 sccm
Oxygen (O2) gas ... 10 sccm
・ Microwave power: 3500W
・ Microwave power input time: 4 minutes

Sample 3-1: Gate length L: 0.28 μm
Sample 3-2: Gate length L: 0.25 μm
Sample 3-3: Gate length L: 0.22 μm

Evaluation similar to that of Sample 1-1 was applied to Samples 3-2 to 3-3. The result is shown in graph D of FIG.
As is clear from the results of FIG. 6, in the case of Samples 3-1 to 3-3, it can be seen that the noise voltage reduction effect continues to improve as miniaturization progresses.
This is because a radical oxidation process is performed before the planarization annealing process, so that an oxide film of about 4 nm is formed on the surface of the Si region part, and weak bonds are oxidized by radicals in the SiO 2 film part. It is presumed that the film was less degassed.

Example 4
“Preparation of Samples 4-1 to 3-4”
In Example 1, the annealing conditions for the planarization treatment were increased to 900 ° C. by extending the temperature raising time at a speed of 1.5 ° C./min after the elapse of step (4) from that in Example 1. Then, four samples, samples 4-1 to 4-4, were prepared under the same procedure and conditions as in the example except that step (5) was performed at this temperature.
When the same evaluations as Samples 1-1 to 1-4 were made, the results were far superior to Comparative Examples A and B, although the effect was slightly lower than Samples 1-1 to 1-4.

Sample 4-1: gate length L: 0.40 μm
Sample 4-2: gate length L: 0.28 μm
Sample 4-3: Gate length L: 0.25 μm
Sample 4-4: Gate length L: 0.22 μm

Although the present invention has been described only with respect to the case where it is used for a MOSFET, the present invention is not limited to this, but can be widely applied to other FETs, and can be applied to all integrated semiconductor devices equipped with FETs.
Further, in the description of the present invention so far, the formation of the gate insulating film is typical, and thus the case of radical oxidation, radical nitridation, radical acid / nitridation has been described, but the present invention is limited to this. Not a translation. In addition, it goes without saying that a person skilled in the art can easily arrive at the scope of the present invention when forming a film by deposition by a method such as CVD, sputtering, or vapor deposition. Understood.
For example, the present invention can also be effectively applied to the case where hafnium oxide or the like is formed by ALD (Atomic Layer Deposition), which is employed in FIN-FETs or the like.
As can be easily inferred from the above description, the present invention can greatly contribute to many fields related to semiconductors.

100 ... MOSFET
102 ... Source region 103 ... Drain region 104 ... Semiconductor region 105 ... Gate oxide film 106 ... Gate electrode 301 ... SiO2 film 302 ... Si3N4 film 303 ... Shallow Trench 304 ... trench oxide film 305 ... oxide film 900 ... MOSFET
901 ... Semiconductor substrate 902 ... Field insulating film 903 ... Silicide film 904 ... Gate insulating film 905 ... Gate electrode 906 ... Source region 907 ... Drain region 908 ... Interlayer insulating film 909... Gate extraction electrode 910... Source extraction electrode 911... Drain extraction electrode 912.

Claims (4)

  A method for forming a semiconductor element, comprising: a step of forming a FET in a process in which an Si semiconductor substrate having an element isolation pattern formed thereon is placed in an inert gas atmosphere and annealed at 900 ° C. or lower for a predetermined time.   The method for forming a semiconductor element according to claim 1, further comprising a step of performing a heat treatment at a temperature lower than an annealing temperature of the annealing treatment before the annealing treatment. The method for forming a semiconductor device according to claim 1, comprising a step of performing radical oxidation treatment by plasma excitation before the annealing treatment. The method for forming a semiconductor device according to claim 1, wherein the inert gas is at least one of argon (Ar), krypton (Kr), and xenon (Xe).

Images