JPH118206A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce contact the resistance between a diffusion layer and a silicide layer, while suppressing the layer resistance of a titanium silicide by depositing titanium on the surface of silicon substrate at a specified temperature. SOLUTION: An isolation insulator 2, a gate insulation film 3, a gate electrode 4, an LDD region 5, a gate sidewall 6 and a source-drain diffusion layer 7 are formed on a silicon substrate 1, and then the surface of the source-drain and the gate electrode is rendered amorphous by injecting arsenic. Subsequently, titanium 11 is deposited by sputtering, for example, while keeping the substrate temperature in the range of 400-600 deg.C. Thereafter, heat treatment for solidification is performed at the range of 600 deg.C or higher to 800 deg.C or lower in a nonocxidative atmosphere, so that the deposited titanium reacts on the silicon composing the source-drain or the gate. Finally, the non-silicified titanium and the nitrided titanium are removed by selective etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device including a step of forming a titanium silicide film in a self-aligned manner.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, it is important to reduce the resistance of a polysilicon layer used as a diffusion layer or a gate electrode formed on a substrate in order to improve circuit performance. One way to achieve this goal is to use self-aligned silicide.
de, for short, salicide) technology is known. This is a method in which a metal is deposited on silicon, and a compound of silicon and a metal (silicide) is selectively formed by heating only in a portion where the silicon is exposed. A conventional salicide forming method using titanium, which is widely used, will be described with reference to FIG. First, an isolation insulator 2, a gate insulating film 3, a gate electrode 4, an LDD region 5, a gate sidewall 6, and a source / drain diffusion layer 7 are formed on a silicon substrate 1. Next, titanium is deposited by sputtering or the like (FIG. 4A).
When the first heat treatment is performed at a relatively low temperature of about 0 ° C. for about 30 seconds, the silicon in the source / drain portion and the polysilicon in the gate react with titanium, and the titanium silicide layer 8 ′ is formed on the source / drain and in the gate. It is selectively formed on top (FIG. 4B). Next, titanium 11 'remaining without being silicide is selectively removed by wet etching (FIG. 4C). By the first heat treatment, the formed titanium silicide 8 ′ is a metastable and relatively high-resistance phase (C
This is referred to as the 49 phase, hereinafter referred to as the high resistance phase). next,
A second heat treatment at a relatively high temperature of about 900 ° C. is performed for about 10 seconds to cause a phase transition from the high-resistance phase titanium silicide 8 ′ to the low-resistance phase (referred to as C54 phase) titanium silicide 8 (FIG. 4D). ). If the temperature of the second heat treatment is too low, the phase transition to the low-resistance phase is insufficient, and if it is too high, silicide aggregates to cause disconnection. For this reason, the temperature is selected so as to minimize the final silicon layer resistance. The reason why the heat treatment is divided into two is that if the heat treatment is performed at a high temperature from the beginning, silicon diffuses through titanium, resulting in a short circuit between the gate and the source / drain.

[0003]

Further, in the salicide using titanium, the gate electrode 4 or the source electrode is not used.
When the width of the pattern of the drain 7 is reduced, the silicidation reaction hardly progresses, or the phase transition to the low resistance phase hardly progresses. In order to compensate for this, it is necessary to raise the heat treatment temperature. However, this causes aggregation of titanium silicide, and disconnection occurs when the pattern width is small. For the above reasons, when the pattern width is reduced, it is difficult to sufficiently reduce the layer resistance of the gate 4 and the source / drain 7 (resistance when current flows in the horizontal direction or the direction perpendicular to the paper in FIG. 4). There is.

Various measures have been proposed for this problem. For example, VLSI Technology in 1992
On page 66 of the proceedings of the symposium, a method is described in which silicon is made amorphous by ion implantation before titanium 11 is deposited. Amorphization has the effect of promoting the silicidation reaction and stably forming titanium silicide even in a narrow pattern. On the other hand, in the 1995 VLSI Technology Symposium Proceedings, p. 57, in addition to the above-mentioned amorphization, a method of increasing the temperature at the time of titanium deposition to 400 ° C. or more is described. This describes that titanium silicide of a low-resistance phase is formed very thinly at the interface immediately after the deposition, and the formation of titanium silicide in a narrow pattern is further facilitated.

However, when using silicide, not only the layer resistance but also the contact resistance between the silicide 8 and the source / drain diffusion layer 7 becomes a problem. That is, in the salicide using titanium, the impurities contained in the source / drain 7 diffuse during the heat treatment, and are absorbed in the silicide or form a compound with titanium. Therefore, at the contact surface between the titanium silicide 8 and the source / drain 7, there is a problem that the impurity concentration contained in the source / drain 7 decreases and the contact resistance between the titanium silicide 8 and the source / drain 7 increases. .

The layer resistance is a resistance when a diffusion layer or a gate layer is regarded as a wiring. By paying attention to the arrangement of patterns so as to shorten the length of the wiring, the disadvantage of a high layer resistance is eliminated. It is possible to avoid it considerably. However, it is difficult to avoid the problem of contact resistance between the silicide and the diffusion layer by disposing the pattern. For example, even if the area of the source / drain is increased in the horizontal direction of the paper in FIG. 4, the degree of integration of the entire circuit is reduced, and the current of the contact portion is almost concentrated on the end close to the gate electrode. The effect is small. Further, as the miniaturization of the semiconductor element progresses, the importance of the contact resistance is further increased as compared with the layer resistance. When various dimensions are reduced to 1 / k times, the layer resistance is length / (width ×
Height), it increases k times, but the contact resistance is 1 /
This is because it is proportional to (length × width) and increases by k ² times. Due to this property, in a fine FET having a gate width of less than 0.2 μm, the contact resistance is more important than the layer resistance.

In the conventional method of improving titanium salicide, only the layer resistance is considered, and no consideration is given to reducing the contact resistance. Gate width 0.2 μm
In the case of a fine FET having a resistance smaller than the contact resistance, it is necessary to lower the contact resistance in preference to the layer resistance. At the same time, the layer resistance must be kept low enough for practical use. The ultimate issue is how to achieve this.

An object of the present invention is to provide a method for reducing the contact resistance between a diffusion layer and a silicide layer while keeping the layer resistance of titanium silicide sufficiently low.

[0009]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a titanium silicide film, comprising: forming a diffusion layer and a gate electrode on a silicon substrate; And a second step of amorphizing a predetermined portion on the silicon substrate by ion implantation.
The method includes a third step of depositing titanium at a temperature of not lower than 650 ° C. and a fourth step of heating a silicon substrate on which the titanium has been deposited at a temperature of not lower than 600 ° C. and not higher than 800 ° C.

According to the present invention, titanium is deposited at a temperature of 400 ° C. or more and 650 ° C. or less, so that titanium silicide having low resistance is formed during the deposition of titanium. Therefore, a subsequent heat treatment temperature for converting titanium silicide to a low resistance layer can be set to a low temperature of 800 ° C. or less. Therefore, the problem of the conventional method described above, that is, at the contact surface between titanium silicide and the source / drain,
The problem that the concentration of impurities contained in the source / drain decreases and the contact resistance between the titanium silicide and the source / drain increases does not occur, and the contact resistance between the titanium silicide film and the diffusion layer is effectively reduced. be able to.

When the gate pattern width is less than 0.2 μm, not only the contact resistance but also the layer resistance can be reduced as compared with the conventional method, and the resistance can be further reduced.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a method of manufacturing a semiconductor device according to the present invention, first, a predetermined portion on a silicon substrate is made amorphous by ion implantation. The predetermined portion refers to a portion where titanium silicide is to be formed in a later step. The implantation energy of the ion implantation is typically about 50 keV, and is set to be sufficiently shallower than the depth of the source / drain. The substance to be implanted may be an atom or a molecule having a mass sufficient to make the substrate amorphous.
Examples include arsenic, phosphorus, silicon, germanium, and boron fluoride. Among them, arsenic, silicon, and boron fluoride are preferable.

After amorphization is performed by ion implantation, the surface of the silicon substrate is heated to 400 ° C. or more and 650 ° C. or less.
Preferably, titanium is deposited at a temperature of 450 ° C. or more and 550 ° C. or less. If the temperature is lower than 400 ° C., low-resistance titanium silicide is not formed during titanium deposition. If the temperature exceeds 650 ° C., a short circuit between the gate and the source / drain may occur.

After titanium is deposited, the semiconductor substrate is heated at a temperature of 600 ° C. or more and 800 ° C. or less, preferably 650 ° C. or more and 750 ° C. or less, to reduce the resistance of titanium silicide. 60
If the temperature is lower than 0 ° C., the reduction in resistance becomes insufficient. 800 ° C
If the ratio exceeds the above, silicide may aggregate and the layer resistance may increase.

The method of manufacturing a semiconductor device according to the present invention exhibits a more remarkable effect when the width of the titanium silicide film becomes narrower than the conventional method. Therefore, the width of the silicon pattern forming titanium silicide is preferably less than 0.2 μm, and more preferably less than 0.1 μm. When the pattern width is less than 0.2 μm, the conventional method causes agglomeration of silicide and increases the layer resistance, whereas the manufacturing method of the present invention does not cause such a problem. This is because a lower layer resistance can be realized.

[0016]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment according to the present invention. First, an element isolation insulator 2, a gate insulating film 3, a gate electrode 4, an LDD
A region 5, a gate side wall 6, and a source / drain diffusion layer 7 are formed. Subsequently, arsenic was added at 1 × 10 ¹⁴ cm ⁻² per unit area.
More than 1 × 10 ¹⁶ cm ⁻² or less is implanted to amorphize the surface of the source / drain region and the gate electrode (FIG. 1).
A).

At this time, the arsenic implantation energy is typically 50 keV, and is set to be sufficiently shallower than the depth of the source / drain. The substance to be injected at this time is
Not limited to arsenic, any atom or molecule having a mass sufficient to make the substrate amorphous, such as phosphorus, silicon, germanium, and boron fluoride, may be used.

Subsequently, with the substrate temperature kept at 400 ° C. or higher, titanium 1 is deposited by a method such as sputtering or CVD.
1 is deposited to a thickness of about 30 nm (FIG. 1B). During the deposition process, a slight reaction between titanium and silicon occurs at the contact surface between the titanium 11 and the gate 4 or between the titanium 11 and the source / drain 7 to form a very thin titanium silicide layer (this layer is thin). Therefore, it is not shown in FIG. 1B). When the titanium silicide formed at this time is analyzed, when the substrate temperature is lower than 400 ° C., only the high resistance phase is observed. On the other hand, if the substrate temperature is 400 ° C. or higher,
The low resistance phase is observed in addition to the high resistance phase, and the higher the temperature, the higher the ratio of the latter. However, if the deposition temperature is too high, the above-mentioned short circuit between the gate and the source / drain tends to occur. Since the deposition is performed for a relatively long time, it is desirable to lower the deposition temperature to 650 ° C. or lower in order to prevent a short circuit as compared with the first heat treatment in the conventional titanium salicide method. Further, by setting such a temperature, the production of the deposition apparatus is facilitated. The deposition of titanium is performed in a vacuum device, but the lower the temperature in the device, the easier it is to increase the degree of vacuum.

Next, a heat treatment for silicidation is performed in a non-oxidizing atmosphere such as nitrogen or argon at a temperature of 800 ° C. or less for 10 to 60 seconds, and the deposited titanium is converted into silicon constituting a source / drain or a gate. (FIG. 1C). Finally, titanium remaining without being silicided or titanium nitride remaining after being nitrided by nitrogen is selectively removed by etching. As an etching solution, a mixed solution of ammonia and hydrogen peroxide may be used.
Thus, titanium silicide is selectively formed only on the gate 4 and the source / drain 8 (FIG. 1D). The conventional second heat treatment at 800 ° C. or higher is omitted,
When additional heat treatment is performed, the temperature is set to 800 ° C. or lower.

The heat treatment temperature for silicidation is 800
When the temperature is lower than or equal to ° C., the contact resistance between the source / drain 7 and the gate 4 to which arsenic or boron is added and the titanium silicide 8 does not substantially depend on the heat treatment temperature. This is because, by lowering the temperature, the diffusion of impurities in silicon is suppressed, the amount of impurities (arsenic and boron) taken into the titanium silicide side is reduced, and the decrease in impurity concentration at the contact surface is suppressed. On the other hand, in the conventional manufacturing method, if the maximum heat treatment temperature is lowered to 800 ° C. or lower, the layer resistance of titanium silicide increases. This is because a high-resistance phase is preferentially formed during the silicidation reaction, and the once formed high-resistance phase is not converted to a low-resistance phase unless a temperature of 800 ° C. or more is applied. However, in the method according to the present invention, since the titanium is deposited at 400 ° C. or higher, titanium silicide in the low-resistance phase is slightly present before the heat treatment. Since this functions as a nucleus for crystal growth during the subsequent heat treatment, even if the heat treatment temperature is low, the crystal of the low resistance phase grows preferentially instead of the high resistance phase. That is, since the low-resistance phase is formed from the beginning, the layer resistance can be suppressed to a practically low level even if the heat treatment temperature is suppressed to 800 ° C. or lower. Note that the heat treatment temperature for silicidation is desirably 600 ° C. or higher in order to obtain a sufficient reaction rate.

By keeping the maximum heat treatment temperature low,
The method according to the invention has the effect of suppressing aggregation.
Agglomeration causes the thin wire to break, increasing its layer resistance and increasing its variability. From this, the present invention is more advantageous with respect to the layer resistance, especially when the pattern width is smaller.

FIG. 2 shows a second embodiment according to the present invention. The difference from the first embodiment is that the top of the gate electrode 4 is covered with the cap insulating film 9 and no titanium silicide is formed thereon. In the structure around the gate as shown in FIG. 2, a gate electrode material and a cap insulating film material are laminated, and then both are continuously etched,
Subsequently, it can be obtained by forming the gate side wall 6. Other steps are the same as in the first embodiment. This structure is used when the gate electrode 4 itself is originally made of a material having low resistance, such as a metal or a laminated film of silicon and a metal, and it is not necessary to form titanium silicide thereon.

FIG. 3 shows data showing the gate pattern width dependence of the layer resistance of silicide formed on the gate. In order to cause a phase transition from a high resistance phase to a low resistance phase,
In a conventional method of performing heat treatment at a high temperature of 800 ° C. or higher (840 ° C. in this example), a low resistance is realized when the gate width is wide. However, when the gate width is reduced, the resistance is rapidly increased because the silicide aggregates and breaks during the high-temperature heat treatment. On the other hand, according to the method of the present invention in which the maximum temperature of the heat treatment is suppressed to 800 ° C. or less (690 ° C. in this example), while the gate width is wide, the layer resistance is higher than the conventional method. This is because a part of the silicide is in a high resistance phase. However, as a result of performing the amorphization and titanium deposition at a high temperature, a low-resistance phase is also formed at the same time. For this reason, the resistivity of the high-resistance phase is four times or more that of the low-resistance phase, but the difference in resistance in FIG. 4 is at most about 1.7 times, and the layer resistance according to the present invention is within a practical range. It is suppressed. In a region where the gate width is small, the conventional method causes an increase in the layer resistance due to aggregation. On the other hand, according to the present invention, aggregation is less likely to occur because the heat treatment temperature is suppressed. Therefore, when the gate width is reduced to less than 0.2 μm, the present invention is equal to or rather advantageous with respect to the layer resistance.

On the other hand, with respect to the contact resistance between the source / drain diffusion layers and titanium silicide, it was confirmed that the resistance value was reduced to about 2/3 by the method according to the present invention. For example, arsenic is added to 3 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻² ,
The contact resistance with respect to the n-type diffusion layer formed by ion implantation at 0 keV is 3 × 10 ⁻⁷ Ωcm ² to 2 × 10 ⁻⁷ Ωcm ^2.
Decreased to. If the layer resistance is somewhat high, it is possible to prevent the effect by contriving the arrangement of the elements. But,
Since the contact resistance at the source / drain is inserted in series between the source and the drain where a large current needs to flow in the FET, the influence cannot be avoided by contriving the arrangement. When the gate width becomes smaller than 0.2 μm as the FET becomes finer, the contact resistance becomes a more important problem than the layer resistance. The present invention can reduce the contact resistance and prevent the performance of the fine FET circuit from deteriorating. Although the heat treatment temperature for silicidation in the above example was 690 ° C., an effect of reducing the contact resistance was obtained in the range of 800 ° C. or less. When the heat treatment temperature is increased in this range, the effect of reducing the contact resistance is reduced, but the layer resistance can be reduced particularly when the pattern width is wide. The specific value of the heat treatment temperature for silicidation may be a sufficiently low temperature to achieve a desired contact resistance.

In the above embodiment, the MIS type FE
Although the case of T has been described as an example, it is clear that the present method can be applied to a circuit including a bipolar transistor.

[0026]

As described above, according to the present invention, 400
Since titanium is deposited at a temperature of not lower than 650 ° C., low-resistance titanium silicide is formed during the deposition of titanium. Therefore, the subsequent heat treatment temperature for converting titanium silicide to a low resistance layer can be lowered, and the contact resistance between the titanium silicide film and the diffusion layer can be reduced.

By setting the gate pattern width to less than 0.2 μm, not only the contact resistance but also the layer resistance can be reduced as compared with the conventional method, and the resistance can be further reduced.

[Brief description of the drawings]

FIG. 1 is a schematic process sectional view illustrating an example of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic sectional view illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a diagram showing a polysilicon width dependency of a layer resistance.

FIG. 4 is a schematic sectional view showing an example of a method for manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation insulating film 3 Gate insulating film 4 Gate electrode 5 LDD diffusion layer 6 Gate side wall 7 Source / drain diffusion layer 8 Titanium silicide 9 Cap insulating film 10 Amorphous region 11 Titanium 11 'Titanium which did not become silicide

Claims (4)

[Claims] In a method of manufacturing a semiconductor device having a titanium silicide film, a first step of forming a diffusion layer and a gate electrode on a silicon substrate and a second step of amorphizing a predetermined portion on the silicon substrate by ion implantation. And 400 ° C. to 650 ° C. on the surface of the silicon substrate.
A method of manufacturing a semiconductor device, comprising: a third step of depositing titanium at the following temperature; and a fourth step of heating a silicon substrate on which the titanium is deposited at a temperature of 600 ° C. or more and 800 ° C. or less. . 2. The method according to claim 1, wherein, in the second step, a surface of the silicon pattern having a width of less than 0.2 μm formed on the silicon substrate is made amorphous by ion implantation.
13. The method for manufacturing a semiconductor device according to item 5. 3. The method according to claim 3, wherein in the third step, 450 ° C. or more and 550
3. The method for manufacturing a semiconductor device according to claim 1, wherein titanium is deposited at a temperature equal to or lower than C. 4. The method according to claim 1, wherein in the fourth step, the silicon substrate on which the titanium is deposited is heated at a temperature of 650 ° C. or more and 750 ° C. or less.