JPH09326487A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method capable of relieving the compression stress in a silicon thermal oxide film formed on the surface of a silicon substrate for obviating the defect, and of improving the electric breakdown characteristics as the whole laminated oxide film. SOLUTION: After depositing a CVD silicon oxide film 5 on a CVD silicon thermal oxide film 4 for burying a weak spot in a silicon thermal oxide film 4, the whole body is heat-treated to be densified at a temperature not exceeding 900 deg.C while leaving the tension stress inside the CVD silicon oxide film 5 or preferably at 850 deg.C. Through these procedures, the residual compression stress in the silicon thermal oxide film 4 is relieved by the tension stress of the CVD silicon oxide film 5 in addition to the weak spot buried in the silicon thermal oxide film 4 to reduce the defective density, thereby enabling the CVD silicon oxide film itself to be densified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which various elements are formed on a silicon semiconductor substrate and, for example, improves the characteristics of a silicon oxide film applied as a gate oxide film of a MOS (Metal Oxide Semiconductor) transistor. Therefore, the present invention relates to a semiconductor device manufacturing method and a semiconductor device suitable for the above.

[0002]

2. Description of the Related Art With the progress of high integration of semiconductor devices, in order to improve device performance, Metal Oxide Semiconducto
The gate oxide film thickness of an r (hereinafter abbreviated as MOS) transistor tends to be thinned. For example, 4 megabit DR
In AM (Dynamic Random Access Memory), the gate oxide film thickness was about 15 nm, but in 16-megabit DRAM, the film thickness is reduced to about 10 nm. This gate oxide film is conventionally formed by a method of thermally oxidizing the surface of a single crystal silicon substrate (hereinafter, the oxide film thus formed is referred to as a silicon thermal oxide film). During the thermal oxidation process of the silicon thermal oxide film, minute voids called weak spots are generated in the region of about 5 nm in the vicinity of the interface with the silicon substrate in the formed silicon thermal oxide film, and the gate oxide film thickness is increased. It is known that the weak spots are exposed and the electrical breakdown voltage characteristics of the gate oxide film are remarkably deteriorated when the thickness is simply reduced. Therefore, using a silicon thermal oxide film as the gate oxide film,
In order to continue high integration of the semiconductor device, it is necessary to remove the weak spot. As a specific method for removing this weak spot, for example, IEEE Ele
ctron Devices Letters, vol. 14, No. 2 (1993), pp. 7
As disclosed in 2-73, after forming a thin silicon thermal oxide film, a chemical vapor deposition silicon oxide film (hereinafter, appropriately referred to as a CVD method) is used (hereinafter,
A method has been proposed in which a CVD silicon oxide film) is deposited and a weak spot is buried to remove the weak spot.

[0003]

When a surface of a semiconductor substrate, for example, a single crystal silicon substrate is thermally oxidized to form a silicon thermal oxide film as described above, a large machine is formed in the newly formed silicon thermal oxide film. Stress (compressive stress) is generated. This is because when the substrate (Si) is oxidized and converted into a silicon thermal oxide film (SiO ₂ ), the volume expands about twice. When the mechanical stress increases in this way, crystal defects such as dislocations and stacking faults are likely to occur in the substrate, which deteriorates the reliability of the product. Also, regarding the oxidation reaction process, it has been clarified that the diffusion behavior of oxygen, which is an oxidizing species, the reaction rate at the oxidation interface, etc. are affected by the above stress and the shape of the silicon thermal oxide film changes. . Further, the generated stress concentrates near the end points (corner points) of the two-dimensional or three-dimensional lattice shape, so that it is necessary to pay particular attention to crystal defects and shape change in this stress concentration field.

The reason why weak spots are formed in the silicon thermal oxide film is that the crystal structure (bonding state of atoms) in the silicon thermal oxide film is strained in order to relieve the stress caused by the thermal oxidation. It is conceivable that vacancies are formed and voids are formed as a result. In fact, when a silicon thermal oxide film is grown in a state where stress is applied to the surface of the silicon substrate on which the gate oxide film is formed, the electrical breakdown voltage characteristics of the oxide film are as shown in FIG. The lower the residual stress of, the lower the defect density. Regarding the relationship between the residual stress in the silicon thermal oxide film and the defect density of the oxide film, the defect density decreases as the residual stress in the oxide film becomes lower, as shown in FIG. 3, for example. Therefore, in order to reduce the defect density represented by the weak spot, stress relaxation in the oxide film is indispensable.

For the silicon thermal oxide film as described above,
It is generally known that a CVD silicon oxide film has a tensile internal stress. Therefore, when a CVD silicon oxide film is deposited on the silicon thermal oxide film, the compressive stress of the silicon thermal oxide film and the tensile stress of the CVD silicon oxide film have opposite signs. The deposition on the silicon thermal oxide film not only fills the weak spots, but also relaxes the residual stress in the silicon thermal oxide film.

In general, the CVD silicon oxide film itself has a rough crystal structure as compared with a silicon thermal oxide film, and therefore does not necessarily have good electrical withstand voltage characteristics. Therefore, the CVD silicon oxide film is densified by annealing or additional oxidation after the film formation. Will be required. However, if such a thermal history is applied after the film is deposited, the tensile stress in the CVD silicon oxide film may disappear. For example, as shown in FIG. 4, C, which had a tensile stress of about 200 MPa immediately after deposition,
The VD silicon oxide film shows almost no decrease in tensile stress when heat-treated at a temperature of 700 ° C. or lower, but when heat-treated at a temperature of 700 ° C. or higher, the tensile stress begins to decrease and disappears at about 900 ° C. or higher. It is considered that this is due to the viscous flow of the CVD silicon oxide film itself.

Therefore, if annealing or additional oxidation is performed for densification after formation of the CVD silicon oxide film, CV
D The relaxation of the compressive stress of the silicon thermal oxide film due to the tensile stress of the silicon oxide film, that is, the stress relaxation effect of the entire laminated oxide film structure disappears, and the weak spots formed in the silicon thermal oxide film are apparently CVD silicon. It is not always possible to sufficiently improve the electric breakdown voltage characteristics of the oxide film by only burying it in the oxide film.

An object of the present invention is to alleviate the compressive stress in the silicon thermal oxide film formed on the surface of a silicon substrate to eliminate defects, and to improve the electrical breakdown voltage characteristics of the laminated oxide film as a whole. It is an object of the present invention to provide a method of manufacturing a semiconductor device and a semiconductor device capable of performing the same.

[0009]

In order to achieve the above object, according to the present invention, after an element isolation film having a predetermined pattern is formed on a surface of a silicon substrate, an element formation region where the element isolation film is not formed is formed. The surface of the silicon substrate is thermally oxidized to form a silicon thermal oxide film as an element insulating film, and then CV is formed on the silicon thermal oxide film by chemical vapor deposition.
In the method of manufacturing a semiconductor device, in which a D silicon oxide film is deposited and various elements are formed on the CVD silicon oxide film, in the CVD silicon oxide film after the CVD silicon oxide film is deposited and before the various elements are formed. There is provided a method of manufacturing a semiconductor device, characterized in that the CVD silicon oxide film is subjected to a densification heat treatment at a temperature at which the existing tensile residual stress remains.

In the above, first, an element isolation film for selectively insulating and isolating elements according to a predetermined pattern is formed on the silicon substrate surface, and the silicon substrate surface in the element formation region where the element isolation film is not formed is formed. Thermal oxidation is performed to form a silicon thermal oxide film as an element insulating film. This silicon thermal oxide film is used, for example, as a gate oxide film of a MOS transistor or an insulating film of a capacitance element. Then, a CVD silicon oxide film is deposited on the silicon thermal oxide film by chemical vapor deposition, thereby filling the weak spots generated near the interface with the silicon substrate in the silicon thermal oxide film, and at the same time, the silicon thermal oxide film is deposited. The compressive stress remaining in the oxide film is relaxed by the tensile stress of the CVD silicon oxide film, and the defect density is reduced.

However, as described above, the CVD silicon oxide film itself has a rough crystal structure and does not necessarily have good electrical withstand voltage characteristics as compared with the silicon thermal oxide film. Therefore, before forming various elements such as transistors, After film formation, densification heat treatment is performed. At this time, in the present invention, this densification heat treatment of the CVD silicon oxide film is performed at a temperature at which the tensile residual stress existing in the CVD silicon oxide film remains. As a result, the tensile stress in the CVD silicon oxide film does not disappear, and it is possible to leave a tensile stress at least enough to relax the compressive stress remaining in the silicon thermal oxide film. After the above, the introduction of impurities necessary for forming various elements such as transistors, the formation of electrodes and wiring,
A semiconductor device is manufactured by forming an insulating film and the like.

Therefore, a weak spot is buried in the silicon thermal oxide film by depositing the CVD silicon oxide film,
Also, it becomes possible to reduce the defect density due to the relaxation of the residual compressive stress due to the tensile stress of the CVD silicon oxide film, and to improve the electrical breakdown voltage characteristics by densifying the CVD silicon oxide film itself. In the transistor, the capacitor, and the like that form the circuit of the semiconductor device manufactured as described above, the electrical breakdown voltage characteristics can be prevented from being deteriorated, and the reliability of the product can be improved.

The densification heat treatment of the present invention is preferably an annealing treatment performed in an inert gas atmosphere, an additional oxidation treatment performed in an oxidizing gas atmosphere, or an additional nitriding treatment performed in a nitriding gas atmosphere.

Among the above, particularly when utilizing the additional nitriding treatment, a stable silicon nitride bond can be formed by introducing a large amount of nitrogen atoms into the silicon thermal oxide film, which traps electrons and holes. The decrease causes the interface state density to be reduced, the oxide film leakage current to be suppressed, and the dielectric breakdown charge to be increased. Therefore, it is possible to further improve the electrical breakdown voltage characteristics of the laminated oxide film as a whole.

Further, in such a densification heat treatment,
In order to prevent the tensile stress remaining in the CVD silicon oxide film from disappearing, it is preferable to perform the heat treatment at a temperature of 900 ° C. or lower, and it is preferable that the treatment time of the densification heat treatment is 30 minutes or longer. .

In order to achieve the above-mentioned object, according to the present invention, an element isolation film having a predetermined pattern is formed on the surface of the silicon substrate, and an element is formed on the surface of the silicon substrate in an element formation region where the element isolation film is not formed. A silicon thermal oxide film is formed as an insulating film for CVD, and a CVD silicon oxide film is deposited by chemical vapor deposition on the silicon thermal oxide film.
Provided is a semiconductor device in which various elements are formed on a silicon oxide film, wherein a part of tensile residual stress at the time of deposition exists in the CVD silicon oxide film. The mechanism by which a part of the tensile residual stress existing in the CVD silicon oxide film relaxes the compressive stress of the CVD silicon oxide film is as described above.

At this time, if the lattice spacing in the in-plane direction of the CVD silicon oxide film is wider than the lattice spacing of the silicon thermal oxide film as the device insulating film, the tensile force during deposition in the CVD silicon oxide film is obtained. There may be some of the residual stress.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram for explaining the manufacturing process of the semiconductor device of this embodiment,
It is a schematic cross-sectional structure diagram. Hereinafter, the method for manufacturing the semiconductor device according to the present embodiment and the structure thereof will be described with reference to FIG. First, as shown in FIG. 1A, an element isolation insulating film 2 is partially formed on a silicon substrate 1 by a selective oxidation method using a resist film or the like. This element isolation insulating film 2 is
It should be made of a silicon thermal oxide film, a CVD silicon oxide film, a silicon nitride film, or a laminated film of these, and the shape does not necessarily have to have a curvature as shown in FIG. Etc. may be used. Next, as shown in FIG. 1B, the surface of the silicon substrate 1 is thermally oxidized to form a silicon thermal oxide film 4 as a gate oxide film of a MOS transistor or an insulating film for forming a capacitance element. As described above, in the silicon thermal oxide film 4, strain is generated in the crystal structure in order to relax the stress generated due to the thermal oxidation, and as a result, voids (weak spots) are formed as defects. It

In FIG. 2, the horizontal axis represents the residual stress of the silicon substrate 1 before the silicon thermal oxide film 4 is formed, and the vertical axis represents the defect density of the silicon thermal oxide film 4 formed. It is a figure which shows the defect density (relative value) at the time of growing the silicon thermal oxide film 4 in the state which applied the stress to the surface. As is clear from FIG. 2, the lower the residual stress in the silicon substrate 1, the lower the defect density.

Next, as shown in FIG. 1C, a CVD silicon oxide film 5 is deposited on the silicon thermal oxide film 4 and the element isolation insulating film 2. At this time, if there are holes such as weak spots in the silicon thermal oxide film 4, the holes are filled with the CVD silicon oxide film 5 as described above, and the CVD silicon oxide film 5 has them. The residual stress in the silicon thermal oxide film 4 is relaxed by the tensile stress. FIG. 3 shows the residual stress inside the silicon thermal oxide film 4 when the CVD silicon oxide film 5 is deposited on the silicon thermal oxide film 4 on the horizontal axis and the defect density of the silicon thermal oxide film 4 on the vertical axis. 6 is a diagram showing the relationship between the residual stress inside the thermal oxide film 4 and the defect density of the silicon thermal oxide film 4. FIG. As is clear from FIG. 3, as the residual stress in the silicon thermal oxide film 4 becomes lower, the defect density decreases. Therefore, in order to reduce the defect density represented by a weak spot, stress relaxation in the oxide film is indispensable. It can be seen that it is important to relax the compressive stress of the silicon thermal oxide film 4 due to the tensile stress of the CVD silicon oxide film 5.

Since the CVD silicon oxide film 5 itself has a rough crystal structure and does not necessarily have good electrical withstand voltage characteristics as compared with the silicon thermal oxide film 4, the densification heat treatment is performed after the deposition of the CVD silicon oxide film 5. . The heat treatment at this time is
90% in an inert gas atmosphere of argon, nitrogen, hydrogen, etc.
The annealing treatment is performed at a temperature of 0 ° C. or lower, preferably 850 ° C. or lower. The heat treatment time may be about 30 minutes or longer. The heat treatment atmosphere may be a mixed gas of the above-mentioned inert gas or several% (specifically, 5%).
It may be one to which oxygen or nitrogen oxide of about the following) is added.

FIG. 4 shows an example of measurement of heat treatment temperature dependence of residual stress (tensile stress) in the CVD silicon oxide film 5 (heat treatment time is 30 minutes). As is clear from FIG. 4, CVD
The tensile stress of the silicon oxide film 5 is hardly changed by the heat treatment at 700 ° C. or less, and the tensile stress of 200 MPa or more immediately after the deposition can be maintained, but when the heat treatment is performed at the temperature of 700 ° C. or more, the tensile stress starts to decrease. It becomes very small at a temperature higher than 900 ° C and disappears at a temperature of 1000 ° C or higher. It is considered that this is due to the viscous flow of the CVD silicon oxide film 5 itself. However, there is almost no change in the characteristics of FIG. 4 even if the heat treatment is performed for 30 minutes or more. Therefore, if the densification heat treatment after the formation of the CVD silicon oxide film 5 is performed at a temperature higher than 900 ° C., the compressive stress of the silicon thermal oxide film 4 is relaxed by the tensile stress of the CVD silicon oxide film 5, that is, the laminated oxide film. The stress relaxation effect of the entire structure disappears, and it is not always possible to sufficiently improve the electrical breakdown voltage characteristics of the oxide film.

However, in the present embodiment, since the temperature of the densification heat treatment is set to 900 ° C. or lower, preferably 850 ° C. or lower, tensile stress remains inside the CVD silicon oxide film 5 as shown in FIG. The compressive stress of the silicon thermal oxide film 4 can be relaxed by the tensile stress of the oxide film 5, and the stress of the laminated oxide film structure as a whole can be relaxed to reduce the defect density. At this time, if the lattice spacing in the in-plane direction of the CVD silicon oxide film 5 is wider than the lattice spacing of the silicon thermal oxide film 4 when the atomic spacing is measured by, for example, the electron diffraction method, this is true. Therefore, some of the tensile residual stress at the time of deposition may exist in the CVD silicon oxide film 5.

After the densification heat treatment, the gate electrode 6 is formed as shown in FIG. The gate electrode 6 is formed by depositing and etching a thin film, and is made of a polycrystalline silicon thin film, a metal thin film such as tungsten, a silicide thin film, or a laminated structure of these thin films. Next, impurities necessary for forming an element such as a transistor are introduced to form an impurity introduction region 3 as shown in FIG. Next, as shown in FIG. 1F, the interlayer insulating film 7 and the electric wiring 8 are formed.

Furthermore, if necessary, a second
Wiring and an insulating film are formed in the layers after that, and the structure of an element such as a MOS transistor is completed. Note that the procedure of element formation after the densification heat treatment is not limited to this procedure, the impurity introduction region is not limited to the region shown in this embodiment, and the number of wiring layers is not limited to that of this embodiment. As such, it is not limited to a single layer. When the element is a MOS type transistor, the MOS type transistor is mainly a DRAM (Dynamic Random Access Memory), S
It is used in RAM (Static Random Access Memory), a memory circuit such as a flash memory, or an arithmetic circuit.

According to this embodiment as described above, after the CVD silicon oxide film 5 is deposited on the silicon thermal oxide film 4, the temperature at which the tensile stress remains inside the CVD silicon oxide film 5, for example, 900 ° C. or lower, Since the densification heat treatment is preferably performed at 850 ° C. or less, the tensile stress in the CVD silicon oxide film 5 does not disappear. Therefore, not only the weak spots in the silicon thermal oxide film 4 are buried by the deposition of the CVD silicon oxide film 5, but also the compressive stress remaining in the silicon thermal oxide film 4 is relaxed by the tensile stress of the CVD silicon oxide film 5, As a result, the defect density can be reduced and the CVD silicon oxide film 5 itself can be densified, so that the electrical breakdown voltage characteristics of the entire laminated oxide film structure can be improved. Thereby, the reliability of the product can be improved.

A second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a diagram for explaining the manufacturing process of the semiconductor device of the present embodiment, and is a schematic cross-sectional structure diagram. Hereinafter, the manufacturing method and the structure of the semiconductor device of the present embodiment will be described with reference to FIG. . First, FIG.
As shown in (a), the element isolation insulating film 12 is partially formed on the silicon substrate 11 by a selective oxidation method using a resist film or the like. The element isolation insulating film 12 is made of a silicon thermal oxide film, a CVD silicon oxide film, a silicon nitride film, or a laminated film of these, and the shape thereof does not necessarily have to have a curvature as shown in FIG. Alternatively, it may have a groove shape or a rectangular shape. next,
As shown in FIG. 5B, the surface of the silicon substrate 11 is thermally oxidized to form a first silicon thermal oxide film 14 as a gate oxide film of a MOS transistor or an insulating film for forming a capacitance element. Next, as shown in FIG. 5C, the first silicon thermal oxide film 14 and the element isolation insulating film 12 are formed.
A CVD silicon oxide film 15 is deposited on top. At this time, holes such as weak spots existing in the first silicon thermal oxide film 14 are filled with the CVD silicon oxide film 15, and the residual stress in the silicon thermal oxide film 4 due to the tensile stress of the CVD silicon oxide film 15. Stress is relieved.
Also in this case, the residual stress relaxation in the first silicon thermal oxide film 14 contributes to the reduction of the defect density represented by the weak spot. The steps up to this point are almost the same as in the first embodiment.

Also in this embodiment, the densification heat treatment of the CVD silicon oxide film 15 is performed. In this case, the heat treatment is performed in an oxidizing atmosphere such as dry oxygen, a mixed gas of oxygen and hydrogen, an oxidizing gas such as steam, or the like. The additional oxidation treatment is performed at a temperature of 900 ° C. or lower, preferably 850 ° C. or lower. The heat treatment time may be about 30 minutes or longer. Further, the heat treatment atmosphere may be a mixed gas of the above-mentioned oxidizing gas or a mixed gas of nitrogen oxide. By this additional oxidation treatment, the CVD silicon oxide film 15 is densified and a new silicon substrate 1 is formed as shown in FIG.
A second silicon thermal oxide film 19 is formed at the interface between 1 and the first silicon thermal oxide film 14.

As described above, the temperature of the additional oxidation treatment as the densification heat treatment is set to 900 ° C. or lower, preferably 850 ° C. or lower. Therefore, as in the case of the first embodiment, the inside of the CVD silicon oxide film 15 is pulled. Since the stress remains, the compressive stress of the first silicon thermal oxide film 14 can be relaxed by the tensile stress of the CVD silicon oxide film 15, and the stress of the entire laminated oxide film structure can be relaxed to reduce the defect density. Is possible.

After the densification heat treatment, as shown in FIG. 5 (e), a thin film is deposited and etched to form a polycrystalline silicon thin film, a metal thin film of tungsten or the like, a silicide thin film, or a laminated structure of these thin films. A film is formed to serve as the gate electrode 16. Next, impurities necessary for forming an element such as a transistor are introduced, and
The impurity introduction region 13 as shown in FIG. 5F is formed, and then the interlayer insulating film 17 and the electric wiring 18 are formed as shown in FIG.

Furthermore, if necessary, a second
Wiring and an insulating film are formed in the layers after that, and the structure of an element such as a MOS transistor is completed. Note that, as in the first embodiment, the procedure of forming the element after the densification heat treatment is not limited to this procedure, and the impurity introduction region is not limited to the region shown in this embodiment. The number of wiring layers is not limited to one as in this embodiment. When the element is a MOS transistor, the MOS transistor is mainly a DRAM (Dynamic Ra
ndom Access Memory), SRAM (Static Random Acce
ss Memory), a memory circuit such as a flash memory, or an arithmetic circuit.

According to the present embodiment as described above, the temperature at which tensile stress remains inside the CVD silicon oxide film 15 after depositing the CVD silicon oxide film 15 on the first silicon thermal oxide film 14, for example, 900 ° C. Below, preferably 8
Since the additional oxidation treatment as the densification heat treatment, that is, the formation of the second silicon thermal oxide film 19 is performed at 50 ° C. or less, the tensile stress in the CVD silicon oxide film 15 does not disappear as in the first embodiment. Therefore, not only the weak spots in the first silicon thermal oxide film 14 are buried by the deposition of the CVD silicon oxide film 15, but also the compressive stress remaining in the first silicon thermal oxide film 14 causes the tensile stress of the CVD silicon oxide film 15. And the CVD silicon oxide film 15 itself is densified, so that the electrical breakdown voltage characteristics of the laminated oxide film structure as a whole can be improved. Thereby, the reliability of the product can be improved.

A third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram for explaining the manufacturing process of the semiconductor device of the present embodiment, and is a schematic cross-sectional structure diagram. Hereinafter, the manufacturing method of the semiconductor device of the present embodiment and its structure will be described with reference to FIG. . First, FIG.
As shown in (a), the element isolation insulating film 22 is partially formed on the silicon substrate 21 by a selective oxidation method using a resist film or the like. The element isolation insulating film 22 is made of a silicon thermal oxide film, a CVD silicon oxide film, a silicon nitride film, or a laminated film of these, and the shape thereof does not necessarily have to have a curvature as shown in FIG. Alternatively, it may have a groove shape or a rectangular shape. next,
As shown in FIG. 6B, the silicon thermal oxide film 24 is formed by thermally oxidizing the surface of the silicon substrate 21 as a gate oxide film of a MOS transistor or an insulating film for forming a capacitance element. Next, as shown in FIG. 6C, CVD is performed on the silicon thermal oxide film 24 and the element isolation insulating film 22.
A silicon oxide film 25 is deposited. At this time, holes such as weak spots existing in the silicon thermal oxide film 24 are filled with the CVD silicon oxide film 25, and C
The residual stress in the silicon thermal oxide film 24 is relaxed by the tensile stress of the VD silicon oxide film 25. Again,
Relaxation of residual stress in the silicon thermal oxide film 24 contributes to reduction of defect density represented by a weak spot. The steps up to this point are almost the same as those in the first and second embodiments.

Also in this embodiment, the densification heat treatment of the CVD silicon oxide film 25 is performed, and the heat treatment in this case is nitrogen, a mixed gas of nitrogen and an inert gas, nitrogen oxide,
The additional nitriding treatment is performed in a nitriding atmosphere at a temperature of 900 ° C. or lower, preferably 850 ° C. or lower. The heat treatment time may be about 30 minutes or longer. Further, the heat treatment atmosphere may be a mixed gas of the above nitriding gas. By this nitriding treatment, the CVD silicon oxide film 25 is densified, and a silicon nitride film 30 is newly formed at the interface between the silicon substrate 21 and the silicon thermal oxide film 24 as shown in FIG. 6D.

Since the temperature of the additional nitriding treatment as the densification heat treatment is set to 900 ° C. or lower, preferably 850 ° C. or lower as described above, the CV is the same as in the first and second embodiments.
The tensile stress remains inside the D silicon oxide film 25, and C
The compressive stress of the first silicon thermal oxide film 24 can be relaxed by the tensile stress of the VD silicon oxide film 25, and the stress of the entire laminated oxide film structure can be relaxed to reduce the defect density.

Further, in this embodiment, since the CVD silicon oxide film 25 is densified by the additional nitriding process, a stable silicon nitride bond can be formed by introducing a large amount of nitrogen atoms into the silicon thermal oxide film 24. It reduces the capture of electrons and holes. As a result, the effect of reducing the interface state density, suppressing the oxide film leak current, and increasing the dielectric breakdown charge is obtained, and the electrical breakdown voltage characteristics of the laminated oxide film as a whole are further improved.

After the densification heat treatment, as shown in FIG. 6 (e), a thin film is deposited and etched to form a polycrystalline silicon thin film, a metal thin film such as tungsten, a silicide thin film, or a laminated structure of these thin films. A film is formed to serve as the gate electrode 26. Next, impurities necessary for forming elements such as transistors are introduced, and
An impurity introduction region 23 as shown in FIG. 6F is formed, and then an interlayer insulating film 27 and an electric wiring 28 are formed as shown in FIG.

Furthermore, if necessary, a second
Wiring and an insulating film are formed in the layers after that, and the structure of an element such as a MOS transistor is completed. Similar to the first and second embodiments, the procedure for forming the element after the densification heat treatment is not limited to this procedure, and the impurity introduction region is also limited to the region shown in this embodiment. However, the number of wiring layers is not limited to one as in the present embodiment. When the element is a MOS type transistor, the MOS type transistor is mainly a DRAM (Dy
namic Random Access Memory), SRAM (Static Ran)
dom access memory), a memory circuit such as a flash memory, or an arithmetic circuit.

According to the present embodiment as described above, after the CVD silicon oxide film 25 is deposited on the first silicon thermal oxide film 24, the temperature at which the tensile stress remains inside the CVD silicon oxide film 25, for example, 900 ° C. Below, preferably 8
Since the additional oxidation treatment as the densification heat treatment, that is, the formation of the silicon nitride layer 30 is performed at 50 ° C. or less, the tensile stress in the CVD silicon oxide film 25 does not disappear as in the first and second embodiments. Therefore, not only the weak spots in the first silicon thermal oxide film 24 are buried by the deposition of the CVD silicon oxide film 25, but also the first silicon thermal oxide film 24 is formed.
The compressive stress remaining inside is relaxed by the tensile stress of the CVD silicon oxide film 25, whereby the defect density can be reduced, and the CVD silicon oxide film 25 itself is also densified. It is possible to improve the electrical breakdown voltage characteristics of the. Thereby, the reliability of the product can be improved.

Further, according to the present embodiment, since the densification heat treatment of the CVD silicon oxide film 25 is the additional nitriding treatment, electrons and holes are trapped by the stable silicon nitride bond formed in the silicon thermal oxide film 24. The effect of reducing the interface state density, suppressing the oxide film leak current, and increasing the dielectric breakdown charge can be obtained. Therefore, the electrical breakdown voltage characteristics of the laminated oxide film as a whole can be further improved.

[0041]

According to the present invention, since the CVD silicon oxide film is deposited on the silicon thermal oxide film, the densification heat treatment is performed at a temperature at which the tensile stress remains inside the CVD silicon oxide film. The defect density is reduced by burying the weak spots in the inside and relaxing the compressive stress in the silicon thermal oxide film due to the tensile stress of the CVD silicon oxide film, and further, the CVD silicon oxide film itself is densified, and the laminated oxide film structure as a whole is formed. It is possible to improve the electrical breakdown voltage characteristics of the. Thereby, the reliability of the product can be improved.

Further, since the densification heat treatment of the CVD silicon oxide film is an additional nitriding process, the capture of electrons and holes can be reduced by the stable silicon nitride bond, the interface state density is reduced, and the oxide film leaks. The effects of suppressing the current and increasing the dielectric breakdown charge can be obtained, and thereby the electrical breakdown voltage characteristics can be further improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional structure diagram illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

[FIG. 2] Defect density (relative value) when a silicon thermal oxide film is grown with stress applied to the surface of a silicon substrate.
FIG.

FIG. 3 is a diagram showing the relationship between the residual stress inside the silicon thermal oxide film and the defect density of the silicon thermal oxide film.

FIG. 4 is a diagram showing a measurement example of heat treatment temperature dependence of residual stress (tensile stress) in a CVD silicon oxide film.

FIG. 5 is a view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention, which is a schematic cross-sectional structure diagram.

FIG. 6 is a diagram illustrating a manufacturing process of the semiconductor device according to the third embodiment of the present invention, which is a schematic cross-sectional structure diagram;

[Explanation of symbols]

 1 Silicon Substrate 2 Element Isolation Insulation Film 3 Impurity Introduction Region 4 Silicon Thermal Oxide Film 5 CVD Silicon Oxide Film 6 Gate Electrode 7 Interlayer Insulation Film 8 Electrical Wiring 11 Silicon Substrate 12 Element Isolation Insulation Film 13 Impurity Introduction Region 14 First Silicon Thermal Oxidation Film 15 CVD silicon oxide film 16 Gate electrode 17 Interlayer insulating film 18 Electrical wiring 19 Second silicon thermal oxide film 21 Silicon substrate 22 Element isolation insulating film 23 Impurity introduction region 24 Silicon thermal oxide film 25 CVD silicon oxide film 26 Gate electrode 27 Interlayer Insulation film 28 Electric wiring 30 Silicon nitride film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takayuki Kanda 4, 6 Kanda Surugadai, Chiyoda-ku, Tokyo Inside Hitachi Semiconductor Business Division (72) Inventor Shuji Ikeda 4, 6 Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi Semiconductor Division

Claims (8)

[Claims] 1. A silicon thermal oxidation as an insulating film for a device by forming a device isolation film having a predetermined pattern on the surface of a silicon substrate and then thermally oxidizing the surface of the silicon substrate in a device forming region where the device isolation film is not formed. A method of manufacturing a semiconductor device, comprising forming a film, then depositing a CVD silicon oxide film on the silicon thermal oxide film by chemical vapor deposition, and forming various elements on the CVD silicon oxide film. Of the CVD silicon oxide film at a temperature that maintains a state in which the residual tensile stress existing in the CVD silicon oxide film remains after the deposition of the above and before the formation of the various elements. Device manufacturing method. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the densification heat treatment is an annealing process performed in an inert gas atmosphere. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the densification heat treatment is an additional oxidation process performed in an oxidizing gas atmosphere. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the densification heat treatment is an additional nitriding process performed in a nitriding gas atmosphere. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the densification heat treatment is performed at a temperature of 900 ° C. or lower. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the densification heat treatment is performed for 30 minutes or more. 7. An element isolation film having a predetermined pattern is formed on the surface of a silicon substrate, and a silicon thermal oxide film as an element insulating film is formed on the surface of the silicon substrate in an element formation region where the element isolation film is not formed. In a semiconductor device in which a CVD silicon oxide film is deposited on the silicon thermal oxide film by chemical vapor deposition and various elements are formed on the CVD silicon oxide film, a tensile residue at the time of deposition is deposited in the CVD silicon oxide film. A semiconductor device characterized in that a part of stress is present. 8. The semiconductor device according to claim 7, wherein the lattice spacing of the CVD silicon oxide film in the in-plane direction is wider than the lattice spacing of the silicon thermal oxide film as the element insulating film. Semiconductor device.