JP2005079215A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which has a process wherein temperature can be decreased and can perform reduction of a natural oxide film. <P>SOLUTION: The method for manufacturing a semiconductor device is provided with (a) a step for preparing a substrate which has at least a silicon surface layer, (b) a step for forming the natural oxide film whose thickness is 0.1 - 0.5 nm on the surface of the silicon surface layer, (c) a step wherein the reduction of the natural oxide film whose thickness is 0.1 - 0.5 nm is performed by using hydrogen annealing treatment, and (d) a step for forming a gate insulating film on a surface of the silicon surface layer, following the above process (c). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of removing a natural oxide film. The “natural oxide film” is a concept indicating a low density and incomplete oxide film including a chemical oxide film.

  The miniaturization of semiconductor integrated circuit devices has been further advanced. When the gate length is 90 nm or less, the thickness of the gate insulating film is required to be 1.5 nm or less. A low-density natural oxide film is formed on the silicon substrate by oxidation in the atmosphere, chemical agent treatment, or oxidation by pure water cleaning. The natural oxide film has incomplete crystallinity, low density, and low properties as an insulating layer, compared to a thermal oxide film having excellent crystallinity.

  When the gate insulating film is formed while leaving the natural oxide film, a gate insulating film having a large leakage current is formed. Although a gate insulating film having a large leakage current is useful for some purposes, it is unsuitable for manufacturing a semiconductor integrated circuit with low power consumption. The thickness of the natural oxide film varies depending on its history. When forming the gate insulating film, the film thickness of the natural oxide film is changed by the immediately preceding chemical treatment. When forming an extremely thin gate insulating film, the control of the natural oxide film is important for the thickness control and characteristic control of the gate insulating film.

  The saturation current of the MOS transistor also depends on the state of the channel region surface and microroughness. If the microroughness is large, carrier transport is hindered and the saturation drain current is reduced.

  Various methods for forming a gate insulating film having excellent characteristics have been reported.

  Japanese Patent No. 3296268 (Japanese Patent Laid-Open No. 11-135508) discloses a heat treatment in a hydrogen atmosphere in which heavy metals are diffused into the substrate. The heat treatment in a hydrogen atmosphere at 1050 ° C. or higher reduces and removes the natural oxide film on the substrate surface to expose the substrate surface, thereby generating microroughness. Therefore, the heat treatment is performed in a hydrogen atmosphere at 800 ° C. to 1050 ° C. Propose to diffuse inside. Thereafter, a gate oxide film is formed in an oxidizing atmosphere.

  In Japanese Patent Laid-Open No. 2002-184774, a silicon wafer having a natural oxide film is heat-treated in a hydrogen atmosphere to improve the quality, and a gate insulating film is formed by additionally forming an oxide film if necessary. Propose that.

  Japanese Patent Application Laid-Open No. 2000-91342 discloses a method in which a natural oxide film is removed with an aqueous HF solution, and then the wafer from which the natural oxide film has been removed is heat-treated at 950 ° C. to 1150 ° C., which is lower than before, in an atmosphere containing hydrogen. We propose to reduce the microroughness of the surface and improve the characteristics.

  An SOI (silicon on insulator) wafer is known as a wafer for providing a high-performance semiconductor device. The use of a silicon (SOI) layer disposed on an insulating layer provides advantages not available with bulk silicon substrates.

  Partial depletion (PD) in which a shallow source / drain extension and deep high-concentration source / drain regions on both sides thereof are formed in the silicon layer on the insulating film, and the bottom surface of the high-concentration source / drain region reaches or approaches the insulating layer. ) Type MOS transistor can reduce the parasitic capacitance of the source / drain and promote high-speed operation.

  The silicon layer on the insulating film is thinned to form source / drain extensions on the thin silicon layer on the insulating film, and the outer insulating layer is removed as necessary to form a low resistance source / drain region. A depletion (FD) type MOS transistor facilitates prevention of narrow channel punch-through, and facilitates miniaturization of the MOS transistor and enhancement of functionality.

  Japanese Patent Laid-Open No. 10-041241 points out that the film quality is not improved sufficiently if heat treatment in a hydrogen atmosphere of a SIMOX type SOI wafer is performed at around 1000 ° C., and the characteristics of the buried oxide film deteriorate when it is performed at a high temperature. Proposed to perform heat treatment at high temperature in an active gas atmosphere and heat treatment in hydrogen atmosphere at a temperature higher than the temperature causing the reduction reaction of interstitial oxygen or lower than the temperature causing the reduction reaction of the buried oxide film, or hydrogen plasma treatment To do.

Japanese Patent Laid-Open No. 2-56952 proposes to use a single crystal CaF ₂ film epitaxially grown on a Si substrate as a buried insulating film of an SOI wafer. A Si layer is further epitaxially grown on the single crystal CaF ₂ film having excellent surface morphology and withstand voltage.

JP-A-6-97401 uses a fluoride layer such as a CaF ₂ film or a Ca _x Sr _1-x F ₂ film as a buried insulating film of an SOI wafer, and a GaAs layer is epitaxially grown on the fluoride layer. Then, a method for forming a light emitting diode or the like is proposed.

  A strained Si layer obtained by applying a tensile stress to the single crystal Si layer greatly improves carrier mobility. When the SOI wafer and the strained Si layer are combined, the characteristics of the semiconductor element can be further improved due to the advantages of both. (For example, the following non-patent documents 1 and 2).

Japanese Patent No. 3296268 JP 2002-184774 A JP 2000-91342 A Japanese Patent Laid-Open No. 10-041241 JP-A-2-56952 JP-A-6-97401 T. Mizuno et al., 2002 Symposium on VLSI Technologies T. A. Langdo et al., 2002 IEEE International SOI Conference

  An object of the present invention is to provide a method of manufacturing a semiconductor device having a process capable of reducing the temperature so that a natural oxide film can be reduced and removed.

  According to one aspect of the present invention, (a) preparing a substrate having at least a silicon surface layer, and (b) forming a natural oxide film having a thickness of 0.1 nm to 0.5 nm on the surface of the silicon layer. A step of (c) reducing and removing the natural oxide film having a thickness of 0.1 nm to 0.5 nm by hydrogen annealing, and (d) following the step (c), the surface of the silicon surface layer And a step of forming a gate insulating film on the semiconductor device.

  By limiting the thickness of the natural oxide film, the natural oxide film can be reduced and removed even by hydrogen annealing at a low temperature.

Embodiments of the present invention will be described below with reference to the drawings. One of the inventors, Hori, previously reduced and removed the natural oxide film by heating the semiconductor substrate in a reducing atmosphere such as hydrogen before forming the gate insulating film. Has proposed a method for forming the image (Japanese Patent Application No. 2002-249205). Suitable conditions for reducing and removing the natural oxide film were an H ₂ atmosphere pressure of 100 torr or less and a heating temperature of 900 ° C. to 1050 ° C. This time, using an SOI substrate, the conditions for reducing and removing the natural oxide film and improving the microroughness of the surface were obtained.

  1A to 1F schematically show a sample preparation procedure.

  As shown in FIG. 1A, a plurality of silicon oxide layers 25 having a thickness of about 200 nm and a single crystal silicon (SOI) layer 20 having a plurality of thicknesses thereon are formed on a silicon substrate 26 as a support substrate. Kinds of SOI substrates were prepared. The thickness of the SOI layer 20 was 30 nm, 50 nm, and 86 nm.

  A buffer oxide film 51 was formed on the surface of the SOI layer 20 by thermal oxidation or the like, and a silicon nitride layer 52 functioning as a stopper during chemical mechanical polishing (CMP) was formed thereon. When the buffer oxide film 51 is formed by thermal oxidation, the thickness of the SOI layer 20 decreases.

  As shown in FIG. 1B, an element isolation trench 53 that etches through the silicon nitride layer 52, the silicon oxide layer 51, and the SOI layer 20 and partially enters the buried silicon oxide layer 25 is etched using a resist mask. Thereafter, the resist mask is removed. A silicon oxide layer 54 is deposited by CVD or the like on the substrate on which the element isolation trench 53 is formed, and the element isolation trench 53 is embedded.

  As shown in FIG. 1C, the silicon oxide layer 54 on the silicon nitride layer 52 is polished and removed by using chemical mechanical polishing (CMP). In CMP, the silicon nitride layer 52 functions as a stopper. The silicon oxide layer 54 remains only in the element isolation trench 53. In this way, shallow trench isolation (STI) 54 is formed.

  As shown in FIG. 1D, the silicon nitride layer 52 used as the CMP stopper is removed by hot phosphoric acid or the like, and the buffer silicon oxide layer 51 is removed by dilute hydrofluoric acid or the like. The shallow trench isolation (STI) 54 is also slightly etched.

  As shown in FIG. 1E, a sacrificial silicon oxide film 20x is formed on the surface of the SOI layer 20 by thermal oxidation or the like, desired ion implantation is performed, and an impurity concentration distribution suitable for forming a MOS transistor in the SOI layer 20 is obtained. Form. Thereafter, the sacrificial silicon oxide layer 20x is removed. The thickness of the SOI layer 20 decreases due to sacrificial oxidation or the like.

  As shown in FIG. 1F, the surface of the SOI layer 20 is thermally oxidized to form a silicon oxide gate insulating film 55. A polycrystalline silicon layer 56 is deposited on the gate insulating film 55. The polycrystalline silicon layer 56 and the gate insulating film 55 are etched using the resist pattern as a mask to form an insulated gate electrode. The thickness of the SOI layer 20 decreases due to gate oxidation or the like.

  When the thin gate insulating film is formed, if the natural oxide film on the surface of the SOI layer 20 is left, the gate insulating film including the natural oxide film is formed, and the quality of the gate insulating film is deteriorated. In order to form a gate insulating film having excellent insulating characteristics, it is desirable to remove the natural oxide film on the surface of the SOI layer.

In the step shown in FIG. 1F, before forming the gate insulating film 55, an attempt was made to remove the natural oxide film present on the surface of the SOI layer 20 by annealing in a hydrogen atmosphere. However, the aggregation of the SOI layer occurred depending on the thickness of the SOI layer 20 and the annealing temperature in the H ₂ atmosphere.

FIG. 2 shows the state of the substrate surface when an SOI wafer using an SOI layer having a thickness of 30 nm, 50 nm, and 86 nm is annealed at 880 ° C., 930 ° C., 980 ° C., 985 ° C., and 1000 ° C. in an H ₂ atmosphere. Is a photograph showing the state of the substrate surface of Comparative Example NON that was not annealed. The H ₂ atmosphere pressure was 20 torr and the treatment time was 10 sec. An SOI layer defined by STI is shown.

In the sample of NON that was not annealed in the H ₂ atmosphere, separation of the SOI layer from the STI did not occur. It is considered that the SOI layer does not aggregate.

In a sample having an SOI layer having a thickness of 30 nm, it is considered that the SOI layer does not aggregate at an annealing temperature in an H ₂ atmosphere of 880 ° C. When the annealing temperature in the H ₂ atmosphere is 930 ° C., aggregation occurs in the SOI layer, and a part away from the STI layer is generated. When the annealing temperature in the H ₂ atmosphere is 980 ° C., the SOI layer is completely separated from the STI layer and aggregated in an elliptical shape. When the annealing temperature in the H ₂ atmosphere is 1000 ° C., the SOI layer shrinks in an island shape.

That is, if annealing is performed in a H ₂ atmosphere at a temperature of 930 ° C. or higher for a 30 nm SOI layer, aggregation occurs in the SOI layer. Aggregation of the SOI layer is lightly extent that occurs in an _{H 2} atmosphere in the annealing of 930 ° C., from 880 ° C. and 930 ° C. in an atmosphere of _{H 2} in the annealing results, 905 ° C. or less, more preferably annealed in _{H 2} atmosphere at 900 ° C. or less If done, the agglomeration of the SOI layer will hardly occur and, if so, will be negligible or acceptable.

In the SOI layer having a thickness of 50 nm, the SOI layer and the STI layer are not separated by annealing in an H ₂ atmosphere at 900 ° C. and 985 ° C. However, if the annealing temperature in the H ₂ atmosphere is 1000 ° C., the SOI layer is aggregated in an elliptical shape.

Even in the case of an SOI layer having a thickness of 86 nm, the separation of the SOI layer and the STI layer does not occur in the annealing in the H ₂ atmosphere up to 985 ° C. However, if the annealing temperature in the H ₂ atmosphere is increased to 1000 ° C., the SOI layer Is observed to begin shrinking.

In the case of thicknesses of 50 nm and 86 nm, if the annealing temperature in the H ₂ atmosphere is 1000 ° C. or higher, the SOI layer will aggregate. If the annealing temperature in the H ₂ atmosphere is set to 990 ° C. or less, the agglomeration of the SOI layer hardly occurs, and even if it occurs, it will be negligible or acceptable. In the case where an SOI layer having a thickness exceeding 30 nm and having a thickness of 100 nm or less is annealed in an H ₂ atmosphere, the heat treatment temperature is desirably set to 990 ° C. or less.

  Note that the thickness of the SOI layer described here is an initial thickness. Actually, there is a thickness consumed as an oxide film or the like. The SOI layer with an initial thickness of 30 nm is about 13 nm thick after the gate electrode is formed, the SOI layer with an initial thickness of 50 nm is about 33 nm after the gate electrode is formed, and the SOI layer with an initial thickness of 86 nm is after the gate electrode is formed. In FIG. 5, the thickness is reduced to about 68 nm.

  From the above experimental results, when an SOI layer having an initial thickness of 30 nm or less is used, it is desired that the heat treatment temperature in a hydrogen atmosphere be 905 ° C. or less, more preferably 900 ° C. or less. When an SOI layer having an initial thickness exceeding 30 nm and an initial thickness of 100 nm or less is used, it is desirable that the heat treatment temperature in the hydrogen atmosphere be 990 ° C. or lower.

  In other heat treatments, these temperatures will be indicative. By reducing the heat treatment temperature in this way, it becomes possible to prevent the aggregation of the SOI layer. In particular, when an SOI layer having an initial thickness of 30 nm or less is heat-treated in a hydrogen atmosphere, it is desired to lower the heat treatment temperature.

  Prior to the formation of the gate insulating film, various types of wet cleaning of the wafer with a chemical solution are performed for the purpose of metal impurity removal, particle removal, oxide film removal, and the like. SC2 (hydrochloric acid: hydrogen peroxide: water) and POS (sulfuric acid: hydrogen peroxide) are generally used for removing metals, SC1 (ammonia: hydrogen peroxide: water) for removing particles, and diluted HF aqueous solution for removing oxide films. (Hydrofluoric acid: water) or the like is used. Chemical treatment is performed by immersing the wafer in these chemicals or spraying the chemical. After the chemical treatment, pure water cleaning is performed.

  These chemical treatments are treatments that oxidize the Si surface except for HF, and depending on the ratio of hydrogen peroxide, etc., if a subsequent water washing treatment is included, a natural oxide film is formed beyond 1 nm. In some cases.

This time, the particle removal and metal removal treatments were performed first, and then the HF aqueous solution treatment for natural oxide film removal was performed. The inventors of the present invention realized an oxide film removal process in which the etching rate for the oxide film was sufficiently reduced by diluting HF into an ultradiluted state with pure water. An aqueous solution diluted with H ₂ O = 200 or more with respect to HF = 1 is referred to as a super diluted aqueous solution. The ultra-diluted HF aqueous solution with HF: H ₂ O = 1: 700 has an etching rate of about 0.1 nm / min with respect to the oxide film. As will be described later, the oxide film can be uniformly etched.

  When this ultra-diluted aqueous solution is used, a small amount of oxide film etching of about 0.25 nm to 0.5 nm can be adjusted with an accuracy of 10% or less. Even when a silicon oxide film having two or more types of thickness is formed, the thickness can be sufficiently controlled. Furthermore, this ultra-diluted HF aqueous solution treatment was performed for 5 minutes, followed by washing with water and drying to realize a natural oxide film of 0.5 nm or less.

  With reference to FIGS. 3A to 3F, a method of manufacturing a semiconductor device according to the first embodiment will be described.

  As shown in FIG. 3A, an element isolation trench is formed on the surface of the silicon substrate 10, and silicon oxide or the like is buried to form an element isolation region 11 by STI. The element isolation region 11 defines a plurality of active regions AR1 and AR2.

  As shown in FIG. 3B, a first silicon oxide layer 12 is formed on the surfaces of the active regions AR1 and AR2 defined by the element isolation region 11 by thermal oxidation. For example, by steam (wet) oxidation at 800 ° C., a thickness of about 7 nm is obtained by adding a thickness of about 0.5 nm to an etching thickness of about 7 nm to a silicon oxide film corresponding to a driving voltage of 3.3 V on the active region surface. A 5 nm silicon oxide film 12 is formed.

  As shown in FIG. 3C, a resist mask 14 exposing the active region AR2 is formed, and the silicon oxide layer 12 in the exposed active region AR2 is removed with a dilute hydrofluoric acid aqueous solution 15. Since the other active regions are covered with the resist mask 14, this oxide film etching may be performed with, for example, a 2% diluted HF aqueous solution as in the prior art. Thereafter, the resist mask 14 is removed by washing with pure water. Although this step may be performed with an ultra-diluted HF aqueous solution, the processing time becomes longer.

As shown in FIG. 3D, after performing chemical treatment as necessary, treatment is performed for 5 minutes with an ultradiluted hydrofluoric acid aqueous solution 16 of HF: H ₂ O = 1: 700. Subsequently, washing and drying are performed. The silicon oxide film 12 is etched by a thickness of about 0.5 nm by an ultra-diluted HF aqueous solution treatment for 5 minutes to a thickness of about 7 nm. On the surface of the active region from which the silicon oxide layer 12 has been removed, a natural oxide film 17 having a thickness of about 0.5 nm is formed. By further searching for conditions, a natural oxide film having a thickness of 0.5 nm or less can be formed. However, it will be difficult to make the thickness thinner than 0.1 nm.

  As shown in FIG. 3E, a hydrogen atmosphere heat treatment is performed on the wafer on which the thin natural oxide film 17 is formed in a 100% hydrogen gas atmosphere 18 of 20 torr at 900 ° C. for 10 seconds. The natural oxide film 17 having a thickness of about 0.5 nm is reduced and removed by heat treatment in a hydrogen atmosphere.

  As shown in FIG. 3F, a relatively thin gate insulating film having a thickness of 1.5 nm or less, for example, a thickness of about 1.2 nm, in a dry (dry) oxygen atmosphere on the active region surface from which the natural oxide film 17 has been removed. 19 is formed. A relatively thick silicon oxide film 12 also grows slightly.

After the silicon oxide film is formed by dry thermal oxidation, nitriding is performed in a nitriding atmosphere, for example, a gas atmosphere such as N ₂ O or NO. In particular, in the relatively thin silicon oxide film, the introduced nitrogen migrates to form a silicon oxynitride film or a silicon nitride film in the vicinity of the interface with the substrate. As another nitrogen introduction method, there is a method of introducing into the insulating layer or on the surface side using active nitrogen. The reason why nitrogen is introduced into the relatively thin gate insulating film is to prevent the influence of impurities in the gate electrode, but other means can be adopted and the introduction of nitrogen can be omitted.

  Thereafter, a polycrystalline silicon layer is formed to a thickness of about 150 nm, for example, and patterned with a desired gate electrode width. The extension region is ion-implanted using the gate electrode as a mask. After the sidewall spacers are formed, impurity ion implantation is performed again to create high concentration source / drain regions. Thereafter, the gate electrode is covered with an interlayer insulating film. Lead electrodes are formed for the gate, source, and drain, respectively.

  In this manner, a semiconductor device having two types of gate insulating films with different thicknesses can be formed. Note that in the above description, a semiconductor device having two types of gate insulating films is formed, but a semiconductor device having three types of gate insulating films can also be formed.

  In order to confirm the effect of the above-described embodiment, first, it was investigated whether or not local overetching of the silicon oxide film was caused by etching with the super diluted HF aqueous solution. A silicon oxide film having a thickness of 7.7 nm is formed by thermal oxidation in the first oxidation process shown in FIG. 3B, and subsequently, oxide film etching for 0.5 nm is performed by wet treatment with an ultra-diluted HF aqueous solution shown in FIG. 3D. Subsequently, in the second oxidation process shown in FIG. 3F, a process corresponding to forming silicon oxide having a thickness of 1.8 nm on the bare Si surface was performed.

  For comparison, a sample that was not treated with the ultra-diluted HF aqueous solution was also formed. First, a thick silicon oxide film 12 having a thickness of 7.2 nm is formed by the oxidation treatment shown in FIG. 3B, and then a silicon oxide film having a thickness of 1.8 nm is formed on the bare Si surface. The second oxidation treatment shown was performed. The second oxidation treatment hardly increased the film thickness.

  4A and 4B show measurement results obtained by measuring the withstand voltage of the gate insulating films of these samples. The horizontal axis represents the applied voltage in units of V, and the vertical axis represents the leakage current in units of A and a logarithmic scale.

  FIG. 4A shows the measurement results of the comparative example. Since the oxide film is not etched, insulation failure does not occur. Good dielectric strength characteristics are shown.

  FIG. 4B is a graph showing the results of the breakdown voltage test of the gate oxide film of the test example. Since the silicon oxide film once formed is etched with an HF aqueous solution, if the conventional etching is performed, the etching is locally promoted, and a region in which the film thickness is reduced in a pinhole is generated, and the breakdown voltage is deteriorated. Degradation of reliability may occur. The graph shown in the figure shows neither initial failure nor B-mode failure. It can be seen that the gate insulating film of FIG. 4A is excellent in breakdown voltage. It can be seen that the etching of the ultra-diluted hydrofluoric acid solution does not cause a phenomenon that impairs the reliability of the gate insulating film such as etch pits.

  The oxide film thickness was measured using a Rudolph ellipsometer, Matrix S200S (use wavelength: 633 nm single wavelength), with a refractive index of 1.462. Film thickness measurement with an ellipsometer is excellent in reproducibility compared with other measurement methods, but in film thickness measurement of 1 nm or less, the reproducibility has a width of about 0.02 nm. Even in the same type of ellipsometer, the difference between measuring instruments generally exists to the extent that it exceeds 0.02 nm. Even with an ellipsometer, the film thickness measurement results may differ if the model is different. The measured value with an ellipsometer using a single wavelength of 633 nm from KLA showed a measurement result of 0.2 nm thick.

  Next, three types of natural oxide film thicknesses finally formed by wet cleaning with a chemical solution were prepared at 1 nm or less. For a natural oxide film having these three types of film thickness, in a rapid thermal anneal apparatus, a heat treatment in a hydrogen atmosphere shown in FIG. 3E is performed in a 100% hydrogen atmosphere of 20 torr at a plurality of types of temperatures for 10 seconds. The oxide film thickness after the heat treatment was measured.

  The oxide film thickness was measured in an air atmosphere after the heat treatment. For this reason, even if the natural oxide film is completely reduced and removed during the heat treatment in the hydrogen atmosphere, the natural oxide film grows until the measurement, and the oxide film thickness is not measured as zero. This time, it was assumed that the sample that obtained 0.15 nm or less as the measurement value of the film thickness measuring device was that the silicon oxide film was completely reduced and removed during the heat treatment in the hydrogen atmosphere.

  FIG. 5 is a graph showing the measurement results. The horizontal axis indicates the hydrogen annealing temperature in units of ° C., and the vertical axis indicates the natural oxide film thickness in units of nm. No horizontal center treatment indicates the oxide film thickness before the hydrogen annealing treatment. There are three types of film thicknesses of natural oxide films prepared before heat treatment in a hydrogen atmosphere: about 0.73 nm, about 0.51 nm, and about 0.37 nm. Hydrogen annealing treatment was performed in the range of 850 ° C. to 1000 ° C. for these three types of natural oxide films.

  A natural oxide film having an initial film thickness of 0.73 nm still has a considerable thickness even when hydrogen annealing treatment at 900 ° C. and 950 ° C. is performed. In order to remove the natural oxide film, a processing temperature of about 980 ° C. or higher is required. It is shown that it is necessary.

  The natural oxide film having an initial film thickness of 0.37 nm is judged to be almost completely removed by the hydrogen annealing treatment at 850 ° C. When the temperature of the hydrogen annealing treatment is increased to 880 ° C., 890 ° C., and 900 ° C. It is considered that the natural oxide film has been removed more reliably.

  The natural oxide film with an initial film thickness of 0.51 nm seems to be almost removed by hydrogen annealing at 900 ° C., and is considered to be completely removed by hydrogen annealing at about 980 ° C. and about 1000 ° C. It is done.

  When processing temperatures of about 980 ° C. and about 1000 ° C. are reached, it is considered that the natural oxide film is almost completely removed regardless of the initial film thickness.

  The measurement results shown in FIG. 5 indicate that the temperature at which the natural oxide film can be reduced and removed by the hydrogen annealing process differs depending on the initial natural oxide film thickness. When the initial film thickness is thick, it is difficult to completely remove the natural oxide film unless the temperature is set to about 980 ° C. or higher. If the initial film thickness is about 0.5 nm or less, it is considered that the natural oxide film can be almost completely removed even by hydrogen annealing at 900 ° C. or less. If the initial film thickness is 0.4 nm or less, it is considered that the natural oxide film can be almost completely removed if the hydrogen annealing temperature is about 850 ° C. or higher.

  From these results, when the natural oxide film is to be completely removed by heat treatment in a hydrogen atmosphere at about 900 ° C., more specifically, 905 ° C. or less, the natural oxide film thickness is desirably 0.5 nm or less. I understand. As long as wet cleaning is performed, a natural oxide film having a thickness of 0.1 nm or more will be generated.

  Next, it was examined how the natural oxide film thickness reduced and removed by the heat treatment in the hydrogen atmosphere changes depending on the processing temperature and the processing pressure.

  6A shows the case where the initial natural oxide film thickness is 0.842 nm, and FIG. 6B shows the case where the initial natural oxide film thickness is 0.426 nm. In the figure, the horizontal axis represents the processing pressure in unit torr and logarithmic scale, and the vertical axis represents the natural oxide film thickness in unit nm and linear scale.

  In FIG. 6A, the initial oxide film thickness is indicated by a cross. This natural oxide film was annealed in a hydrogen atmosphere at 1000 ° C., 980 ° C., 950 ° C., 930 ° C., and 880 ° C. A change in the remaining oxide film thickness when the processing pressure of the annealing process in the hydrogen atmosphere is changed is shown. It is shown that at a processing temperature of 1000 ° C., the natural oxide film is almost completely reduced and removed regardless of the processing pressure. Even when the processing temperature is lowered to 980 ° C., it is considered that the oxide film thickness is almost completely removed regardless of the processing pressure.

  It is shown that when the processing temperature is lowered to 950 ° C., the remaining oxide film thickness decreases as the processing pressure decreases. In order to remove the oxide film almost completely, a low processing pressure of 10 torr or less is desirable.

When the processing temperature is lowered to 930 ° C., the characteristics that the remaining oxide film thickness decreases with a decrease in the processing pressure are the same, but the remaining oxide film thickness is large and it is difficult to completely remove the oxide film. When the processing temperature is lowered to 880 ° C., almost no change due to the processing pressure is observed. That is, a part of the oxide film is removed by the heat treatment in H ₂ , but a considerable part remains, and the change in the remaining oxide film thickness is slight even if the processing pressure is changed.

FIG. 6B shows a case where the initial oxide film is 0.426 nm. The processing temperature was 930 ° C. and 880 ° C. Although the processing pressure was changed to 5 torr, 10 torr, and 20 torr, the remaining oxide film thickness after the heat treatment in the H ₂ atmosphere was almost 0, and no change due to the processing temperature and the processing pressure was observed. If the natural oxide film thickness before processing is 0.5 nm or less and the processing pressure is 20 torr or less, the natural oxide film can be reduced and removed sufficiently effectively even if the heat treatment temperature in the hydrogen atmosphere is 900 ° C. or less. It is shown.

  Considering the measurement results shown in FIGS. 5, 6A and 6B, if the initial natural oxide film is 0.5 nm or less, the natural oxide film can be almost completely removed by heat treatment in a hydrogen atmosphere at 860 ° C. or higher. It is guessed that it will be. Even if the temperature of the heat treatment in the hydrogen atmosphere is limited to 900 ° C. or less, there is a margin for the heat treatment temperature of about 40 ° C. In the first embodiment shown in FIGS. 3A to 3F, in order to form a relatively thin gate insulating film, the semiconductor wafer is exposed to the atmosphere in the same processing chamber or following the annealing process in a hydrogen atmosphere. In order to ensure the stability of the final insulation film thickness, it is preferable to carry it into the insulation film formation processing chamber and perform the next insulation film formation.

  The carrier mobility that governs the performance of a semiconductor device also depends on the microroughness of the substrate surface. The effect of initial natural oxide thickness on microroughness was investigated. First, samples having different initial natural oxide film thicknesses were prepared, and these natural oxide films were reduced and removed by annealing in a hydrogen atmosphere. An insulating layer was formed on the obtained Si surface, the surfaces of these samples were observed with an atomic force microscope (AFM), and evaluation was performed with RMS which is a parameter of surface roughness. The experimental procedure is described below.

  As shown in FIG. 7A, a silicon substrate 10 having a natural oxide film 17 is prepared. The natural oxide film 12 having a thickness of 0.8 nm, 1.1 nm, 1.2 nm, and 1.3 nm was prepared by wet processing.

  As shown in FIG. 7B, annealing was performed in a hydrogen atmosphere capable of reducing and removing these natural oxide films at a temperature of 1000 ° C., an atmospheric pressure of 20 torr, and a processing time of 10 sec.

  As shown in FIG. 7C, some samples were further annealed in a He atmosphere to promote migration and improve microroughness. The He annealing treatment was also performed at 1000 ° C., an atmospheric pressure of 20 torr, and a treatment time of 10 seconds.

  As shown in FIG. 7D, following the heat treatment in a hydrogen atmosphere (or further in the He atmosphere), a 0.85 nm oxide film 19 was formed without exposure to the air.

  As shown in FIG. 7E, after the oxide film 19 was formed, nitriding treatment with NO gas was performed. Finally, an insulating film having a thickness of 1.1 nm was obtained.

  FIG. 7F is a graph showing microroughness measurement results finally obtained with respect to the initial natural oxide film thickness. The horizontal axis represents the initial natural oxide film thickness in units of nm and a linear scale, and the vertical axis represents RMS in units of nm and a logarithmic scale. The measurement results after the hydrogen annealing are indicated by Δ, and the measurement results after performing the He annealing following the hydrogen annealing are indicated by ◇. When the initial oxide film thickness is 1.2 nm or less, it is observed that the RMS changes almost in proportion to the initial oxide film thickness. When the initial oxide film thickness is about 1.3 nm or more, the RMS increases rapidly.

  From the result shown in FIG. 7F, in order to improve the microroughness, it is desirable to set the initial oxide film thickness to about 1.2 nm or less, and it is determined that the microroughness decreases as the initial oxide film thickness decreases.

  It can be seen that the microroughness is also strongly influenced by the initial natural oxide film thickness. Note that although a nitrided oxide film is formed as the gate insulating film, it is considered that the same result can be obtained even if the oxide film does not contain nitrogen. It is also possible to use a metal oxide film containing Hf, Zr, Al or the like, which is generally called a high-k material.

  A method for manufacturing a semiconductor device according to a modification of the first embodiment using an SOI substrate will be described below.

  As shown in FIG. 8A, element isolation trenches are formed on the surface of an SOI substrate including a silicon oxide buried insulating layer 25 and a single crystal silicon (SOI) layer 20 on a silicon substrate 26 as a support substrate. STI element isolation regions 21 are formed by embedding silicon oxide or the like. The active regions AR1 and AR2 are defined by the element isolation region 21.

  As shown in FIG. 8B, a relatively thick silicon oxide gate insulating film 22 having a thickness of about 7.5 nm is formed on the surface of the SOI layer 20 by steam (wet) oxidation at 800 ° C.

  As shown in FIG. 8C, a resist layer is formed on the substrate surface, and exposed and developed to form a resist pattern 24 that opens the active region AR2. Using the resist pattern 24 as a mask, the silicon oxide film 22 on the active region AR2 is removed with a hydrofluoric acid aqueous solution.

  As shown in FIG. 8D, the resist pattern 24 is removed with a chemical solution. Further, chemical treatment such as SC1, SC2 is performed. Finally, a wet treatment for 5 minutes is performed with the above-described ultradiluted HF aqueous solution 27 to form a natural oxide film 28 having a thickness of 0.5 nm or less on the surface of the active region AR2. The silicon oxide film on the active region AR1 is etched by 0.5 nm to a thickness of 7 nm.

  As shown in FIG. 8E, the SOI layer 20 is heated at 900 ° C. for 10 seconds in a hydrogen gas 100% atmosphere 29 of 20 torr to perform heat treatment in a hydrogen atmosphere. The natural oxide film 28 having a thickness of 0.5 nm or less on the active region AR2 is removed by the heat treatment in the hydrogen atmosphere.

As shown in FIG. 8F, a relatively thin gate insulating film in a dry (dry) oxygen atmosphere in the same processing chamber as that in which the heat treatment is performed in a hydrogen atmosphere or a processing chamber in which a substrate can be transferred without breaking a vacuum. 31 is formed. After the silicon oxide film is formed by dry thermal oxidation, nitriding is performed in a nitriding atmosphere, for example, a gas atmosphere such as N ₂ O or NO.

  The introduced nitrogen migrates the silicon oxide film 31 to form a silicon oxynitride film or a silicon nitride film in the vicinity of the interface with the SOI layer 20. In this manner, a relatively thin gate insulating film having a thickness of about 1.2 nm is formed in the active region AR2. The reason why nitrogen is introduced into the relatively thin gate insulating film is to prevent the influence of impurities in the gate electrode, but other means can be adopted and the introduction of nitrogen can be omitted.

  As shown in FIG. 8G, a polycrystalline silicon layer 33 is formed to a thickness of about 150 nm and patterned with a desired gate electrode width. The extension region 34 is ion-implanted using the gate electrode as a mask. After the sidewall spacer 35 is formed, impurity ions are implanted again to form a deep high concentration source / drain region 36.

  By making the bottom surface of the deep source / drain region reach or close to the buried insulating layer, insulation isolation can be realized and parasitic capacitance can be reduced. Thereafter, the gate electrode is covered with an interlayer insulating film 38. Note that lead electrodes G, S, and D are formed for the gate, source, and drain, respectively.

  In this manner, an SOI type semiconductor device having two types of gate insulating films having different thicknesses can be formed.

  Note that in the above description, a semiconductor device having two types of gate insulating films is formed, but a semiconductor device having three types of gate insulating films can also be formed. In this case, a thick gate insulating film and a medium thickness gate insulating film are formed by the steps shown in FIGS. 8A to 8F, and the steps shown in FIGS. 8C to 8F are repeated to form a thinner gate insulating film 32. .

  As shown in FIG. 8H, after three types of gate insulating films are formed in this way, a gate electrode, an extension region, a sidewall oxide film, a source / drain region, and an interlayer insulating film are formed.

  In the step of removing a part of the gate insulating film, the resist removal and the subsequent chemical treatment of the surface treatment are performed. At the end of the chemical treatment, the ultra-diluted HF aqueous solution is washed, pure water washing, and drying are performed. The thickness of the natural oxide film can be 0.5 nm or less, and the temperature of the hydrogen atmosphere heat treatment can be 900 ° C. or less. Further, the substrate surface is planarized by the hydrogen atmosphere heat treatment, and the gate breakdown voltage can be improved.

  Note that similar heat treatment in a hydrogen atmosphere may be performed before the gate insulating film to be formed first. The conditions for the heat treatment in the hydrogen atmosphere can be selected within a range that does not significantly affect the remaining gate insulating film. Instead of the hydrogen atmosphere, an atmosphere containing hydrogen may be used. For example, an atmosphere in which hydrogen is diluted with a gas such as nitrogen or argon may be used.

  The thinnest gate insulating film is formed of a silicon oxide film formed by thermal oxidation and nitrogen is introduced into the silicon oxide film. However, an oxide film formed by plasma oxidation or radical oxidation may be used. It would also be possible to use an oxide film that does not contain nitrogen.

  Although the case where the partially depleted SOI transistor is formed has been described above, a fully depleted SOI transistor can also be formed.

  9A to 9D show a modification in which a fully depleted SOI transistor is formed.

  As shown in FIG. 9A, an SOI wafer having a buried insulating layer 25 and an SOI silicon layer 20 on a silicon support substrate 26 is prepared. The SOI layer is selected such that the final thickness is 5 nm, for example. An STI element isolation region 21 that penetrates the SOI layer 20 and the buried insulating layer 25 and enters the support substrate 26 is formed.

  As shown in FIG. 9B, p-type impurities are ion-implanted to form a p-type well 30 in the support substrate 26. Thereafter, a gate insulating film 31, a polycrystalline silicon gate electrode 33, and an insulating cover layer 39 such as silicon oxide are stacked on the SOI layer 20 and patterned. A gate electrode structure is formed.

  Source / drain extensions 34 are formed by ion implantation of n-type impurities using the gate electrode structure as a mask. The SOI layer 20 between the extensions 34 is electrically isolated and is completely depleted during operation. An insulating layer such as silicon oxide is deposited and anisotropically etched to form side wall spacers 35 on the side walls of the gate electrode structure. The SOI layer 20 is exposed on both sides of the sidewall spacer 35.

As shown in FIG. 9C, the SOI layer 20 and the buried insulating layer 25 are etched using the gate electrode structure and the sidewall spacer as a mask. The surface of the silicon support substrate 26 is exposed.
As shown in FIG. 9D, a silicon layer is epitaxially grown on the silicon surface. Deep source / drain regions 50 are formed by ion implantation of n-type impurities. Further, the cover layer 39 may be removed and silicidation may be performed to form a silicide layer on the surface of the gate electrode 33 and the deep source / drain region 50.

  In the fully depleted SOI transistor, since the extension depth is regulated by the buried insulating layer, it is easy to realize a miniaturized transistor that prevents punch-through.

  Note that carrier mobility can be improved by introducing tensile stress into the silicon layer forming the semiconductor element. In order to form a strained Si layer containing such tensile stress, a technique of epitaxially forming a Si layer on a base substrate having a lattice constant larger than that of Si can be used.

Si is a diamond crystal having a lattice constant of about 5.43A, Ge is a diamond crystal having a lattice constant of about 5.66, and Si—Ge can form a mixed crystal. When the Ge composition of the Si—Ge mixed crystal is increased, the lattice constant gradually increases. CaF ₂ is a cubic system having a lattice constant of 5.46 A, and can grow epitaxially on a Si single crystal or a Si—Ge mixed crystal. When a Si layer is epitaxially grown using a Si—Ge mixed crystal once the lattice constant is increased, a Si layer containing a tensile strain can be formed. When a CaF ₂ layer is inserted into a Si—Ge mixed crystal whose lattice constant changes, an SOI strained Si layer can be realized.

  10A to 10H show a second embodiment of the present invention.

FIG. 10A is a graph showing the lattice constant of the Si—Ge mixed crystal. The horizontal axis shows the ratio of the number of Ge atoms to the number of Si atoms in%. The vertical axis represents the lattice constant in units A. As the Ge concentration of the Si—Ge mixed crystal increases, the lattice constant increases almost linearly. CaF ₂ has a lattice constant of about 5.46 A and corresponds to the lattice constant of a SiGe mixed crystal having a Ge concentration of about 13 to 17%.

As shown in FIG. 10B, a (100) -plane silicon wafer 41 is placed on a susceptor in a chemical vapor deposition (CVD) chamber, and the temperature of the silicon wafer 41 is stabilized at about 600 ° C. to 700 ° C. A mixed gas obtained by mixing SiH ₄ gas, GeH ₄ gas, and H ₂ gas at a predetermined mixing rate is supplied into the chamber at a flow rate of 2000 sccm, and the Si—Ge mixed crystal layer 42 a is epitaxially grown on the silicon wafer 41.

The flow ratio of GeH ₄ to SiH ₄ is changed during film formation. Initially, a Si—Ge mixed crystal having a very low Ge concentration grows on the Si wafer and is substantially lattice matched. As the Ge concentration in the mixed gas increases, the first composition-gradient Si—Ge layer 42a, whose Ge concentration in the epitaxial layer increases from the lower surface to the upper surface, grows epitaxially on the silicon wafer 41. The thickness of the first composition gradient Si—Ge layer 42a is, for example, 1 μm to 3 μm.

  As shown in FIG. 10C, when the Ge concentration (Ge / Si) × 100 on the upper surface of the first composition gradient Si—Ge layer 42 becomes about 13% to 17%, the Ge concentration is fixed, and the film is further formed. Continue. On the first composition gradient Si—Ge layer 42a, a first constant composition Si—Ge layer 42b whose composition of Ge does not change in the film thickness direction is epitaxially grown. The thickness of the first constant composition Si—Ge layer 42b is, for example, about 1 μm to 3 μm.

As shown in FIG. 10D, the silicon wafer 41 is removed from the CVD chamber and transferred into an MBE chamber equipped with a Knudsen cell. In the MBE chamber, the temperature of the silicon wafer is stabilized at about 600 ° C. to 900 ° C. CaF ₂ filled in the Knudsen cell is heated to about 1800 ° C. to generate a CaF ₂ molecular beam, which is irradiated onto the surface of the Si—Ge layer 42. The single crystal CaF ₂ layer 43 is epitaxially grown on the Si—Ge layer at a film formation rate of about 1 atomic layer to 3 atomic layers / minute. The film formation is stopped when the thickness of the CaF ₂ layer 43 reaches 10 nm to 1000 nm. In this way, the single crystal insulating layer 43 is obtained.

In addition to the CaF ₂ layer, mixed crystal fluorides such as (Ca, Sr) F ₂ , Al ₂ O ₃ layer, SeO ₂ layer, MgO—Al ₂ O ₃ layer, etc. may be formed as a single crystal insulating layer. Good. When a (Ca—Sr) F ₂ layer is grown, the composition of SrF ₂ can be gradually increased during growth using CaF ₂ Knudsen cell and SrF ₂ Knudsen cell. As the SrF ₂ composition increases, the lattice constant increases.

As shown in FIG. 10E, the wafer is transferred back into the CVD chamber and the substrate temperature is fixed at about 600 ° C. to 700 ° C. GeH _4, using mixed gas of SiH _4, by changing the flow ratio SiH ₄ of GeH _4, monocrystalline insulating the second composition graded Si-Ge layer 44a which Ge concentration, the higher toward the upper surface from the lower surface The layer 3 is epitaxially grown to a thickness of about 0.5 μm to 2 μm. The Ge concentration in the second composition gradient Si—Ge layer 44a is about 13 to 17% on the lower surface and 20 to 50% on the upper surface.

As shown in FIG. 10F, after the second composition gradient Si—Ge layer 44a is grown, the flow rate ratio of GeH ₄ to SiH ₄ is fixed, and the second composition gradient Si—Ge layer 4a is formed on the second composition gradient Si—Ge layer 4a. The constant composition Si—Ge layer 44b is epitaxially grown. The film thickness of the second constant composition Si—Ge layer 44b is, for example, about 1 μm to 3 μm.

As shown in FIG. 10G, the supply of GeH ₄ is stopped, a mixed gas of SiH ₄ and H ₂ is supplied as a source gas, and a Si layer 45 is formed on the second Si—Ge layer 44 to a thickness of about 10 nm. Grow epitaxially to ˜30 nm.

  The lattice constant of single crystal silicon without stress is about 5.43 A, which is smaller than the lattice constant of the second constant composition Si—Ge layer 4 b, about 5.48 A to about 5.54 A. Therefore, the epitaxially grown Si layer 45 becomes a strained Si layer containing a tensile strain in accordance with the lattice constant of the underlying Si—Ge layer 44b.

In the above embodiment, a Si-Ge layer having a monotonically increasing Ge concentration is grown on a silicon wafer, a strained Si layer is grown thereon, and a CaF ₂ layer is inserted between the Si-Ge mixed crystal layers. did. In crystal growth, a crystal close to the underlying lattice constant is first grown, and then the lattice constant gradually changes. For this reason, it is difficult to form crystal defects due to lattice mismatch. The lattice constant of the Si—Ge mixed crystal is once increased to about 5.46A to 5.47A to enable lattice matching with CaF ₂ having a lattice constant of 5.46A. A Si—Ge mixed crystal is further grown on the CaF ₂ layer, and the lattice constant is gradually increased. For this reason, a high-quality single crystal layer can be formed.

  In addition, since a constant composition mixed crystal layer is formed on the composition gradient mixed crystal layer, even if a defect occurs in the composition gradient mixed crystal layer, it is absorbed in the constant composition mixed crystal layer, and a crystal defect is formed on the upper surface thereof. Is difficult to enter.

  The lattice constant on the upper surface of the second Si—Ge layer is 5.48 A to 5.54 A, which is considerably larger than the lattice constant of silicon, which is about 5.43 A. In this way, the lattice mismatch between the strained Si layer 45 and the base can be increased, and a strong tensile strain can be generated.

As shown in FIG. 10H, a shallow trench reaching from the substrate surface to at least the surface of the single crystal insulating layer 43 is formed, and an insulator such as SiO ₂ is embedded to form the STI element isolation region 46.

  As in the previous embodiment, the natural oxide film on the substrate surface is removed, and the surface of the strained Si layer 45 is thermally oxidized to form the gate insulating film 31. A polycrystalline silicon gate electrode 33 is formed on the gate insulating film 31 and patterned into a gate electrode shape. Shallow ion implantation is performed to form source / drain extensions 34. An insulating layer such as silicon oxide is deposited and anisotropic etching is performed to form sidewall spacers 35 on the side walls of the gate electrode. After ion implantation for the source / drain 36 is performed on the gate electrode surface and the silicon surface exposed on both sides of the sidewall spacer, a silicidation reaction is performed to form a silicide layer 37.

  Thereafter, the substrate surface is covered with a cover layer 40 such as silicon nitride. On the cover layer 40, an interlayer insulating layer 38 of silicon oxide is formed by plasma CVD using TEOS as a source gas. A contact hole is formed through the interlayer insulating layer 38 and the cover layer 40 to expose the silicide layer 37. A TiN layer is sputtered in the contact hole, a tungsten film is subsequently grown by CVD, and unnecessary portions are removed by chemical mechanical polishing (CMP) to form a conductive plug 47 composed of a TiN layer 47a and a W layer 47b.

  A metal wiring 48 is formed on the interlayer insulating film 38 with aluminum or the like.

In this embodiment, since the buried insulating layer is formed of a single crystal insulating film, the thermal conductivity is high. A silicon oxide insulating layer has a thermal conductivity of about 1.4 W / mK, whereas a single crystal insulating layer such as CaF ₂ has a thermal conductivity of about 9.71 W / mK. For this reason, the heat generated in the MOS transistor is quickly dissipated from the back surface of the silicon wafer 41 through the single crystal insulating layer 43 having a high thermal conductivity.

In the above-described embodiment, a Si—Ge mixed crystal layer was formed between the base silicon substrate and the CaF ₂ single crystal insulating layer, and a Si—Ge mixed crystal layer was further formed on the CaF ₂ single crystal insulating layer. Depending on the purpose, the lower Si-Ge layer can be omitted. Since the CaF ₂ single crystal insulating layer has a lattice mismatch with the underlying silicon, crystal defects are likely to occur, but if the crystal defects are allowed to some extent or can be prevented by other methods, the lower side The Si—Ge mixed crystal can be omitted. It is also possible to omit the Si—Ge mixed crystal layer under the strained Si layer. For example, the upper Si-Ge mixed crystal layer can be omitted when tensile stress is not so much required, or when the required lattice mismatch is obtained by further increasing the lattice constant in the single crystal insulating layer. .

The features of the present invention will be described below.
(Appendix 1)
(A) preparing a substrate having at least a silicon surface layer;
(B) forming a natural oxide film having a thickness of 0.1 nm to 0.5 nm on the surface of the silicon layer;
(C) reducing and removing the natural oxide film having a thickness of 0.1 nm to 0.5 nm by hydrogen annealing;
(D) following the step (c), forming a gate insulating film on the surface of the silicon surface layer;
A method for manufacturing a semiconductor device comprising: (1)
(Appendix 2)
_{2. The} method of manufacturing a semiconductor device according to claim 1, wherein the step (b) etches the silicon oxide layer with a dilute hydrofluoric acid aqueous solution of HF = 1 and H ₂ O = 200 or more, and then performs pure water cleaning and drying. (2)
(Appendix 3)
The method for manufacturing a semiconductor device according to appendix 1, wherein the step (c) performs annealing at 905 ° C. or lower in a hydrogen atmosphere. (3)
(Appendix 4)
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (d) is performed without exposing the substrate to the atmosphere after the step (c).

(Appendix 5)
4. The method of manufacturing a semiconductor device according to appendix 3, wherein the substrate in the step (a) is an SOI substrate, and the silicon surface layer is a silicon layer having a thickness of 30 nm or less disposed on the insulating layer.

(Appendix 6)
The method of manufacturing a semiconductor device according to claim 3, wherein the substrate in the step (a) is an SOI substrate including a Si—Ge mixed crystal layer, and the silicon surface layer is a strained silicon layer in which tensile stress is inherent. (4-1)
(Appendix 7)
The method for manufacturing a semiconductor device according to claim 6, wherein the substrate in the step (a) includes a silicon support substrate, and includes a single crystal insulating layer disposed between the silicon surface layer and the silicon support substrate. (4-2)
(Appendix 8)
Appendix 7 wherein the step (a) includes: (a-1) a step of epitaxially growing a Si—Ge mixed crystal layer by CVD; and (a-2) a step of epitaxially growing a single crystal insulating layer by MBE. Semiconductor device manufacturing method.

(Appendix 9)
The method of manufacturing a semiconductor device according to appendix 8, wherein the step (a-1) includes a step of epitaxially growing a Si—Ge mixed crystal layer in which the Ge concentration monotonously increases.

(Appendix 10)
The method of manufacturing a semiconductor device according to appendix 9, wherein the step (a-1) further includes a step of epitaxially growing a Si—Ge mixed crystal layer having a constant Ge concentration.

(Appendix 11)
The single crystal insulating layer is disposed between the silicon support substrate and the Si—Ge mixed crystal layer, in the Si—Ge mixed crystal layer, or between the Si—Ge mixed crystal layer and the silicon surface layer. A method for manufacturing a semiconductor device according to appendix 7.

(Appendix 12)
Item 12. The method for manufacturing a semiconductor device according to Item 11, wherein the single crystal insulating layer is a fluoride insulating layer.

(Appendix 13)
The monocrystalline insulating _{layer, CaF 2, Al 2 O 3} , SeO 2, the manufacturing method of the _MgO-Al 2 _{O 3} of Supplementary Notes 11, characterized in that formed in one of.

(Appendix 14)
(A) preparing an SOI substrate having a silicon surface layer having a thickness of more than 30 nm and not more than 100 nm;
(B) annealing the SOI substrate in a hydrogen atmosphere at a temperature of 990 ° C. or less to remove a natural oxide film;
A method for manufacturing a semiconductor device comprising: (5)
(Appendix 15)
(A) preparing a substrate having at least a silicon surface layer;
(B) forming a natural oxide film having a thickness of 0.1 nm to 1.2 nm on the surface of the silicon surface layer;
(C) reducing and removing the natural oxide film having a thickness of 0.1 nm to 1.2 nm by hydrogen annealing;
(D) following the step (c), forming a gate insulating film on the surface of the silicon surface layer;
A method for manufacturing a semiconductor device comprising:

(Appendix 16)
(A) preparing an SOI substrate having a silicon layer having a thickness of 100 nm or less and thicker than 30 nm on the insulating film;
(B) reducing and removing a natural oxide film on the surface of the SOI substrate by hydrogen annealing;
(C) following the step (b), forming a gate insulating film on the surface of the silicon surface layer;
A method for manufacturing a semiconductor device comprising:

(Appendix 17)
18. The method for manufacturing a semiconductor device according to appendix 16, wherein the step (b) performs annealing at 990 ° C. or less in a hydrogen atmosphere.

(Appendix 18)
A support substrate;
A single crystal Si-Ge mixed crystal layer formed above the support substrate, the Si-Ge mixed crystal layer monotonically increasing as it goes upward;
A strained Si layer formed above the Si-Ge mixed crystal layer and having an inherent tensile stress;
A single crystal insulating layer inserted between the support substrate and the strained Si layer;
A semiconductor device.

(Appendix 19)
The semiconductor device according to appendix 18, wherein the support substrate is a single crystal Si substrate, and the single crystal insulating layer is formed of any one of CaF ₂ , Al ₂ O ₃ , SeO ₂ , and MgO—Al ₂ O ₃ .

(Appendix 20)
19. The semiconductor device according to appendix 18, wherein the SiGe mixed crystal layer includes a composition gradient layer in which a Ge component increases as it goes upward, and a composition constant layer formed thereon and having a certain Ge component.

(Appendix 21)
Furthermore, an insulated gate electrode formed on the surface of the strained Si layer,
Source / drain regions formed in the strained Si layer on both sides of the insulated gate electrode;
Item 19. The semiconductor device according to appendix 18.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  Provided is a method for manufacturing a semiconductor device having a process capable of reducing a natural oxide film by reduction. It can be used for miniaturized highly functional semiconductor integrated circuits.

It is sectional drawing of the board | substrate which shows the preparation procedure of the sample used for experiment. It is a photograph which shows the surface state after heat processing in the hydrogen atmosphere of the produced sample. It is sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor device by a 1st Example. It is a graph which shows the experimental result which confirms the effect of a 1st Example. It is a graph which shows the experimental result which confirms the effect of a 1st Example. It is a graph which shows the experimental result which confirms the effect of a 1st Example. It is a sectional view showing the preparation procedure of the sample which measured microroughness, and a graph which shows a measurement result. It is sectional drawing of the board | substrate which shows the manufacturing process of the modification of a 1st Example. It is sectional drawing of the board | substrate which shows the manufacturing process of the modification of a 1st Example. It is sectional drawing which shows the manufacturing process of the semiconductor device by the graph which shows the change of a lattice constant, and 2nd Example.

Explanation of symbols

10 Si substrate 11 STI
12 Gate insulating film 14 Resist mask 15 Diluted HF aqueous solution 16 Super diluted HF aqueous solution 17 Natural oxide film 18 Hydrogen atmosphere 19 Gate insulating film 20 SOI layer 20x Sacrificial oxide film 21 STI
22 Gate insulating film 24 Resist mask 25 Embedded insulating layer 26 Support substrate 27 Super diluted HF aqueous solution 28 Natural oxide film 29 H ₂ atmosphere 31, 32 Gate insulating film 33 Gate electrode 34 Source / drain extension 35 Side wall spacer 36 Deep source / Drain region 37 Silicide layer 38 Interlayer insulating film 39 Cover film 41 Support substrate 42 Si-Ge layer 43 Single crystal insulating layer 44 Si-Ge layer 45 Strained Si layer 46 STI
47 Conductive plug 48 Metal wiring

Claims (5)

(A) preparing a substrate having at least a silicon surface layer;
(B) forming a natural oxide film having a thickness of 0.1 nm to 0.5 nm on the surface of the silicon layer;
(C) reducing and removing the natural oxide film having a thickness of 0.1 nm to 0.5 nm by hydrogen annealing;
(D) following the step (c), forming a gate insulating film on the surface of the silicon surface layer;
A method for manufacturing a semiconductor device comprising: _{2. The} method of manufacturing a semiconductor device according to claim 1, wherein the step (b) etches the silicon oxide layer with a dilute hydrofluoric acid aqueous solution of HF = 1 and H ₂ O = 200 or more, and then performs pure water cleaning and drying.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (c) performs annealing at 905 ° C. or less in a hydrogen atmosphere.   The substrate in the step (a) is an SOI substrate including a Si—Ge mixed crystal layer, and the silicon surface layer is a strained silicon layer in which tensile stress is inherent, or the silicon surface layer in the step (a) is 4. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor layer is a silicon layer formed on an insulating surface having a lattice constant larger than that of Si. (A) preparing an SOI substrate having a silicon surface layer having a thickness of more than 30 nm and not more than 100 nm;
(B) annealing the SOI substrate in a hydrogen atmosphere at a temperature of 990 ° C. or less to remove a natural oxide film;
A method for manufacturing a semiconductor device comprising: