JP5632240B2 - Method for forming fine pattern - Google Patents

Description

  The present invention relates to a method for forming a fine pattern used in a semiconductor manufacturing process.

  As the semiconductor integrated circuit is further miniaturized, a technique for realizing a dimension smaller than a dimension (limit dimension) that can be exposed by exposure light having a wavelength of 193 nm has been put into practical use. One of them is a so-called sidewall transfer (SWT) technique.

  In the SWT technique, a resist pattern including lines and / or spaces having a width corresponding to a critical dimension is formed. Next, by trimming the resist pattern, lines and / or spaces narrower than the critical dimension are formed. Next, a silicon oxide film is deposited so as to cover the trimmed resist pattern. When this silicon oxide film is etched back, silicon oxide (side wall portions) remains only on the side surfaces of the resist pattern. Thereafter, when the resist pattern is removed, only the side wall portion remains. Since the width of the side wall is determined by the thickness of the silicon oxide film, the width can be made smaller than the critical dimension, and the distance between the side walls is determined by the line width of the trimmed resist pattern, so that the distance is smaller than the critical dimension. It can be.

  By using the SWT technique in this manner, a pattern including a dimension smaller than the limit dimension that can be exposed can be formed. Further, by using this pattern as an etching mask pattern, a dimension smaller than the limit dimension can be formed. It is possible to realize a semiconductor integrated circuit having

  Also, a predetermined pattern (line / space) is formed with a material different from that of the resist, the pattern is trimmed to a width smaller than the critical dimension, and the side wall portion is formed using the trimmed pattern (line / space). (Patent Document 1).

JP 2009-88085 A

  SWT is becoming an indispensable technology for manufacturing semiconductor integrated circuits having dimensions smaller than the exposure limit dimension. However, as the dimensions become smaller, the resist pattern that forms the basis for forming the sidewall portion is removed. In such a case, the side wall portion is inclined and may not be used as an etching mask having a desired pattern. In particular, when the aspect ratio of the side wall part exceeds a predetermined value, the side wall part falls down.

  In order to cope with this, when a pattern (line / space) is formed with a film material having a physical strength higher than that of the resist pattern to form the side wall, the film made of the film material and the film are patterned. As a result, it is necessary to laminate the resist film, and problems such as a decrease in throughput, a decrease in yield, and an increase in manufacturing cost occur as the number of process steps increases.

  In view of the above circumstances, the present invention intends to provide a method for forming a fine pattern capable of suppressing the inclination of the sidewall portion even when the pattern serving as the basis for forming the sidewall portion is formed of a resist. .

According to the first aspect of the present invention, an organic film forming step of forming an organic film on an etching target layer formed on a substrate, a resist film is formed on the organic film, and the resist film is patterned. A patterning step, a first deposition step of depositing a silicon oxide film at room temperature so as to cover the organic film exposed from the patterned resist film, and the patterned resist film, and the silicon oxide film A second deposition step in which a silicon nitride film is deposited at a temperature in the range of 300 to 550 ° C. to generate a tensile stress in the silicon oxide film, and the silicon oxide film and the sidewall of the patterned resist film first etching scan for etching the silicon oxide film and the silicon nitride film so that the silicon nitride film remains Tsu including a flop, and a removal step of removing the patterned resist film, method of forming a fine pattern.

  According to the embodiment of the present invention, there is provided a fine pattern forming method capable of suppressing the inclination of the side wall portion even when the pattern serving as the basis for forming the side wall portion is formed of a resist.

It is a flowchart for demonstrating the procedure of each process in the fine pattern formation method by the 1st Embodiment of this invention. It is a figure explaining the fine pattern formation method by the 1st Embodiment of this invention. FIG. 2 is a diagram for explaining a fine pattern forming method according to the first embodiment of the present invention, following FIG. 1. It is a figure which shows typically a mode that a wafer curves by the heat processing process of the fine pattern formation method by the 1st Embodiment of this invention. It is sectional drawing which shows typically the molecular layer deposition apparatus suitable for the fine pattern formation method by the 1st Embodiment of this invention. FIG. 6 is another cross-sectional view of the molecular layer deposition apparatus of FIG. 5. It is a time chart which shows the process of the fine pattern formation method by the 1st Embodiment of this invention performed using the molecular layer deposition apparatus shown in FIG. 5 and FIG. It is a flowchart for demonstrating the procedure of each process in the fine pattern formation method by the 2nd Embodiment of this invention. It is a figure explaining the fine pattern formation method by the 2nd Embodiment of this invention. FIG. 10 is a diagram for explaining the fine pattern forming method according to the second embodiment of the present invention, following FIG. 9. It is explanatory drawing explaining the stress measurement apparatus used when examining the heating temperature dependence of the tensile stress produced by the heat processing process of the fine pattern formation method by the 1st Embodiment of this invention, and its measurement principle. It is a graph which shows the heating temperature dependence of the tensile stress produced by the heat processing process of the fine pattern formation method by the 1st Embodiment of this invention. It is a schematic diagram which shows the result of the experiment conducted in order to confirm the effect of the fine pattern formation method by 1st Embodiment and 2nd Embodiment. It is a graph which shows an example of the deposition temperature dependence of the tensile stress which arises in a silicon nitride film. It is a graph which shows the result of the experiment further performed in order to confirm the effect of the fine pattern formation method by 1st Embodiment and 2nd Embodiment. It is a table | surface which shows the result of the experiment further performed in order to confirm the effect of the fine pattern formation method by 1st Embodiment and 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same or corresponding members (layers, films, etc.) are denoted by the same or corresponding reference numerals, and redundant descriptions are omitted.
(First embodiment)
First, a fine pattern forming method according to the first embodiment of the present invention will be described with reference to FIGS.
The fine pattern forming method according to the present embodiment includes steps S101 to S110 as shown in FIG.

  As shown in FIG. 2A, first, the thin film 102 is formed on the wafer W (S101 in FIG. 1), and the organic film 103 is formed on the thin film 102 (S102). The thin film 102 is formed of, for example, amorphous silicon, polysilicon, or the like. In this embodiment, the thin film 102 is a patterning target film that is patterned later. In another embodiment, the thin film 102 may be used as a mask for etching the wafer W after being patterned. The thickness of the thin film 102 is not specifically limited, For example, it can be 20-200 nm.

  The organic film 103 is later patterned and used as a mask for patterning the thin film 102. In this embodiment, the organic film 103 is an antireflection film (BARC: Bottom Anti-Virus) that prevents multiple reflections of exposure light generated in the resist film 104 when the resist film 104 formed on the organic film 103 is exposed. -Reflecting Coating). The thickness of the organic film 103 is not particularly limited, and may be, for example, 150 to 300 nm.

  Referring to FIG. 2B, a resist film 104 is formed on the organic film 103 (step S103). In the present embodiment, the resist film 104 is formed of an ArF resist. The thickness of the resist film 104 is not particularly limited, and may be, for example, 50 to 200 nm.

  Next, the resist film 104 is patterned by photolithography using a predetermined photomask to form a resist pattern 104a as shown in FIG. 2C (step S104). In this embodiment, the line width LL4 and the space width SS4 of the resist pattern 104a are both 60 nm, for example.

  Next, as shown in FIG. 2D, the resist pattern 104a is trimmed (or slimmed) to obtain a trimmed resist pattern 104b (step S105). As a result of the trimming, the line width LL1 of the resist pattern 104b is, for example, 30 nm narrower than the line width LL4 (eg, 60 nm) of the resist pattern 104a, and the space width SS1 of the resist pattern 104b is the space width SS4 (eg, 60 nm) of the resist pattern 104a. ) Wider, for example 90 nm. Although trimming is not particularly limited, the trimming is performed by exposing the wafer W on which the resist pattern 104a is formed to ozone gas or oxygen radicals obtained by exciting an oxygen-containing gas. The temperature of the wafer W at this time may be room temperature to 100 ° C.

  Referring to FIG. 3E, a silicon oxide film 105 is deposited on the organic film 103 exposed in the space of the resist pattern 104b so as to cover the resist pattern 104b (step S106). The deposition of the silicon oxide film 105 is preferably performed by a molecular layer deposition (MLD) method in a room temperature atmosphere. According to the MLD method, (conformal) deposition reflecting the shape of the underlayer is possible. Therefore, a silicon oxide film 105 having a deposition surface substantially parallel to the side surface can be deposited on the side surface of the resist pattern 104b. If the thickness on the organic film 103 is D, the resist pattern 104b The thickness on the upper and side surfaces of the film is also substantially D. Here, the thickness D is not particularly limited, and can be, for example, 30 nm. The silicon oxide film 105 may be deposited at a predetermined temperature in a temperature range from 5 ° C. to about 100 ° C. instead of a predetermined temperature in a temperature range from 5 ° C. to 35 ° C., for example.

  Next, the wafer W including the silicon oxide film 105 deposited at room temperature is heated to a predetermined temperature, for example, in the range from 150 ° C. to 630 ° C. (while leaving the resist pattern 104b) (step S107). The silicon oxide film 105 deposited at room temperature includes moisture and impurities and has a relatively low density. However, when moisture and impurities are released by heating, the silicon oxide film 105 is densified and contracts. Then, as shown in FIG. 3F, the wafer W on which the silicon oxide film 105 is deposited warps upward in a concave shape.

A tensile stress is generated on the film surface warped in a concave shape as shown by an arrow in FIG. FIG. 4 schematically shows a state after silicon oxide film is formed and subsequently subjected to heat treatment, that is, a state before the side wall portion is formed. Thus, the tensile stress generated in the film after the heat treatment can be obtained by measuring the warpage of the wafer W using, for example, laser light before and after the heating. This measurement will be described later.
As long as the wafer W can be heated in the above temperature range, the heating apparatus used for this heating is not limited, but an example of a suitable apparatus (FIGS. 5 and 6) will also be described later.

  Subsequently, as shown in FIG. 3G, when the silicon oxide film 105 is etched back and the silicon oxide film 105 on the upper surface of the organic film 103 and the resist pattern 104b is removed, the side wall of the silicon oxide is formed on the side surface of the resist pattern 104b. The part 105a remains (step S108). By this etch back, the silicon oxide film 105 covering the surface of the wafer W is removed, so that the tensile stress applied to the film surface is reduced and the warpage of the wafer W is reduced. Further, a force that opens outwardly acts on the side wall portion 105a of the silicon oxide remaining on the side surface of the resist pattern 104b.

The etch back is not particularly limited. For example, a CF-based gas such as CF ₄ , C ₄ F ₈ , CHF ₃ , CH ₃ F, or CH ₂ F ₂ and an inert gas such as Ar gas. Or a gas obtained by adding oxygen to the mixed gas as necessary. Here, for convenience of explanation, a pattern including the resist pattern 104b and the side wall portion 105a is referred to as a third pattern 106. If the line width of the third pattern 106 is LL3 and the space width is SS3,
・ LL3 = LL1 + D × 2
・ SS3 = SS1-D × 2
This relationship holds. In this embodiment,
The line width LL1 of the resist pattern 104b = 30 nm,
The space width SS1 of the resist pattern 104b = 90 nm,
The thickness (width) D of the side wall portion 105a is 30 nm,
Because
The line width LL3 of the third pattern 106 = 90 nm,
The space width SS3 of the third pattern 106 = 30 nm,
It becomes.

  Next, etching using plasma of oxygen, nitrogen, hydrogen, ammonia, or the like is performed, and the resist pattern 104b formed from the resist film 104 is removed while leaving the side wall portion 105a.

Subsequently, when the organic film 103 is etched using the remaining sidewall portion 105a as a mask, an etching mask 107 composed of the sidewall portion 105a and the organic film 103 is formed as shown in FIG. 3H (step S109). . In etching mask 107, lines having width LL2 and spaces having width SS2 are alternately arranged. here,
Line width LL2 = Width D (= 30 nm) of the side wall portion 105a,
Space width SS2 = Line width LL1 of resist pattern 104b = Space width SS3 of third pattern 106 (= 30 nm)
This relationship holds. That is, in the etching mask 107, lines having a width LL2 of 30 nm and spaces having a width SS2 of 30 nm are alternately arranged.

When the thin film 102 is etched using the etching mask 107 as a mask, a desired etching mask is obtained (step S110). For example, etching of the thin film 102 made of amorphous silicon or polysilicon is performed by using a gas such as Cl ₂ , Cl ₂ + HBr, Cl ₂ + O ₂ , CF ₄ + O ₂ , SF ₆ , Cl ₂ + N ₂ , Cl ₂ + HCl, HBr + Cl ₂ + SF _6, or the like. Etc. can be performed using plasma.

  In the fine pattern forming method according to the present embodiment, the silicon oxide film 105 is deposited at room temperature so as to cover the resist pattern 104b in order to form the sidewall portion 105a used as an etching mask. After the silicon oxide film 105 is deposited, the wafer W on which the silicon oxide film 105 is formed is heated to a high temperature (about 150 ° C. to about 630 ° C.), so that two-dimensional tensile stress is applied to the silicon oxide film 105. It becomes. Thereby, even after the resist pattern 104b is removed, the side wall portion 105a is not inclined. That is, even if the resist pattern 104b is used as the basis (base) of the silicon oxide film 105 deposited to form the sidewall portion 105a, the inclination of the sidewall portion 105a can be suppressed.

  In addition, the sidewall of the resist pattern 104b may be inclined at an angle of 90 ° or more with respect to the surface of the organic film 103 which is a base layer. In other words, for example, in FIG. 2D, the resist pattern 104b may have a trapezoidal shape. In some cases, the side wall of the resist pattern 104b is inclined near the surface of the organic film 103 (having a shape with a skirt). In these cases, it is considered that the side wall portion 105a is more easily inclined, but according to the fine pattern forming method according to the present embodiment, the inclination can be suppressed even in this case.

  The silicon oxide film 105 may be deposited in a room temperature CVD apparatus, the wafer W on which the silicon oxide film 105 is deposited may be heated in an annealing furnace, and the silicon oxide film 105 may be etched in an etching apparatus ( In other words, each step may be performed by a separate apparatus), but the deposition (at room temperature) of the silicon oxide film 105 and the subsequent heating may be performed in the same CVD apparatus, and etching may be performed in the etching apparatus. . Alternatively, after the silicon oxide film 105 is deposited in the room temperature CVD apparatus, the subsequent heating and etching may be performed in the same etching apparatus.

  Further, trimming of the resist pattern 104a (formation of the resist pattern 104b), deposition of the silicon oxide film 105, and heating of the wafer W on which the silicon oxide film 105 is deposited may be performed in the same MLD apparatus. Hereinafter, an MLD apparatus capable of such processing will be described.

  FIG. 5 is a longitudinal sectional view schematically showing an MLD apparatus suitable for the fine pattern forming method according to the present embodiment, and FIG. 6 is a transverse sectional view of the MLD apparatus of FIG.

  As shown in FIG. 4, the MLD apparatus 80 has a processing container 1 having a cylindrical shape with a ceiling with a lower end opened, for example, formed of quartz. Above the inside of the processing container 1, a ceiling plate 2 made of quartz is provided on the ceiling. Further, a manifold 3 formed in a cylindrical shape by, for example, stainless steel is connected to a lower end opening of the processing container 1 via a seal member 4 such as an O-ring.

  The manifold 3 serves as a support member that supports the lower end of the processing container 1 and supplies a predetermined gas into the processing container 1 from pipes respectively connected to a plurality of through holes provided on the side surface. A lid 9 made of, for example, stainless steel that opens and closes the lower end opening of the manifold 3 is connected to the lower portion of the manifold 3 via a seal member 12 made of, for example, an O-ring. The lid portion 9 has an opening in the center, and the rotary shaft 10 passes through the opening. A table 8 is attached to the upper end of the rotary shaft 10, and a wafer boat 5 is provided on the table 8 via a quartz heat insulating cylinder 7. The wafer boat 5 has three columns 6 (see FIG. 6), and a large number of wafers W are supported by grooves formed in the columns 6. The wafer boat 5 can also rotate by rotating the rotating shaft 10 around the central axis by a rotating mechanism (not shown).

  The lower end portion of the rotary shaft 10 is attached to an arm 13 that is instructed to be movable up and down by a lifting mechanism (not shown). As the arm 13 moves up and down, the wafer boat 5 is carried into and out of the processing container 1. In addition, a magnetic fluid seal 11 is provided between the rotary shaft 10 and the opening of the lid 9, thereby sealing the processing container 1.

In addition, the MLD apparatus 80 includes an oxygen-containing gas supply mechanism 14 that supplies an oxygen-containing gas, for example, O ₂ gas, into the processing container 1, a Si source gas supply mechanism 15 that supplies an Si source gas into the processing container 1, A purge gas supply mechanism 16 that supplies an inert gas such as N ₂ gas as a purge gas into the processing container 1 is provided.

  The oxygen-containing gas supply mechanism 14 is connected to the oxygen-containing gas supply source 17, the oxygen-containing gas pipe 18 that guides the oxygen-containing gas from the oxygen-containing gas supply source 17, and the oxygen-containing gas pipe 18. And an oxygen-containing gas dispersion nozzle 19 made of a quartz tube that is bent upward and extends vertically. A plurality of gas discharge holes 19a are formed at a predetermined interval in the vertical portion of the oxygen-containing gas dispersion nozzle 19, and the oxygen-containing gas is contained almost uniformly from the gas discharge holes 19a toward the processing container 1 in the horizontal direction. Gas can be discharged.

  The Si source gas supply mechanism 15 is connected to the Si source gas supply source 20, the Si source gas pipe 21 that guides the Si source gas from the Si source gas supply source 20, and the Si source gas pipe 21. And a Si source gas dispersion nozzle 22 made of a quartz tube that is bent upward and extends vertically. In the illustrated example, two Si source gas dispersion nozzles 22 are provided (see FIG. 6), and each Si source gas dispersion nozzle 22 has a plurality of gas discharge holes 22a along a length direction thereof. Are formed with an interval of. Thereby, Si source gas containing organic silicon can be discharged from the gas discharge holes 22a in the processing container 1 in the horizontal direction almost uniformly. Note that there may be only one Si source gas dispersion nozzle 22.

Further, the purge gas supply mechanism 16 includes a purge gas supply source 23, a purge gas pipe 24 that guides the purge gas from the purge gas supply source 23, and a purge gas nozzle 25 that is connected to the purge gas pipe 24 and provided through the side wall of the manifold 3. Have. An inert gas or N ₂ gas can be suitably used as the purge gas.

  The oxygen-containing gas pipe 18, the Si source gas pipe 21, and the purge gas pipe 24 are provided with on-off valves 18a, 21a, 24a and flow rate controllers 18b, 21b, 24b such as a mass flow controller, respectively. As a result, the oxygen-containing gas, the Si source gas, and the purge gas can be supplied while controlling their flow rates.

  A plasma generation mechanism 30 that forms plasma of the oxygen-containing gas is formed on a part of the side wall of the processing vessel 1. The plasma generation mechanism 30 has an opening 31 that is vertically elongated on the side wall of the processing vessel 1 and a plasma partition wall 32 that is airtightly welded to the outer wall of the processing vessel 1 so as to cover the opening 31 from the outside. ing. The plasma partition wall 32 has a concave cross-sectional shape and is elongated vertically, and is made of, for example, quartz. Further, the plasma generation mechanism 30 includes a pair of elongated plasma electrodes 33 disposed on the outer surfaces of both side walls of the plasma partition wall 32 so as to face each other in the vertical direction, and the plasma electrode 33 via a power supply line 34. And a high frequency power supply 35 for supplying high frequency power to the plasma electrode 33. Then, a plasma of oxygen-containing gas can be generated by applying a high frequency voltage of 13.56 MHz, for example, from the high frequency power supply 35 to the plasma electrode 33 to the plasma electrode 33. Note that the frequency of the high-frequency voltage is not limited to 13.56 MHz, and may be another frequency such as 400 kHz.

  By forming the plasma partition wall 32 as described above, a part of the side wall of the processing container 1 is recessed outward in the shape of a recess, and the internal space of the plasma partition wall 32 communicates with the internal space of the processing container 1. Is done. The opening 31 is formed long enough in the vertical direction so as to cover all the wafers W held by the wafer boat 5 in the height direction.

  The oxygen-containing gas dispersion nozzle 19 is bent outward in the radial direction of the processing container 1 while extending upward in the processing container 1, and extends upward along the upright surface of the plasma partition wall 32. Therefore, when a high frequency voltage is applied from the high frequency power source 35 to the plasma electrode 33 and a high frequency electric field is formed between the electrodes 33, the oxygen gas discharged from the gas discharge holes 19a of the oxygen-containing gas dispersion nozzle 19 is turned into plasma. And flows toward the center of the processing container 1.

  An insulating protective cover 36 made of, for example, quartz is attached to the outside of the plasma partition wall 32 so as to cover it. In addition, a refrigerant passage (not shown) is provided in an inner portion of the insulating protective cover 36, and the plasma electrode 33 can be cooled by flowing a cooled nitrogen gas, for example.

  The two Si source gas dispersion nozzles 22 are provided upright at positions sandwiching the opening 31 on the side wall of the processing container 1, and the processing container is provided with a plurality of gas discharge holes 22 a formed in the Si source gas dispersion nozzle 22. The Si source gas can be discharged toward the center direction of 1. The Si source gas may be an aminosilane gas having one or two amino groups in one molecule.

  On the other hand, an exhaust port 37 for exhausting the inside of the processing container 1 is provided at a portion facing the opening 31 of the processing container 1. The exhaust port 37 is formed in an elongated shape by scraping the side wall of the processing container 1 in the vertical direction. An exhaust port cover member 38 having a concave shape in cross section so as to cover the exhaust port 37 is attached to the outside of the processing container 1 by welding. The exhaust port cover member 38 extends upward along the side wall of the processing container 1, and defines a gas outlet 39 above the processing container 1. Then, the inside of the processing container 1 is exhausted through a gas outlet 39 by a vacuum exhaust mechanism including a vacuum pump (not shown).

  A casing-shaped heating unit 40 that heats the processing container 1 and the wafer W inside the processing container 1 is provided so as to surround the outer periphery of the processing container 1. In FIG. 6, the heating unit 40 is omitted.

  Control of each component of the MLD apparatus 80, for example, supply / stop of each gas by opening / closing valves 18a, 21a, 24a, control of gas flow rate by the mass flow controllers 18b, 21b, 24b, and on / off control of the high frequency power supply 35, The control and the like of the heating unit 40 are performed by a controller 50 composed of, for example, a microprocessor (computer). Connected to the controller 50 is a user interface 51 including a keyboard on which a process manager manages command input to manage the MLD apparatus 80, a display for displaying the operation status of the MLD apparatus 80, and the like.

  In addition, the controller 50 causes a control program for realizing various processes executed by the MLD device 80 under the control of the controller 50 and causes each component of the MLD device 80 to execute processes according to processing conditions. A storage unit 52 in which a program, that is, a recipe is stored, is connected. The recipe is stored in a storage medium in the storage unit 52. The storage medium may be a hard disk or a semiconductor memory, or may be a portable medium such as a CD-ROM, DVD, or flash memory. Moreover, you may make it transmit a recipe suitably from another apparatus via a dedicated line, for example.

  If necessary, an arbitrary recipe is called from the storage unit 52 by the instruction from the user interface 51 and is executed by the controller 50, so that a desired process in the MLD apparatus 80 can be performed under the control of the controller 50. Done.

Next, with reference to FIGS. 5 to 7, a procedure for performing the above-described trimming of the resist pattern 104 a, deposition of the silicon oxide film 105, and heating of the wafer W in the MLD apparatus 80 will be described.
(trimming)
For example, after the wafer boat 5 loaded with 50 to 100 wafers W (for example, silicon wafers having a diameter of 300 mm) is loaded into the processing container 1 from the lower end opening, the lower end opening is sealed with the lid 9. After purging the inside of the processing container 1 with N ₂ gas, an O ₂ gas, for example, is supplied from the oxygen-containing gas supply mechanism 14 through the oxygen-containing gas dispersion nozzle 19 into the processing container 1 and a vacuum exhaust mechanism (not shown) through the gas outlet 39. Thus, the inside of the processing container 1 is evacuated, and the inside of the processing container 1 is maintained at a predetermined process pressure (time T1 in FIG. 7). Further, the wafer boat 5 is rotated as necessary.

  Subsequently, high frequency power is supplied from the high frequency power source 35 of the plasma generation mechanism 30 to the plasma electrode 33, and trimming of the resist pattern 104a formed on the wafer W is started (time T2 in FIG. 7). Oxygen plasma is ignited in the plasma partition wall 32 by the supply of the high frequency power. Oxygen radicals or the like excited in the oxygen plasma flow toward the wafer boat 5, whereby the wafer W held on the wafer boat 5 is exposed to the oxygen radicals. Then, the resist pattern 104a exposed on the surface of the wafer W at this time is ashed by oxygen radicals, and the resist pattern 104a is trimmed to obtain a resist pattern 104b.

As an example of this trimming condition, the flow rate of the oxygen-containing gas (O ₂ gas) is 100 to 20000 mL / min (sccm) depending on the number of wafers W mounted on the wafer boat 5, and is within the processing container 1. The pressure is 13.3 to 665 Pa, the frequency of the high frequency power supply 35 is 13.56 MHz, the high frequency power is 5 to 1000 W, and the trimming time is 1 to 7200 seconds. In addition to O ₂ gas, NO gas, N ₂ O gas, H ₂ O gas, and O ₃ gas may be used as the oxygen-containing gas. The temperature of the wafer W during trimming may be room temperature to 300 ° C. However, as described below, since the silicon oxide film 105 to be subsequently formed is deposited at room temperature, it is preferably room temperature. . This is because the time required for temperature adjustment can be saved and the throughput can be increased.
(Deposition of silicon oxide film 105)
Next, the deposition of the silicon oxide film 105 performed in the MLD apparatus 80 following the trimming of the resist pattern 104a will be described with reference to FIGS.
First, after the supply of high-frequency power to the plasma electrode 33 (FIGS. 5 and 6) is stopped (time point T3), the purge gas (N) is supplied from the purge gas supply source 23 of the purge gas supply mechanism 16 through the purge gas pipe 24 and the purge gas nozzle 25. ₂ gas), the O ₂ gas used for trimming is purged from the processing container 1. The purge gas flow rate at this time may be, for example, 0.1 to 10,000 mL / min (sccm), and the purge time may be 1 to 7200 seconds.

Subsequently, while maintaining the inside of the processing container 1 at a predetermined process pressure, the temperature of the wafer W is maintained at room temperature, the wafer boat 5 is rotated, and the film forming process is started (time T4).
As shown in FIG. 7, in the present embodiment, a process SSi in which an Si source gas containing organic silicon is caused to flow into the processing container 1 to adsorb the Si source to the wafer W, and the Si source gas in the processing container 1 is N. A process PSi for purging with _two gases, a process So for oxidizing the Si source gas adsorbed on the wafer W by exposing the wafer W to oxygen radicals generated by exciting the oxygen-containing gas, A cycle having a process Po for purging oxygen radicals or oxygen gas with N ₂ gas is repeated. As a result, the Si source gas adsorbed on the wafer W at the molecular layer level does not react with the oxygen radicals (the wafer temperature is normal temperature) without the Si source gas and oxygen radicals reacting in the gas phase in the processing chamber 1. And the silicon oxide film 105 is formed on the wafer W. In addition, since a single molecular layer (or several molecular layers) of silicon oxide layer can be deposited every cycle, the thickness D of the silicon oxide film 105 can be controlled by the number of cycles.

In the present embodiment, specifically, the Si source gas is BTBAS gas, the flow rate thereof is 10 to 500 mL / min (sccm), and the time required for the step SSi for supplying BTBAS may be 1 to 600 seconds. . The flow rate of O ₂ gas for generating oxygen radicals is 100 to 20000 mL / min (sccm), and the time required for the process So for oxidizing the BTBAS gas adsorbed to the wafer W by oxygen radicals is 1 to 600 seconds. Good. In step So, the frequency of the high frequency power supplied from the high frequency power supply 35 to the plasma electrode 33 may be 13.56 MHz, and the power may be 5 to 1000 W. Furthermore, the pressure in the processing container 1 in the process SSi and the process So may be 13.3 to 665 Pa.

In the purge steps PSi and Po, the flow rate of N ₂ gas as the purge gas is 0.1 to 5000 mL / min (sccm), the required time is 1 to 60 seconds, and the pressure in the processing container 1 is 0.133 to It may be 665 Pa.

When the number of cycles for realizing the thickness D of the silicon oxide film 105 is reached, the deposition of the silicon oxide film 105 is terminated.
(Heating of silicon oxide film 105)
Next, heating of the silicon oxide film 105 performed in the MLD apparatus 80 following the deposition of the silicon oxide film 105 will be described.
After the deposition of the silicon oxide film 105 is completed, the inside of the processing vessel 1 is purged by supplying N ₂ gas from the purge gas supply mechanism through the purge gas nozzle 25 while leaving the wafer W (wafer boat 5) in the processing apparatus 1. At the same time, the pressure in the processing container 1 is maintained at a pressure of, for example, 13.3 to 10.1 × 10 ⁴ Pa. Next, power supply to the heating unit 40 is started (time T5), and the wafer temperature is maintained at a predetermined temperature in a range from 150 ° C. to 630 ° C., for example. When the wafer W is heated for a predetermined period of time ranging from 1 to 3600 seconds after the predetermined temperature is maintained, the silicon oxide film 105 on the wafer W is densified.
Thereafter, the supply of power to the heating unit 40 is stopped, the heating of the silicon oxide film 105 is finished (time T6), and the wafer W is taken out from the processing container 1 to take out the wafer W.

As described above, according to the MLD apparatus 80, trimming of the resist pattern 104a (formation of the resist pattern 104b), deposition of the silicon oxide film 105, and heating of the silicon oxide film 105 can be performed continuously. There is no concern of wafer contamination associated with loading / unloading of wafers W between processing apparatuses. Further, since the time required for loading and unloading the wafer W can be saved, the throughput can be increased.
(Second Embodiment)
Next, a fine pattern forming method according to a second embodiment of the present invention will be described with reference to FIGS. The fine pattern forming method according to the present embodiment includes steps S801 to S810 as shown in FIG.

  As shown in FIG. 9A, first, the thin film 102 is formed on the wafer W (S801 in FIG. 8), and the organic film 103 is formed on the thin film 102 (S802). The thin film 102 is formed of, for example, amorphous silicon, polysilicon, or the like. In this embodiment, the thin film 102 is a patterning target film that is patterned later. In another embodiment, the thin film 102 may be used as a mask for etching the wafer W after being patterned. The thickness of the thin film 102 is not specifically limited, For example, it can be 20-200 nm.

  The organic film 103 is later patterned and used as a mask for patterning the thin film 102. In this embodiment, the organic film 103 is an antireflection film (BARC: Bottom Anti-Virus) that prevents multiple reflections of exposure light generated in the resist film 104 when the resist film 104 formed on the organic film 103 is exposed. -Reflecting Coating). The thickness of the organic film 103 is not particularly limited, and may be, for example, 150 to 300 nm.

  Referring to FIG. 9B, a resist film 104 is formed on the organic film 103 (step S803). In the present embodiment, the resist film 104 is formed of an ArF resist. The thickness of the resist film 104 is not particularly limited, and may be, for example, 50 to 200 nm.

  Next, the resist film 104 is patterned by photolithography using a predetermined photomask to form a resist pattern 104a as shown in FIG. 9C (step S804). In this embodiment, the line width LL4 and the space width SS4 of the resist pattern 104a are both 60 nm, for example.

  Next, as shown in FIG. 9D, the resist pattern 104a is trimmed (or slimmed) to obtain a trimmed resist pattern 104b (step S805). As a result of the trimming, the line width LL1 of the resist pattern 104b is, for example, 30 nm narrower than the line width LL4 (eg, 60 nm) of the resist pattern 104a, and the space width SS1 of the resist pattern 104b is the space width SS4 (eg, 60 nm) of the resist pattern 104a. ) Wider, for example 90 nm. Although trimming is not particularly limited, the trimming is performed by exposing the wafer W on which the resist pattern 104a is formed to ozone gas or oxygen radicals obtained by exciting an oxygen-containing gas. The temperature of the wafer W at this time may be room temperature to 100 ° C.

  Referring to FIG. 10E, a silicon oxide film 105 is deposited on the organic film 103 exposed in the space of the resist pattern 104b so as to cover the resist pattern 104b (step S806). The deposition of the silicon oxide film 105 is preferably performed by a molecular layer deposition (MLD) method in a room temperature atmosphere. According to the MLD method, (conformal) deposition reflecting the shape of the underlayer is possible. Therefore, a silicon oxide film 105 having a deposition surface substantially parallel to the side surface can be deposited on the side surface of the resist pattern 104b. If the thickness on the organic film 103 is D1, the resist pattern 104b The thickness on the upper and side surfaces of the film is also substantially D1. Here, the thickness D1 is not particularly limited, and can be set to, for example, 15 nm.

  Next, as shown in FIG. 10F, a silicon nitride film 110 is deposited on the silicon oxide film 105. The temperature of the wafer W at this time may be, for example, in the range of 300 to 630 ° C., preferably in the range of 300 to 400 ° C., and more preferably about 300 ° C., for example. In the present embodiment, the thickness of the silicon nitride 110 is adjusted so that the sum of the thickness of the silicon nitride 110 and the thickness D1 of the silicon oxide film 105 serving as the base layer becomes the thickness D (30 nm). That is, in the present embodiment, the ratio of the thickness of the silicon oxide film 105 to the thickness of the silicon nitride film 110 is 1: 1.

The MLD apparatus 80 can also be used for depositing the silicon nitride film 110. According to this, the silicon nitride film 110 can also have a conformal shape by molecular layer growth, and the side surface of the side wall portion 105a formed by the subsequent etch back is made to stand upright with respect to the upper surface of the organic film 103. Can do. Further, after the silicon oxide film 105 is deposited at room temperature, the temperature of the wafer W can be adjusted and the silicon nitride film 110 can be continuously deposited without unloading the wafer W (wafer boat 5). In this case, the BTBAS gas used for depositing the silicon oxide film 105 can be used as the Si source gas for depositing silicon nitride, and the nitriding gas for nitriding the BTBAS gas adsorbed on the silicon oxide film 105 on the wafer W As such, ammonia (NH ₃ ), hydrazine (N ₂ H ₂ ), or the like can be used. Further, when using the MLD apparatus 80 shown in FIGS. 5 and 6, it is needless to say that a nitriding gas supply mechanism having the same configuration as the oxygen-containing gas supply mechanism 14 needs to be added.

  Next, as shown in FIG. 10G, when the two-layer film of the silicon oxide film 105 and the silicon nitride film 110 is etched back and the two-layer film on the resist pattern 104b and the organic film 103 is removed, the resist pattern A third pattern 106 including 104b, a side wall portion 105a derived from the silicon oxide film 105, and a side wall portion 110a derived from the silicon nitride film 110 is obtained. As described above, since the total thickness of the silicon oxide film 105 and the silicon nitride film 110 is D, the line width LL3 (or space width SS3) of the third pattern 106 is equal to the third width in the first embodiment. It becomes equal to the line width LL3 (or space width SS3) of the pattern 106.

  Subsequently, when the resist pattern 104b is removed by the same method as described in the first embodiment, and the organic film 103 is etched by the side wall portions 105a and 110a remaining on the organic film 103, FIG. The etching mask 107 is obtained as shown in FIG. For convenience of description, in the following description, the side wall portions 105a and 110a are referred to as the side wall portion 115 without distinction.

  In the fine pattern forming method according to the present embodiment, the side wall 115 used as an etching mask is formed from the silicon oxide film 105 deposited so as to cover the resist pattern 104 and the silicon nitride film 110 deposited thereon. It is formed. Since the silicon nitride film 110 is deposited on the silicon oxide film 105 deposited on the resist pattern 104 at room temperature, the silicon oxide film 105 has a two-dimensional structure due to the difference in thermal expansion coefficient between silicon oxide and silicon nitride. Tensile stress is applied. For this reason, it can suppress that the side wall part 115 inclines. That is, it is possible to use the resist pattern 105a as a foundation (base) for forming the side wall 115.

  Further, since the silicon nitride film 110 is deposited at a high temperature on the silicon oxide film 105 deposited at room temperature, the silicon oxide film 105 is substantially subjected to heat treatment. For this reason, in addition to the tensile stress accompanying the increase in density by heat treatment, the tensile stress due to the silicon nitride film 110 is applied to the silicon oxide film 105. Therefore, even if the resist pattern 104b is removed after the sidewall 115 is formed by etch back, it is possible to more reliably suppress the sidewall 115 from being inclined.

  Subsequently, an experiment conducted to confirm the effect of the embodiment of the present invention and the result thereof will be described. In this experiment, the tensile stress applied to the silicon oxide film was measured using a widely used thin film stress measuring apparatus. First, the outline and measurement principle of the measurement apparatus used for this measurement will be described.

  FIG. 11 is a schematic view of a measuring apparatus used for measuring stress. As illustrated, the measuring apparatus 70 includes a stage S on which the wafer W is placed, a laser element LD that irradiates the wafer W placed on the stage S with laser light L, and a laser light L from the laser element LD. And a detector PD that detects the laser light L reflected from the surface of the wafer W. The measuring device 70 controls the laser element LD, the mirror M, the detector PD, and the like, and also obtains the following reflection angle θ from the position of the mirror M and the detector PD with respect to the wafer W (not shown). ) Is included. The mirror M can be moved so as to irradiate the laser beam L from the vertical direction on almost the entire surface of the wafer W by an instruction signal from the control unit, and the angle with respect to the wafer W can be adjusted. It is configured. Further, the detector PD can be moved along with the movement of the mirror M, and thereby, the reflected laser light L from the wafer W can be detected.

  When the reflected laser beam L from the wafer W is detected by the detector PD while moving the mirror M, the reflection angle θ of the laser beam L at each measurement point can be obtained. Thereby, the average curvature R of the wafer W is obtained. Thus, when the average curvature Rb of the wafer W after the deposition of the silicon oxide film 105 and the average curvature Ra of the wafer W after the heating of the silicon oxide film 105 (or after the deposition of the silicon nitride film 110) are obtained, The stress σ applied to the silicon oxide film 105 can be calculated from the following relational expression (1).

ここで、
Ｅ_ｗ：ウエハＷの弾性率
ν_ｗ：ウエハＷのポアソン比
ｔ_ｗ：ウエハＷの厚さ
ｔ_ｆ：酸化シリコン膜１０５の厚さ
次に、図１２を参照しながら、加熱処理工程（図１のステップＳ１０７、図３（ｆ））によって、常温で堆積した酸化シリコン膜１０５に加わることとなった引っ張り応力の熱処理温度依存性について説明する。

here,
E _w : Elastic modulus of wafer W
ν _w : Poisson's ratio of wafer W
t _w : thickness of wafer W
t _f : Thickness of the silicon oxide film 105 Next, referring to FIG. 12, the heat treatment process (step S107 in FIG. 1, FIG. 3 (f)) adds to the silicon oxide film 105 deposited at room temperature. A description will be given of the dependency of the tensile stress on the heat treatment temperature.

  First, three bare wafers having a diameter of 300 mm were prepared, and a silicon oxide film having a thickness of 17.5 nm was deposited thereon at room temperature. At this time, the deposition conditions such as the supply amount of the silicon source gas were the same for the three wafers. Next, one of these three wafers is heat-treated at about 300 ° C., the other one wafer is heat-treated at about 450 ° C., and the remaining one wafer is heated at about 630 ° C. Processed. In addition, before and after the heat treatment, the warpage of the wafer was measured as described above, and the tensile stress applied to the silicon oxide film was calculated based on the above equation (1). Note that the warpage of the wafer was measured before and after the deposition of the silicon oxide film at room temperature, and the tensile stress generated on the wafer by the deposition of the silicon oxide film was obtained.

  Referring to FIG. 12, it can be seen that almost no tensile stress is applied after the deposition of the silicon oxide film (see the left end column), but a relatively large tensile stress is applied after the heat treatment. Moreover, it can be seen that the tensile stress applied to the silicon oxide film increases as the heat treatment temperature is increased to about 300 ° C., about 450 ° C., and about 630 ° C. This can be attributed to the fact that the temperature of the heat treatment increases and moisture, impurities, and the like in the silicon oxide film deposited at room temperature are released and become more dense.

  Next, the results of experiments conducted to confirm the effects of the first embodiment and the second embodiment of the present invention will be described with reference to FIG. FIG. 13 schematically shows an observation result obtained by observing a sample obtained by the experiment with a scanning microscope (SEM).

  In FIG. 13, the top row indicated by “no heat treatment” is a cross-section after heating the silicon oxide film 105 (thickness 17.5 nm) at room temperature so as to cover the resist pattern 104b from the left, heating. The cross section after etching back the silicon oxide film 105 without performing the process and the cross section after removing the resist pattern 104b are schematically shown. 1 shows a cross section after each step when steps S106, S108, and S109 in FIG. 1 are sequentially performed, and corresponds to a comparative example in which the heat treatment (step S107) is not performed.

  In the center row shown as “with heat treatment”, a silicon oxide film 105 is deposited at room temperature so as to cover the resist pattern 104b from the left, and a cross section after the heat treatment is performed, and the silicon oxide film 105 after the heat treatment is deposited. A cross section after etching back and a cross section after removing the resist pattern 104b are schematically shown. That is, a cross-section after each of steps S107, S108, and S109 when steps S106, S107, S108, and S109 in FIG. 1 are sequentially performed is shown, which corresponds to the first embodiment.

  In the bottom row indicated by “SiN film deposition”, from the left, a silicon oxide film 105 is deposited at room temperature so as to cover the resist pattern 104b, and a silicon nitride film 110 is deposited on the silicon oxide film 105. 3 schematically shows a cross section after etching back the silicon nitride film 110 and the silicon oxide film 105 and a cross section after removing the resist pattern 104b. That is, a cross section after each step when steps S807, S808, and S809 in FIG. 8 are sequentially performed is shown, which corresponds to the second embodiment.

  Referring to FIG. 13, when the heat treatment is not performed, after etch back, the side wall portions 105a on both sides of one resist pattern 104b are inclined to each other, and the resist pattern 104b and the side wall portions 105a on both sides are trapezoidal as a whole. It has a cross section.

  On the other hand, in the case of “with heat treatment”, the inclination of the two side wall portions 105a is suppressed after the etch back. Therefore, after removing the resist pattern 104b between them, the tip of the side wall portion 105a is removed. Although the portion is slightly curved inward, the interval between the two side wall portions 105a is wider than the interval in the case of “no heat treatment”. That is, according to the first embodiment of the present invention, it is understood that the inclination of the side wall portion 105a is suppressed even when the side wall portion 105a is formed on the basis (base) of the resist pattern 104b. Therefore, a pattern having a uniform line width and space width can be formed.

  Further, in the case of “SiN film deposition”, the two side wall portions 105a are almost upright, and no bending is observed at the tip portion. From this, the effect of the second embodiment is understood.

Next, the results of experiments that were further performed to further confirm the effects of the embodiment of the present invention will be described.
FIG. 14 is a graph showing the deposition temperature dependence of the tensile stress applied to the silicon nitride film. In this experiment, the warpage of the wafer was measured before and after the silicon nitride film was deposited on the bare wafer using the above-described measuring apparatus 70 (FIG. 11), and in the deposited silicon nitride film based on the formula (1). The working tensile stress was determined. The film thickness of the silicon nitride film was about 5 nm.

  As shown in this graph, when a silicon nitride film is deposited at a deposition temperature in the range of about 450 ° C. to about 520 ° C., a relatively large tensile stress of about 1.5 GPa acts on the silicon nitride film. I understand that. Further, even when the deposition temperature is about 400 ° C. and 550 ° C., a tensile stress of about 1.2 GPa works. That is, it is expected that the inclination of the side wall 115 is further suppressed by depositing the silicon nitride film in such a temperature range.

  FIG. 15 shows the measurement result of the opening width CD of the side wall 115 after removing the resist pattern 104b (FIG. 10G). Here, Top CD indicates the opening width at the upper end of the opening of the side wall portion 115, and Bottom CD indicates the opening width (the width along the base layer) at the lower end of the opening of the side wall portion 115. In addition, the opening width of the side wall portion 105b after removing the resist pattern 104b in FIG. 3G is also shown (see “silicon oxide film + heat treatment” in FIG. 15). Note that the film thickness of the silicon oxide film 105 (FIG. 10E) deposited at room temperature is about 10 nm, and the film thickness of the silicon nitride film 110 (FIG. 10F) is about 5 nm.

  Referring to FIG. 15, when the silicon nitride film 110 is deposited on the silicon oxide film 105 deposited at room temperature at a deposition temperature of 400 ° C., the opening of the side wall 115 is about 23 nm at both the upper end and the lower end. The value was almost equal. This result can be said to indicate that the side wall 115 is substantially upright without being inclined. On the other hand, when the silicon nitride film 110 was deposited at a deposition temperature of 630 ° C., the opening of the side wall 115 was about 22 nm at the upper end and about 16 nm at the lower end. Even when the deposition temperature is 630 ° C., the inclination of the side wall portion 115 is sufficiently reduced, but a better result is obtained when the deposition temperature is 400 ° C. As shown in FIG. 14, it can be considered that the tensile stress acting on the silicon nitride film deposited at the deposition temperature of 400 ° C. is larger than the tensile stress acting on the silicon nitride film deposited at the deposition temperature of 630 ° C. it can.

  Even when the silicon oxide film 105 is deposited at room temperature without depositing the silicon nitride film 110 and only the heat treatment is performed, the inclination of the side wall portion 105a (FIG. 3H) is sufficiently suppressed. ing. Further, when the silicon nitride film 110 is deposited, the silicon oxide film 105 is substantially heat-treated while the temperature is raised to the deposition temperature.

  Further, the ratio between the thickness of the silicon oxide film 105 and the thickness of the silicon nitride film 110 was examined, and the result is shown in FIG. When room temperature deposition and heat treatment of the silicon oxide film 105 were performed, the opening width of the side wall portion 105a was narrow at the upper end regardless of the film thickness of the silicon oxide film 105. On the other hand, when the silicon nitride film 110 was deposited (deposition temperature 400 ° C.), it was found that the opening width of the side wall 115 depends on the relative film thickness of the silicon nitride film 110 to the silicon oxide film 105. As a result of the experiment, when the thickness of the silicon nitride film 110 is 5 nm and the thickness of the silicon oxide film 105 is 20 nm, the opening width of the side wall 115 is narrow at the upper end, but the silicon nitride film 110 is thin. When the film thickness is 5 nm (when the silicon nitride film 110 is relatively thick), it can be said that the sidewall 115 is upright at both the upper end and the lower end.

  The present invention has been described above with reference to some embodiments and experimental results. However, the present invention is not limited to the above-described embodiments and the like, and various modifications can be made in light of the description of the appended claims. And changes are possible.

  For example, as the Si source gas, an aminosilane gas having two amino groups in one molecule can be used. Such aminosilane gas includes BTBAS gas, bisdiethylaminosilane (BDBAS), and bisdimethylaminosilane (BDMAS) gas. As the Si source gas, an aminosilane gas having 3 or more amino groups in one molecule (for example, trisdimethylaminosilane (3DMAS)) or an aminosilane gas having one amino group in one molecule can be used. is there.

  Further, dichlorosilane (DCS), hexachlorodisilane (HCD), tetraethoxysilane (TEOS), or the like may be used as a source gas for forming a molecular layer of a silicon oxide film or a silicon nitride film.

  The wafer W is not limited to a semiconductor bare wafer, and may be a semiconductor wafer on which various conductive patterns, insulating layers, and the like are formed in the process of manufacturing semiconductor elements and integrated circuit patterns.

  In addition, the line width and the space width described above are merely examples, and may be appropriately determined according to a semiconductor device or an integrated circuit manufactured in or on the wafer W by the fine pattern forming method according to the embodiment of the present invention. Of course, the pattern may be determined appropriately.

  W ... wafer, 102 ... thin film, 103 ... organic film (antireflection film), 104 ... resist film, 104a, 104b ... resist pattern, 105 ... silicon oxide film, 105a. .. Side wall portion 107... Etching mask 110... Silicon nitride film 80.

Claims (3)

An organic film forming step of forming an organic film on the etching target layer formed on the substrate;
Forming a resist film on the organic film, and patterning the resist film; and
A first deposition step of depositing a silicon oxide film at room temperature so as to cover the organic film exposed from the patterned resist film and the patterned resist film;
A second deposition step of depositing a silicon nitride film on the silicon oxide film at a temperature in the range of 300 to 550 ° C. to generate a tensile stress in the silicon oxide film ;
A first etching step of etching the silicon oxide film and the silicon nitride film so that the silicon oxide film and the silicon nitride film remain on the sidewall of the patterned resist film;
And a removing step of removing the patterned resist film. After said removing step, the using the silicon oxide film and the silicon nitride film remains on the organic film, further comprising a third etching step of etching the etching target layer, a fine pattern according to claim 1 Forming method. 3. The fine pattern forming method according to claim 2 , further comprising a second substrate etching step of etching the substrate using the etching target layer etched in the third etching step as an etching mask.

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