JP6832088B2 - Method of Integrating Halide-Containing ALD Membrane on Sensitive Material - Google Patents

Description

Various semiconductor devices are processed to include a barrier layer. The barrier layer may be provided to protect the material in the device, eg, to prevent damage resulting from exposure to the atmosphere and / or exposure to other layers or treatments during manufacturing. Such a barrier layer can delay or prevent the deterioration of the semiconductor device.

Various embodiments herein relate to methods and devices for depositing a double barrier layer on an in-process semi-conductor device. The double barrier layer typically comprises at least two sublayers. The first sublayer may protect the underlying material from damage associated with exposure to halides or other harmful chemicals used to deposit the second sublayer. The second sublayer can protect the underlying material from oxidation. This double layer approach helps ensure that the underlying material is properly protected during manufacturing.

In one aspect of the disclosed embodiments, a method of depositing a double barrier layer on a semiconductor device in the process of manufacture is provided, the method of which is:
(A) A step of preparing a substrate containing a first halide-sensitive material layer, wherein the first halide-sensitive material layer is at least partially exposed when prepared in step (a). With the process;
(B) A thin-film deposition process for depositing a double barrier layer.
(I) A step of depositing the first sublayer of the double barrier layer on the substrate, wherein the first sublayer contains at least about 40% by weight of carbon and is the first halide-sensitive material layer. The process and the process, which is deposited on the exposed part,
(Ii) A step of depositing a second sublayer of the double barrier layer on the first sublayer of the double barrier layer, wherein the second sublayer of the double barrier layer contains silicon nitride. It is vapor-deposited using a halide-containing chemical, and during the deposition of the second sub-layer of the double-barrier layer, the first sub-layer of the double-barrier layer contains a halide-containing first halide-sensitive material layer. Protecting from chemicals, processes and
It comprises a vapor deposition process performed by.

The method may be performed in the context of forming a phase-change random access memory (PCRAM) device in some examples. In certain embodiments, the first halide sensitive material layer comprises a chalcogenide material. The chalcogenide material may be sandwiched between carbon layers.

In these or other embodiments, the first sublayer of the double barrier layer comprises amorphous carbon deposited by chemical vapor deposition. In some other embodiments, the first sublayer of the double barrier layer comprises a parylene material deposited by a process involving thermal decomposition and polymerization. An example of a parylene material is parylene AF-4.

Various techniques may be used to deposit a second sublayer of the double barrier layer. In one example, steps (b) and (ii) include a step of depositing a second sublayer of the double barrier layer in an atomic layer deposition process. In another example, steps (b) and (ii) include the step of depositing a second sublayer of the double barrier layer by chemical vapor deposition. In a particular example, the substrate comprises a second halide sensitive material layer located below the first halide sensitive material layer, and the method further:
( C ) After the steps (b) and (ii), a part of the second halide-sensitive material layer is exposed, but the first halide-sensitive material layer is not exposed, and the first halide-sensitive material layer is exposed. With the step of etching the substrate so that is at least partially covered by the double barrier layer;
( D ) A step of depositing a second double barrier layer on a substrate.
(I) A step of depositing a second sublayer of the double barrier layer on a substrate, wherein the first sublayer of the second double barrier layer contains at least about 40% by weight of carbon and is the first. The step of depositing on the exposed part of the halide-sensitive material layer of No. 2 and
(Ii) A step of depositing a second sublayer of the second double barrier layer on the first sublayer of the second double barrier layer, which is a second step of the second double barrier layer. The sub-layer contains silicon nitride and is vapor-deposited with a halide-containing chemical in the atomic layer deposition process, and during the deposition of the second sub-layer of the second double-barrier layer, the second double-barrier layer. The first sublayer protects the second halide-sensitive material layer from halide-containing chemicals.
It comprises a process performed by.

In some embodiments, the first sublayer of the double barrier layer may be deposited to a thickness of about 15-100 Å and the second sublayer of the double barrier layer may be deposited to a thickness of at least about 20 Å. May be done.

Halide-containing chemicals may contain chlorine in some examples. For example, the halide-containing chemical may include chlorosilane. In one example, chlorosilane is dichlorosilane. Dichlorosilane may be used in combination with a nitrogen-containing reactant. An example of a nitrogen-containing reactant is ammonia.

In certain embodiments, the first sublayer of the dual barrier layer is formed by plasma chemical vapor deposition, which involves exposing the substrate to plasma generated using a single RF frequency. The RF frequency used to generate the plasma may be a radio frequency (HF) RF frequency. The first and second sublayers may be deposited in the same reaction chamber or in different reaction chambers. In one embodiment, the first sublayer of the double barrier layer is deposited in the reaction chamber and the second sublayer of the double barrier layer is deposited in the same reaction chamber. In another embodiment, the first sublayer of the double barrier layer is deposited in the first reaction chamber and the second sublayer of the double barrier layer is deposited in the second reaction chamber. Both the first and second reaction chambers are provided on a multi-chamber tool. In this case, the method may further comprise the step of moving the substrate from the first reaction chamber to the second reaction chamber under vacuum conditions.

In many cases, the first and second sublayers of the double barrier layer are conformally deposited. In some cases, for each of the first and second sublayers, the thinnest part of the sublayer is at least about 60% of the thickest part of the sublayer.

In another aspect of the disclosed embodiments, an apparatus is provided for depositing a double barrier layer onto a semiconductor device in the process of being manufactured, wherein the apparatus is:
One or more reaction chambers, at least one of which is configured to deposit a first sublayer of the double barrier layer, and at least one of the chambers is a double barrier layer. The reaction chamber is configured to deposit a second sublayer of the above, and the reaction chamber includes an inlet for supplying the treatment gas and an outlet for removing the treatment gas and by-products;
(I) A step of depositing the first sublayer of the double barrier layer on the substrate, wherein the first sublayer contains at least about 40% by weight of carbon and is the first halide-sensitive material layer. The process of depositing on the exposed part and
(Ii) A step of depositing a second sublayer of the double barrier layer on the first sublayer of the double barrier layer, wherein the second sublayer of the double barrier layer contains silicon nitride. It is vapor-deposited using a halide-containing chemical, and during the deposition of the second sub-layer of the double-barrier layer, the first sub-layer of the double-barrier layer contains a halide-containing first halide-sensitive material layer. Protecting from chemicals, processes and
It comprises a controller configured to deposit a double barrier layer.

In one example, the reaction chamber configured to deposit the first sublayer of the double barrier layer is the same as the reaction chamber configured to deposit the second sublayer of the double barrier layer. In this case, the apparatus is further configured to deposit a first reaction chamber configured to deposit a first sublayer of the double barrier layer and a second sublayer of the double barrier layer. A vacuum transfer chamber may be provided for moving the substrate under vacuum conditions to and from the second reaction chamber.

In a further aspect of the disclosed embodiments, a method of depositing a double barrier layer on a substrate having recessed features is provided, the method of which is:
(I) A step of depositing a first sublayer of a double barrier layer on a substrate, wherein the first sublayer of the double barrier layer contains amorphous carbon or a carbon-containing polymer and is at least about 40. A process that contains% by weight of carbon and is co-deposited to line the recessed features,
(Ii) A step of depositing a second sublayer of the double barrier layer on the first sublayer of the double barrier layer, wherein the second sublayer of the double barrier layer contains silicon nitride. It is co-deposited using a halide-containing chemical, and during the deposition of the second sublayer of the double barrier layer, the first sublayer of the double barrier layer becomes the first sub of the double barrier layer. The process of protecting the material underneath the layer from halide-containing chemicals,
To be equipped.

These features and other features will be described below with reference to the relevant drawings.

A cross-sectional view showing a device in the process of being manufactured in the context of forming a phase-change random access memory (PCRAM) device. A cross-sectional view showing a device in the process of being manufactured in the context of forming a phase-change random access memory (PCRAM) device. A cross-sectional view showing a device in the process of being manufactured in the context of forming a phase-change random access memory (PCRAM) device. A cross-sectional view showing a device being manufactured in the context of forming a phase-change random access memory (PCRAM) device. A cross-sectional view showing a device in the process of being manufactured in the context of forming a phase-change random access memory (PCRAM) device.

FIG. 6 is a cross-sectional view showing a device being manufactured in the context of forming a PCRAM according to a particular embodiment. FIG. 6 is a cross-sectional view showing a device being manufactured in the context of forming a PCRAM according to a particular embodiment. FIG. 6 is a cross-sectional view showing a device being manufactured in the context of forming a PCRAM according to a particular embodiment. FIG. 6 is a cross-sectional view showing a device being manufactured in the context of forming a PCRAM according to a particular embodiment. FIG. 6 is a cross-sectional view showing a device being manufactured in the context of forming a PCRAM according to a particular embodiment. FIG. 6 is a cross-sectional view showing a device being manufactured in the context of forming a PCRAM according to a particular embodiment.

A flowchart showing a method of depositing a high carbon-containing material that can be used as a first sublayer of a double barrier layer according to various embodiments.

A flowchart showing a method of depositing a parylene film that can be used as a first sublayer of a double barrier layer according to various embodiments.

FIG. 6 is a simplified diagram showing an apparatus that can be used to form a parylene film as described in connection with FIG. 3B.

FIG. 6 shows a reaction mechanism that can be used to form a parylene AF-4 membrane as described in connection with FIG. 3B.

The flowchart which shows the method of forming a film (for example, the first sublayer of a double barrier layer) by a molecular layer deposition method.

FIG. 5 is a flowchart showing a method of vapor-depositing a film (for example, a second sub-layer of a double barrier layer) by an atomic layer deposition method.

The flowchart which shows the method of vapor-depositing a film (for example, the second sub-layer of a double barrier layer) by a chemical vapor deposition method.

Schematic representation of a single station reaction chamber available to perform the various vapor deposition methods described herein.

Schematic representation of a multi-station reaction chamber available to perform the various vapor deposition methods described herein.

Schematic showing a cluster tool having multiple reaction chambers according to a particular embodiment herein.

A table showing leakage current and breakdown voltage for the different membranes tested.

Graph showing the results of the HCl bubble test for the different types of membranes tested.

In the present application, the terms "semiconductor wafer", "wafer", "substrate", and "semiconductor substrate" are used interchangeably. It is also mentioned as "semiconductor device in the process of manufacturing". Those skilled in the art will appreciate that the term "semiconductor device in the process of manufacturing" can refer to a semiconductor device wafer between any of the many stages of manufacturing. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the embodiment is performed on a workpiece that is a semiconductor wafer. However, the embodiments are not limited to them. Workpieces may have a variety of shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optics, micromechanical elements, and the like. Similarly, the following description primarily refers to phase-change random access memory (PCRAM) devices, but embodiments are not limited thereto. Other devices, including any off-the-shelf device that is susceptible to damage from halide-containing chemicals, may also have the advantages of the disclosed embodiments.

In the following description, a number of specific details are provided to facilitate a complete understanding of the presented embodiments. The disclosed embodiments can be implemented without some or all of these specific details. Further, in order to avoid unnecessarily obscuring the disclosed embodiments, detailed description of well-known processing operations has been omitted. Although the disclosed embodiments have been described in the context of specific embodiments, it should be understood that there is no intent to limit the disclosed embodiments.

Many semiconductor devices contain materials that are sensitive to oxidation. Such materials quickly deteriorate when exposed to oxygen-containing or water vapor-containing air. To prevent such deterioration, these materials are often coated with a barrier layer. The barrier layer blocks the passage of oxidants so that the underlying oxidation sensitive material is not oxidized.

One of the materials that has been used as a barrier layer is silicon nitride (SiN). As used herein, the term silicon nitride includes the doped and undoped forms of silicon nitride, as well as the constant and non-constant ratio forms of silicon nitride. Understood. For example, the membrane may be a silicon nitride film, an oxygen nitride silicon film, or the like in some examples. In various contexts, SiN is desirable as a barrier layer material because it is non-conductive and functions very well to block the passage of oxidants. Further, SiN can be deposited using an atomic layer deposition (ALD) reaction such as a plasma atomic layer deposition reaction (PEALD). Therefore, it can be deposited with high conformality within features with a high aspect ratio (eg, features with a depth / width aspect ratio of at least about 10). In various embodiments of the specification performed in the context of forming a phase-change random access memory (PCRAM) device, recessed features can have an aspect ratio of at least about 10. In most cases, the recess feature has an aspect ratio of about 15. An example of the critical dimension (eg, width) of such a feature may be about 300 Å (eg, between about 200 and 400 Å).

However, SiN (particularly ALD-deposited SiN) is usually deposited using a halide-containing chemical. In many cases, SiN is deposited using _{dichlorosilane (DCS, H 2} SiCl _{2) as one of the reactants.} For example, DCS can _{react with ammonia (NH 3} ) to form a layer of SiN. Unfortunately, this halide-containing chemical can attack and degrade certain halide-sensitive materials present in semiconductor devices in the process of manufacture. As used herein, a halide sensitive material is a material that deteriorates (eg, undergoes an undesired reaction) when exposed to a halide-containing chemical.

The chalcogenide material is an example of a group of materials that are vulnerable to halides. Calcogenide materials (eg, chalcogenide glass, eg, GeSbTe and AgInSbTe) can be utilized in the manufacture of phase change memory devices. When the SiN barrier layer is deposited on the chalcogenide material using the chemicals described above, _{the HCl formed from the reaction between DCS and NH 3} can attack and degrade the exposed chalcogenide material.

1A-1E are cross-sectional views showing PCRAM semiconductor devices in the middle of manufacturing during various manufacturing processes. As shown in FIG. 1A, a stack of materials is deposited on top of the lower layer, the lower layer of this example being the oxide layer 101. The stack of materials in this example includes a metal layer 102 (eg, tungsten or another metal), a first carbon layer 103, a first chalcogenide layer 104, a second carbon layer 105, a second chalcogenide layer 106, a first. The carbon layer 107 of 3 and the nitride cap layer 108 are provided. The metal layer 102 functions as an electrical contact layer. Calcogenide layers 104 and 106 are layers that undergo a phase change during device operation. Carbon layers 103, 105, and 107 provide electrical pathways used to phase change the chalcogenide layers 104 and 106 while preventing the chalcogenide layers 104 and 106 from interfering with each other.

During the process, the recessed features are partially etched into the stack, as shown in FIG. 1B. This etching process may etch a part of the stack, such as penetrating the second chalcogenide layer 106. Next, as shown in FIG. 1C, the first silicon nitride barrier layer 109 is vapor-deposited. The first silicon nitride barrier layer 109 can help protect the second chalcogenide layer 106 as the stack is further etched. For example, as shown in FIG. 1D, the process continues the second etching process to further etch the stack to the oxide layer 101. If the first silicon nitride barrier layer 109 was not deposited, etching by-products from one chalcogenide layer (eg, chalcogenide layer 104) would re-deposit on the other chalcogenide layer (eg, chalcogenide layer 106). Can cause contamination / defects. After the stack has been etched as shown in FIG. 1D, the second silicon nitride barrier layer 110 may be deposited as shown in FIG. 1E. An insulating film (not shown) may be deposited in the etched recesses. The insulating film may be an oxide (silicon oxide, spin-on glass, etc.).

The first and second SiN barrier layers 109 and 110 help protect the underlying layer from contamination and oxidation. In particular, the SiN barrier layer provides very good protection against oxidation during the subsequent integration process, for example when the recesses are filled with an oxide material. In order to function as a good barrier layer in the context of PCRAM, the barrier layer material must be (a) deposited at low temperatures (eg, about 250 ° C or less) and (b) relatively uniform within the high aspect ratio features. To exhibit good step coverage / symmetry to be deposited on, (c) to provide good resistance to oxidation, (d) to minimize secondary contamination of the chalcogenide layer, (e). It is advantageous to provide good control of the critical dimension of the recessed features, (f) to be non-conductive, and (g) to provide good adhesion to the underlying layer. In general, the SiN barrier layer exhibits these properties. However, the first and / or second silicon nitride barrier layers 109 and 110 are typically vapor-deposited with a halide-containing chemical, as described above. Often, the halide is chlorine (eg, supplied as dichlorosilane (also referred to as DCS)), but other halides may be used in some examples. The halide reacts with other reactants (eg ammonia) to form species (eg HCl) that unnecessarily attack and degrade the chalcogenide layers 104 and 106.

Double Barrier Layer In various embodiments herein, the barrier layer may be deposited as two sublayers. The two sublayers may be collectively referred to as a bilayer. The first sublayer of the barrier layer can (a) deposit the first sublayer without attacking / degrading the layers in the stack, and (b) the first sublayer is the layer in the stack (particularly). It may be optimized to protect the first and / or second chalcogenide layers 104 and 106). The second sublayer of the barrier layer may be optimized to provide a high quality barrier layer against oxidation. In this way, the stack material can be protected from degradation due to both oxidation and the chemicals used to deposit the oxidation barrier (eg SiN).

2A-2E are cross-sectional views showing a PCRAM structure in the middle of manufacturing during various manufacturing steps according to a particular embodiment. FIG. 2F is an enlarged view showing a part of FIG. 2E. In this embodiment, a stack of materials is deposited on top of the lower layer, the lower layer of this example being the oxide layer 101. The stack comprises a metal layer 102 (eg, tungsten or another metal), a first carbon layer 103, a first carbonide layer 104, a second carbon layer 105, a second carbonide layer 106, a third carbon layer 107. , And a nitride cap layer 108. The stack of FIG. 2A is the same as that shown in FIG. 1A. As shown in FIG. 2B, the stack is partially etched during the initial etching operation. The first barrier layer may then be deposited as shown in FIG. 2C. Here, the first barrier layer includes two sub-layers 109a and 109b. The first sublayer 109a of the first barrier layer may be a first material (eg, a carbon material such as amorphous carbon, parylene, or other non-conductive / high carbon-containing material). The second sublayer 109b of the first barrier layer is a second material (eg, SiN, or another material that provides good protection against oxidation and good adhesion to the first sublayer). It may be there.

The recessed features may then be further etched, as shown in FIG. 2D. After the stack has been etched to expose the underlying oxide layer 101, a second barrier layer may be deposited as shown in FIG. 2E. Like the first barrier layer, the second barrier layer may be composed of two sublayers. The first sublayer 110a of the second barrier layer may be a first material (eg, a carbon material such as amorphous carbon, parylene, or other non-conductive / high carbon-containing material). The second sublayer 110b of the second barrier layer is a second material (eg, SiN, or another material that provides good protection against oxidation and good adhesion to the first sublayer). It may be there. The first sub-layer 109a of the first barrier layer may be made of the same or different material as the first sub-layer 110a of the second barrier layer. Similarly, the second sublayer 109b of the first barrier layer may be made of the same or different material as the second sublayer 110b of the second barrier layer.

A dotted box is shown in the upper corner of FIG. 2E. This part of the figure is shown in the enlarged view of FIG. 2F. In the examples shown in FIGS. 2A-2F, each of the first and second barrier layers is implemented as two sublayers. The two sublayers may be referred to as the double layer. In some embodiments, only one barrier layer may be implemented as two sublayers. Referring to FIG. 1E, in some embodiments, the first barrier layer 109 may be a single layer and the second barrier layer 110 may be a bilayer. In other embodiments, the first barrier layer 109 may be a bilayer and the second barrier layer 110 may be a single layer. Barrier layers processed to contain ALD-deposited SiN utilize the dual layer technology disclosed herein, especially when the barrier layer is deposited on a material that is sensitive to halide-containing chemicals. It can be particularly suitable for processing. However, the techniques described herein are not limited to this context.

1A-1E and 2A-2F are provided in the context of forming a PCRAM device, but embodiments are not limited thereto. The techniques described herein are useful in many different contexts. In general, embodiments are useful in applications where it is desirable to protect the underlayer from damage from exposure to halide-containing chemicals (eg, chlorine-containing chemicals that lead to exposure of the substrate to harmful species such as HCl). is there. In addition to the chalcogenide materials described above, other examples of halide sensitive materials include, but are not limited to, copper and aluminum films. The first sublayer of the bilayer provides protection against damage from halide-containing chemicals (eg, HCl). This first sublayer is sometimes referred to as a halide blocking layer, or more specifically, an HCl blocking layer. The second sublayer of the bilayer provides protection against oxidation so that the underlying material is not oxidized. Both of these sublayers provide high quality / versatile protection to the underlayer.

Many of the embodiments herein are presented in the context of a barrier layer that includes two sublayers implemented as a double layer, but in some examples additional sublayers may be present. I want to be understood. Sublayers of additional barrier layers may be provided between the two sublayers described herein, or outside such layers (eg, below or above both sublayers described herein). It may be provided in. The two sublayers described herein are often in direct physical contact with each other, but not necessarily.

Materials for Sublayers in the Double Barrier Layer As mentioned above, the sublayers described herein are provided for different purposes. To achieve these different objectives, the sublayers may be made of different materials. Typically, the first sublayer (which can be deposited directly on a material that is vulnerable to damage from HCl or other halide-containing chemicals) is of high quality against HCl and / or other harmful halide-containing chemicals. Formed from a material that provides a barrier. The second sublayer, which can be deposited on top of the first sublayer, is typically formed of a material that provides a high quality barrier to oxidation. The materials selected for the first and / or second sublayers have high quality step coverage and conformability for coating trenches with low deposition temperatures (eg, about 250 ° C. or less) and high aspect ratios. Can indicate certain additional qualities, such as. With respect to conformality, the thinnest part of the sublayer may be at least about 60% of the thickness of the thickest part of the sublayer, often measured on the sidewalls of the recessed features. The first and / or second sublayers are typically formed of an electrically insulating material.

For the first sublayer, materials with high carbon content have been shown to provide a high quality barrier to halides such as HCl. Therefore, in many embodiments, the first sublayer of the barrier layer is formed of a material with a high carbon content. In some examples, the material of the first barrier layer may have at least about 40% by weight carbon (eg, at least about 99% by weight carbon). A group of materials that may be suitable for use as a first sublayer is an ashable hardmask (AHM) material. Examples of AHM materials include amorphous carbon materials that are predominantly composed of carbon, the remaining component is usually hydrogen, and in some cases contains trace amounts of other elements such as nitrogen.

In some other examples, the material of the first sublayer may be a parylene material. Parylenes are various organic polymers that are typically deposited by thin-film deposition techniques. There are many different types of parylene that can be useful as materials for the first sublayer, such as parylene AF-4 and parylene N, but not limited to these. Other high carbon materials that can be utilized in the first sublayer in various embodiments are polynaphthalene-N, polynaphthalene-F, fluorinated amorphous carbon, fluorinated hydrocarbons, Teflon-AF (Teflon is registered). Trademarks) and, but are not limited to, thermally vapor-deposited fluorocarbons (eg, CVD fluorocarbons). High carbon-containing membranes such as those mentioned herein have been shown to provide a high quality barrier against damaging halides (such as HCl).

In certain embodiments, the first sublayer may be an organic polymer or an organometallic polymer material. Various polymer materials have been shown to provide high quality HCl barriers. In many examples, the first sublayer is deposited without the use of halide-containing chemicals. Similarly, the first sublayer can be deposited using reactants / conditions that do not oxidize the underlying material. In various embodiments, the first sublayer can be deposited on either the oxide plasma or the hydrogen-based plasma without exposing the substrate.

The material of the second sublayer preferably provides good protection against oxidation of the underlying material. One of the materials known to provide high quality oxidative protection is SiN. In addition, SiN is useful because it can be deposited conformally at a relatively low temperature. SiN is particularly suitable as a second sublayer material as it can be deposited with a halide-containing chemical that can damage the material beneath the first sublayer.

Many of the embodiments herein are provided in the context of a dual barrier layer with SiN as the second sublayer, but this is not always the case. The material of the second sublayer may be any non-conductive material that provides good protection against oxidation. Often, the second sublayer is a material that is deposited with a halide-containing (eg, chlorine-containing) chemical. In various examples, the second sublayer can be deposited with a chemical that leads to exposure of the substrate to damaging chemicals (such as HCl). In the case of SiN (eg, in many cases ALD-deposited SiN), the deposition of SiN material can involve exposure of the substrate to dichlorosilane and ammonia, which can react with each other to form HCl. Further examples of materials available for the second sublayer include, but are not limited to, SiCN and SiC. These materials can be deposited with chemicals (eg, hydrogen plasma) that damage the material beneath the first sublayer. However, the first sublayer can protect the underlying material during the deposition of the second sublayer.

Formation of First Sublayer in Double Barrier Layer The first sublayer in the double barrier layer is typically a high carbon material as described above. The first sublayer is generally deposited using a thin-film deposition technique. Several different methods are described.

Many of the process parameters listed herein correspond to Vector ™ modules (manufactured by Lam Research, Fremont, Calif.) That have four stations for depositing material on 300 mm wafers. 5 to 7 (discussed later) provide an example of a suitable device for performing the method shown in FIG. 3A. Those skilled in the art will readily appreciate that process parameters may be increased or decreased based on the volume of the deposition chamber, wafer size, and other factors. For example, the power output of an LF generator and an HF generator is typically directly proportional to the vapor deposition surface area of the wafer. The power used for a 300 mm wafer is generally 2.25 higher than the power used for a 200 mm wafer. Similarly, the flow rate depends on the empty capacity of the vapor deposition chamber, which is 195 L for each of the four Novellus Vector ™ vapor deposition chambers.

FIG. 3A shows the steps in a general processing flow for forming a high carbon-containing material according to a particular embodiment. The high carbon-containing material may be a material generally used as an ashable hard mask material. This high carbon-containing material can form a first sublayer of the double barrier layer, as disclosed herein. The ashable hard mask material is a carbon-based film generally used as an etching mask. In various embodiments, the hardmask material is an amorphous carbon-based film. In the embodiment of the figure, method 300 begins with the step of preparing a semiconductor substrate in the vapor deposition chamber (block 302). For example, the semiconductor substrate may be a 300 mm semiconductor wafer suitable for the Vector ™ module. The precursor treatment gas is then introduced into the chamber (block 304). In certain examples, the precursor treatment gas comprises at least acetylene. Other examples of precursor gases include methane, propylene, and other hydrocarbons (eg, C _{x Hy} , but 2 <x <4 and 2 <y <10).

Depending on the deposition chamber size and other process parameters, the flow rate of acetylene may be from about 3,000 to 10,000 sccm during the deposition process. In one embodiment, the flow rate of acetylene may be from about 5,000 to 8,000 sccm. As mentioned above, the treatment gas may include other carbon-containing precursors such as methane, ethylene, propylene, butane, cyclohexane, benzene, and toluene.

The carrier gas may be used to dilute the precursor. The transport gas may include any suitable transport gas used in semiconductor processing, such as helium, argon, nitrogen, hydrogen, or a combination thereof. The total flow rate of the carrier gas may depend on the deposition chamber size and other process parameters and may range from about 500 to 10,000 sccm. In one specific embodiment, nitrogen and helium are used as transport gases with corresponding flow ranges of about 500-5,000 sccm and about 300-3,000 sccm.

In the embodiment of the figure, the high carbon-containing material is then deposited onto the semiconductor substrate by plasma chemical vapor deposition (PECVD) or other vapor deposition process (block 306). For example, in a single frequency plasma generation process, the high frequency generator may be between about 1000 and 3000 W at about 2-60 MHz (eg, about 7 to 13.56 MHz in some examples) during the vapor deposition process. Power may be supplied between about 1500 and 2500 W (in one example, about 2000 W). This power is supplied to four stations / boards. This power can correspond to a power density between ^{about 3500 to 11000 W / m 2} (taking into account the set power and substrate area). This can correspond to a received power density between ^{about 500-4400 W / m 2} (taking into account the power efficiency / supply to the substrate). An example of the frequency is 13.56 MHz. Power efficiency is typically between about 70-80% with respect to set power. In one example, about 70-80% of the input power is transferred to the showerhead / pedestal by ionic impact, while the rest is consumed to maintain the plasma and heat the gas. The vapor deposition process may be performed when the temperature of the substrate is between about 50 and 400 ° C. The pressure in the deposition chamber may be maintained at about 2-8 Torr. Table 1 summarizes examples of treatment conditions for vapor deposition of high carbon-containing materials. The deposition is continued until a film of the desired thickness is deposited. According to various embodiments, the first sublayer may be deposited to a thickness between about 15-100 Å (eg, between about 20-50 Å). Examples of deposition rates may be about 20 Å / min in some cases.

All of the above treatment conditions are shown in Table 1 as long as the resulting membrane is a non-conductive high carbon membrane that provides a high quality barrier to HCl (or other harmful halide-containing chemicals). It may be changed to the outside of the range example shown. Examples of flow rates are shown in Table 1, but in certain embodiments, the methods of the invention are used in low flow rate treatments (eg, acetylene flow rates of 100-1000 sccm or less). The use of low vapor pressure stabilizers is advantageous because these low flow dilutions can be particularly detrimental to reproducibility. Methods for forming high carbon-containing washable hardmask materials are further described in the following patents and patent applications, each of which is incorporated herein by reference in its entirety: US Pat. No. 7,820. , 556; U.S. Patent No. 7,955,990; U.S. Patent Application No. 14 / 270,001 filed May 5, 2014 "SULFUR DOPED CARBON HARD MASKS"; and filed April 8, 2014. US Patent Application No. 14 / 248,046 "HIGH SELECTIVITY AND LOW STRESS CARBON HARDMASK BY PULSED LOW FREQUENCY RF POWER".

FIG. 3B shows a flow chart of a method of forming a parylene film that can be used as the first sublayer of the double barrier layer. The method is described in the context of forming parylene AF-4, but other types of parylene membranes may be used in some examples. FIG. 3C is a simplified diagram of an apparatus that can be used to perform the method shown in FIG. 3B. FIG. 3D shows the reactions that can be used to form the parylene AF-4 membrane using the method shown in FIG. 3B and the apparatus shown in FIG. 3C. The method of FIG. 3B will be described with reference to FIGS. 3C and 3D.

As shown in FIG. 3B, method 310 begins by feeding substrate 326 to reaction chamber 322 (block 312). Method 310 sublimates a dimer (eg, solid dimer AF-4) to form a gas phase dimer (eg, gas dimer AF-4), and the gas phase in the thermal decomposer 320. Proceed to the step of thermally decomposing the dimer to form a gas phase monomer (block 314). The pyrolysis step involves thermochemically decomposing the organic material at high temperatures in the absence of oxygen (and / or any halogen). An example of a pyrolysis temperature may be above about 400 ° C. An example of a pyrolysis pressure may be between about 10 m toll and 100 toll. The gas phase monomer is then fed to the reaction chamber 322 and polymerized to form a layer of polymer film (eg, parylene AF-4 film) on the substrate (eg, on the sidewalls of the recessed features) (block 316). ..

The reaction chamber 322 may house the substrate 326 on the substrate support pedestal 324. The substrate support pedestal may maintain the substrate at a particular temperature (eg, above about 400 ° C.). The reaction chamber may be maintained at a pressure between about 10 m toll and 100 toll. Prior to the formation of the polymer film, the substrate 326 may have exposed materials that are sensitive to HCl or other harmful halide-containing chemicals (eg, chalcogenide layer, copper layer, aluminum layer, etc.). After the formation of the parylene AF-4 film, the deposition of the first sublayer of the double barrier layer may be completed, and the second sublayer may be deposited. Similar to the method described above, the first sublayer may be deposited to a thickness between about 15-100 Å (eg, between about 20-50 Å). In many examples, the first sublayer is at least about 20 Å thick. The upper limit of the thickness of the first sublayer is the aspect ratio of the features on the substrate (if such features are present) and whether the features are completely filled with the second sublayer (eg SiN). It may depend on whether it is only lined with a second sublayer and later filled with another material such as an oxide.

If the first sublayer is a parylene film other than parylene AF-4, other dimers may be utilized. Similarly, other reaction parameters (temperature, pressure, etc.) may be used as suitable for the formation of the associated parylene membrane.

FIG. 3E is a flowchart showing a method of forming an organic polymer film by using a molecular layer deposition (MLD) method. In some embodiments, this method may be used to form a first sublayer of the double barrier layer. The MLD method can deposit a thin film of organic polymer using an ALD-like cycle involving two half-reactions. In some examples, the MLD method can be driven with less restricted adsorption than the conventional ALD method. For example, certain MLD methods may utilize unsaturated or supersaturated reactants. The ALD and MLD methods are particularly well suited to form conformal membranes that line the sidewalls of features in certain embodiments. The MLD method is further discussed in the following U.S. patent applications, each of which is incorporated herein by reference in its entirety: U.S. Patent Application No. 14 / 446,427 filed July 30, 2014. No. "METHOD OF CONDITIONING VACUUM CHAMBER OF SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS" and US Patent Application No. 14 / 724,574 "TECHNIQUE TODEPORT

Method 330 begins with step 331 in which the first reactant is flowed into the reaction chamber and adsorbed on the substrate surface. The reactants can penetrate deep into the partially etched features and adsorb on the sidewalls of the features. The first reactant forms an adsorption layer. In some examples, the first reactant is an organometallic material. In certain embodiments, the organometallic material comprises aluminum. An example of an aluminum-containing organometallic material that can be used as the first reactant is trimethylaluminum (TMA). In some other examples, the organometallic material may be a tungsten-containing material (eg, WCN). Many other organometallic materials may be used. In some examples, the first reactant may be an acid anhydride. An example of a suitable acid anhydride is maleic anhydride. The first reactant may be supplied with an inert carrier gas (eg, nitrogen, argon, helium, neon, etc.). The duration of flow of the first reactant may be between about 0.1 and 20 seconds.

The reaction chamber may then be optionally purged in step 333 to remove excess first reactants from the reaction chamber. Next, in step 335, a second reactant is supplied to the reaction chamber. An example of the duration of step 335 may be between about 0.1 and 20 seconds. In some embodiments, the second reactant may be a diamine, diol, thiol, or trifunctional compound. In certain embodiments, the second reactant may be ethylene glycol and / or ethanolamine. The second reactant reacts with the first reactant to form a protective film on the substrate. In a particular example, the first reactant is an organometallic material (eg, TMA or otherwise) and the second reactant is ethylene glycol. In another particular example, the first reactant is an acid anhydride (eg, maleic anhydride or the like) and the second reactant is ethanolamine. Such reactant combinations have been found to lead to membranes that provide a high quality barrier to HCl. Polymer films can be formed by thermal reaction without any dependence on plasma. In some embodiments, the substrate may be maintained at a temperature between about 25 and 250 ° C. during the formation of the polymer film. During the formation of the polymer membrane, the reaction chamber used for film deposition may be maintained at a pressure between about 0.5-10 tolls.

The reaction chamber may then be optionally purged in step 337. Purging in steps 333 and 337 may be performed by sweeping the reaction chamber with a non-reactive gas, exhausting the reaction chamber, or any combination thereof. The purpose of purging is to remove any non-adsorbed reactants and by-products from the reaction chamber. Although the purging steps 333 and 337 are both optional, they help prevent unwanted gas phase reactions and can lead to improved deposition results.

Next, in step 339, it is determined whether or not the polymer film is sufficiently thick. Such a determination may be made on the basis of the thickness deposited per cycle and the number of cycles performed. In various embodiments, each cycle deposits a film between about 0.1 and 1 nm, the thickness of which is the length of time that the reactants flow into the reaction chamber, and the resulting reactants. Depends on the saturation level of. If the film is not yet thick enough, method 330 repeats from step 331 to add film thickness by depositing additional layers. If not, method 330 is complete. In subsequent iterations, step 331 includes a step of adsorbing a further first reactant onto the substrate and a step of reacting the second reactant that may be present in the previous iteration of step 335 with the first reactant. May include both. In other words, after the first cycle, both steps 331 and 335 may include a reaction between the first and second reactants.

As mentioned above, the first sublayer of the double barrier layer is often a high carbon film. The method used to form the high carbon film is not limited to the methods described with respect to FIGS. 3A-3E.

Formation of a Second Sublayer in the Double Barrier Layer The second sublayer of the double barrier layer is formed on top of the first sublayer. The second sublayer provides protection against oxidation to the underlying material. In various embodiments, the second sublayer is a vapor deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), all of which can be performed by promoting a vapor deposition reaction using thermal energy and / or plasma. Is vapor-deposited using. In many examples, the second sublayer is SiN, but other materials may be used as needed.

FIG. 4A is a flowchart showing a method 400 for depositing a material using plasma atomic layer deposition. Method 400 is described in the context of forming SiN, but other materials may be formed if appropriate reactants and reaction conditions are provided. In some examples, method 400 may be performed in the reaction chamber of the Vector® product line from Lam Research, Fremont, Calif. Examples of devices that can be used to perform method 400 are presented in FIGS. 5-7.

Method 400 begins by feeding the substrate into the reaction chamber (block 401). The substrate may be maintained at a temperature between about 50 and 400 ° C. The reaction chamber may be maintained at a pressure between about 0.1 and 100 tolls. The first reactant is then allowed to flow into the reaction chamber and adsorb on the surface of the substrate (block 403). In various examples, the first reactant may be a halide-containing reactant (eg, a chlorine-containing reactant). The first reactant may be a silicon-containing reactant in many cases. In a particular example, the first reactant is dichlorosilane (DCS). An example of the flow rate of the first reactant may be about 0.25-5 L / min (flow rate to a single station / substrate). The first reactant may be supplied with the inert carrier gas. The duration of supply of the first reactant may be between about 0.1 and 20 seconds. The reaction chamber may then be optionally purged (block 405). Purging may be performed by exhausting the chamber, cleaning the chamber with an inert gas, or any combination thereof.

After the flow of the first reactant has stopped and after the reaction chamber has been optionally purged, the second reactant has been flushed into the reaction chamber and reacted with the first reactant to form a membrane. Form (block 407). In many embodiments, the second reactant is a nitrogen-containing reactant. The second reactant may be a hydrogen-containing reactant in many cases. An example of the second reactant is ammonia. An example of the flow rate of the second reactant may be about 0.25 to 20 L / min (flow rate to a single station / substrate). The second reactant may be supplied with the inert carrier gas. The duration of the second reactant flowing may be between about 0.1 and 20 seconds. In some embodiments, the second reactant may flow continuously onto the substrate.

The reaction chamber is exposed to plasma to facilitate the reaction between the first and second reactants in order to form the desired membrane (block 409). This membrane is the second sublayer of the double barrier layer. The supply of the second reactant at block 407 may be performed prior to plasma exposure at block 409 or at the same time as plasma exposure at block 409. In many embodiments, the plasma is capacitively coupled plasma. However, other types of plasma may be used (eg, inductively coupled plasma). Various types of plasma generators may be used, such as RF, DC, and microwave plasma generators. Both single frequency plasmas and dual frequency plasmas may be used. In some examples, the plasma is generated using a low frequency (LF) component (power to a single station / substrate) between about 25 and 1000 W supplied at a frequency between about 50 and 400 Hz. This power may correspond to a power density between ^{about 350 and 14,500 W / m 2} (considering the set power and the area of the substrate, not the loss from efficiency / supply). In these or other examples, the plasma is supplied at frequencies between about 2-60 Hz (eg, about 13.56 Hz, or in some cases about 27 Hz) and has high frequencies between about 25 and 5000 W. It may be generated using the (HF) component (power to a single station / board), which is (considering the set power and the area of the board, not the loss from efficiency / supply). It can accommodate power densities between about 350 and 70,000 W / m ^2.

In many examples, the first reactant and the second reactant react with each other to form an undesired halide-containing species (in addition to the desired membrane). For example, when the first reactant is DCS and the second reactant is ammonia, chlorine from DCS can combine with hydrogen from ammonia to form HCl. In the absence of a first sublayer that acts as a halide blocking layer, this HCl can damage a variety of materials on manufacturing devices.

After the supply of the second reactant, the reaction chamber is optionally purged (block 411). This purging may be performed by exhausting the reaction chamber, clearing the reaction chamber, or a combination thereof. The film thickness may then be compared to the final desired film thickness (block 413). Blocks 403-413 make up one ALD cycle. If the membrane is not thick enough at block 413, the method continues by repeating the ALD cycle starting at block 403. This cycle may be repeated until the deposited film reaches the desired thickness, at which point the method is complete. ALD and related methods for forming conformal membranes are further described in US Pat. No. 8,728,956, which is incorporated herein by reference in its entirety.

FIG. 4B is a flowchart showing a method 420 for vapor deposition of a material using plasma chemical vapor deposition. Method 420 is presented in the context of forming SiN, but other materials may be used in some examples. Method 420 begins by introducing the substrate into the reaction chamber (block 421). The first and second reactants are then simultaneously flushed into the reaction chamber (block 423). In this example, the first reactant may be dichlorosilane and the second reactant may be ammonia. The first and / or second reactants may have the properties described above with respect to FIG. 4A and may lead to the formation of HCl or other harmful halide-containing species. Many different reactants may be used, including one or more catalysts. The first sublayer (below the second sublayer) protects the underlying material from exposure to harmful halide-containing species. While the reactants are flowing, the reaction chamber is exposed to plasma to facilitate the reaction between the first and second reactants (block 423). The reaction may be a gas phase reaction in which the reaction product is deposited on the surface of the substrate (block 425). The steps shown in blocks 423 and 425 may be performed substantially simultaneously.

An example of the thickness of the second sublayer may be about 15-10,000 Å (limited by line width), regardless of how the sublayer is deposited, in some examples. , May be about 15-50 Å. In various examples, the second sublayer is at least about 15 Å thick (eg, at least about 20 Å thick). The upper limit of the thickness of the second sublayer is the aspect ratio of any recessed feature on the substrate, and whether such feature is completely filled with nitrogen or just lined with nitrogen and another such as oxide. It can depend on whether the material is later filled. In some embodiments, the first and second sublayers together may have a thickness between about 30 and 10,000 Å.

The first and second sublayers may be deposited in the same reaction chamber in some examples. This can be particularly beneficial when the first and second sublayers are deposited by chemical vapor deposition and / or atomic layer deposition techniques. The use of a single reaction chamber for the deposition of both sublayers can be advantageous in that the substrate does not need to be transferred between vapor deposition steps, reducing the potential for unwanted oxidation of the underlying material. The use of two different reaction chambers for the deposition of sublayers can be advantageous in that each chamber can be optimized for the deposition of one of the sublayers. This can further reduce contamination and form higher quality films with good adhesion and particle performance. In some embodiments, the methods described herein may be performed on a cluster tool with multiple reaction chambers. One reaction chamber may be used to deposit the first sublayer and the second reaction chamber may be used to deposit the second sublayer. A vacuum transfer chamber may be provided so that the substrate can be moved between reaction chambers while maintaining vacuum (and thus without exposing the substrate to the atmosphere). In some embodiments, the cluster tool may further include a reaction chamber configured to perform etching. Reaction chambers configured to perform etching may be used to implement the various etching steps described with respect to FIGS. 1A-1E and 2A-2F.

Devices The methods described herein can be performed by any suitable device. A suitable device comprises hardware for completing the processing process and a system controller having instructions for controlling the processing process in accordance with the present invention. For example, in some embodiments, the hardware may include one or more processing stations included in the processing tool.

FIG. 5 is a schematic diagram illustrating an embodiment of a processing station 500 that can be used to deposit materials using atomic layer deposition (ALD) and / or chemical vapor deposition (CVD), both of which may be plasma-enhanced. Is. For simplicity, the processing station 500 is illustrated as a stand-alone processing station with a processing chamber body 502 to maintain a low pressure environment. However, it can be seen that a plurality of processing stations 500 may be included in a common processing tool environment. Further, it can be seen that in some embodiments, one or more hardware parameters of the processing station 500 (such as the parameters detailed below) may be programmed programmatically adjusted by one or more computer controllers.

The processing station 500 is in fluid communication with the reactant supply system 501 for supplying the processing gas to the distribution shower head 506. The reactant supply system 501 includes a mixing vessel 504 for mixing and / or adjusting the processing gas for supply to the shower head 506. One or more mixing vessel inlet valves 520 may control the introduction of processing gas into the mixing vessel 504. Similarly, the shower head inlet valve 505 may control the introduction of processing gas into the shower head 506.

Some reactants, such as BTBAS, may be contained in liquid form prior to vaporization and subsequent supply to the processing station. For example, the embodiment of FIG. 5 comprises a vaporization point 503 for vaporizing the liquid reactants supplied to the mixing vessel 504. In some embodiments, the vaporization point 503 may be a heated vaporizer. The reactant vapor generated from such a vaporizer can condense in the downstream supply line. Exposure of incompatible gases to the condensed reactants can result in the formation of small particles. These small particles can clog pipes, interfere with valve operation, contaminate the board, and so on. Some approaches to address these challenges include clearing and / or evacuating supply lines to remove residual reactants. However, clearing the supply line can increase the cycle time of the processing station and reduce the throughput of the processing station. Therefore, in some embodiments, the supply line downstream of vaporization point 503 may be heat traced. In some examples, the mixing vessel may be heat treated for 504 m. In a non-limiting example, the piping downstream of the vaporization point 503 has a temperature profile that increases from about 100 ° C to about 150 ° C in the mixing vessel 504.

In some embodiments, the liquid reactant may be vaporized with a liquid injector. For example, a liquid injector may inject a pulse of liquid reactant into a transport gas stream upstream of the mixing vessel. In one scenario, the liquid injector may vaporize the reactants by flushing the liquid from high pressure to low pressure. In another scenario, the liquid injector may atomize the liquid into dispersed microdroplets, after which the microdroplets are vaporized in a heated supply tube. It can be seen that smaller droplets can vaporize faster than larger droplets, reducing the delay between liquid injection and complete vaporization. If vaporized more quickly, the length of the pipe downstream from the vaporization point 503 can be shortened. In one scenario, the liquid injector may be attached directly to the mixing vessel 504. In another scenario, the liquid injector may be attached directly to the shower head 506.

In some embodiments, upstream of the vaporization point 503, a liquid flow controller may be provided to control the mass flow rate of the liquid for vaporization and supply to the processing station 500. For example, a liquid flow controller (LFC) may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be telecommunications with the MFM and adjusted in response to a feedback control signal provided by a proportional integral differential (PID) controller. However, it can take more than a second to stabilize the liquid flow using feedback control. This can extend the time to supply the liquid reactant. Therefore, in some embodiments, the LFC may be dynamically switched between feedback control mode and direct control mode. In some embodiments, the LFC may be dynamically switched from feedback control mode to direct control mode by disabling the LFC's detector tube and PID controller.

The shower head 506 distributes the processing gas to the substrate 512. In the embodiment shown in FIG. 5, the substrate 512 is located below the shower head 506 and is illustrated on the pedestal 508. It can be seen that the shower head 506 may have any suitable shape and may have any suitable number and arrangement of ports for distributing the processing gas to the substrate 512.

In some embodiments, the microspace 507 is located below the shower head 506. Time to change treatment conditions (eg, pressure, temperature, etc.) to reduce reactant exposure and clearing time by performing ALD and / or CVD treatment in a small space rather than the entire space of the treatment station. It is possible to shorten the time required for processing, limit the exposure of the processing station robot to the processing gas, and so on. Examples of microspace sizes include, but are not limited to, volumes between 0.1 and 2 liters. This microspace also affects production throughput. As the deposition rate per cycle decreases, so does the cycle time. In certain cases, the latter effect is dramatic enough to improve the overall throughput of the module for a given target film thickness.

In some embodiments, the pedestal 508 may be moved up and down to expose the substrate 512 to the microspace 507 and / or to change the volume of the microspace 507. For example, during the substrate transfer phase, the pedestal 508 may be lowered to allow the substrate 512 to be loaded onto the pedestal 508. During the vapor deposition process, the pedestal 508 may be raised to place the substrate 512 within the microspace 507. In some embodiments, the microspace 507 can completely surround the substrate 512 and a portion of the pedestal 508 to create a region of high flow impedance during the deposition process.

Optionally, the pedestal 508 may be lowered and / or raised during a portion of the deposition process to adjust the treatment pressure, reactant concentration, etc. in the microspace 507. In one scenario where the processing chamber body 502 remains at base pressure during the deposition process, lowering the pedestal 508 may allow exhaust of the microspace 507. Examples of the ratio of microspace to processing chamber space include, but are not limited to, volume ratios between 1: 500 and 1:10. It can be seen that in some embodiments, the height of the pedestal may be programmatically adjusted by an appropriate computer controller.

In another scenario, adjusting the height of the pedestal 508 may allow the plasma density to vary during the plasma activation and / or treatment cycle involved in the deposition process. At the end of the deposition process, the pedestal 508 may be lowered during another substrate transfer step so that the substrate 512 can be recovered from the pedestal 508.

The examples of microspace modifications described herein refer to height-adjustable pedestals, but in some embodiments, the position of the showerhead 506 to vary the volume of the microspace 507. Can be adjusted relative to pedestal 508. Further, it can be seen that the vertical position of the pedestal 508 and / or the shower head 506 may be modified by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 508 may include a rotation axis for rotating the orientation of the substrate 512. It can be seen that in some embodiments, one or more of these examples of regulation may be performed programmatically by one or more suitable computer controllers.

Returning to the embodiment shown in FIG. 5, the shower head 506 and the pedestal 508 electrically communicate with the RF power supply 514 and the matching network 516 to power the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the processing station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 514 and the matching network 516 may be operated with any suitable power to form a plasma with radical species of the desired composition. Examples of suitable powers have been described above. Similarly, the RF power supply 514 may supply RF power of any suitable frequency. In some embodiments, the RF power supply 514 may be configured to control the high frequency RF power supply and the low frequency RF power supply independently of each other. Examples of low frequency RF frequencies can include, but are not limited to, frequencies between 50 kHz and 500 kHz. Examples of radio frequency RF frequencies can include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz. It can be seen that any suitable parameter may be adjusted discretely or continuously to provide plasma energy for the surface reaction. In a non-limiting example, plasma power may be intermittently pulsed to reduce ionic impact with the substrate surface compared to continuously powered plasma.

In some embodiments, the plasma may be monitored in situ by one or more plasma monitors. In one scenario, plasma power may be monitored by one or more voltage and current sensors (eg, VI probes). In another scenario, plasma density and / or processing gas concentration may be measured by one or more emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters may be programmed programmatically based on measurements from such in-situ plasma monitors. For example, an OES sensor may be used in a feedback loop to provide programmed control of plasma power. It can be seen that in some embodiments, other monitors may be used to monitor the plasma and other processing characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, audio monitors, and pressure transducers.

In some embodiments, the plasma may be controlled by input / output control (IOC) sequencing instructions. In one example, the instructions for setting the plasma conditions of the plasma processing step may be included in the corresponding plasma activation recipe step of the deposition process recipe. In some examples, the processing recipe steps may be arranged continuously so that all instructions for the deposition process step are executed at the same time as the process step. In some embodiments, instructions for setting one or more plasma parameters may be included in the recipe step prior to the plasma processing step. For example, the first recipe step is for the instruction to set the flow rate of the inert gas and / or the reaction gas, the instruction to set the plasma generator to the power setting point, and the first recipe step. It may include a time delay instruction. The next second recipe step may include an instruction to activate the plasma generator and a time delay instruction for the second recipe step. The third recipe step may include an instruction to disable the plasma generator and a time delay instruction for the third recipe step. It can be seen that these recipe steps may be further divided and / or repeated in any suitable manner within the scope of the present disclosure.

In some vapor deposition processes, plasma collisions last for durations on the order of seconds or more. In certain embodiments, shorter plasma collisions may be used. These may be on the order of 10 ms to 1 second (usually about 20-80 ms), with 50 ms being a specific example. Such very short RF plasma collisions require very rapid plasma stabilization. To achieve this, the plasma generator may be configured such that impedance matching is preset to a particular voltage with frequency fluctuations allowed. Conventionally, high frequency plasma is generated at an RF frequency of about 13.56 MHz. In the various embodiments described herein, frequencies are allowed to vary to values that differ from this standard value. By allowing frequency fluctuations while fixing impedance matching to a given voltage, the plasma can stabilize much faster, and this result is very relevant for some types of vapor deposition cycles. It can be important when utilizing short plasma collisions.

In some embodiments, the pedestal 508 may be temperature controlled using a heater 510. Further, in some embodiments, pressure control of the vapor deposition processing station 500 may be provided by the butterfly valve 518. As shown in the embodiment of FIG. 5, the butterfly valve 518 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of the processing station 500 may be adjusted by varying the flow rate of one or more gases introduced into the processing station 500.

FIG. 6 is a schematic showing an embodiment of a multi-station processing tool 600 with an inlet load lock 602 and an outlet load lock 604, one or both of which may include a remote plasma source. A robot 606 under atmospheric pressure is configured to move the wafer from a cassette loaded through the pod 608 into the inlet load lock 602 via the atmospheric port 610. The wafer is placed on the pedestal 612 in the inlet load lock 602 by the robot 606, the atmospheric port 610 is closed, and the load lock is pumped out. If the inlet load lock 602 comprises a remote plasma source, the wafer may undergo remote plasma processing within the load lock before being introduced into the processing chamber 614. In addition, the wafer may be heated in the inlet load lock 602, for example to remove moisture and adsorbed gas. The chamber transfer port 616 to the processing chamber 614 is then opened and another robot (not shown) places the wafer in the reactor for processing and the pedestal of the first station shown in the reactor. Place on top. Although the embodiment shown in FIG. 4 includes a load lock, it can be seen that in some embodiments the wafer may be placed directly into the processing station.

The processing chamber 614 of the figure comprises four processing stations numbered 1 to 4 in the embodiment shown in FIG. Each station has a heated pedestal (shown as 618 for station 1) and a gas line inlet. It can be seen that in some embodiments, each processing station may have a different purpose, i.e., a plurality of purposes. Although the processing chamber 614 in the figure comprises four stations, it can be seen that the processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have 5 or more stations, and in other embodiments, the processing chamber may have 3 or less stations.

FIG. 6 further shows an embodiment of a wafer handling system 690 for moving wafers within the processing chamber 614. In some embodiments, the wafer handling system 690 may move wafers between various processing stations and / or between processing stations and load locks. It can be seen that any suitable wafer handling system may be used. Non-limiting examples include wafer carousels and wafer handler robots. FIG. 6 further shows an embodiment of the system controller 650 used to control the processing conditions and hardware state of the processing tool 600. The system controller 650 may include one or more memory devices 656, one or more mass storage devices 654, and one or more processors 652. Processor 652 may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, and the like.

In some embodiments, the system controller 650 controls all operations of the processing tool 600. The system controller 650 is stored in the mass storage device 654, loaded into the memory device 656, and executes the system control software 658 executed by the processor 652. System control software 658 provides timing; gas mixing; chamber and / or station pressure; chamber and / or station temperature; purge conditions and timing; wafer temperature; RF power level; RF frequency; substrate, pedestal, chuck, And / or the position of the susceptor; as well as instructions for controlling other parameters of the particular process performed by the process tool 600. The system control software 658 may be configured in any suitable manner. For example, various processing tool component subroutines or control objects may be written to control the behavior of processing tool components required to perform the processing of various processing tools according to the disclosed methods. The system control software 658 may be coded in any suitable computer readable programming language.

In some embodiments, the system control software 658 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of PEALD processing may comprise one or more instructions for execution by the system controller 650. Instructions for setting processing conditions for the PEALD processing stage may be included in the corresponding PEALD recipe stage. In some embodiments, the PEALD recipe steps may be arranged consecutively so that all instructions for the PEALD process step are executed at the same time as the process step.

Other computer software and / or programs stored in the mass storage device 654 and / or memory device 656 associated with the system controller 650 may be used in some embodiments. Examples of programs or program sections for this purpose include substrate positioning programs, processing gas control programs, pressure control programs, heater control programs, and plasma control programs.

The board positioning program may include program code for processing tool components used to load the board onto the pedestal 618 and control the spacing between the board and the other components of the processing tool 600.

The processing gas control program is a code for flowing gas into one or more processing stations prior to deposition to control the gas composition and flow rate, and optionally to stabilize the pressure in the processing station. May be equipped. The processing gas control program may include a code for controlling the composition and flow rate of the gas within any of the disclosed ranges. The pressure control program may include a code for controlling the pressure in the processing station, for example, by adjusting the throttle valve of the exhaust system of the processing station, the gas flow rate to the processing station, and the like. The pressure control program may include a code for maintaining the pressure at the processing station within any of the disclosed pressure ranges.

The heater control program may include a code for controlling the current to the heating unit used to heat the substrate. Alternatively, the heater control program may control the supply of a heat conductive gas (such as helium) to the substrate. The heater control program may include instructions for maintaining the temperature of the substrate within any of the disclosed ranges.

The plasma control program comprises a code for setting the RF power level and frequency applied to the processing electrodes in one or more processing stations, eg, using any of the RF power levels disclosed herein. You can. The plasma control program may include a code for controlling the duration of each plasma exposure.

In some embodiments, there may be a user interface associated with the system controller 650. The user interface may include a display screen (a device and / or a graphical software display of processing conditions) and a user input device such as a pointing device, keyboard, touch screen, microphone.

In some embodiments, the parameters adjusted by the system controller 650 may be with respect to processing conditions. Non-limiting examples include the composition and flow rate of the processing gas, temperature, pressure, plasma conditions (RF power level, frequency, and exposure time, etc.). These parameters may be provided to the user in the form of a recipe and may be entered using the user interface.

Signals for monitoring processing may be provided by various processing tool sensors via the analog and / or digital input connections of the system controller 650. The signal for controlling the processing may be output by the analog and digital output connections of the processing tool 600. Non-limiting examples of processing tool sensors that can be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples and the like. Well-programmed feedback and control algorithms may be used with the data from these sensors to maintain processing conditions.

The disclosed embodiments can be implemented using any suitable chamber. Examples of vapor deposition equipment include ALTUS® products, VECTOR® products, and / or SPEED® products available from Lam Research, Fremont, California, or a variety of other equipment. Includes, but is not limited to, any of the other commercially available processing systems. Two or more of the stations may perform the same function. Similarly, two or more stations may perform different functions. Each station may be designed / configured to perform a particular function / method as needed.

FIG. 7 is a block diagram showing a processing system suitable for performing a thin film deposition process according to a particular embodiment. The system 700 includes a transport module 703. The transport module 703 provides a clean pressurized environment to minimize the risk of contamination when the substrate being processed is moved between various reactor modules. Two multi-station reactors 709 and 710 are attached to the transfer module 703, which can perform atomic layer deposition (ALD) and / or chemical vapor deposition (CVD), respectively, according to specific embodiments. Reactors 709 and 710 may include a plurality of stations 711, 713, 715, and 717 capable of performing operations according to the disclosed embodiments sequentially or non-sequentially. The station may include a heated pedestal or substrate support and one or more gas inlets or shower heads or diffusion plates.

Also, one or more single station modules or multi-station modules 707 capable of performing plasma pre-cleaning or chemical (non-plasma) pre-cleaning, or any other process described in connection with the disclosed method. It may be mounted on the transport module 703. Module 707 may be used in some examples, for example, in various processes for preparing a substrate for a vapor deposition process. Module 707 may be designed / configured to perform various other processes (such as etching or polishing). In certain embodiments, the first sublayer of the double barrier layer may be deposited in the reactor 709 and the second sublayer of the double barrier layer may be deposited in the reactor 710, module 707. May be used for etching. In this example, all the processes described with respect to FIGS. 1A-1E and 2A-2F can be accomplished within the processing system 700. This multi-function / multi-tool system can be particularly useful for manufacturing PCRAMs and other devices in a controlled atmosphere.

The system 700 also includes one or more wafer source modules 701 in which wafers are housed before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 719 may first remove the wafer from the source module 701 to the load lock 721. A wafer transfer device (generally a robot arm unit) within the transfer module 703 moves the wafer from the load lock 721 to and between the modules mounted on the transfer module 703.

In various embodiments, a system controller 729 is used to control processing conditions during deposition. The controller 729 typically comprises one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, and the like.

The controller 729 may control all operations of the vapor deposition apparatus. The system controller 729 is a set of controls for timing, gas mixing, chamber pressure, chamber temperature, wafer temperature, high frequency (RF) power level, wafer chuck or pedestal position, and other parameters of a particular process. Run the system control software that contains the instructions. Other computer programs stored in the memory device associated with the controller 729 may be used in some embodiments.

Typically, there is a user interface associated with the controller 729. The user interface may include a display screen (a device and / or a graphical software display of processing conditions) and a user input device such as a pointing device, keyboard, touch screen, microphone.

The system control logic may be configured in any suitable way. In general, logic can be designed or configured in hardware and / or software. Instructions for controlling the drive circuit may be hard-coded or provided as software. Instructions can be provided by "programming". Such programming is understood to include any form of logic, such as digital signal processors, application-specific integrated circuits, and logic hard-coded within other devices that have specific algorithms implemented as hardware. .. Programming is also understood to include software or firmware instructions that can be executed on general purpose processors. The system control software may be coded in any suitable computer-readable program language.

Computer programming code for controlling germanium-containing reducing agent pulses, hydrogen streams, and tungsten-containing precursor pulses, as well as other processes within the procedure, can be described, for example, in assembly language, C, C ++, Pascal, Fortran, etc. It can be written in any traditional computer-readable programming language. The compiled object code or script is executed by the processor to perform the tasks identified in the program. Further, as described above, the program code may be hard-coded.

Controller parameters relate, for example, to processing conditions such as composition and flow rate of processing gas, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be entered using the user interface. Signals for monitoring processing may be provided by the analog and / or digital input connections of the system controller 729. Signals for controlling processing are output on the analog and digital output connections of the system 700.

System software can be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be used to control the operation of the chamber components required to perform the vapor deposition process (and other processes in some cases) according to the disclosed embodiments. May be written. Examples of programs or program sections for this include board placement code, processing gas control code, pressure control code, and heater control code.

In some embodiments, the controller 729 is part of the system and the system may be part of the above example. Such systems include semiconductor processing equipment such as one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). Can be equipped. These systems may be integrated with electronic devices to control the operation of the system before, during, and after processing the semiconductor wafer or substrate. Electronic devices, also referred to as "controllers," can control various components or sub-components of a system. The controller 729 may supply processing gas, temperature settings (eg, heating and / or cooling), pressure settings, vacuum settings, power settings, and radio frequencies (RF) in some systems, depending on the processing requirements and / or type of system. ) Generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and motion settings, and inside and outside load locks connected or coupled to tools and other mobile tools and / or specific systems. It may be programmed to control any of the processes disclosed herein, such as moving the wafer.

In general, the controller receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and so on, with various integrated circuits, logic, memory, and / or , May be defined as an electronic device with software. An integrated circuit executes a chip in the form of a firmware for storing program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or a program instruction (eg, software). It may include one or more microprocessors or microcontrollers. Program instructions are transmitted to the controller in the form of various individual settings (or program files) and are operating parameters to or to the system to perform specific processing on or for the semiconductor wafer. It may be an instruction that defines. The operating parameters are, in some embodiments, one or more processing steps during the processing of one or more layers of the wafer, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies. May be part of a recipe defined by a processing engineer to achieve.

In some embodiments, the controller is a computer that is integrated with the system, is connected to the system, is otherwise networked with the system, or is coupled to the system in a combination thereof. It may be part or connected to such a computer. For example, the controller may be in the "cloud" or may be all or part of a fab host computer system that allows remote access to wafer processing. The computer monitors the current progress of the manufacturing operation by allowing remote access to the system to change the parameters of the current process, set the process according to the current process, or start a new process. You can look up the history of past manufacturing operations, look at trends or performance indicators from multiple manufacturing operations. In some examples, a remote computer (eg, a server) may provide processing recipes to the system over a network (which may include a local network or the Internet). The remote computer may have a user interface that allows input or programming of parameters and / or settings, and the parameters and / or settings are communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data, and the instructions specify parameters for each of the processing steps performed during one or more operations. It should be understood that the parameters may be specific to the type of processing performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controllers may be distributed, such as by including one or more separate controllers that are networked and operate for a common purpose (such as the processing and control described herein). .. An example of a distributed controller for this purpose is one or more remotely located (such as at the platform level or as part of a remote computer) working together to control processing in the chamber. One or more integrated circuits on the chamber that communicate with the integrated circuits of.

Examples of systems, but not limited to, are plasma etching chambers or modules, vapor deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD). Machining chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion injection chambers or modules, track chambers or modules, and semiconductor wafers. And / or any other semiconductor processing system that may be related to or utilized in manufacturing.

As mentioned above, depending on one or more processing steps performed by the tool, the controller may have other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby. Tools, tools located throughout the factory, main computer, another controller, or tools used to transport materials that carry containers of wafers to or from the tool location and / or load port within a semiconductor manufacturing plant. You may communicate with one or more of.

The various hardware and method embodiments described above may be used in conjunction with a lithographic patterning tool or process for, for example, processing or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Usually, but not always, such tools / processes are used or performed together in a common manufacturing facility.

Thin film lithography patterning typically involves some or all of the following steps, each step being achieved with multiple possible tools:
(1) A step of applying a photoresist on a workpiece (such as a substrate on which a silicon nitride thin film is formed) using a spin-on or spray-on tool;
(2) The step of curing the photoresist using a hot plate or a furnace or other suitable curing tool;
(3) A step of exposing the photoresist to visible light, UV or x-rays with a tool such as a wafer stepper;
(4) A step of developing a resist for patterning by selectively removing the resist using a tool such as a wet bench or a spray developer;
(5) A step of transferring a resist pattern to an underlying film or workpiece using a dry etching tool or a plasma assisted etching tool;
(6) A step of removing a resist using a tool such as an RF plasma or a microwave plasma resist stripper.
In some embodiments, an ashable hardmask layer (such as an amorphous carbon layer) and another suitable hardmask (such as an antireflection layer) may be deposited prior to the application of the photoresist.

It is understood that these specific embodiments or examples are not considered to be limiting, as the configurations and / or approaches described herein are exemplary in nature and many modifications are possible. I want to be. The specific routines or methods described herein may represent one or more of any number of processing strategies. Therefore, the various illustrated actions may be performed in the order exemplified, in the other order, or in parallel, and may be omitted in some examples. Similarly, the order of the above-mentioned processes may be changed.

The subject matter of this disclosure is all new and non-trivial and partial combinations of various processes, systems, and configurations, as well as other features, functions, behaviors, and / or those disclosed herein. Includes properties and all their equivalents.

Experimental Experimental results have shown that the described dual barrier layer approach can be used to protect halide-sensitive materials from damage as well as from oxidation. Experimental results suggest that the disclosed methods are particularly useful in the context of forming PCRAM devices, but embodiments are not limited to this.

Several types of membranes were examined for the first sublayer of the double barrier layer. Various high carbon-containing membranes have been shown to provide high quality protection against damage from HCl. For example, the conformal carbon layer was deposited using the PECVD method (eg, as described above in connection with the formation of the ashable hardmask material in FIG. 3A). The deposited film was substantially conformal and had a 1 sigma thickness non-uniformity of less than 2.5%. 1 Sigma thickness non-uniformity is calculated using spectroscopic ellipsometry. Thickness non-uniformity is calculated based on a map pattern of film thickness that examines 49 (or 50 or more) points on the substrate. Up to 3 mm from the outside of the substrate is excluded from consideration. Within 49 (or 50 or more) points, the average thickness and standard deviation are calculated. One sigma thickness non-uniformity is calculated as 100 × (standard deviation of thickness) / (average thickness). In various examples, the thickness non-uniformity of the first sublayer can be about 2% or less. The refractive index of the vapor-deposited film was about 1.61 at 633 nm. The formed film is non-conductive and has low leakage and high breakdown voltage. An example of leakage current and breakdown voltage is shown in FIG. Four samples (1-4) are shown. Each sample was formed at about 250 ° C. using PECVD. In various embodiments, the first sublayer may have a breakdown voltage having a magnitude of at least about 4 MV / cm (eg, a field voltage with ^{a leakage current of 0.001 A / cm 2).}

FIG. 9 shows the results of experiments on HCl bubble tests performed on multiple different types of membranes. This test was performed to evaluate different materials with respect to resistance to exposure to HCl. In other words, this test assesses how much the material (eg, the material of the first sublayer) is expected to protect the underlying material from damage from exposure to HCl. In the HCl bubble test, various films were deposited on an aluminum coupon prepared on a bare silicon wafer carrier. After the deposition, the films were immersed in a solution containing of _{H 2} O to 5% HCl and 95% (by volume). Membranes were monitored for signs of bubble formation. Foam is formed as a result of the reaction between HCl and the underlying aluminum material. For each membrane, the following three different times were recorded:
(1) The time when bubbles first appeared on the surface of the film,
(2) The time when bubbles started to rise discontinuously from the membrane, and
(3) The time when the stable flow of bubbles started to rise from the membrane.
These three times were defined as the damage conditions. The longer the time frame, the more resistant it is to HCl.

The membrane tested with respect to FIG. 9 includes:
(1) Ashable hardmask carbon material (referred to as "SF AHM") deposited using a single frequency RF PECVD process,
(2) Ashable hardmask carbon material (referred to as "DF AHM") deposited using dual frequency RF PECVD processing,
(3) Non-doped silicate glass (referred to as "SF USG") deposited using a single frequency RF PECVD treatment,
(4) Non-doped silicate glass (referred to as "DF USG") deposited using dual frequency RF PECVD treatment,
(5) Silicon nitride material (referred to as "DF SiN") deposited using dual frequency RF PECVD processing,
(6) A silicon nitride silicon material (referred to as "NDC") vapor-deposited using PECVD treatment, and
(7) Silicon nitride material deposited by ALD treatment (referred to as "ALD SiN").

As shown in FIG. 9, single-frequency and dual-frequency washable hardmask materials showed the best resistance to HCl. Therefore, these high carbon-containing materials provide a high quality barrier against damage from exposure to HCl. The single frequency ashable hardmask material performed particularly well, with breakage occurring after about 240 minutes. Although not bound by the theory or mechanism of action, single-frequency PECVD AHM membranes have lower densities, higher hydrogen content, and higher hydrogen content than double-frequency membranes. Due to its low SP3 binding, it is believed to be more resistant to HCl than dual frequency PECVD AHM membranes.
The present invention can also be realized as the following application examples.
<Application example 1>
A method of depositing a double barrier layer on a semiconductor device in the middle of manufacturing.
(A) A step of preparing a substrate containing a first halide-sensitive material layer, wherein the first halide-sensitive material layer is at least partially exposed when prepared in step (a). Preparation process and
(B) A thin-film deposition step for depositing the double barrier layer.
(I) A step of depositing a first sublayer of the double barrier layer on the substrate, wherein the first sublayer contains at least about 40% by weight of carbon and is the first halide. The process, which is deposited on the exposed part of the sensitive material layer,
(Ii) A step of depositing a second sublayer of the double barrier layer on the first sublayer of the double barrier layer, wherein the second sublayer of the double barrier layer is formed. It contains silicon nitride and is vapor-deposited with a halide-containing chemical, and during the deposition of the second sub-layer of the double-barrier layer, the first sub-layer of the double-barrier layer is subjected to the first sub-layer. To protect the halide-sensitive material layer from the halide-containing chemicals,
The vapor deposition process performed by
A method.
<Application example 2>
The method according to Application Example 1, wherein the first halide-sensitive material layer comprises a chalcogenide material.
<Application example 3>
The method according to Application Example 1 or 2, wherein the first sublayer of the double barrier layer contains amorphous carbon deposited by chemical vapor deposition.
<Application example 4>
The method according to Application Example 1 or 2, wherein the first sublayer of the double barrier layer comprises a parylene material deposited by a process comprising thermal decomposition and polymerization.
<Application example 5>
The method according to Application Example 4, wherein the parylene material comprises parylene AF-4.
<Application example 6>
The method according to any one of Application Examples 1 to 5, wherein the step (c) includes a step of vapor-depositing the second sub-layer of the double barrier layer by an atomic layer deposition treatment.
<Application example 7>
The method according to any one of Application Examples 1 to 5, wherein the step (c) includes a step of vapor-depositing the second sub-layer of the double barrier layer by a chemical vapor deposition treatment.
<Application example 8>
The method according to any one of Application Examples 1 to 7, wherein the substrate includes a second halide-sensitive material layer arranged below the first halide-sensitive material layer. further,
(D) After the step (c), the first halide-sensitive material layer is exposed without exposing the first halide-sensitive material layer, although a part of the second halide-sensitive material layer is exposed. And the step of etching the substrate so that is at least partially covered by the double barrier layer.
(E) A vapor deposition step of depositing a second double barrier layer on the substrate.
(I) In the step of depositing the first sublayer of the second double barrier layer on the substrate, the first sublayer of the second double barrier layer is at least about 40 weight by weight. The steps, which contain% carbon and are deposited on the exposed portion of the second halide sensitive material layer,
(Ii) A step of depositing a second sublayer of the second double barrier layer on the first sublayer of the second double barrier layer, wherein the second double barrier layer is deposited. The second sub-layer contains silicon nitride and is vapor-deposited using a halide-containing chemical substance in the atomic layer deposition treatment, and during the deposition of the second sub-layer of the second double barrier layer, A step in which the first sublayer of the second double barrier layer protects the second halide-sensitive material layer from the halide-containing chemicals.
The vapor deposition process performed by
A method.
<Application example 9>
The method according to any one of Application Examples 1 to 8, wherein the first sublayer of the double barrier layer is deposited to a thickness of about 15-100 Å and the second sublayer of the double barrier layer. The sublayer is deposited to a thickness of at least about 20 Å, the method.
<Application example 10>
The method according to any one of Application Examples 1 to 9, wherein the halide-containing chemical substance contains chlorosilane.
<Application example 11>
The method of Application Example 10, wherein the chlorosilane is dichlorosilane.
<Application example 12>
The method according to any one of Application Examples 1 to 11, wherein the method is performed when forming a phase change memory device.
<Application example 13>
The method according to any one of Application Examples 1 to 3 or 6 to 12, wherein the first sublayer of the double barrier layer is the substrate in plasma generated using a single RF frequency. A method formed by plasma chemical vapor deposition, which involves the step of exposing.
<Application example 14>
The method according to Application Example 13, wherein the RF frequency used to generate the plasma is a radio frequency (HF) RF frequency.
<Application example 15>
In the method according to any one of Application Examples 1 to 14, the first sublayer of the double barrier layer is vapor-deposited in a reaction chamber, and the second sublayer of the double barrier layer is formed. , The method of being deposited in the same reaction chamber.
<Application example 16>
The method according to any one of Application Examples 1 to 14, wherein the first sublayer of the double barrier layer is deposited in a first reaction chamber and the second sublayer of the double barrier layer is deposited. The method, wherein the sub-layer is deposited in a second reaction chamber, both the first and second reaction chambers being provided on a multi-chamber tool.
<Application example 17>
The method according to Application Example 16, further comprising the step of moving the substrate from the first reaction chamber to the second reaction chamber under vacuum conditions.
<Application example 18>
The method according to any one of Application Examples 1 to 17, wherein the first and second sublayers of the double barrier layer are of the sublayer for each of the first and second sublayers. A method of conformal deposition such that the thinnest portion is at least about 60% of the thickest portion of the sublayer.
<Application example 19>
The method according to Application Example 2, wherein the chalcogenide material is sandwiched between carbon layers.

Claims (19)

A method of depositing a double barrier layer on a semiconductor device in the middle of manufacturing.
(A) A step of preparing a substrate containing a first halide-sensitive material layer, wherein the first halide-sensitive material layer is at least partially exposed when prepared in step (a). Preparation process and
(B) A thin-film deposition step for depositing the double barrier layer.
(I) A step of depositing a first sublayer of the double barrier layer on the substrate, wherein the first sublayer contains at least 40 % by weight of carbon and is susceptible to the first halide. The process, which is deposited on the exposed part of the material layer,
(Ii) A step of depositing a second sublayer of the double barrier layer on the first sublayer of the double barrier layer, wherein the second sublayer of the double barrier layer is formed. It contains silicon nitride and is vapor-deposited with a halide-containing chemical, and during the deposition of the second sub-layer of the double-barrier layer, the first sub-layer of the double-barrier layer is subjected to the first sub-layer. To protect the halide-sensitive material layer from the halide-containing chemicals,
The vapor deposition process performed by
A method. The method according to claim 1, wherein the first halide-sensitive material layer contains a chalcogenide material. The method according to claim 1 or 2, wherein the first sublayer of the double barrier layer contains amorphous carbon vapor-deposited by chemical vapor deposition. The method according to claim 1 or 2, wherein the first sublayer of the double barrier layer comprises a parylene material deposited by a process including thermal decomposition and polymerization. The method according to claim 4, wherein the parylene material comprises parylene AF-4. The method according to any one of claims 1 to 5, wherein the steps (b) and (ii) include a step of vapor-depositing the second sub-layer of the double barrier layer by an atomic layer deposition treatment. .. The method according to any one of claims 1 to 5, wherein the steps (b) and (ii) include a step of vapor-depositing the second sub-layer of the double barrier layer by chemical vapor deposition. The method according to any one of claims 1 to 7, wherein the substrate includes a second halide-sensitive material layer arranged below the first halide-sensitive material layer. further,
(C) After the steps (b) and (ii), the first halide-sensitive material layer is exposed but the first halide-sensitive material layer is not exposed. A step of etching the substrate so that the sensitive material layer remains at least partially covered by the double barrier layer.
(D) A vapor deposition step in which a second double barrier layer is vapor-deposited on the substrate.
(I) In the step of depositing the first sublayer of the second double barrier layer on the substrate, the first sublayer of the second double barrier layer is at least 40 % by weight. The process of depositing carbon on the exposed portion of the second halide-sensitive material layer.
(Ii) A step of depositing a second sublayer of the second double barrier layer on the first sublayer of the second double barrier layer, wherein the second double barrier layer is deposited. The second sub-layer contains silicon nitride and is vapor-deposited using a halide-containing chemical substance in the atomic layer deposition treatment, and during the deposition of the second sub-layer of the second double barrier layer, A step in which the first sublayer of the second double barrier layer protects the second halide-sensitive material layer from the halide-containing chemicals.
The vapor deposition process performed by
A method. The method according to any one of claims 1 to 8, wherein the first sub-layer of the double-barrier layer is deposited to a thickness of 15 to 100 Å and the second sub-layer of the double-barrier layer. The method, in which the layers are deposited to a thickness of at least 20 Å. The method according to any one of claims 1 to 9, wherein the halide-containing chemical substance contains chlorosilane. The method of claim 10, wherein the chlorosilane is dichlorosilane. The method according to any one of claims 1 to 11, wherein the method is executed when forming a phase change memory device. The method according to any one of claims 1 to 3 or 6 to 12, wherein the first sublayer of the double barrier layer is the substrate in plasma generated using a single RF frequency. A method formed by a plasma chemical vapor deposition process involving an exposure step. The method of claim 13, wherein the RF frequency used to generate the plasma is between 1.8 MHz and 2.45 GHz . The method according to any one of claims 1 to 14, wherein the first sublayer of the double barrier layer is vapor-deposited in a reaction chamber, and the second sublayer of the double barrier layer is formed. , The method of being deposited in the same reaction chamber. The method according to any one of claims 1 to 14, wherein the first sublayer of the double barrier layer is deposited in a first reaction chamber and the second sublayer of the double barrier layer. The method, wherein the sub-layer is deposited in a second reaction chamber, both the first and second reaction chambers being provided on a multi-chamber tool. The method according to claim 16, further comprising the step of moving the substrate from the first reaction chamber to the second reaction chamber under vacuum conditions. The method according to any one of claims 1 to 17, wherein the first and second sublayers of the double barrier layer are of the sublayer for each of the first and second sublayers. A method of conformal deposition such that the thinnest portion is at least 60 % of the thickest portion of the sublayer. The method according to claim 2, wherein the chalcogenide material is sandwiched between carbon layers.