KR20120021253A - Micro pattern forming method - Google Patents

Abstract

PURPOSE: A method for forming a micro-pattern is provided to control the inclination of a sidewall part by heating a wafer which forms a silicon oxide layer in the high temperatures. CONSTITUTION: A resist film(104) formed on an organic film(103) is patterned. A silicon dioxide film(105) is piled on a substrate in the room temperature in order to cover the organic film and the patterned resist film. Tensile stress is created on the silicon dioxide film by heating the substrate in which the silicon dioxide film is piled. A silicon nitride film is piled on the heated silicon dioxide film. A sidewall part(105a) is formed by etching the silicon dioxide film. The patterned resist film is eliminated.

Description

Method of Forming Fine Pattern {MICRO PATTERN FORMING METHOD}

The present invention relates to a method of forming a fine pattern used in a semiconductor manufacturing process.

The miniaturization of semiconductor integrated circuits is further progressed, and the technique of realizing a dimension smaller than the dimension (limit dimension) which can be exposed by exposure light of wavelength 193nm is put into practical use. One of them is the so-called sidewall transfer (SWT) technology.

In the SWT technique, a resist pattern including a line and / or a space having a width corresponding to the limit dimension is formed. Next, by trimming this resist pattern, lines and / or spaces narrower than the limit dimension are formed. Subsequently, a silicon oxide film is deposited to cover the trimmed resist pattern. When the silicon oxide film is etched back, silicon oxide (side wall portion) remains only on the side surfaces of the resist pattern. After that, if the resist pattern is removed, only the sidewall portion remains. Since the width of the side wall portion is determined by the thickness of the silicon oxide film, it can be made smaller than the limit dimension, and the distance of the side wall portion is determined by the line width of the trimmed resist pattern, so that it can be made smaller than the limit dimension.

Thus, by using the SWT technique, it is possible to form a pattern including a dimension smaller than the allowable limit dimension and to use the pattern as an etching mask pattern, thereby to realize a semiconductor integrated circuit having a dimension smaller than the limit dimension. It becomes possible.

In addition, a predetermined pattern (line space) may be formed of a material different from the resist, the pattern may be trimmed to a width smaller than the limit dimension, and the sidewall portion may be formed using the pattern (line space) after trimming. (Patent Document 1).

Japanese Patent Application Publication No. 2009-88085

SWT is an indispensable technique for manufacturing a semiconductor integrated circuit having a dimension smaller than the exposure limit dimension. However, as the dimension becomes smaller, the sidewall portion is inclined when the resist pattern which is the basis of the formation of the sidewall portion is removed. It may not be used as an etching mask which has a desired pattern. In particular, when the aspect ratio of the side wall portion exceeds a predetermined value, the side wall portion may collapse.

In order to cope with this, when a pattern (line space) is made of a film material having a physical strength higher than that of the resist pattern to form the sidewall portion, it is necessary to laminate a film by the film material and a resist film for patterning the film. Therefore, problems such as a decrease in throughput, a decrease in yield, an increase in manufacturing cost, and the like occur with an increase in the number of process steps.

In view of the above circumstances, the present invention is intended to provide a method of forming a fine pattern which can suppress the inclination of the side wall portion even when the resist is formed with a pattern that forms the basis of the side wall portion formation.

According to the first aspect of the present invention, an organic film forming step of forming an organic film on an etching target layer formed on a substrate, a patterning step of forming a resist film on the organic film and patterning the resist film, and the patterned resist A first deposition step of depositing the silicon oxide film at room temperature so as to cover the organic film exposed from the film, the patterned resist film, and heating the substrate on which the silicon oxide is deposited to generate tensile stress in the silicon oxide film. A method of forming a fine pattern is provided, comprising a processing step, a first etching step of etching the silicon oxide film so that the silicon oxide film remains on a sidewall of the patterned resist film, and a removing step of removing the patterned resist film.

According to the embodiment of the present invention, even when the pattern on which the sidewall portion is formed is formed by the resist, there is provided a method of forming a fine pattern which can suppress the inclination of the sidewall portion.

BRIEF DESCRIPTION OF THE DRAWINGS The flowchart for demonstrating the procedure of each process in the fine pattern formation method by 1st Embodiment of this invention.
FIG. 2 is a view for explaining a fine pattern forming method according to the first embodiment of the present invention. FIG.
FIG. 3 is a view for explaining a fine pattern forming method according to the first embodiment of the present invention, following FIG. 1. FIG.
It is a figure which shows typically a state that a wafer bends by the heat processing process of the fine pattern formation method which concerns on 1st Embodiment of this invention.
Fig. 5 is a sectional view schematically showing a molecular layer deposition apparatus suitable for the method for forming a fine pattern according to the first embodiment of the present invention.
6 is another cross-sectional view of the molecular layer deposition apparatus of FIG. 5.
FIG. 7 is a time chart showing a process of a fine pattern forming method according to the first embodiment of the present invention, which is performed using the molecular layer deposition apparatus shown in FIGS. 5 and 6.
8 is a flowchart for explaining a procedure of each step in the method for forming a fine pattern according to the second embodiment of the present invention.
9 is a view for explaining a fine pattern forming method according to the second embodiment of the present invention.
FIG. 10 is a view for explaining a fine pattern forming method according to the second embodiment of the present invention following FIG. 9.
It is explanatory drawing explaining the stress measuring apparatus used when examining the heating temperature dependence of the tensile stress produced by the heat processing process of the fine pattern formation method which concerns on the 1st Embodiment of this invention, and its measuring principle.
12 is a graph showing the heating temperature dependence of the tensile stress generated by the heat treatment step of the method for forming a fine pattern according to the first embodiment of the present invention.
It is a schematic diagram which shows the result of the experiment performed in order to confirm the effect of the fine pattern formation method by 1st Embodiment and 2nd Embodiment.
14 is a graph showing an example of deposition temperature dependency of tensile stress generated in a silicon nitride film.
15 is a graph showing the results of experiments performed again to confirm the effects of the fine pattern forming method according to the first embodiment and the second embodiment.
16 is a table showing the results of experiments performed again to confirm the effects of the fine pattern forming method according to the first embodiment and the second embodiment.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described, referring an accompanying drawing. In the following description, the same or corresponding members (layers, films, etc.) are given the same or corresponding reference numerals, and redundant descriptions are omitted.

(1st embodiment)

First, the fine pattern formation method which concerns on 1st Embodiment of this invention is demonstrated, referring FIGS.

The fine pattern forming method according to the present embodiment includes steps S101 to S110 as shown in FIG. 1.

As shown in Fig. 2A, first, the thin film 102 is formed on the wafer W (S101 in Fig. 1), and the organic film 103 is formed on the thin film 102 (S102). . The thin film 102 is formed of, for example, amorphous silicon, polysilicon, or the like, and is a patterning target film that is later patterned in the present embodiment. In another embodiment, the thin film 102 may be used as a mask for etching the wafer W after being patterned. The thickness of the thin film 102 is not particularly limited, and may be, for example, 20 to 200 nm.

The organic film 103 is later patterned and used as a mask for patterning the thin film 102. The organic film 103 is an antireflection film BARC that prevents multiple reflection of exposure light generated in the resist film 104 when the resist film 104 formed on the organic film 103 is exposed in the present embodiment. : Bottom Anti-Reflecting Coating. The thickness of the organic film 103 is not specifically limited, For example, what is necessary is just 150-300 nm.

Referring to FIG. 2B, a resist film 104 is formed on the organic film 103 (step S103). The resist film 104 is formed of an ArF resist in this embodiment. The thickness of the resist film 104 is not particularly limited, and may be, for example, 50 to 200 nm.

Next, the resist film 104 is patterned by photolithography using a predetermined photomask, and a resist pattern 104a is formed as shown in Fig. 2C (step S104). The line width LL4 and the space width SS4 of the resist pattern 104a are all 60 nm, for example in this embodiment.

Subsequently, as shown in Fig. 2D, the resist pattern 104a is trimmed (or slimmed) to obtain a trimmed resist pattern 104b (step S105). As a result of trimming, the line width LL1 of the resist pattern 104b is narrower, for example 30 nm, than the line width LL4 (for example 60 nm) of the resist pattern 104a, and the resist pattern 104b The space width SS1 of is larger than the space width SS4 (for example, 60 nm) of the resist pattern 104a, for example, 90 nm. The trimming is not particularly limited, but is performed by exposing the wafer W on which the resist pattern 104a is formed to ozone gas or to oxygen radicals obtained by exciting the oxygen-containing gas. The temperature of the wafer W at this time may be room temperature to 100 degreeC.

Referring to FIG. 3E, a silicon oxide film 105 is deposited on the organic film 103 exposed to the space of the resist pattern 104b so as to cover the resist pattern 104b (step S106). The silicon oxide film 105 is deposited in a normal temperature atmosphere, preferably by a molecular layer deposition (MLD) method. According to the MLD method, deposition (conformal) reflecting the shape of the underlying layer is possible. For this reason, the silicon oxide film 105 which has a deposition surface substantially parallel to this side surface can be deposited on the side surface of the resist pattern 104b, and if the thickness on the organic film 103 is set to D, The thickness on the upper surface and the side surface of the pattern 104b also becomes approximately D. Here, thickness D is not specifically limited, For example, it can be 30 nm. In addition, deposition of the silicon oxide film 105 may be performed at a predetermined temperature in the temperature range of 5 ° C. to about 100 ° C., instead of a predetermined temperature in the temperature range of 5 ° C. to 35 ° C., for example.

Next, the wafer W including the silicon oxide film 105 deposited at room temperature (with the resist pattern 104b left) is heated to a predetermined temperature, for example, in the range from 150 ° C to 630 ° C. (Step S107). The silicon oxide film 105 deposited at room temperature has a relatively low density, including moisture, impurities, etc., but when moisture, impurities, etc. are released by heating, the silicon oxide film 105 is densified to shrink. As a result, as shown in Fig. 3F, the wafer W on which the silicon oxide film 105 is deposited is curved upward in a concave shape.

Tensile stress is generated on the concave film surface as indicated by the arrow in FIG. 4. FIG. 4 schematically shows a state after the oxide film silicon is formed and subsequently subjected to heat treatment, that is, before the side wall portion is formed. Thus, the tensile stress which generate | occur | produces in the film | membrane after heat processing can be calculated | required by measuring the curvature of the wafer W before and after heating, for example using a laser beam. This measurement will be described later.

In addition, as long as the wafer W can be heated in the above-mentioned temperature range, the heating apparatus used for this heating is not limited, An example of a suitable apparatus (FIGS. 5 and 6) is also mentioned later.

Subsequently, as shown in Fig. 3G, the silicon oxide film 105 is etched back to remove the silicon oxide film 105 on the upper surface of the organic film 103 and the resist pattern 104b. The side wall portion 105a of the silicon oxide remains on the side of the pattern 104b (step S108). By this etch back, since the silicon oxide film 105 covering the surface of the wafer W is removed, the tensile stress applied to the film surface is reduced, and the warping of the wafer W is reduced. In addition, a force that opens outwardly acts on the sidewall portion 105a of the silicon oxide remaining on the side of the resist pattern 104b.

Further, in the etch-back is not particularly limited, for example, _{CF 4, C 4 F 8,} CHF 3, CH 3 F, CH 2 F 2 and so on CF-based gas and a mixed gas of an inert gas such as Ar gas Or a gas in which oxygen is added to the mixed gas as necessary. For convenience of explanation, the pattern including the resist pattern 104b and the sidewall portion 105a is referred to as a third pattern 106. If the line width of the third pattern 106 is LL3 and the space width is SS3,

LL3 = LL1 + D × 2

SS3 = SS1-D × 2

Relationship is established. In this embodiment,

The line width LL1 of the resist pattern 104b = 30 nm,

The space width (SS1) of the resist pattern 104b = 90 nm,

The thickness (width) (D) of the sidewall portion 105a = 30 nm

Because of,

The line width LL3 of the third pattern 106 = 90 nm,

The space width (SS3) of the third pattern 106 = 30 nm

.

Next, etching using plasma of oxygen, nitrogen, hydrogen, ammonia or the like is performed to remove the resist pattern 104b formed from the resist film 104 while leaving the sidewall portion 105a.

Subsequently, when the organic film 103 is etched using the remaining side wall portion 105a as a mask, as shown in FIG. 3H, an etching mask composed of the side wall portion 105a and the organic film 103 is used. 107 is formed (step S109). In the etching mask 107, a line having a width LL2 and a space having a width SS2 are alternately arranged. here,

Line width LL2 = width D of the side wall portion 105a (= 30 nm),

Space width SS2 = line width LL1 of resist pattern 104b = space width SS3 of third pattern 106 (= 30 nm)

Relationship is established. That is, in the etching mask 107, a line having a width LL2 of 30 nm and a space having a width SS2 of 30 nm are alternately arranged.

When the thin film 102 is etched using such an etching mask 107 as a mask, a desired etching mask is obtained (step S110). For example, the etching of the thin film 102 made of amorphous silicon or polysilicon is performed by Cl ₂ , Cl ₂ + HBr, Cl ₂ + O ₂ , CF ₄ + O ₂ , SF ₆ , Cl ₂ + N ₂ , Cl ₂ + HCl, HBr + Cl ₂ + SF _It can carry out using plasma, such as gas, such as _six .

In the fine pattern formation method according to the present embodiment, the silicon oxide film 105 is deposited at room temperature so as to cover the resist pattern 104b to form the sidewall portion 105a used as the etching mask. After deposition of the silicon oxide film 105, the wafer W on which the silicon oxide film 105 is formed is heated to a high temperature (about 150 ° C. to about 630 ° C.), so that two-dimensional tensile stress is applied to the silicon oxide film 105. You lose. Thus, even after the resist pattern 104b is removed, the side wall portion 105a does not tilt. That is, even when the resist pattern 104b is used as the basis (base) of the silicon oxide film 105 deposited to form the sidewall portion 105a, the sidewall portion 105a can be prevented from tilting.

In addition, the side wall of the resist pattern 104b may be inclined at an angle of 90 ° or more with respect to the surface of the organic film 103 serving as the underlying layer. In other words, for example, in FIG. 2D, the resist pattern 104b may be trapezoidal. In addition, the sidewall of the resist pattern 104b may be inclined in the vicinity of the surface of the organic film 103 (when the lower end is pulled out). In these cases, the side wall portion 105a is considered to be more inclined, but according to the fine pattern formation method according to the present embodiment, it is possible to suppress the inclination even in this case.

In addition, the above-described deposition of the silicon oxide film 105 is performed in a room temperature CVD apparatus, and heating of the wafer W on which the silicon oxide film 105 is deposited is performed in an anneal to etch the silicon oxide film 105. May be performed in the etching apparatus (that is, each process may be performed in a separate apparatus), but deposition (after normal temperature) of the silicon oxide film 105 and subsequent heating are performed in the same CVD apparatus, and etching is performed. It can also be performed in an etching apparatus. In addition, after depositing the silicon oxide film 105 in a normal temperature CVD apparatus, subsequent heating and etching may be performed in the same etching apparatus.

Further, trimming of resist pattern 104a (formation of resist pattern 104b), deposition of silicon oxide film 105, and heating of wafer W on which silicon oxide film 105 is deposited are performed on the same MLD apparatus. You may carry out. Hereinafter, the MLD apparatus which can perform such a process is demonstrated.

FIG. 5 is a longitudinal sectional view schematically showing an MLD device suitable for the method for forming a fine pattern according to the present embodiment, and FIG. 6 is a cross sectional view of the MLD device of FIG. 5.

As shown in Fig. 4, the MLD apparatus 80 has a processing container 1 formed of, for example, quartz having a cylindrical shape with a ceiling with an open lower end. Above the inside of the processing container 1, the ceiling top plate 2 made of quartz is provided in the ceiling. Moreover, the manifold 3 shape | molded in cylindrical shape by stainless steel, for example is connected to the lower end opening part of the processing container 1 via sealing members 4, such as an O-ring.

The manifold 3 acts as a supporting member for supporting the lower end of the processing container 1, and supplies a predetermined gas into the processing container 1 from a pipe connected to a plurality of through holes formed in the side surface, respectively. In the lower part of the manifold 3, the lid part 9 which opens and closes the opening part of the manifold 3, for example, is made of stainless steel, for example, is connected through the sealing member 12 which consists of O rings, for example. have. The lid part 9 has an opening in the center, and the rotation shaft 10 penetrates this opening. The table 8 is provided in the upper end part of the rotating shaft 10, and the wafer boat 5 is provided on the table 8 via the quartz heat insulation container 7. The wafer boat 5 has three pillars 6 (see FIG. 6), and a plurality of wafers W are supported by grooves formed in the pillars 6. By rotating the rotation shaft 10 around the central axis by a rotation mechanism not shown, the wafer boat 5 can also be rotated.

The lower end part of the rotating shaft 10 is provided in the arm 13 instructed so that it can move up and down by the lifting mechanism which is not shown in figure. By the vertical movement of the arm 13, the wafer boat 5 is carried into the processing container 1, and is carried out. In addition, a magnetic fluid seal 11 is provided between the rotary shaft 10 and the opening of the lid portion 9, whereby the processing container 1 is sealed.

In addition, the MLD apparatus 80 includes an oxygen-containing gas supply mechanism 14 for supplying an oxygen-containing gas, for example, an O ₂ gas into the processing container 1, and a Si for supplying a Si source gas into the processing container 1. as a purge gas into the source gas supply mechanism 15, a treatment container (1) has a purge gas supply mechanism 16 for supplying N ₂ gas an inert gas, e.

The oxygen-containing gas supply mechanism 14 is connected to an oxygen-containing gas supply source 17, an oxygen-containing gas pipe 18 for guiding an oxygen-containing gas from the oxygen-containing gas supply source 17, and an oxygen-containing gas pipe 18. And an oxygen-containing gas dispersion nozzle 19 made of a quartz tube which penetrates the side wall of the manifold 3 inward and is bent upward and vertically extended. In the vertical portion of the oxygen-containing gas dispersion nozzle 19, a plurality of gas discharge holes 19a are formed at predetermined intervals, and are substantially uniform toward the processing container 1 in the horizontal direction from each gas discharge hole 19a. The oxygen-containing gas can be discharged.

In addition, the Si source gas supply mechanism 15 includes a Si source gas supply source 20, a Si source gas pipe 21 for guiding a Si source gas from the Si source gas supply source 20, and a Si source gas pipe 21. It has a Si source gas dispersion nozzle 22 which consists of a quartz tube which penetrates into the side wall of the manifold 3 inward, bends upward, and extends vertically. In the illustrated example, two Si source gas dispersion nozzles 22 are provided (see FIG. 6), and each of the Si source gas dispersion nozzles 22 is provided with a plurality of gas discharge holes 22a along the longitudinal direction thereof. It is formed at intervals of. Thereby, the Si source gas containing organic silicon can be discharged | emitted substantially uniformly in the processing container 1 in the horizontal direction from each gas discharge hole 22a. In addition, only one Si source gas dispersion nozzle 22 may be provided.

In addition, the purge gas supply mechanism 16 is connected to the purge gas supply source 23, the purge gas pipe 24 which guides the purge gas from the purge gas supply source 23, and the purge gas pipe 24, and the manifold is connected. It has the purge gas nozzle 25 provided through the side wall of (3). As the purge gas, an inert gas or an N ₂ gas can be appropriately used.

In the oxygen-containing gas pipe 18, the Si source gas pipe 21, and the purge gas pipe 24, flow controllers 18b, 21b, 24b, such as open / close valves 18a, 21a, 24a, and mass flow controllers, respectively, are provided. It is. By these, oxygen-containing gas, Si source gas, and purge gas can be supplied while controlling the flow rate, respectively.

A part of the side wall of the processing container 1 is provided with a plasma generating mechanism 30 for forming a plasma of an oxygen-containing gas. The plasma generating mechanism 30 has an opening 31 formed in the vertical and long sides on the side wall of the processing container 1, and a plasma compartment hermetically welded to the outer wall of the processing container 1 so as to cover the opening 31 from the outside. It has a wall 32. The plasma partition wall 32 has a cross-sectional recess shape and is formed thin and long vertically, for example, made of quartz. In addition, the plasma generating mechanism 30 includes a pair of elongated plasma electrodes 33 and plasma electrodes 33 disposed so as to face each other along the vertical direction on the outer surfaces of both side walls of the plasma partition wall 32. It is connected via the power supply line 34, and has the high frequency power supply 35 which supplies a high frequency electric power to the plasma electrode 33. As shown in FIG. The plasma of the oxygen-containing gas can be generated by applying, for example, a high frequency voltage of 13.56 MHz to the plasma electrode 33 from the high frequency power supply 35 to the plasma electrode 33. The frequency of the high frequency voltage is not limited to 13.56 MHz, but may be another frequency, for example, 400 Hz.

By forming the plasma partition wall 32 as described above, a part of the side wall of the processing container 1 is recessed outwardly in the shape of a recess, and the internal space of the plasma partition wall 32 is the processing container 1. Is communicated with the internal space. In addition, the opening 31 is formed sufficiently long in the vertical direction so as to cover all the wafers W held in the wafer boat 5 in the height direction.

The oxygen-containing gas dispersion nozzle 19 is bent radially outward of the processing container 1 in the middle of extending the inside of the processing container 1 upward, and is extended upward along the upstanding surface of the plasma partition wall 32. have. For this reason, when a high frequency voltage is applied from the high frequency power supply 35 to the plasma electrode 33, and a high frequency electric field is formed between the both electrodes 33, from the gas discharge hole 19a of the oxygen-containing gas dispersion nozzle 19 The discharged oxygen gas becomes plasma and flows toward the center of the processing container 1.

The outer side of the plasma partition wall 32 is covered with this, and an insulating protective cover 36 made of, for example, quartz is provided. In addition, a coolant passage (not shown) is provided in the inner portion of the insulating protective cover 36, and the plasma electrode 33 can be cooled by flowing, for example, cooled nitrogen gas.

The two Si source gas dispersion nozzles 22 stand up at positions sandwiching the opening 31 of the side wall of the processing container 1, and are provided with a plurality of gas discharge holes formed in the Si source gas dispersion nozzle 22. Si source gas can be discharged from 22a toward the center direction of the processing container 1. The Si source gas may be an aminosilane gas having one or two amino groups in one molecule.

On the other hand, the exhaust port 37 for exhausting the inside of the processing container 1 is formed in the part which opposes the opening 31 of the processing container 1. This exhaust port 37 is formed long and thin by scraping off the side wall of the processing container 1 in the up-down direction. On the outside of the processing container 1, an exhaust port cover member 38 formed in the shape of a cross-sectional recess to cover the exhaust port 37 is provided by welding. The exhaust port cover member 38 extends upward along the side wall of the processing container 1, and defines a gas outlet 39 above the processing container 1. And the inside of the processing container 1 is exhausted through the gas outlet 39 by the vacuum exhaust mechanism containing a vacuum pump etc. which are not shown in figure.

Moreover, the heating unit 40 of the housing shape which heats the processing container 1 and the wafer W inside it is provided so that the outer periphery of the processing container 1 may be enclosed. In addition, the heating unit 40 is abbreviate | omitted in FIG.

Control of each component of the MLD device 80, for example, supply / stop of each gas by opening and closing the valves 18a, 21a, 24a, control of the gas flow rate by the mass flow controllers 18b, 21b, 24b, and On / off control of the high frequency power supply 35, control of the heating unit 40, etc. are performed by the controller 50 which consists of a microprocessor (computer), for example. The controller 50 is connected to a user interface 51 including a keyboard for performing a command input operation or the like for the process manager to manage the MLD device 80, a display for displaying the operation status of the MLD device 80, and the like. have.

In addition, the controller 50 causes a control program for realizing various processes executed in the MLD apparatus 80 under the control of the controller 50, or causes the components of the MLD apparatus 80 to execute the processes in accordance with processing conditions. The storage unit 52 for storing a program, i.e., a recipe, is connected. The recipe is stored in the storage medium in the storage unit 52. The storage medium may be a hard disk or a semiconductor memory, or may be portable such as a CD-ROM, a DVD, a flash memory, or the like. In addition, the recipe may be appropriately transmitted from another device, for example, via a dedicated line.

Then, if necessary, an arbitrary recipe is called from the storage unit 52 by the instruction from the user interface 51 and executed in the controller 50, so that the MLD device 80 is controlled under the control of the controller 50. Desired processing is performed.

Next, referring to FIG. 5 to FIG. 7, in the MLD apparatus 80, the procedures for trimming the resist pattern 104a described above, depositing the silicon oxide film 105, and heating the wafer W are performed. Explain.

(Trimming)

For example, the wafer boat 5 on which 50 to 100 wafers W (for example, a silicon wafer having a diameter of 300 mm) is mounted is loaded into the processing container 1 from the lower end opening, and then the lower end The opening is sealed with the lid 9. After purging the inside of the processing container 1 with N ₂ gas, the O ₂ gas, for example, is supplied from the oxygen-containing gas supply mechanism 14 into the processing container 1 through the oxygen-containing gas dispersion nozzle 19. At the same time, the inside of the processing container 1 is exhausted by the vacuum exhaust mechanism not shown through the gas outlet 39, and the inside of the processing container 1 is maintained at a predetermined process pressure (point T1 in FIG. 7). Moreover, the wafer boat 5 is rotated as needed.

Subsequently, high frequency power is supplied from the high frequency power supply 35 of the plasma generating mechanism 30 to the plasma electrode 33 to start trimming of the resist pattern 104a formed on the wafer W (Fig. 7). Time point T2). By the supply of high frequency power, the oxygen plasma is ignited in the plasma partition wall 32. Oxygen radicals and the like excited in the oxygen plasma flow toward the wafer boat 5, whereby the wafer W held in the wafer boat 5 is exposed to the oxygen radicals. Then, at this time, the resist pattern 104a exposed to the surface of the wafer W is carbonized by oxygen radicals, the resist pattern 104a is trimmed, and the resist pattern 104b is obtained.

Illustrating this trimming condition, the flow rate of the oxygen-containing gas (O ₂ gas) is 100 to 20000 mL / min (sccm), depending on the number of wafers W mounted on the wafer boat 5, and the processing container ( The pressure in 1) is 13.3 to 665 Hz, the frequency of the high frequency power supply 35 is 13.56 MHz, the high frequency power is 5 to 1000 W, and the trimming time is 1 to 7200 seconds. As the oxygen-containing gas, in addition to O ₂ gas, NO gas, N ₂ O gas, H ₂ O gas, and O ₃ gas may be used. In addition, although the temperature of the wafer W during trimming may be room temperature to 300 degreeC, as described below, since the silicon oxide film 105 performed continuously is deposited at normal temperature, it is preferable at normal temperature. This is because the time required for temperature adjustment can be omitted and the throughput can be increased.

[Deposition of Silicon Oxide Film 105]

Next, the deposition of the silicon oxide film 105 performed in the MLD apparatus 80 following the trimming of the resist pattern 104a will be described with reference to FIGS. 5 to 7.

First, after the supply of the high frequency electric power to the plasma electrode 33 (FIGS. 5 and 6) is stopped (time T3), the purge gas piping 24 is removed from the purge gas supply source 23 of the purge gas supply mechanism 16. And the purge gas (N ₂ gas) is supplied through the purge gas nozzle 25 to purge the O ₂ gas used for trimming from the processing container 1. The purge gas flow rate at this time may be 0.1 to 10000 mL / min (sccm), for example, and the purge time may be 1 to 7200 seconds.

Subsequently, while maintaining the inside of the processing container 1 at a predetermined process pressure, the temperature of the wafer W is maintained at room temperature, the wafer boat 5 is rotated, and a film forming process is started (time T4).

As shown in FIG. 7, in this embodiment, the process (SSi) which makes Si source adsorb | suck to the wafer W by flowing Si source gas containing organic silicon in the processing container 1, and the processing container 1 A step (PSi) of purging the Si source gas therein with N ₂ gas and a step of oxidizing the Si source gas adsorbed to the wafer (W) by exposing the wafer (W) to oxygen radicals generated by exciting the oxygen-containing gas. this cycle is repeated and a step (Po) for purging the oxygen radicals and the oxygen gas to the N ₂ gas in the (So) and the process vessel (1). As a result, the Si source gas and the oxygen radical do not react in the gas phase in the processing container 1, and the Si source gas adsorbed at the molecular layer level on the wafer W is caused by the oxygen radical (even if the wafer temperature is normal temperature). It is oxidized and the silicon oxide film 105 is formed on the wafer (W). In addition, since the silicon oxide layer of one molecular layer (or water molecule layer) can be deposited every cycle, the thickness D of the silicon oxide film 105 can be controlled according to the number of cycles.

In this embodiment, specifically, Si source gas is BTBAS gas, the flow volume is 10-500 mL / min (sccm), and the required time of the process (SSi) which supplies BTBAS should just be 1-600 second. In addition, the flow rate of the O ₂ gas for generating oxygen radicals is 100 to 20000 mL / min (sccm), and the time required for the step (So) of oxidizing the BTBAS gas adsorbed to the wafer W by the oxygen radicals is 1 to 600. Seconds are fine. In the step (So), the frequency of the high frequency power supplied from the high frequency power supply 35 to the plasma electrode 33 may be 13.56 MHz, and the power may be 5 to 1000W. In addition, the pressure in the process container 1 in a process SSi and a process So should just be 13.3-665 Pa.

In the purge processes PSi and Po, the flow rate of the N ₂ gas as the purge gas is 0.1 to 5000 mL / min (sccm), the required time is 1 to 60 seconds, and the pressure in the processing container 1 is 0.133 to 665. ㎩can be.

The deposition of the silicon oxide film 105 is terminated when the number of cycles for achieving the thickness D of the silicon oxide film 105 is reached.

[Heating of Silicon Oxide Film 105]

Next, the heating of the silicon oxide film 105 performed in the MLD apparatus 80 following the deposition of the silicon oxide film 105 will be described.

After the deposition of the silicon oxide film 105 is finished, the N ₂ gas is discharged from the purge gas supply mechanism through the purge gas nozzle 25 while leaving the wafer W (wafer boat 5) in the processing apparatus 1. By supplying, the inside of the processing container 1 is purged and the pressure in the processing container 1 is maintained at a pressure of, for example, 13.3 to 10.1 × 10 ⁴ Pa. Next, the power supply to the heating unit 40 is started (time T5), and the wafer temperature is maintained at a predetermined temperature in the range of, for example, 150 ° C to 630 ° C. After the wafer W is heated at a predetermined temperature, for example, for a predetermined period ranging from 1 to 3600 seconds, the silicon oxide film 105 on the wafer W is densified.

Thereafter, the power supply to the heating unit 40 is stopped, the heating of the silicon oxide film 105 is finished (time T6), and the wafer W 5 is taken out of the processing container 1 to carry out the wafer W. Take out.

As described above, according to the MLD apparatus 80, the trimming of the resist pattern 104a (formation of the resist pattern 104b), the deposition of the silicon oxide film 105, and the heating of the silicon oxide film 105 can be performed continuously. As a result, there is no fear of contamination of the wafer accompanying the loading and unloading of the wafer W between the respective processing apparatuses. In addition, since the time required for carrying in and out of the wafer W can be saved, the throughput can be increased.

(2nd embodiment)

Next, the fine pattern formation method by 2nd Embodiment of this invention is demonstrated, referring FIG. The fine pattern formation method by this embodiment includes step S801 thru | or S810 as shown in FIG.

As shown in FIG. 9A, first, a thin film 102 is formed on the wafer W (S801 in FIG. 8), and an organic film 103 is formed on the thin film 102 (S802). . The thin film 102 is formed of, for example, amorphous silicon, polysilicon, or the like, and is a patterning target film that is later patterned in the present embodiment. In another embodiment, the thin film 102 may be used as a mask for etching the wafer W after being patterned. The thickness of the thin film 102 is not particularly limited, and may be, for example, 20 to 200 nm.

The organic film 103 is later patterned and used as a mask for patterning the thin film 102. The organic film 103 is an antireflection film BARC that prevents multiple reflection of exposure light generated in the resist film 104 when the resist film 104 formed on the organic film 103 is exposed in the present embodiment. : Bottom Anti-Reflecting Coating. The thickness of the organic film 103 is not specifically limited, For example, what is necessary is just 150-300 nm.

Referring to FIG. 9B, a resist film 104 is formed on the organic film 103 (step S803). The resist film 104 is formed of an ArF resist in this embodiment. The thickness of the resist film 104 is not particularly limited, and may be, for example, 50 to 200 nm.

Next, the resist film 104 is patterned by photolithography using a predetermined photomask, and a resist pattern 104a is formed as shown in Fig. 9C (step S804). The line width LL4 and the space width SS4 of the resist pattern 104a are all 60 nm, for example in this embodiment.

Subsequently, as shown in Fig. 9D, the resist pattern 104a is trimmed (or slimmed) to obtain a trimmed resist pattern 104b (step S805). As a result of trimming, the line width LL1 of the resist pattern 104b is narrower, for example 30 nm, than the line width LL4 (for example 60 nm) of the resist pattern 104a, and the resist pattern 104b The space width SS1 of is larger than the space width SS4 (for example, 60 nm) of the resist pattern 104a, for example, 90 nm. The trimming is not particularly limited, but is performed by exposing the wafer W on which the resist pattern 104a is formed to ozone gas or to oxygen radicals obtained by exciting the oxygen-containing gas. The temperature of the wafer W at this time may be room temperature to 100 degreeC.

Referring to FIG. 10E, a silicon oxide film 105 is deposited on the organic film 103 exposed to the space of the resist pattern 104b so as to cover the resist pattern 104b (step S806). The silicon oxide film 105 is deposited in a normal temperature atmosphere, preferably by a molecular layer deposition (MLD) method. According to the MLD method, deposition (conformal) reflecting the shape of the underlying layer is possible. For this reason, the silicon oxide film 105 which has a deposition surface substantially parallel to this side surface can be deposited on the side surface of the resist pattern 104b, and when the thickness on the organic film 103 is set to D1, The thicknesses on the top and side surfaces of the pattern 104b are also approximately D1. Here, thickness D1 is not specifically limited, For example, it can be 15 nm.

Next, as shown in FIG. 10F, a silicon nitride film 110 is deposited on the silicon oxide film 105. The temperature of the wafer W at this time should just be the temperature of the range of 300-630 degreeC, for example, It should just be the temperature of the range of 300-400 degreeC, for example, it is more preferable if it is about 300 degreeC. In addition, in this embodiment, the thickness of the silicon nitride 110 is adjusted so that the sum total with the thickness D1 of the silicon oxide film 105 of the underlying layer may be the thickness D (30 nm). That is, in this embodiment, the ratio of the thickness of the silicon oxide film 105 and the thickness of the silicon nitride film 110 is 1: 1.

In addition, the MLD apparatus 80 can also be used for depositing the silicon nitride film 110. According to this, the silicon nitride film 110 may also have a conformal shape due to molecular layer growth, and the side surface of the sidewall portion 105a formed by the later etch back is upright with respect to the upper surface of the organic film 103. You can. In addition, after deposition of the silicon oxide film 105 at room temperature, the temperature of the wafer W is adjusted without carrying out the wafer W (wafer boat 5), and then the silicon nitride film 110 is continued. Can be deposited. In this case, the BTBAS gas used for the deposition of the silicon oxide film 105 can be used as the Si source gas for the deposition of the silicon nitride, and the BTBAS gas adsorbed to the silicon oxide film 105 on the wafer W is nitrided. As the nitriding gas, ammonia (NH ₃ ), hydrazine (N ₂ H ₂ ), or the like can be used. In addition, when using the MLD apparatus 80 shown in FIG. 5 and FIG. 6, it goes without saying that it is necessary to add the nitriding gas supply mechanism which has the same structure as the oxygen containing gas supply mechanism 14. As shown in FIG.

Next, as shown in FIG. 10G, the two-layer film of the silicon oxide film 105 and the silicon nitride film 110 is etched back, and the two layers on the resist pattern 104b and the organic film 103 are etched back. When the film is removed, the third pattern 106 including the resist pattern 104b and the sidewall portion 105a derived from the silicon oxide film 105 and the sidewall portion 110a derived from the silicon nitride film 110 is formed. Obtained. As described above, since the total thickness of the silicon oxide film 105 and the silicon nitride film 110 is D, the line width LL3 (or the space width SS3) of the third pattern 106 is determined by the first embodiment. It becomes equal to the line width LL3 (or the space width SS3) of the third pattern 106 in FIG.

Subsequently, the resist pattern 104b is removed in the same manner as the method described in the first embodiment, whereby the organic film 103 is etched by the sidewall portions 105a and 110a remaining on the organic film 103. Then, as shown in Fig. 10H, an etching mask 107 is obtained. In addition, for convenience of description, in the following description, it is called the side wall part 115, without distinguishing the side wall parts 105a and 110a.

In the method for forming a fine pattern according to the present embodiment, the sidewall portion 115 used as the etching mask includes the silicon oxide film 105 deposited so as to cover the resist pattern 104 and the silicon nitride film deposited thereon ( 110). Since the silicon nitride film 110 is deposited on the silicon oxide film 105 deposited at room temperature on the resist pattern 104, the silicon oxide film 105 is formed in accordance with the difference in the coefficient of thermal expansion of silicon oxide and silicon nitride. Two-dimensional tensile stress is applied. For this reason, it can suppress that the side wall part 115 inclines. That is, it becomes possible to use the resist pattern 105a as a foundation (base) for the formation of the side wall portion 115.

In addition, since the silicon nitride film 110 is deposited at a high temperature on the silicon oxide film 105 deposited at room temperature, the silicon oxide film 105 is subjected to substantially heat treatment. For this reason, in addition to the tensile stress accompanying the high density by heat processing, the tensile stress by the silicon nitride film 110 is applied to the silicon oxide film 105. Therefore, even after removing the resist pattern 104b after forming the side wall portion 115 by the etch back, it is possible to more reliably suppress the inclination of the side wall portion 115.

Next, the experiment and the result which were performed in order to confirm the effect of embodiment of this invention are demonstrated. In this experiment, the tensile stress applied to the silicon oxide film was measured using a general-purpose thin film stress measuring device. First, the outline of the measuring device used for this measurement and a measuring principle are demonstrated.

It is a schematic diagram of the measuring apparatus used for the measurement of a stress. As shown in the drawing, the measuring device 70 includes a stage S on which a wafer W is loaded, and a laser element LD that irradiates a laser light L onto a wafer W loaded on a stage S. And a mirror M for reflecting the laser light L from the laser element LD and irradiating the surface of the wafer W, and a detector for detecting the laser light L reflected from the surface of the wafer W. (PD). In addition, the measuring device 70 controls the laser element LD, the mirror M, the detector PD, and the like, and simultaneously reflects the following reflection angles from the positions of the mirror M and the detector PD with respect to the wafer W. A control unit (not shown) for obtaining (θ) is included. The mirror M can be moved so as to irradiate the laser light L from a direction perpendicular to an approximately entire surface of the surface of the wafer W by an instruction signal from the controller, and also to the angle with respect to the wafer W. Is configured to be adjusted. In addition, the detector PD can move with the movement of the mirror M, whereby the reflected laser light L from the wafer W can be detected.

When the reflection laser light L from the wafer W is detected by the detector PD while moving the mirror M, the reflection angle θ of the laser light L at each measurement point can be obtained. Thereby, the average curvature R of the wafer W is calculated | required. In this manner, the average curvature Rb of the wafer W after deposition of the silicon oxide film 105 and the wafer W after heating (or after deposition of the silicon nitride film 110) of the silicon oxide film 105. When the average curvature Ra of?) Is obtained, the stress? Applied to the silicon oxide film 105 can be calculated from the following relational formula (1).

here,

E _w : Elastic modulus of the wafer (W)

ν _w : Poisson's ratio of wafer (W)

t _w : thickness of wafer (W)

t _f : thickness of the silicon oxide film 105

Next, referring to FIG. 12, the heat treatment temperature dependence of the tensile stress applied to the silicon oxide film 105 deposited at normal temperature by the heat treatment process (step S107 in FIG. 1, FIG. 3 (f)). Explain.

First, three bare wafers having a diameter of 300 mm were prepared, and a silicon oxide film having a film thickness of 17.5 nm was deposited thereon at room temperature. At this time, deposition conditions such as the supply amount of the silicon raw material gas were the same for the three wafers. Next, one of these three wafers was heat treated at about 300 ° C, the other wafer was heat treated at about 450 ° C, and the remaining one wafer was heat treated at about 630 ° C. In addition, before and after the heat treatment, the warpage of the wafer was measured as described above, and the tensile stress applied to the silicon oxide film was calculated based on the above equation (1). In addition, before and after deposition at room temperature of the silicon oxide film, the warpage of the wafer was measured to determine the tensile stress generated on the wafer due to the deposition of the silicon oxide film.

Referring to Fig. 12, it is understood that a tensile stress was hardly applied after the silicon oxide film was deposited (see the left end column), but a relatively large tensile stress was applied after the heat treatment. Moreover, it turns out that the tensile stress applied to a silicon oxide film becomes large by raising heat processing temperature to about 300 degreeC, about 450 degreeC, and about 630 degreeC. This is considered to be because the temperature of the heat treatment increases, and moisture, impurities, and the like in the silicon oxide film deposited at room temperature are released, thereby making it more compact.

Next, with reference to FIG. 13, the result of the experiment performed in order to confirm the effect of 1st Embodiment and 2nd Embodiment of this invention is demonstrated. FIG. 13: shows typically the observation result which observed the sample obtained by experiment with the scanning microscope (SEM).

In FIG. 13, the upper row indicated by "no heat treatment" does not perform cross-section and heat treatment after depositing the silicon oxide film 105 (thickness 17.5 nm) at room temperature so as to cover the resist pattern 104b from the left side. The cross section after the silicon oxide film 105 is etched back and the cross section after removing the resist pattern 104b are schematically shown. That is, the later cross section of each step when step S106, S108, and S109 in FIG. 1 is performed sequentially is shown, and it corresponds to the comparative example which did not perform heat processing (step S107).

In the center row indicated by " with heating treatment, " the silicon oxide film 105 is deposited from the left side at a room temperature so as to cover the resist pattern 104b, and the cross section after the heat treatment and the heat treatment are performed. The cross section after etching back and the cross section after removing the resist pattern 104b are typically shown. That is, the cross section after each step of step S107, S108, and S109 when step S106, S107, S108, and S109 in FIG. 1 is performed sequentially is shown, and corresponds to 1st Embodiment.

The lower row indicated as "SiN film deposition" deposits the silicon oxide film 105 at room temperature so as to cover the resist pattern 104b from the left side, and the silicon nitride film 110 on the silicon oxide film 105. The cross section after depositing, the cross section after etching back the silicon nitride film 110, and the silicon oxide film 105, and the cross section after removing the resist pattern 104b are typically shown. That is, the cross section after each step when step S807, S808, and S809 in FIG. 8 is performed sequentially is shown, and corresponds to 2nd Embodiment.

Referring to FIG. 13, when the heat treatment is not performed, after the etch back, the side wall portions 105a on both sides of one resist pattern 104b are inclined to each other, and the resist pattern 104b and the side wall portions 105a on both sides are etched. ) Has a trapezoidal cross section as a whole.

On the other hand, in the case of "with heating treatment", the inclination of the two side wall portions 105a is suppressed after the etch back, and therefore, after removing the resist pattern 104b therebetween, the side wall portions 105a are removed. Although the front end part is bent inward slightly, the space | interval of two side wall part 105a becomes wider than the space | interval in the case of "no heating process." That is, according to the first embodiment of the present invention, even when the sidewall portion 105a is formed based on the resist pattern 104b, the inclination of the sidewall portion 105a is suppressed. Therefore, it becomes possible to form a pattern having a uniform line width and a space width.

In the case of " SiN film deposition ", the two side wall portions 105a are almost upright, and no curvature at the tip portion is also seen. From this, the effect of 2nd Embodiment is understood.

Next, the result of the experiment which was performed again in order to confirm the effect of embodiment of this invention again is demonstrated.

14 is a graph showing the deposition temperature dependency of the tensile stress applied to the silicon nitride film. In this experiment, the warpage of the wafer was measured before and after the silicon nitride film was deposited on the bare wafer using the above-described measuring device 70 (Fig. 11), and it acts in the deposited silicon nitride film based on Equation (1). Tensile stress was calculated | required. In addition, the film thickness of the silicon nitride film was about 5 nm.

As shown in this graph, when the silicon nitride film was deposited at a deposition temperature ranging from about 450 ° C to about 520 ° C, it can be seen that a relatively large tensile stress of about 1.5 kPa is applied to the silicon nitride film. . Further, even when the deposition temperature is about 400 ° C and 550 ° C, a tensile stress of about 1.2 kPa acts. That is, it is expected that the inclination of the sidewall portion 115 is further suppressed by depositing the silicon nitride film in such a temperature range.

FIG. 15 shows the measurement result of the opening width CD of the side wall portion 115 after removing the resist pattern 104b (FIG. 10G). Here, Top CD represents the opening width in the upper end part of the opening of the side wall part 115, and Bottom CD represents the opening width in the lower end part of the opening of the side wall part 115 (width along an underlying layer). In addition, the opening width of the side wall portion 105b after removing the resist pattern 104b in Fig. 3G is also shown (see "Silicone Oxide Film + Heating Treatment" in Fig. 15). The film thickness of the silicon oxide film 105 (FIG. 10E) deposited at room temperature is about 10 nm, and the film thickness of the silicon nitride film 110 (FIG. 10F) is about 5 nm. to be.

Referring to FIG. 15, when the silicon nitride film 110 is deposited at a deposition temperature of 400 ° C. on the silicon oxide film 105 deposited at room temperature, the opening of the sidewall portion 115 is approximately at the upper end and at the lower end. It became the value substantially equivalent to 23 nm. This result shows that the side wall part 115 is standing upright substantially without inclination. On the other hand, when the silicon nitride film 110 was deposited at the deposition temperature of 630 ° C., the opening of the sidewall portion 115 was about 22 nm at the upper end and about 16 nm at the lower end. Even in the case of the deposition temperature of 630 ° C, the inclination of the side wall portion 115 is sufficiently reduced, but the result of the deposition temperature of 400 ° C is more preferable. This is considered to be because the tensile stress acting on the silicon nitride film deposited at the deposition temperature of 400 ° C is larger than the tensile stress acting on the silicon nitride film deposited at the deposition temperature of 630 ° C.

Further, even when the silicon oxide film 105 is deposited at room temperature without depositing the silicon nitride film 110, the inclination of the sidewall portion 105a (Fig. 3 (h)) is sufficiently suppressed. It is. When the silicon nitride film 110 is deposited, the silicon oxide film 105 is substantially heated while the temperature is raised to the deposition temperature.

Moreover, since the ratio regarding the film thickness of the silicon oxide film 105 and the film thickness of the silicon nitride film 110 was examined, the result is shown in FIG. When room temperature deposition and heat treatment of the silicon oxide film 105 were performed, the opening width of the side wall portion 105a was narrow at the upper end regardless of the film thickness of the silicon oxide film 105. On the other hand, in the case where the silicon nitride film 110 is deposited (deposit temperature 400 ° C.), the opening width of the sidewall portion 115 depends on the relative film thickness of the silicon nitride film 110 with respect to the silicon oxide film 105. I could see that. As a result of the experiment, when the thickness of the silicon nitride film 110 is 5 nm, when the thickness of the silicon oxide film 105 is 20 nm, the opening width of the side wall portion 115 becomes narrow at the upper end portion. However, when the thickness of the silicon nitride film 110 is 5 nm (when the silicon nitride film 110 is relatively thick), the side wall portion 115 is substantially upright, even at the upper end and at the lower end. Can be.

As mentioned above, although this invention was demonstrated referring some embodiment and the experiment result, this invention is not limited to embodiment mentioned above, In the light of description of an attached claim, various deformation | transformation and change are possible. .

For example, as a Si source gas, the aminosilane gas which has two amino groups in 1 molecule can be used. Such aminosilane gas includes BTBAS gas, bisdiethylaminosilane (BDBAS), and bisdimethylaminosilane (BDMAS) gas. As the Si source gas, it is also possible to use an aminosilane gas having three or more amino groups in one molecule (for example, trisdimethylaminosilane (3DMAS)) or an aminosilane gas having one amino group in one molecule. Do.

Dichlorosilane (DCS), hexachlorodisilane (HCD), tetraethoxysilane (TEOS), or the like may be used as a source gas for forming a molecular layer of a silicon oxide film or a silicon nitride film.

In addition, the wafer W may not only represent a bare wafer of semiconductor but may be a semiconductor wafer in which various conductive patterns, insulating layers, etc. are formed in the process of manufacturing a semiconductor element or an integrated circuit pattern.

Note that the above-described line width and space width are merely examples, and may be appropriately determined in addition to the semiconductor device or integrated circuit fabricated inside or on the wafer W by the fine pattern forming method according to the embodiment of the present invention. It goes without saying that the pattern may also be appropriately determined.

W: Wafer
102: thin film
103: organic film (reflective film)
104: resist film
104a, 104b: resist pattern
105: silicon oxide film
105a: side wall portion
107: etching mask
110: silicon nitride film
80: MLD device

Claims (6)

An organic film forming step of forming an organic film on the etching target layer formed on the substrate,
A patterning step of forming a resist film on the organic film to pattern the resist film;
A first deposition step of depositing a silicon oxide film at room temperature so as to cover the organic film exposed from the patterned resist film and the patterned resist film;
A processing step of heating the substrate on which the silicon oxide is deposited to generate a tensile stress in the silicon oxide film;
A first etching step of etching the silicon oxide film so that the silicon oxide film remains on sidewalls of the patterned resist film;
And a removing step of removing the patterned resist film. The method of forming a fine pattern according to claim 1, further comprising a second deposition step of depositing a silicon nitride film on the silicon oxide film heated in the processing step. The method of forming a fine pattern according to claim 1, further comprising a second etching step of etching the etching target layer using the silicon oxide film remaining on the organic film after the removing step. The method of forming a fine pattern according to claim 3, further comprising a first substrate etching step of etching the substrate using the etching target layer etched in the second etching step as an etching mask. The fine pattern forming method according to claim 2, further comprising a third etching step of etching the etching target layer using the silicon oxide film and the silicon nitride film remaining on the organic film after the removing step. The method of forming a fine pattern according to claim 5, further comprising a second substrate etching step of etching the substrate using the etching target layer etched in the third etching step as an etching mask.

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