JP2016048735A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a loss at the time when a semiconductor device is turned on.SOLUTION: A semiconductor device comprises an N-type semiconductor layer 2, a P-type base region 3, an N-type source region 4, a P-type contact region 5, a gate insulating film 6, a gate electrode 7, and a source electrode 8, on an N-type semiconductor substrate 1 formed of silicon carbide. The semiconductor device has a drain electrode 9 on a rear face of the semiconductor substrate 1. The gate electrode 7 is formed of a metal. A polysilicon layer 10 formed of polysilicon is provided under a terminal end part of the gate electrode 7.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

FIG. 5 is a cross-sectional view showing a first example of a conventional semiconductor device. As shown in FIG. 5, the semiconductor device has n-type silicon carbide semiconductor layer 102 on the front surface of n ⁺ -type silicon carbide semiconductor substrate 101. A plurality of p-type semiconductor regions 103 are provided in the surface region of n-type silicon carbide semiconductor layer 102. An n ⁺ type source region 104 and a p ⁺ type contact region 105 are provided in the surface region of the p type semiconductor region 103. A gate electrode 107 is provided on the p-type semiconductor region 103 between the n ⁺ -type source region 104 and the n-type silicon carbide semiconductor layer 102 with a gate insulating film 106 interposed therebetween. A source electrode 108 is in contact with the n ⁺ type source region 104 and the p ⁺ type contact region 105. A drain electrode 109 is formed on the back surface of n ⁺ -type silicon carbide semiconductor substrate 101.

FIG. 6 is a cross-sectional view showing a second example of a conventional semiconductor device. As shown in FIG. 6, the semiconductor device has n-type silicon carbide semiconductor layer 202 on the front surface of n ⁺ -type silicon carbide semiconductor substrate 201. A plurality of p ⁺ type semiconductor regions 210 are provided in the surface region of n type silicon carbide semiconductor layer 202. A p-type silicon carbide semiconductor layer 211 is provided on p ⁺ -type semiconductor region 210 and n-type silicon carbide semiconductor layer 202. In p-type silicon carbide semiconductor layer 211, n-type semiconductor region 212 is provided on n-type silicon carbide semiconductor layer 202 between adjacent p ⁺ -type semiconductor region 210 and p ⁺ -type semiconductor region 210. . In p-type silicon carbide semiconductor layer 211, p-type semiconductor region 203, n ⁺ -type source region 204, and p ⁺ -type contact region 205 are provided on each p ⁺ -type semiconductor region 210. A gate electrode 207 is provided on the p-type semiconductor region 203 between the n ⁺ -type source region 204 and the n-type semiconductor region 212 with a gate insulating film 206 interposed therebetween. A source electrode 208 is in contact with the n ⁺ type source region 204 and the p ⁺ type contact region 205. A drain electrode 209 is formed on the back surface of n ⁺ -type silicon carbide semiconductor substrate 201.

  A semiconductor device similar to the first example or the second example described above is disclosed in which the gate electrode is made of polysilicon (for example, see Patent Documents 1 and 2).

JP 2013-187302 A JP 2013-102106 A

  In a semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), when a voltage higher than a threshold is applied to the gate electrode when a high potential is applied to the drain electrode, the capacitance between the drain and the source is increased. The charged charge is discharged through the gate and drain. In the conventional silicon carbide semiconductor device described above, since the gate electrode is made of polysilicon, the resistance of the gate electrode is relatively large. Therefore, the gate voltage rises due to the discharge current that flows when the charge charged in the drain-source capacitance is discharged via the gate-drain. As a result, the threshold voltage Vth is transiently lowered, an excessive current flows between the drain and the source, and there is a problem that the loss increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a semiconductor device manufacturing method capable of suppressing a loss at turn-on in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention includes a semiconductor substrate made of silicon carbide of a first conductivity type, and the semiconductor substrate provided on the first main surface of the semiconductor substrate. A first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate, a second conductivity type base region provided on the surface of the semiconductor layer, and a first conductivity type provided in the surface region of the base region Source region, a second conductivity type contact region having an impurity concentration higher than that of the base region, a source electrode in contact with the source region and the contact region, and the base region A gate insulating film provided on a surface of a region sandwiched between the semiconductor layer and the source region, a gate electrode provided on the surface of the gate insulating film, and a second main body of the semiconductor substrate Includes a drain electrode provided above the, the gate electrode is characterized in that is made of metal.

  In addition, a semiconductor device according to the present invention includes a semiconductor substrate made of silicon carbide of a first conductivity type, and a first conductivity having a lower impurity concentration than the semiconductor substrate provided on the first main surface of the semiconductor substrate. Type semiconductor layer, a second conductivity type semiconductor region provided in a part of the surface region of the semiconductor layer, and a second impurity concentration lower than that of the semiconductor region provided on the surface of the semiconductor region. A conductivity type base region; a well region made of silicon carbide of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate provided on the surface of the semiconductor layer in contact with the base region; and the base region A source region of a first conductivity type having a higher impurity concentration than the well region, which is provided in a surface region of the semiconductor region, and on the surface of the semiconductor region, in contact with the source region and the base region. The second conductivity type contact region having a higher impurity concentration than the base region, the source region and the source electrode in contact with the contact region, and the well region and the source region of the base region. A gate insulating film provided on the surface of the region, a gate electrode provided on the surface of the gate insulating film, and a drain electrode provided on the second main surface of the semiconductor substrate, The gate electrode is made of metal.

  Further, a layer made of polysilicon is provided under the terminal portion of the gate electrode.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a semiconductor substrate made of silicon carbide of a first conductivity type; and an impurity concentration lower than that of the semiconductor substrate provided on the first main surface of the semiconductor substrate. A first conductivity type semiconductor layer; a second conductivity type base region provided on a surface of the semiconductor layer; a first conductivity type source region provided in a surface region of the base region; and the base region A contact region of a second conductivity type having a higher impurity concentration than the base region, a source electrode in contact with the source region and the contact region, and the semiconductor layer and the source of the base region A gate insulating film provided on the surface of the region sandwiched between the regions, a gate electrode provided on the surface of the gate insulating film, and a drain electrode provided on the second main surface of the semiconductor substrate. If, in the manufacturing method of a semiconductor device having a, characterized in that the gate electrode is formed by metal.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a semiconductor substrate made of silicon carbide of a first conductivity type; and an impurity concentration lower than that of the semiconductor substrate provided on the first main surface of the semiconductor substrate. A first conductivity type semiconductor layer; a second conductivity type semiconductor region provided in a part of a surface region of the semiconductor layer; and an impurity concentration higher than that of the semiconductor region provided on the surface of the semiconductor region. A base region of a low second conductivity type, and a well region made of silicon carbide of the first conductivity type having a lower impurity concentration than the semiconductor substrate provided on the surface of the semiconductor layer in contact with the base region; A source region of a first conductivity type having a higher impurity concentration than the well region, provided in a surface region of the base region apart from the well region; and the source region and the base region on the surface of the semiconductor region A contact region of a second conductivity type having a higher impurity concentration than the base region, a source electrode in contact with the source region and the contact region, the well region and the source region of the base region, A gate insulating film provided on the surface of the region sandwiched between, a gate electrode provided on the surface of the gate insulating film, and a drain electrode provided on the second main surface of the semiconductor substrate, In the semiconductor device manufacturing method provided, the gate electrode is made of metal.

  According to the present invention, since the gate electrode is made of a metal having a resistance smaller than that of polysilicon, the time constant determined by the product of the gate-drain capacitance and the gate electrode resistance is reduced. As a result, the charge charged in the drain-source capacitance is discharged at turn-on, the gate-source potential is lowered, and an increase in current at turn-on is suppressed. Further, the unevenness of the surface of the layer made of polysilicon increases the adhesion strength between the terminal portion of the gate electrode and the surface of the layer made of polysilicon, so that the gate electrode is hardly peeled off.

  According to the present invention, loss at turn-on can be suppressed.

It is sectional drawing which shows an example of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing which shows an example of the semiconductor device concerning Embodiment 2 of this invention. It is a wave form diagram which shows an example of the current-voltage waveform at the time of turn-on of the semiconductor device concerning Embodiment 1, 2 of this invention. It is a wave form diagram which shows an example of the current-voltage waveform at the time of turn-on of the conventional semiconductor device. It is sectional drawing which shows the 1st example of the conventional semiconductor device. It is sectional drawing which shows the 2nd example of the conventional semiconductor device.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached thereto.

(Embodiment 1)
Example of Semiconductor Device According to First Embodiment FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to the first embodiment of the present invention. FIG. 1 shows an active region of the semiconductor device according to the first embodiment. In the active region, a MOS structure of a semiconductor device, that is, an element structure is formed. In the example shown in FIG. 1, only one MOS structure is shown in the active region, but a plurality of MOS structures may be provided in parallel. The active region may be surrounded by a breakdown voltage structure (not shown).

As shown in FIG. 1, the semiconductor device includes an n ⁺ semiconductor substrate 1 and an n semiconductor layer 2 made of silicon carbide. N ⁺ semiconductor substrate 1 may be, for example, a silicon carbide single crystal substrate in which silicon carbide is doped with an N-type impurity. The n ⁺ semiconductor substrate 1 becomes a drain region, for example. In the description of the present embodiment, it is assumed that the front surface of the n ⁺ semiconductor substrate 1 is the first main surface and the back surface is the second main surface.

The n semiconductor layer 2 is provided on the first main surface of the n ⁺ semiconductor substrate 1. The impurity concentration of the n semiconductor layer 2 is lower than that of the n ⁺ semiconductor substrate 1. The n semiconductor layer 2 may be a semiconductor layer in which silicon carbide is doped with an N-type impurity, for example. The n semiconductor layer 2 becomes an N type drift layer, for example.

The semiconductor device has, for example, a p base region 3, an n ⁺ source region 4, a p ⁺ contact region 5, a gate insulating film 6, a gate electrode 7 and a source electrode as a MOS structure on the first main surface side of the n ⁺ semiconductor substrate 1. 8 is provided. The semiconductor device is provided with a back surface electrode to be, for example, the drain electrode 9 on the second main surface side of the n ⁺ semiconductor substrate 1.

  The p base region 3 is provided in a part of the surface region of the n semiconductor layer 2. The p base region 3 may be provided, for example, so as to sandwich another part of the surface region of the n semiconductor layer 2. That is, there may be a region of the n semiconductor layer 2 between the adjacent p base regions 3 and 3. The p base region 3 may be a semiconductor region in which silicon carbide is doped with a P-type impurity, for example.

The n ⁺ source region 4 is provided in the surface region of the p base region 3. N ⁺ source region 4 is provided apart from the region of n semiconductor layer 2 between adjacent p base region 3 and p base region 3. The impurity concentration of the n ⁺ source region 4 is higher than that of the n semiconductor layer 2.

In the surface region of p base region 3, p ⁺ contact region 5 is provided away from the region of n semiconductor layer 2 between adjacent p base region 3 and p base region 3. The p ⁺ contact region 5 is in contact with the p base region 3 and the n ⁺ source region 4. The impurity concentration of the p ⁺ contact region 5 is higher than that of the p base region 3.

Gate insulating film 6 is provided on the surface of p base region 3, which is sandwiched between n semiconductor layer 2 region and n ⁺ source region 4 between adjacent p base region 3 and p base region 3. It has been. The gate insulating film 6 is formed, for example, on the surface of one p base region 3 adjacent to the n semiconductor layer 2 through the surface of the n semiconductor layer 2 and on the surface of the other p base region 3. It may extend to.

  The gate electrode 7 is provided on the surface of the gate insulating film 6. The gate electrode 7 extends, for example, from one p base region 3 adjacent to the n semiconductor layer 2 across the region to the other p base region 3 through the surface of the n semiconductor layer 2 region. May be. The gate electrode 7 may be made of a conductive material having a smaller resistance than polysilicon. The gate electrode 7 may be made of metal, for example. The gate electrode 7 may be made of, for example, aluminum (Al) or titanium nitride (TiN), or a metal (Ti / Al) having a structure in which titanium (Ti) and aluminum are stacked. A polysilicon layer 10 made of polysilicon is provided under the terminal portion of the gate electrode 7.

The source electrode 8, the surface of the n ⁺ source region 4 and the p ⁺ contact region 5 is provided in contact with the n ⁺ source region 4 and the p ⁺ contact region 5. Source electrode 8 is electrically connected to n ⁺ source region 4 and p ⁺ contact region 5. The source electrode 8 is insulated from the gate electrode 7 by an interlayer insulating film (not shown).

The drain electrode 9 is provided on the second main surface of the n ⁺ semiconductor substrate 1. The drain electrode 9 may be made of a conductive film, such as a metal film. The drain electrode 9 is in ohmic contact with the n ⁺ semiconductor substrate 1.

Example of Method for Manufacturing Semiconductor Device According to First Embodiment First, an n ⁺ semiconductor substrate 1 made of N-type silicon carbide is prepared. An n semiconductor layer 2 made of silicon carbide is epitaxially grown on the first main surface of the n ⁺ semiconductor substrate 1 while doping an N-type impurity.

Next, a P-type impurity is ion-implanted into a region to be the p base region 3 in the surface region of the n semiconductor layer 2 by a photolithography technique and an ion implantation method. Next, an N-type impurity is ion-implanted into a region to be the n ⁺ source region 4 in the ion implantation region to be the p base region 3 by a photolithography technique and an ion implantation method.

Next, a P-type impurity is ion-implanted into the region to be the p ⁺ contact region 5 in the ion implantation region to be the p base region 3 by the photolithography technique and the ion implantation method. Note that the order of ion implantation for providing the p base region 3, ion implantation for providing the n ⁺ source region 4, and ion implantation for providing the p ⁺ contact region 5 is not limited to the order described above, and various changes can be made. Is possible.

Next, heat treatment (annealing) is performed to activate each ion implantation region that becomes, for example, the p base region 3, the n ⁺ source region 4, and the p ⁺ contact region 5. Thereby, the p base region 3, the n ⁺ source region 4 and the p ⁺ contact region 5 are formed. As described above, the respective ion implantation regions may be activated collectively by one heat treatment, or may be activated by performing heat treatment every time ion implantation is performed.

Next, the surface on which the p base region 3, the n ⁺ source region 4 and the p ⁺ contact region 5 are provided is thermally oxidized, and the gate insulating film 6 is provided on the entire surface. Next, a layer made of polysilicon is provided on the gate insulating film 6. The polysilicon layer 10 is provided by patterning the layer made of polysilicon and leaving it at a position corresponding to the terminal portion of the gate electrode 7.

Next, a metal layer having a structure in which, for example, aluminum or titanium nitride, or titanium and aluminum is stacked is provided on the gate insulating film 6 and the polysilicon layer 10. For example, the metal layer serving as the gate electrode 7 may be provided by a physical vapor deposition (PVD) method such as sputtering or a chemical vapor deposition (CVD) method. By patterning this metal layer, leaving the p base region 3 on the gate insulating film 6 on the region sandwiched between the n ⁺ source region 4 and the n semiconductor layer 2 and on the polysilicon layer 10 The gate electrode 7 is provided.

Next, a source electrode 8 is provided so as to be in contact with the n ⁺ source region 4 and the p ⁺ contact region 5. Next, the drain electrode 9 is provided on the second main surface of the n ⁺ semiconductor substrate 1. Then, the n ⁺ semiconductor substrate 1 and the drain electrode 9 are ohmic-bonded by heat treatment. As described above, the semiconductor device shown in FIG. 1 is completed.

(Embodiment 2)
Example of Semiconductor Device According to Second Embodiment FIG. 2 is a cross-sectional view showing an example of a semiconductor device according to the second embodiment of the present invention. FIG. 2 shows an active region of the semiconductor device according to the second embodiment. An embodiment in which the MOS structure of the semiconductor device is formed in the active region, a plurality of MOS structures may be provided in the active region, and the active region may be surrounded by a withstand voltage structure portion. Same as 1.

As shown in FIG. 2, the semiconductor device includes an n ⁺ semiconductor substrate 1 and an n semiconductor layer 2. Since the n ⁺ semiconductor substrate 1 and the n semiconductor layer 2 are the same as those in the first embodiment, a duplicate description is omitted.

The semiconductor device has, for example, a p base region 3, an n ⁺ source region 4, a p ⁺ contact region 5, a gate insulating film 6, a gate electrode 7, and a source electrode on the first main surface side of the n ⁺ semiconductor substrate 1. 8, p ⁺ semiconductor region 11 and n well region 12 are provided. The semiconductor device is provided with a back surface electrode to be, for example, the drain electrode 9 on the second main surface side of the n ⁺ semiconductor substrate 1.

The p ⁺ semiconductor region 11 is provided in a part of the surface region of the n semiconductor layer 2. For example, the p ⁺ semiconductor region 11 may be provided so as to sandwich another part of the surface region of the n semiconductor layer 2. That is, there may be a region of the n semiconductor layer 2 between the adjacent p ⁺ semiconductor regions 11 and p ⁺ semiconductor regions 11. The p ⁺ semiconductor region 11 may be a semiconductor region in which silicon carbide is doped with a P-type impurity, for example.

The p base region 3 is provided on the surface of the p ⁺ semiconductor region 11. The impurity concentration of the p base region 3 is lower than that of the p ⁺ semiconductor region 11. The p base region 3 may be a semiconductor region in which silicon carbide is doped with a P-type impurity, for example. The p base region 3 may be a part of a p semiconductor layer stacked on the n semiconductor layer 2 by, for example, an epitaxial growth method.

N well region 12 is provided on the surface of a region between adjacent p ⁺ semiconductor regions 11 and p ⁺ semiconductor region 11 of n semiconductor layer 2. N well region 12 is provided in contact with p base region 3. The impurity concentration of n well region 12 is lower than that of n ⁺ semiconductor substrate 1. The n-well region 12 is a region obtained by inverting the conductivity type of a part of the p-semiconductor layer stacked on the n-semiconductor layer 2 by the epitaxial growth method as described above by ion implantation of N-type impurities and heat treatment, for example. May be. For example, the n-well region 12 becomes an n-type drift region together with the n semiconductor layer 2.

The n ⁺ source region 4 is provided in the surface region of the p base region 3 on the p ⁺ semiconductor region 11. N ⁺ source region 4 is provided apart from n well region 12. The impurity concentration of n ⁺ source region 4 is higher than that of n well region 12.

The p ⁺ contact region 5 is provided on the opposite side of the n well region 12 across the p base region 3, that is, away from the n well region 12. The p ⁺ contact region 5 is in contact with the p base region 3 and the n ⁺ source region 4. For example, as described above, the p ⁺ contact region 5 penetrates the p semiconductor layer to be the p base region 3 on the n semiconductor layer 2 and contacts the p ⁺ semiconductor region 11. The impurity concentration of the p ⁺ contact region 5 is higher than that of the p base region 3.

Gate insulating film 6 is provided on the surface of p base region 3 between n well region 12 and n ⁺ source region 4. For example, the gate insulating film 6 extends from the surface of one p base region 3 adjacent to the n well region 12 through the surface of the n well region 12 to the surface of the other p base region 3. Also good.

  The gate electrode 7 is provided on the surface of the gate insulating film 6. For example, the gate electrode 7 may extend from the top of one adjacent p base region 3 across the n well region 12 to the top of the other p base region 3 via the n well region 12. The gate electrode 7 may be made of a conductive material having a lower resistance than polysilicon, for example, a metal. The gate electrode 7 may be made of, for example, aluminum or titanium nitride, or a metal having a structure in which titanium and aluminum are stacked. A polysilicon layer 10 made of polysilicon is provided under the terminal portion of the gate electrode 7.

  Since the source electrode 8 and the drain electrode 9 are the same as those in the first embodiment, redundant description is omitted.

Example of Method for Manufacturing Semiconductor Device According to Second Embodiment First, an n ⁺ semiconductor substrate 1 made of N-type silicon carbide is prepared. An n semiconductor layer 2 made of silicon carbide is epitaxially grown on the first main surface of the n ⁺ semiconductor substrate 1 while doping an N-type impurity.

Next, a P-type impurity is ion-implanted into a region to be the p ⁺ semiconductor region 11 in the surface region of the n semiconductor layer 2 by a photolithography technique and an ion implantation method. Next, a p semiconductor layer made of silicon carbide is epitaxially grown on the surface of the n semiconductor layer 2 while doping a P-type impurity. This p semiconductor layer becomes the p base region 3.

Next, N-type impurities are ion-implanted into a region to be the n-well region 12 of the p-semiconductor layer to be the p-base region 3 by photolithography and ion implantation. Next, N-type impurities are ion-implanted into the region to be the n ⁺ source region 4 of the p semiconductor layer to be the p base region 3 by photolithography and ion implantation.

Next, a P-type impurity is ion-implanted into a region to be the p ⁺ contact region 5 of the p semiconductor layer to be the p base region 3 by a photolithography technique and an ion implantation method. Note that ion implantation for providing the p ⁺ semiconductor region 11, ion implantation for providing the n well region 12, ion implantation for providing the n ⁺ source region 4, and ion implantation for providing the p ⁺ contact region 5 are performed. The order is not limited to the order described above, and various changes can be made.

Next, heat treatment (annealing) is performed to activate each ion implantation region that becomes, for example, the p ⁺ semiconductor region 11, the n well region 12, the n ⁺ source region 4, and the p ⁺ contact region 5. Thereby, a p ⁺ semiconductor region 11, an n well region 12, an n ⁺ source region 4 and a p ⁺ contact region 5 are formed. As described above, the respective ion implantation regions may be activated collectively by one heat treatment, or may be activated by performing heat treatment every time ion implantation is performed.

Next, the surface on which the p base region 3, the n ⁺ source region 4, the p ⁺ contact region 5 and the n well region 12 are provided is thermally oxidized, and the gate insulating film 6 is provided on the entire surface. Next, a layer made of polysilicon is provided on the gate insulating film 6. The polysilicon layer 10 is provided by patterning the layer made of polysilicon and leaving it at a position corresponding to the terminal portion of the gate electrode 7.

Next, for example, aluminum or titanium nitride, or a metal layer having a structure in which titanium and aluminum are laminated on the gate insulating film 6 and the polysilicon layer 10 by physical vapor deposition or chemical vapor deposition such as sputtering. Is provided. By patterning this metal layer, leaving the p base region 3 on the gate insulating film 6 on the region sandwiched between the n ⁺ source region 4 and the n well region 12 and on the polysilicon layer 10. The gate electrode 7 is provided.

Next, a source electrode 8 is provided so as to be in contact with the n ⁺ source region 4 and the p ⁺ contact region 5. Then, n ⁺ a second main surface of the semiconductor substrate 1, a drain electrode 9 is provided, by performing the heat treatment, an ohmic junction with the n ⁺ semiconductor substrate 1 and the drain electrode 9. As described above, the semiconductor device shown in FIG. 2 is completed.

  In the semiconductor device according to the first embodiment or the second embodiment, a voltage lower than the threshold voltage Vth is applied to the gate electrode 7 while a positive voltage is applied to the drain electrode 9 with respect to the source electrode 8. And In this case, in the semiconductor device according to the first embodiment, the PN junction between the p base region 3 and the n semiconductor layer 2, and in the semiconductor device according to the second embodiment, the p base region 3 and the n well region 12 are connected. Since the PN junctions between them are reversely biased, no current flows through the semiconductor device.

  On the other hand, in the semiconductor device according to the first or second embodiment, a voltage higher than the threshold voltage Vth is applied to the gate electrode 7 while a positive voltage is applied to the drain electrode 9 with respect to the source electrode 8. Suppose that In this case, since an inversion layer is formed in the p base region 3 under the gate electrode 7, a current flows through the semiconductor device. Thus, the switching operation of the semiconductor device can be performed by the voltage applied to the gate electrode 7.

Example A semiconductor device according to the embodiment shown in FIG. 1 or FIG. 2, that is, a semiconductor device in which the gate electrode 7 is made of metal is taken as an example. A conventional semiconductor device shown in FIG. 5 or 6, that is, a semiconductor device in which the gate electrodes 107 and 207 are made of polysilicon is used as a comparative example.

  About the Example and the comparative example, the current-voltage waveform at the time of turn-on was evaluated. FIG. 3 is a waveform diagram showing an example of a current-voltage waveform when the semiconductor device according to the first and second embodiments of the present invention is turned on. FIG. 4 is a waveform diagram showing an example of a current-voltage waveform when the conventional semiconductor device is turned on. 3 and 4, the vertical axis represents the gate voltage, the drain-source voltage, and the drain current, and the horizontal axis represents time. As shown in FIG. 4, it can be seen that in the comparative example, excessive current flows transiently at the turn-on time. On the other hand, as shown in FIG. 3, it can be seen that in the embodiment, the current that flows transiently at the turn-on time is suppressed.

  According to the first or second embodiment, since the gate electrode 7 is made of metal, the time constant determined by the product of the gate-drain capacitance and the gate electrode resistance is reduced. As a result, the electric charge charged in the drain-source capacitance is discharged at the time of turn-on, the gate-source potential is lowered, and a transient decrease in the threshold voltage Vth is suppressed. Accordingly, an increase in current at turn-on can be suppressed, and loss at turn-on can be suppressed. Further, according to the first embodiment or the second embodiment, since imbalance is less likely to occur in the chip, an excessive decrease in threshold voltage Vth due to local imbalance occurring in the chip is suppressed. Is done. Accordingly, an increase in current at turn-on can be suppressed, loss at turn-on can be suppressed, and excessive imbalance can be suppressed. Further, according to the first or second embodiment, since the polysilicon layer 10 is provided under the terminal portion of the gate electrode 7, the termination of the gate electrode 7 is caused by the unevenness of the surface of the polysilicon layer 10. The adhesion strength between the portion and the surface of the polysilicon layer 10 is increased. Therefore, the gate electrode 7 can be prevented from peeling off. Further, according to the first or second embodiment, since there is no polysilicon under the central portion of the gate electrode 7, the gate capacitance can be reduced.

  In the above, this invention is not restricted to each embodiment mentioned above, A various change is possible. For example, in each embodiment, the first conductivity type is N type and the second conductivity type is P type. However, the present invention similarly applies to the case where the first conductivity type is P type and the second conductivity type is N type. It holds.

  As described above, the present invention is useful for a semiconductor device that can be used, for example, as a switching device formed on a silicon carbide substrate, and is particularly suitable for a semiconductor device such as a vertical MOSFET made of silicon carbide. Yes.

1 n ⁺ semiconductor substrate 2 n semiconductor layer 3 p base region 4 n ⁺ source region 5 p ⁺ contact region 6 gate insulating film 7 gate electrode 8 source electrode 9 drain electrode 10 polysilicon layer 11 p ⁺ semiconductor region 12 n well region

Claims (5)

A semiconductor substrate made of silicon carbide of the first conductivity type;
A first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate, provided on the first main surface of the semiconductor substrate;
A base region of a second conductivity type provided on the surface of the semiconductor layer;
A source region of a first conductivity type provided in a surface region of the base region;
A second conductivity type contact region having a higher impurity concentration than the base region, provided in a surface region of the base region;
A source electrode in contact with the source region and the contact region;
A gate insulating film provided on a surface of a region of the base region sandwiched between the semiconductor layer and the source region;
A gate electrode provided on a surface of the gate insulating film;
A drain electrode provided on the second main surface of the semiconductor substrate,
A semiconductor device, wherein the gate electrode is made of metal. A semiconductor substrate made of silicon carbide of the first conductivity type;
A first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate, provided on the first main surface of the semiconductor substrate;
A semiconductor region of a second conductivity type provided in a part of the surface region of the semiconductor layer;
A base region of a second conductivity type provided on the surface of the semiconductor region and having an impurity concentration lower than that of the semiconductor region;
A well region made of silicon carbide of the first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the surface of the semiconductor layer in contact with the base region;
A source region of a first conductivity type provided in a surface region of the base region apart from the well region and having a higher impurity concentration than the well region;
A second conductivity type contact region having a higher impurity concentration than the base region, provided on the surface of the semiconductor region in contact with the source region and the base region;
A source electrode in contact with the source region and the contact region;
A gate insulating film provided on a surface of a region of the base region sandwiched between the well region and the source region;
A gate electrode provided on a surface of the gate insulating film;
A drain electrode provided on the second main surface of the semiconductor substrate,
A semiconductor device, wherein the gate electrode is made of metal.   3. The semiconductor device according to claim 1, wherein a layer made of polysilicon is provided under a terminal portion of the gate electrode. A semiconductor substrate made of silicon carbide of the first conductivity type, a first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate, provided on the first main surface of the semiconductor substrate; and A base region of a second conductivity type provided on the surface, a source region of a first conductivity type provided in the surface region of the base region, and the base region provided in the surface region of the base region A second conductivity type contact region having a high impurity concentration, the source region, a source electrode in contact with the contact region, and a surface of the base region between the semiconductor layer and the source region. A method of manufacturing a semiconductor device comprising: a gate insulating film; a gate electrode provided on a surface of the gate insulating film; and a drain electrode provided on a second main surface of the semiconductor substrate.
A method of manufacturing a semiconductor device, wherein the gate electrode is made of metal. A semiconductor substrate made of silicon carbide of the first conductivity type, a first conductivity type semiconductor layer having a lower impurity concentration than the semiconductor substrate, provided on the first main surface of the semiconductor substrate; and A semiconductor region of a second conductivity type provided in a part of the surface region; a base region of a second conductivity type provided on the surface of the semiconductor region and having a lower impurity concentration than the semiconductor region; and the semiconductor layer A well region made of silicon carbide of the first conductivity type having an impurity concentration lower than that of the semiconductor substrate, the surface region of the base region being away from the well region A first conductivity type source region having an impurity concentration higher than that of the well region; and an impurity higher than the base region provided on the surface of the semiconductor region in contact with the source region and the base region. A high-conductivity second-conductivity type contact region, the source region, a source electrode in contact with the contact region, and a base region provided on the surface of the region sandwiched between the well region and the source region In a method for manufacturing a semiconductor device, comprising: a gate insulating film; a gate electrode provided on a surface of the gate insulating film; and a drain electrode provided on a second main surface of the semiconductor substrate.
A method of manufacturing a semiconductor device, wherein the gate electrode is made of metal.

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