JP2016058656A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve breakdown voltage of a semiconductor device; and suppress an increase in a forward voltage drop (Vf) of a parasitic diode in a semiconductor device.SOLUTION: A semiconductor device has on an n-type silicon carbide substrate composed of silicon carbide, an n-type silicon carbide layer 2, a p-type region 3, an n-type source region 4, a p-type contact region 5, a gate insulation film, a gate electrode 7 and a source electrode 8. The semiconductor device has a drain electrode on a rear face. A surface region of the n-type silicon carbide layer 2 is surrounded by the n-type source region 4, and the p-type contact region 5 is provided around the n-type source region 4 except a portion under a wiring part 7a for connecting the gate electrode 7 and the gate electrode 7 which are adjacent to each other.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  FIG. 7 is a cross-sectional view showing a first example of a conventional semiconductor device. As shown in FIG. 7, the semiconductor device has n-type silicon carbide layer 102 on the front surface of n-type silicon carbide substrate 101. A plurality of p-type regions 103 are provided in the surface region of n-type silicon carbide layer 102. An n-type source region 104 and a p-type contact region 105 are provided in the surface region of the p-type region 103. A gate electrode 107 is provided on a p-type region 103 between the n-type source region 104 and the n-type silicon carbide layer 102 with a gate insulating film 106 interposed therebetween. A source electrode 108 is in contact with the n-type source region 104 and the p-type contact region 105. A drain electrode 109 is provided on the back surface of the n-type silicon carbide substrate 101 (see, for example, Patent Document 1).

  FIG. 8 is a cross-sectional view showing a second example of a conventional semiconductor device. As shown in FIG. 8, the semiconductor device has n-type silicon carbide layer 202 on the front surface of n-type silicon carbide substrate 201. A plurality of p-type base regions 210 are provided in the surface region of n-type silicon carbide layer 202. A p-type silicon carbide layer 211 is provided on p-type base region 210 and n-type silicon carbide layer 202. In p-type silicon carbide layer 211, n-type region 212 is provided on n-type silicon carbide layer 202 between adjacent p-type base region 210 and p-type base region 210. In p-type silicon carbide layer 211, p-type region 203, n-type source region 204, and p-type contact region 205 are provided on each p-type base region 210. A gate electrode 207 is provided on the p-type region 203 between the n-type source region 204 and the n-type region 212 with a gate insulating film 206 interposed therebetween. A source electrode 208 is in contact with the n-type source region 204 and the p-type contact region 205. A drain electrode 209 is provided on the back surface of the n-type silicon carbide substrate 201 (see, for example, Patent Document 2).

JP 2013-187302 A JP 2013-102106 A

  However, the conventional semiconductor device described above incorporates a parasitic NPN transistor 300 and a parasitic diode 301 as shown in FIG. When a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) is turned on, the current tends to concentrate on the p-type regions 103 and 210, so that the potential of the p-type regions 103 and 210 increases when a large current flows. Resulting in. As a result, the parasitic NPN transistor 300 operates, leading to a problem that the element is destroyed. Further, if the area occupied by p-type regions 103 and 210 with respect to the element area is small, the contact resistance of the electrode with respect to the p-type silicon carbide semiconductor is high, leading to an increase in the forward voltage drop (Vf) of parasitic diode 301. There is.

  An object of the present invention is to improve the breakdown tolerance in order to solve the above-mentioned problems caused by the prior art. Another object of the present invention is to suppress an increase in the forward voltage drop (Vf) of the parasitic diode.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention includes a first conductivity type silicon carbide substrate and the first conductivity type silicon carbide substrate provided on the first main surface. A first conductivity type silicon carbide layer having an impurity concentration lower than that of the first conductivity type silicon carbide substrate; a second conductivity type region provided in a part of a surface region of the first conductivity type silicon carbide layer; A first conductivity type source region provided in the surface region of the conductivity type region, and a second conductivity type contact region having a higher impurity concentration than the second conductivity type region, provided in the surface region of the second conductivity type region. A source electrode in contact with the first conductivity type source region and the second conductivity type contact region, and the first conductivity type silicon carbide layer and the first conductivity type source region of the second conductivity type region. Gate insulating film provided on the surface of the region A surface region of the first conductivity type silicon carbide layer, comprising: a gate electrode provided on the gate insulating film; and a drain electrode provided on the second main surface of the first conductivity type silicon carbide substrate. Is surrounded by the first conductivity type source region, and the second conductivity type contact region is provided around the first conductivity type source region except under the wiring portion that connects the adjacent gate electrodes. It is characterized by being.

  The semiconductor device according to the present invention has a first conductivity type silicon carbide substrate and an impurity concentration higher than that of the first conductivity type silicon carbide substrate provided on the first main surface of the first conductivity type silicon carbide substrate. A first conductivity type silicon carbide layer having a low thickness, a second conductivity type base region provided in a part of a surface region of the first conductivity type silicon carbide layer, and a surface provided on the surface of the first conductivity type silicon carbide layer. The second conductivity type silicon carbide layer, and the second conductivity type silicon carbide layer provided so as to penetrate the second conductivity type silicon carbide layer and contact the first conductivity type silicon carbide layer. A first conductivity type region having an impurity concentration lower than that of the one conductivity type silicon carbide substrate, and the first conductivity type region provided in a surface region of the second conductivity type silicon carbide layer apart from the first conductivity type region; A first conductivity type source region having a higher impurity concentration and the second conductivity type A second conductivity type contact region having a higher impurity concentration than the second conductivity type base region, provided in the silicon nitride layer so as to penetrate the second conductivity type silicon carbide layer and contact the second conductivity type base region; And the source electrode in contact with the first conductivity type source region and the second conductivity type contact region, and the second conductivity type silicon carbide layer sandwiched between the first conductivity type region and the first conductivity type source region. A gate insulating film provided on the surface of the region, a gate electrode provided on the gate insulating film, a drain electrode provided on the second main surface of the first conductivity type silicon carbide substrate, The first conductivity type region is surrounded by the first conductivity type source region, and the second conductivity type contact region is excluded except under the wiring portion that connects the adjacent gate electrodes. First conductivity type source region Characterized in that provided around.

  Further, the second conductivity type contact region is separated from the gate electrode and a wiring part connecting the adjacent gate electrodes by 0.5 μm or more.

  According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a first conductivity type silicon carbide substrate; and the first conductivity type silicon carbide substrate provided on the first main surface of the first conductivity type silicon carbide substrate. A first conductivity type silicon carbide layer having a low impurity concentration, a second conductivity type region provided in a part of a surface region of the first conductivity type silicon carbide layer, and a surface region of the second conductivity type region. A first conductivity type source region, a second conductivity type contact region having an impurity concentration higher than that of the second conductivity type region provided in a surface region of the second conductivity type region, and the first conductivity type source. A source electrode in contact with the region and the second conductivity type contact region; and a surface of the second conductivity type region between the first conductivity type silicon carbide layer and the first conductivity type source region. And a gate insulating film formed on the gate insulating film. And a drain electrode provided on the second main surface of the first conductivity type silicon carbide substrate, wherein a surface region of the first conductivity type silicon carbide layer is formed on the surface region of the first conductivity type silicon carbide layer. And surrounding the first conductivity type source region excluding the step of forming the second conductivity type contact region so as to be surrounded by the first conductivity type source region and under the wiring portion connecting the adjacent gate electrodes. And a step of forming.

  According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a first conductivity type silicon carbide substrate; and the first conductivity type silicon carbide substrate provided on the first main surface of the first conductivity type silicon carbide substrate. A first conductivity type silicon carbide layer having a low impurity concentration, a second conductivity type base region provided in a part of a surface region of the first conductivity type silicon carbide layer, and a surface of the first conductivity type silicon carbide layer. A second conductive type silicon carbide layer provided on the first conductive type silicon carbide layer, and the second conductive type silicon carbide layer provided so as to penetrate the second conductive type silicon carbide layer and contact the first conductive type silicon carbide layer; The first conductivity type region having an impurity concentration lower than that of the first conductivity type silicon carbide substrate and the surface region of the second conductivity type silicon carbide layer provided apart from the first conductivity type region. A first conductivity type source region having a higher impurity concentration than the conductivity type region; Second conductivity type having a higher impurity concentration than the second conductivity type base region provided in the two conductivity type silicon carbide layer so as to penetrate the second conductivity type silicon carbide layer and to be in contact with the second conductivity type base region Type contact region, source electrode in contact with the first conductivity type source region and the second conductivity type contact region, and the first conductivity type region and the first conductivity type source region of the second conductivity type silicon carbide layer A gate insulating film provided on the surface of the region sandwiched between the gate insulating film, a gate electrode provided on the gate insulating film, and a second main surface of the first conductivity type silicon carbide substrate. In a method of manufacturing a semiconductor device comprising a drain electrode, the step of forming the first conductivity type region so as to be surrounded by the first conductivity type source region, and the second conductivity type contact region are adjacent to each other. Gate electrode Characterized in that it comprises the steps of forming around the first conductivity type source region excluding the lower wiring portions connecting the Judges, the.

  According to the present invention, the second conductivity type region is disposed so as to surround the gate electrode, whereby the area of the second conductivity type region is increased, and the area where the avalanche carrier is extracted when a high voltage is applied to the drain electrode. Therefore, sufficient interruption capability can be secured even with a large current. Moreover, since the area of the second conductivity type contact region is increased by arranging the second conductivity type region so as to surround the gate electrode, the effective area of the built-in parasitic diode is increased. The amount of carrier injection increases. In addition, when the gate insulating film is formed by thermal oxidation, the gate insulating film on the high-concentration p-type contact region can be prevented from being thinned, so that the reliability of the gate insulating film is improved.

  According to the present invention, the breakdown tolerance can be improved. Further, according to the present invention, an increase in the forward voltage drop (Vf) of the parasitic diode can be suppressed.

It is a top view which shows an example of the layout of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows an example of the cross-section in the cutting line AA of FIG. It is sectional drawing which shows an example of the cross-section in the cutting line BB of FIG. It is sectional drawing which shows another example of the cross-sectional structure in the cutting line AA of FIG. It is sectional drawing which shows another example of the cross-sectional structure in the cutting line BB of FIG. It is a top view which shows another example of the layout of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the 1st example of the conventional semiconductor device. It is sectional drawing which shows the 2nd example of the conventional semiconductor device.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached thereto. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Example of Semiconductor Device FIG. 1 is a plan view showing an example of a layout of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure taken along a cutting line AA in FIG. FIG. 3 is a cross-sectional view showing an example of a cross-sectional structure taken along a cutting line BB in FIG. The cutting line BB passes through a wiring portion that connects adjacent gate electrodes, and the cutting line AA is orthogonal to the cutting line BB and does not pass through a wiring portion that connects adjacent gate electrodes.

As shown in FIGS. 1 to 3, the semiconductor device includes an n silicon carbide substrate 1 made of n-type silicon carbide and an n ⁻ silicon carbide layer 2 made of n-type silicon carbide. N silicon carbide substrate 1 may be, for example, a silicon carbide single crystal substrate obtained by doping silicon carbide with an n-type impurity. The n silicon carbide substrate 1 becomes a drain region, for example. In the description of the present embodiment, it is assumed that the front surface of n silicon carbide substrate 1 is the first main surface and the back surface is the second main surface.

N ⁻ silicon carbide layer 2 is provided on the first main surface of n silicon carbide substrate 1. The impurity concentration of n ⁻ silicon carbide layer 2 is lower than that of n silicon carbide substrate 1. The n ⁻ silicon carbide layer 2 may be, for example, a semiconductor layer in which silicon carbide is doped with an n-type impurity. The n ⁻ silicon carbide layer 2 becomes an n-type drift layer, for example.

The semiconductor device includes, for example, a p region 3, an n source region 4, a p ⁺ contact region 5, a gate insulating film 6, a gate electrode 7 and a source electrode 8 as a MOS structure on the first main surface side of the n silicon carbide substrate 1. I have. The semiconductor device is provided with a back electrode serving as the drain electrode 9 on the second main surface side of the n silicon carbide substrate 1, for example. FIG. 1 shows a planar layout of n ⁻ silicon carbide layer 2, p region 3, n source region 4, p ⁺ contact region 5, gate electrode 7 and source electrode 8. In FIG. 1, in order to make the planar layout of the n ⁻ silicon carbide layer 2, the p region 3, the n source region 4 and the p ⁺ contact region 5 easier to see, a part of the gate electrode 7 and the source electrode 8 is broken in the lower left cell. ing.

P region 3 is provided in part of the surface region of n ⁻ silicon carbide layer 2. P region 3 is provided so as to surround another part of the surface region of n ⁻ silicon carbide layer 2. The p region 3 is also provided under the wiring portion 7 a that connects the adjacent gate electrodes 7 to each other. The p region 3 may be a semiconductor region in which silicon carbide is doped with a p-type impurity, for example.

The n source region 4 is provided in the surface region of the p region 3. N source region 4 is provided away from the surface region of n ⁻ silicon carbide layer 2 surrounded by p region 3. N source region 4 is provided to surround a portion of p region 3 surrounding the surface region of n ⁻ silicon carbide layer 2. The impurity concentration of n source region 4 is higher than that of n ⁻ silicon carbide layer 2.

p ⁺ contact region 5 is provided in the surface region of p region 3 away from the surface region of n ⁻ silicon carbide layer 2 surrounded by p region 3. The p ⁺ contact region 5 is in contact with the p region 3 and the n source region 4. The p ⁺ contact region 5 is provided around the n source region 4. The p ⁺ contact region 5 is not provided under the gate electrode 7 and under the wiring portion 7 a that connects the adjacent gate electrode 7 and the gate electrode 7. The p ⁺ contact region 5 may be separated by 0.5 μm or more from the gate electrode 7 and the wiring portion 7 a connecting the adjacent gate electrode 7 and the gate electrode 7. The impurity concentration of p ⁺ contact region 5 is higher than that of p region 3.

Gate insulating film 6 is provided on the surface of p region 3 of n ⁻ silicon carbide layer 2 sandwiched between a region surrounded by p region 3 and n source region 4.

  The gate electrode 7 is provided in an island shape on the surface of the gate insulating film 6. Adjacent gate electrode 7 and gate electrode 7 are connected by a wiring portion 7a.

The source electrode 8, the surface of the n source region 4 and the p ⁺ contact region 5 is provided in contact with the n source region 4 and the p ⁺ contact region 5. Source electrode 8 is electrically connected to n source region 4 and p ⁺ contact region 5. The source electrode 8 is insulated from the gate electrode 7 by an interlayer insulating film (not shown).

  Drain electrode 9 is provided on the second main surface of n silicon carbide substrate 1. Drain electrode 9 is in ohmic contact with n silicon carbide substrate 1.

-Example of manufacturing procedure of semiconductor device shown in FIGS. 1 to 3 First, an n-silicon carbide substrate 1 made of n-type silicon carbide is prepared. On the first main surface of this n silicon carbide substrate 1, for example, an n ⁻ silicon carbide layer 2 made of silicon carbide is epitaxially grown while doping an n-type impurity.

Next, a p-type impurity is ion-implanted into a region to be the p region 3 in the surface region of the n ⁻ silicon carbide layer 2 by a photolithography technique and an ion implantation method. Next, an n-type impurity is ion-implanted into a region to be the n source region 4 in the ion implantation region to be the p region 3 by a photolithography technique and an ion implantation method.

Next, a p-type impurity is ion-implanted into the region to be the p ⁺ contact region 5 in the ion implantation region to be the p region 3 by photolithography and ion implantation. The order of ion implantation for providing the p region 3, ion implantation for providing the n source region 4, and ion implantation for providing the p ⁺ contact region 5 is not limited to the order described above, and can be variously changed. is there.

Next, heat treatment (annealing) is performed to activate each ion implantation region that becomes, for example, the p region 3, the n source region 4, and the p ⁺ contact region 5. Thereby, the p region 3, the n source region 4, and the p ⁺ contact region 5 are formed. As described above, the respective ion implantation regions may be activated collectively by one heat treatment, or may be activated by performing heat treatment every time ion implantation is performed.

Next, the surface on which the p region 3, the n source region 4 and the p ⁺ contact region 5 are provided is thermally oxidized, and the gate insulating film 6 is provided on the entire surface. Next, a gate electrode 7 is provided on the gate insulating film 6. In addition to the gate electrode 7, a wiring portion 7 a that connects the adjacent gate electrodes 7 to each other is also provided.

Next, a source electrode 8 is provided so as to be in contact with the n source region 4 and the p ⁺ contact region 5. Next, drain electrode 9 is provided on the second main surface of n silicon carbide substrate 1. Then, heat treatment is performed to make ohmic contact between n-silicon carbide substrate 1 and drain electrode 9. As described above, the semiconductor device shown in FIGS. 1 to 3 is completed.

Another Example of Semiconductor Device FIG. 4 is a cross-sectional view showing another example of the cross-sectional structure taken along section line AA in FIG. FIG. 5 is a cross-sectional view showing another example of the cross-sectional structure taken along the cutting line BB in FIG.

As shown in FIGS. 4 and 5, the semiconductor device includes an n silicon carbide substrate 1 and an n ⁻ silicon carbide layer 2. Since n silicon carbide substrate 1 and n ⁻ silicon carbide layer 2 are the same as those shown in FIGS. 2 and 3, redundant description is omitted.

The semiconductor device has, for example, a p region 3, an n source region 4, a p ⁺ contact region 5, a gate insulating film 6, a gate electrode 7, a source electrode 8 on the first main surface side of the n silicon carbide substrate 1. A p base region 10, a p silicon carbide layer 11, and an n ⁻ region 12 are provided. The semiconductor device is provided with a back electrode serving as the drain electrode 9 on the second main surface side of the n silicon carbide substrate 1, for example. In the example shown in FIGS. 4 and 5, n ⁻ silicon carbide layer 2 shown in FIG. 1 is replaced with n ⁻ region 12.

P base region 10 is provided in part of the surface region of n ⁻ silicon carbide layer 2. P base region 10 is provided so as to surround another part of the surface region of n ⁻ silicon carbide layer 2. The p base region 10 is also provided under the wiring portion 7 a that connects the gate electrodes 7 adjacent to each other. The p base region 10 may be a semiconductor region in which silicon carbide is doped with a p-type impurity, for example.

p silicon carbide layer 11 is provided on the surface of n ⁻ silicon carbide layer 2. The p silicon carbide layer 11 may be, for example, a semiconductor layer obtained by doping silicon carbide with a p-type impurity.

N ⁻ region 12 is provided on the surface of the region between adjacent p base regions 10 and 10 of n ⁻ silicon carbide layer 2. N ⁻ region 12 penetrates p silicon carbide layer 11 and is in contact with the region between adjacent p base region 10 and p base region 10 of n ⁻ silicon carbide layer 2. The impurity concentration of n ⁻ region 12 is lower than that of n silicon carbide substrate 1. For example, n ⁻ region 12 may be a region obtained by inverting the conductivity type of a part of p silicon carbide layer 11 by ion implantation of n-type impurities and heat treatment. For example, n ⁻ region 12 becomes an n-type drift region together with n ⁻ silicon carbide layer 2.

P region 3 is a part of p silicon carbide layer 11 and is provided on the surface of p base region 10. The p region 3 is provided so as to surround the n ⁻ region 12. The p region 3 is also provided under the wiring portion 7 a that connects the adjacent gate electrodes 7 to each other.

The n source region 4 is provided in the surface region of the p region 3 on the p base region 10. N source region 4 is provided apart from n ⁻ region 12. The n source region 4 is provided so as to surround a portion of the p region 3 surrounding the n ⁻ region 12. The impurity concentration of n source region 4 is higher than that of n ⁻ region 12.

p ⁺ contact region 5 in p silicon carbide layer 11 penetrates p silicon carbide layer 11 and contacts p base region 10. p ⁺ contact region 5, n ^- and away from the region 12, across the n source region 4 n ^- is provided on the opposite side of the region 12. The p ⁺ contact region 5 is in contact with the p region 3 and the n source region 4. The p ⁺ contact region 5 is provided around the n source region 4. The p ⁺ contact region 5 is not provided under the gate electrode 7 and under the wiring portion 7 a that connects the adjacent gate electrode 7 and the gate electrode 7. The p ⁺ contact region 5 may be separated by 0.5 μm or more from the gate electrode 7 and the wiring portion 7 a connecting the adjacent gate electrode 7 and the gate electrode 7. The impurity concentration of p ⁺ contact region 5 is higher than that of p silicon carbide layer 11.

Gate insulating film 6 is provided on the surface of p silicon carbide layer 11 in a region sandwiched between n ⁻ region 12 and n source region 4 in p region 3.

  The gate electrode 7, the wiring part 7a connecting the adjacent gate electrode 7 and the gate electrode 7, the source electrode 8 and the drain electrode 9 are the same as the example shown in FIGS. .

Example of Manufacturing Procedure of Semiconductor Device shown in FIGS. 1, 4 and 5 First, an n silicon carbide substrate 1 made of n-type silicon carbide is prepared. An n ⁻ silicon carbide layer 2 made of silicon carbide is epitaxially grown on the first main surface of n silicon carbide substrate 1 while doping an n-type impurity.

Next, a p-type impurity is ion-implanted into a region to be the p base region 10 in the surface region of the n ⁻ silicon carbide layer 2 by a photolithography technique and an ion implantation method. Next, a p silicon carbide layer 11 made of silicon carbide is epitaxially grown on the surface of n ⁻ silicon carbide layer 2 while doping a p-type impurity.

Next, an n-type impurity is ion-implanted into a region to be the n ⁻ region 12 of the p silicon carbide layer 11 by, for example, a photolithography technique and an ion implantation method. Next, n-type impurities are ion-implanted into the region to be the n source region 4 of the p silicon carbide layer 11 by photolithography and ion implantation.

Next, a p-type impurity is ion-implanted into a region to be the p ⁺ contact region 5 of the p-silicon carbide layer 11 by a photolithography technique and an ion implantation method. The order of ion implantation for providing the n ⁻ region 12, ion implantation for providing the n source region 4, and ion implantation for providing the p ⁺ contact region 5 is not limited to the order described above, and can be variously changed. It is.

Next, heat treatment (annealing) is performed to activate each ion implantation region that becomes, for example, the p base region 10, the n ⁻ region 12, the n source region 4, and the p ⁺ contact region 5. Thereby, a p base region 10, an n ⁻ region 12, an n source region 4 and a p ⁺ contact region 5 are formed. As described above, the respective ion implantation regions may be activated collectively by one heat treatment, or may be activated by performing heat treatment every time ion implantation is performed.

Next, the surface on which the p region 3, the n source region 4, the p ⁺ contact region 5 and the n ⁻ region 12 are provided is thermally oxidized, and the gate insulating film 6 is provided on the entire surface. Next, a gate electrode 7 is provided on the gate insulating film 6. In addition to the gate electrode 7, a wiring portion 7 a that connects the adjacent gate electrode 7 and the gate electrode 7 is also provided.

Next, a source electrode 8 is provided so as to be in contact with the n source region 4 and the p ⁺ contact region 5. Next, drain electrode 9 is provided on the second main surface of n silicon carbide substrate 1, and heat treatment is performed, so that n silicon carbide substrate 1 and drain electrode 9 are in ohmic contact. As described above, the semiconductor device shown in FIGS. 1, 4 and 5 is completed.

In the example shown in FIGS. 1 to 5, it is assumed that a voltage lower than the threshold voltage Vth is applied to the gate electrode 7 in a state where a positive voltage is applied to the drain electrode 9 with respect to the source electrode 8. In this case, in the example shown in FIGS. 2 and 3, the PN junction between the p region 3 and the n ⁻ silicon carbide layer 2, and in the example shown in FIGS. 4 and 5, the p region 3 and the n ⁻ region 12. Since the PN junctions between them are reversely biased, no current flows through the semiconductor device.

  On the other hand, in the example shown in FIGS. 1 to 5, it is assumed that a voltage higher than the threshold voltage Vth is applied to the gate electrode 7 while a positive voltage is applied to the drain electrode 9 with respect to the source electrode 8. In this case, since an inversion layer is formed in the p region 3 under the gate electrode 7, a current flows through the semiconductor device. Thus, the switching operation of the semiconductor device can be performed by the voltage applied to the gate electrode 7.

FIG. 6 is a plan view showing another example of the layout of the semiconductor device according to the embodiment of the present invention. As shown in FIG. 6, in the example shown in FIGS. 2 and 3, the p ⁺ contact region 5 is surrounded by the n source region 4. N source region 4 is surrounded by a region of p region 3 between n source region 4 and the surface region of n ⁻ silicon carbide layer 2. the p region 3, n source regions 4 and the n ^- region between the silicon carbide layer 2 of the surface area, n ^- region between the p region 3 and the p region 3 of the silicon carbide layer 2, adjacent cells Surrounded by In the example shown in FIGS. 4 and 5, n ⁻ silicon carbide layer 2 shown in FIG. 6 is replaced with n ⁻ region 12.

In the layout shown in FIG. 6, the area of the p ⁺ contact region 5 is smaller than that in the layout shown in FIG. 1, so that the area for extracting the avalanche carrier when a high voltage is applied to the drain electrode 9 is small. Therefore, the layout shown in FIG. 6 has a lower breakdown capability because the interruption capability when a large current flows is lower than the layout shown in FIG. In the layout shown in FIG. 6, since the area of the p ⁺ contact region 5 is smaller than that in the layout shown in FIG. 1, the effective area of the built-in parasitic diode is small. Therefore, in the layout shown in FIG. 6, since the amount of holes injected from the p region 3 or the p base region 10 is smaller than in the layout shown in FIG. 1, the forward voltage drop (Vf) of the parasitic diode is large.

According to the embodiment, the p ⁺ contact region 5 is arranged so as to surround the gate electrode 7, thereby increasing the area of the p ⁺ contact region 5. As a result, the area for extracting avalanche carriers when a high voltage is applied to the drain electrode 9 is increased, and a sufficient blocking capability can be secured even with a large current, so that the breakdown resistance can be improved. Further, since the effective area of the built-in parasitic diode increases and the amount of holes injected from the p region 3 or the p base region 10 increases, an increase in the forward voltage drop (Vf) of the parasitic diode can be suppressed. Further, by not providing the p ⁺ contact region 5 under the wiring portion 7a that connects the adjacent gate electrodes 7 and 7, it is possible to suppress a decrease in breakdown voltage and reliability of the gate insulating film 6. Further, since the p ⁺ contact region 5 is separated from the gate electrode 7 and the wiring part 7a by 0.5 μm or more, the gate insulation is formed on the high concentration p ⁺ contact region 5 when the gate insulating film 6 is formed by thermal oxidation. It is possible to prevent the film 6 from being thinned. Therefore, the reliability of the gate insulating film 6 is improved.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is similarly established when the first conductivity type is p-type and the second conductivity type is n-type. . In addition, for example, in the embodiment, the shape of the cell is a square, but the shape of the cell may be a polygon or a circle other than the rectangle.

  As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a semiconductor device that can be used, for example, as a switching device formed on a silicon carbide substrate, and in particular, a vertical device made of silicon carbide. Suitable for semiconductor devices such as type MOSFETs.

1 n silicon carbide substrate 2 n ^- 3 carbide layer p region 4 n source region 5 p ⁺ contact region 6 the gate insulating film 7 a gate electrode 7a wiring section 8 source electrode 9 drain electrode 10 p base region 11 p silicon carbide layer 12 n ^- area

Claims (5)

A first conductivity type silicon carbide substrate;
A first conductivity type silicon carbide layer having an impurity concentration lower than that of the first conductivity type silicon carbide substrate provided on the first main surface of the first conductivity type silicon carbide substrate;
A second conductivity type region provided in a part of a surface region of the first conductivity type silicon carbide layer;
A first conductivity type source region provided in a surface region of the second conductivity type region;
A second conductivity type contact region provided in a surface region of the second conductivity type region and having a higher impurity concentration than the second conductivity type region;
A source electrode in contact with the first conductivity type source region and the second conductivity type contact region;
A gate insulating film provided on a surface of a region of the second conductivity type region sandwiched between the first conductivity type silicon carbide layer and the first conductivity type source region;
A gate electrode provided on the gate insulating film;
A drain electrode provided on the second main surface of the first conductivity type silicon carbide substrate,
A surface region of the first conductivity type silicon carbide layer is surrounded by the first conductivity type source region;
The semiconductor device according to claim 1, wherein the second conductivity type contact region is provided around the first conductivity type source region except under a wiring portion that connects the adjacent gate electrodes. A first conductivity type silicon carbide substrate;
A first conductivity type silicon carbide layer having an impurity concentration lower than that of the first conductivity type silicon carbide substrate provided on the first main surface of the first conductivity type silicon carbide substrate;
A second conductivity type base region provided in a part of a surface region of the first conductivity type silicon carbide layer;
A second conductivity type silicon carbide layer provided on a surface of the first conductivity type silicon carbide layer;
The second conductivity type silicon carbide layer has an impurity concentration higher than that of the first conductivity type silicon carbide substrate provided so as to penetrate the second conductivity type silicon carbide layer and contact the first conductivity type silicon carbide layer. A low first conductivity type region;
A first conductivity type source region having an impurity concentration higher than that of the first conductivity type region provided in a surface region of the second conductivity type silicon carbide layer apart from the first conductivity type region;
The second conductivity type silicon carbide layer has a higher impurity concentration than the second conductivity type base region provided so as to penetrate the second conductivity type silicon carbide layer and to be in contact with the second conductivity type base region. Two conductivity type contact regions;
A source electrode in contact with the first conductivity type source region and the second conductivity type contact region;
A gate insulating film provided on a surface of a region sandwiched between the first conductivity type region and the first conductivity type source region of the second conductivity type silicon carbide layer;
A gate electrode provided on the gate insulating film;
A drain electrode provided on the second main surface of the first conductivity type silicon carbide substrate,
The first conductivity type region is surrounded by the first conductivity type source region;
The semiconductor device according to claim 1, wherein the second conductivity type contact region is provided around the first conductivity type source region except under a wiring portion that connects the adjacent gate electrodes.   3. The semiconductor device according to claim 1, wherein the second conductivity type contact region is separated by 0.5 μm or more from the gate electrode and a wiring portion that connects the adjacent gate electrodes. A first conductivity type silicon carbide substrate; and a first conductivity type silicon carbide layer having a lower impurity concentration than the first conductivity type silicon carbide substrate provided on the first main surface of the first conductivity type silicon carbide substrate; , A second conductivity type region provided in a part of a surface region of the first conductivity type silicon carbide layer, a first conductivity type source region provided in a surface region of the second conductivity type region, and the second A second conductivity type contact region having a higher impurity concentration than the second conductivity type region, and a source electrode in contact with the first conductivity type source region and the second conductivity type contact region, provided in a surface region of the conductivity type region; A gate insulating film provided on a surface of the second conductivity type region sandwiched between the first conductivity type silicon carbide layer and the first conductivity type source region; and on the gate insulation film And a gate electrode provided on the first conductivity type silicon carbide group A drain electrode provided on the second major surface of a method of manufacturing a semiconductor device including a
Forming a surface region of the first conductivity type silicon carbide layer so as to surround the first conductivity type source region;
Forming the second conductivity type contact region around the first conductivity type source region except under the wiring portion connecting the adjacent gate electrodes;
A method for manufacturing a semiconductor device, comprising: A first conductivity type silicon carbide substrate; and a first conductivity type silicon carbide layer having a lower impurity concentration than the first conductivity type silicon carbide substrate provided on the first main surface of the first conductivity type silicon carbide substrate; A second conductivity type base region provided in a part of a surface region of the first conductivity type silicon carbide layer; a second conductivity type silicon carbide layer provided on the surface of the first conductivity type silicon carbide layer; In the second conductivity type silicon carbide layer, the impurity concentration is higher than that of the first conductivity type silicon carbide substrate provided so as to penetrate the second conductivity type silicon carbide layer and to be in contact with the first conductivity type silicon carbide layer. A first conductivity type region having a lower impurity concentration and a first conductivity type having a higher impurity concentration than the first conductivity type region provided in a surface region of the second conductivity type silicon carbide layer apart from the first conductivity type region The second conductivity type carbonization in the source region and the second conductivity type silicon carbide layer A second conductivity type contact region having an impurity concentration higher than that of the second conductivity type base region, the first conductivity type source region; Provided on the surface of the region sandwiched between the first conductivity type region and the first conductivity type source region of the source electrode in contact with the second conductivity type contact region and the second conductivity type silicon carbide layer In a method for manufacturing a semiconductor device, comprising: a gate insulating film; a gate electrode provided on the gate insulating film; and a drain electrode provided on a second main surface of the first conductivity type silicon carbide substrate. ,
Forming the first conductivity type region so as to be surrounded by the first conductivity type source region;
Forming the second conductivity type contact region around the first conductivity type source region except under the wiring portion connecting the adjacent gate electrodes;
A method for manufacturing a semiconductor device, comprising:

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