JP2014038963A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce sheet resistance of a gate electrode and improve switching speed.SOLUTION: In a semiconductor device 1 including an SiC epitaxial layer 9, a gate insulation film 16 formed in contact with the SiC epitaxial layer 9 and a gate electrode 15 arranged on the gate insulation film 16 for controlling formation of a channel in the SiC epitaxial layer 9, all of a part of the gate electrode 15 is composed of a metal layer 19. Accordingly, in comparison with the case where a gate electrode only composed of polysilicon is used, sheet resistance of the gate electrode 15 can be reduced. As a result, switching speed of the semiconductor device 1 is improved thereby to reduce a switching loss.

Description

  The present invention relates to a semiconductor device using SiC.

2. Description of the Related Art Conventionally, semiconductor power devices mainly used in systems in various power electronics fields such as motor control systems and power conversion systems have attracted attention. As this type of semiconductor power device, for example, a SiC semiconductor device is known (see, for example, Patent Document 1).
The semiconductor device of Patent Document 1 is formed on a SiC substrate, an n-type high resistance layer formed on the SiC substrate, a p-well layer formed on the n-type high-resistance layer, and a surface layer portion of the p-well layer. An n ⁺ emitter region, a p ⁺ contact region penetrating the n ⁺ emitter region and reaching the p well layer, a trench penetrating the p well layer from the surface of the n ⁺ emitter region and reaching the n-type high resistance layer, A gate oxide film formed on the inner surface of the trench and a polysilicon gate electrode embedded in the trench are included.

JP 2008-294210 A

A semiconductor device according to one aspect of the present invention includes a SiC semiconductor layer, a gate insulating film formed in contact with the SiC semiconductor layer, and a channel formed in the SiC semiconductor layer, disposed on the gate insulating film. A gate electrode to be controlled, and the gate electrode includes a metal portion in whole or in part.
According to this configuration, since the metal portion is included, the sheet resistance of the gate electrode can be reduced as compared with the case where the gate electrode made of only polysilicon is used. As a result, the switching speed of the semiconductor device can be improved and the switching loss can be reduced.

Preferably, the gate electrode includes a polysilicon portion disposed between the metal portion constituting a part of the gate electrode and the gate insulating film.
According to this configuration, even when the metal part is formed by vapor deposition, plasma CVD (Chemical Vapor Deposition), sputtering, or the like, the gate insulating film can be protected by the polysilicon part during the formation. . Thereby, it is possible to prevent the metal plasma constituting the metal part from directly colliding with the gate insulating film. As a result, plasma damage can be prevented from occurring in the gate insulating film.

Preferably, the polysilicon portion is selectively formed on the gate insulating film.
According to this configuration, since the ratio of the metal portion in the gate electrode can be increased, the sheet resistance of the gate electrode can be further reduced.
The polysilicon portion is preferably formed on a portion of the SiC semiconductor layer where the channel is formed via the gate insulating film.

According to this configuration, it is possible to prevent the occurrence of plasma damage in the portion of the gate insulating film on the channel. Thereby, characteristics of the semiconductor device (for example, threshold voltage _Vth ) can be prevented from fluctuating with respect to the design specification. As a result, a highly reliable semiconductor device can be provided.
Further, the threshold voltage _Vth can be designed with a polysilicon work function. Therefore, the threshold voltage _Vth can be designed under the same conditions as in the case of a conventional gate electrode made of only polysilicon.

The polysilicon portion may be formed so as to cover the entire region on the gate insulating film.
According to this configuration, plasma damage can be prevented from occurring in the portion of the gate insulating film on the channel, and the polysilicon portion can be easily formed.
The polysilicon part is preferably made of p-type polysilicon.

For example, when the semiconductor device is an n-channel MISFET, the gate electrode made of only p-type polysilicon has an advantage that the threshold voltage _Vth can be increased, but conversely has a disadvantage that the sheet resistance is high. According to this configuration, by using the p-type polysilicon portion and the metal portion in combination, the disadvantage of the p-type polysilicon can be compensated by the metal portion having a low sheet resistance while taking advantage of the p-type polysilicon.

The polysilicon part and the metal part are a polysilicon layer and a metal layer laminated in this order from the SiC semiconductor layer side, and the polysilicon layer is preferably thinner than the metal layer. ).
According to this configuration, since the ratio of the metal layer in the gate electrode can be increased, the sheet resistance of the gate electrode can be further reduced.

The metal part is preferably made of copper (Cu) or tungsten (W).
Since copper (Cu) and tungsten (W) are excellent in step coverage, for example, when a buried gate electrode is formed in a recess such as a trench, the recess can be satisfactorily filled with a metal portion.

Preferably, the gate electrode includes a polysilicon carbide portion disposed between the metal portion constituting a part of the gate electrode and the gate insulating film.
According to this configuration, even when the metal portion is formed by vapor deposition, plasma CVD (Chemical Vapor Deposition), sputtering, or the like, the gate insulating film can be protected by the polysilicon carbide portion during the formation. it can. Thereby, it is possible to prevent the metal plasma constituting the metal part from directly colliding with the gate insulating film. As a result, plasma damage can be prevented from occurring in the gate insulating film.

Polysilicon carbide has a disadvantage that sheet resistance is high, but the disadvantage can be compensated for by using it together with a metal part having low sheet resistance. Furthermore, when the semiconductor device is an n-channel MISFET, the polysilicon carbide is preferably p-type polysilicon carbide. The p-type polysilicon carbide has an advantage that the threshold voltage _Vth can be increased for the n-channel MISFET as compared with the n-type polysilicon carbide. If the threshold voltage _Vth is high, the effect of preventing erroneous ON due to noise at the time of switching and the like is good, and therefore it is preferable that the threshold voltage _Vth is high. That is, in the configuration in which p-type polysilicon carbide is combined with n-channel MISFET, sheet resistance is low while taking advantage of p-type polysilicon carbide having a high threshold voltage _Vth by using p-type polysilicon carbide and a metal part in combination. The metal part can compensate for the disadvantage of p-type polysilicon carbide having high sheet resistance.

Preferably, the polysilicon carbide portion is selectively formed on the gate insulating film.
According to this configuration, since the ratio of the metal portion in the gate electrode can be increased, the sheet resistance of the gate electrode can be further reduced.
A semiconductor device according to another aspect of the present invention is selectively disposed on the SiC semiconductor layer so as to be exposed on the surface side of the SiC semiconductor layer and the first conductivity type SiC semiconductor layer functioning as a drain region. A second conductivity type well, a first conductivity type source region disposed in the well and surrounded by the well, and the SiC semiconductor layer as the source region and the drain region. A gate electrode disposed to control channel formation on the surface of the well; and a gate insulating film disposed between the gate electrode and the surface of the SiC semiconductor layer, the gate electrode comprising the SiC A polysilicon layer and a metal layer stacked in this order from the surface side of the semiconductor layer are included.

  According to this configuration, a planar gate type MIS (Metal Insulator Semiconductor) transistor structure is formed in the semiconductor device. In the planar gate type MIS transistor structure, a metal layer is included. Thereby, the sheet resistance of the gate electrode can be lowered as compared with the case where the gate electrode made of only polysilicon is used. As a result, the switching speed of the semiconductor device can be improved and the switching loss can be reduced.

  Furthermore, even when the metal layer is formed by vapor deposition, plasma CVD (Chemical Vapor Deposition), sputtering, or the like, the gate insulating film can be protected by the polysilicon layer during the formation. This can prevent the metal plasma constituting the metal layer from directly colliding with the gate insulating film. As a result, plasma damage can be prevented from occurring in the gate insulating film.

The polysilicon layer is preferably selectively formed on a portion of the well where the channel is formed via the gate insulating film.
According to this configuration, it is possible to prevent the occurrence of plasma damage in the portion of the gate insulating film on the channel. Thereby, characteristics of the semiconductor device (for example, threshold voltage _Vth ) can be prevented from fluctuating with respect to the design specification. As a result, a highly reliable semiconductor device can be provided.

Further, the threshold voltage _Vth can be designed with a polysilicon work function. Therefore, the threshold voltage _Vth can be designed under the same conditions as in the case of a conventional gate electrode made of only polysilicon.
The polysilicon layer may be formed so as to cover the entire region on the gate insulating film.

According to this configuration, it is possible to prevent the occurrence of plasma damage in the portion of the gate insulating film on the channel and to easily form the polysilicon layer.
A plurality of the wells may be arranged in a lattice pattern.
A semiconductor device according to still another aspect of the present invention is arranged so as to be exposed on a surface side of the SiC semiconductor layer, and a SiC semiconductor layer in which a gate trench is formed, and forms a part of a side surface of the gate trench. A source layer of a first conductivity type, and a second conductivity type of a second conductivity type disposed on and in contact with the source layer on the back side of the SiC semiconductor layer with respect to the source layer, and forming a part of the side surface of the gate trench A channel layer; a drain layer of a first conductivity type disposed on and in contact with the channel layer on the back side of the SiC semiconductor layer with respect to the channel layer; and forming the bottom surface of the gate trench; and the gate trench A gate insulating film formed on the side surface and the bottom surface, and embedded in the gate trench, on the side surface of the gate trench of the channel layer And a gate electrode that controls the formation of Yaneru, the gate electrode includes the aspects and / or polysilicon layer deposited from the bottom side in this order and the metal layer of the gate trench (claim 15).

  According to this configuration, the trench gate type MIS transistor structure is formed in the semiconductor device. In this trench gate type MIS transistor structure, a metal layer is included. Thereby, the sheet resistance of the gate electrode can be lowered as compared with the case where the gate electrode made of only polysilicon is used. As a result, the switching speed of the semiconductor device can be improved and the switching loss can be reduced.

  Furthermore, even when the metal layer is formed by vapor deposition, plasma CVD (Chemical Vapor Deposition), sputtering, or the like, the gate insulating film can be protected by the polysilicon layer during the formation. This can prevent the metal plasma constituting the metal layer from directly colliding with the gate insulating film. As a result, plasma damage can be prevented from occurring in the gate insulating film.

The polysilicon layer is selectively formed on the entire side surface of the gate trench, and the metal layer is in contact with a portion of the gate insulating film on the bottom surface of the gate trench. It is preferable to be embedded in a space surrounded by (claim 16).
According to this configuration, it is possible to prevent the occurrence of plasma damage in the portion of the gate insulating film facing the channel layer. Thereby, characteristics of the semiconductor device (for example, threshold voltage _Vth ) can be prevented from fluctuating with respect to the design specification. As a result, a highly reliable semiconductor device can be provided.

Further, the threshold voltage _Vth can be designed with a polysilicon work function. Therefore, the threshold voltage _Vth can be designed under the same conditions as in the case of a conventional gate electrode made of only polysilicon.
The polysilicon layer is formed so as to cover the entire inner surface of the gate trench following the side surface and the bottom surface of the gate trench, and the metal layer is embedded in a space surrounded by the polysilicon layer. (Claim 17).

According to this configuration, it is possible to prevent the occurrence of plasma damage in the portion of the gate insulating film facing the channel layer, and it is possible to easily form the polysilicon layer.
The SiC semiconductor layer includes an active region in which the channel is formed and an outer peripheral region surrounding the active region, and the gate trench is formed across the active region and the outer peripheral region, and the gate electrode Is formed so as to cover the surface of the SiC semiconductor layer from the opening end of the gate trench in the outer peripheral region, and has an overlap portion made of the metal layer, and the semiconductor device extends along the outer peripheral region. It is preferable to include a gate finger disposed so as to surround the active region and electrically connected to the overlap portion of the gate electrode.

According to this configuration, since the overlap portion to which the gate finger is connected is made of the metal layer, a current can be flowed favorably from the gate finger to the gate electrode.
The gate trench is formed in a lattice shape in the active region, and is formed in a stripe shape drawn from an end of the lattice trench in the outer peripheral region, and the gate finger is formed in the stripe trench. It is preferable that it is laid along the crossing direction (Claim 19).

The semiconductor device further includes an interlayer film formed on the surface of the SiC semiconductor layer so as to cover the gate electrode, and the gate finger penetrates the interlayer film at the center in the width direction to the gate electrode. It is preferable that the contact part to contact is included (claim 20).
Preferably, the contact portion is formed in a straight line surrounding the active region along the outer peripheral region (claim 21).

FIGS. 1A and 1B are schematic plan views of a semiconductor device according to the first embodiment of the present invention. FIG. 1A is an overall view, and FIG. Each is shown. FIG. 2 is a cross-sectional view taken along section line II-II in FIG. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. 4A and 4B are schematic plan views of the semiconductor device according to the third embodiment of the present invention. FIG. 4A is an overall view, and FIG. Each internal enlarged view is shown. FIGS. 5A, 5B, and 5C are cross-sectional views of the semiconductor device, and FIG. 5A is a cross-sectional view taken along section line Va-Va in FIG. FIG. 5B is a cross-sectional view taken along the cutting plane line Vb-Vb in FIG. 4B, and FIG. 5C is a cross-sectional view taken along the cutting plane line Vc-Vc in FIG. 6A, 6B, and 6C are schematic cross-sectional views of a semiconductor device according to the fourth embodiment of the present invention. 7A and 7B are schematic cross-sectional views of a semiconductor device according to the fifth embodiment of the present invention. 8A and 8B are schematic cross-sectional views of the semiconductor device according to the sixth embodiment of the present invention. FIGS. 9A and 9B are schematic cross-sectional views of a semiconductor device according to the seventh embodiment of the present invention. 10A and 10B are schematic cross-sectional views of a semiconductor device according to the eighth embodiment of the present invention. FIG. 11 is a layout diagram of a unit cell of the semiconductor device. FIG. 12 is another layout diagram of the unit cell of the semiconductor device. FIG. 13 is another layout diagram of the unit cell of the semiconductor device. FIG. 14 is another layout diagram of the unit cell of the semiconductor device. 15A and 15B are schematic cross-sectional views of the semiconductor device according to the ninth embodiment of the present invention. FIG. 16 is a layout diagram of a unit cell of the semiconductor device. FIG. 17 is another layout diagram of the unit cell of the semiconductor device. FIG. 18 is another layout diagram of the unit cell of the semiconductor device. FIG. 19 is another layout diagram of the unit cell of the semiconductor device. 20A and 20B are schematic cross-sectional views of the semiconductor device according to the tenth embodiment of the present invention. FIGS. 21A and 21B are schematic cross-sectional views of the semiconductor device according to the tenth embodiment of the present invention. FIG. 22 is a layout diagram of a unit cell of the semiconductor device. FIG. 23 is another layout diagram of the unit cell of the semiconductor device. FIG. 24 is another layout diagram of the unit cell of the semiconductor device. FIG. 25 is another layout diagram of the unit cell of the semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIGS. 1A and 1B are schematic plan views of a semiconductor device according to the first embodiment of the present invention. FIG. 1A is an overall view, and FIG. Each is shown. FIG. 2 is a cross-sectional view taken along section line II-II in FIG.
The semiconductor device 1 has, for example, a square chip shape in plan view as shown in FIG. The chip-like semiconductor device 1 has a length of about several millimeters in the vertical and horizontal directions on the paper surface of FIG. The semiconductor device 1 has an active region 2 that is disposed at the center thereof and functions as a field effect transistor, and an outer peripheral region 3 that surrounds the active region 2. A plurality of annular guard rings 4 are formed between the active region 2 and the outer peripheral region 3.

  In the active region 2, a source pad 5 made of a metal material such as aluminum is formed on the surface of the semiconductor device 1. The source pad 5 has a substantially square shape in plan view with the four corners curved outward, and is formed so as to cover almost the entire surface of the semiconductor device 1. The source pad 5 has a removal region 6 near the center of one side. The removal region 6 is a region where the source pad 5 is not formed.

A gate pad 7 is disposed in the removal region 6. A gap is provided between the gate pad 7 and the source pad 5, and these are insulated from each other.
Next, the internal structure of the semiconductor device 1 will be described.
A semiconductor device 1 includes a power MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) element using SiC (silicon carbide), on an SiC substrate 8 and an SiC substrate 8 as an example of an SiC semiconductor layer of the present invention. A formed SiC epitaxial layer 9 is included. The conductivity types of SiC substrate 8 and SiC epitaxial layer 9 are both n-type as the first conductivity type. Specifically, SiC substrate 8 is n ⁺ type (for example, the concentration is 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ ), and SiC epitaxial layer 9 is n ^{− having a} lower concentration than SiC substrate 8. It is a type | mold (for example, density | concentration is 1 * 10 < ¹⁵ > -1 * 10 < ¹⁷ > cm < ^-3 >). The SiC epitaxial layer 9 functions as a drain region (drift layer) of the field effect transistor.

In the active region 2, a plurality of p-type wells 10 are formed in a matrix form (matrix form) on the surface side of the SiC epitaxial layer 9. Each p-type well 10 constitutes a unit cell 11 in the active region 2. A drain electrode 12 made of, for example, a nickel metal film is formed on the back surface of the SiC substrate 8.
In each p-type well 10, an n ⁺ -type source region 13 and a p ⁺ -type well contact region 14 surrounded by the n ⁺ -type source region 13 are formed. Both n ⁺ type source region 13 and p ⁺ type well contact region 14 are exposed on the surface of SiC epitaxial layer 9. A gate electrode 15 is formed so as to straddle adjacent p-type wells 10, and a gate insulating film 16 is interposed between the gate electrode 15 and the SiC epitaxial layer 9.

The gate electrode 15 has a channel formation region 17 (for example, an annular shape (FIG. 1B)) between the n ⁺ -type source region 13 and the SiC epitaxial layer 9 as a drain region (region between adjacent p-type wells 10). (See reference))) to control the formation of the inversion layer (channel) on the surface of the p-type well 10. That is, the semiconductor device 1 has a so-called planar gate structure MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  Gate electrode 15 includes a polysilicon layer 18 and a metal layer 19 stacked in this order from the surface side of SiC epitaxial layer 9 via gate insulating film 16. The polysilicon layer 18 may be made of, for example, p-type polysilicon, and the metal layer 19 is made of, for example, aluminum (Al), molybdenum (Mo), titanium nitride (TiN), copper (Cu), tungsten (W ) Etc.

The polysilicon layer 18 is formed so as to cover the entire region so that the region on the gate insulating film 16 is hidden. Thereby, the polysilicon layer 18 is arranged over the entire portion between the metal layer 19 and the gate insulating film 16, and the contact between the metal layer 19 and the gate insulating film 16 is prevented by the polysilicon layer 18. .
In this embodiment, both the polysilicon layer 18 and the metal layer 19 have a uniform thickness, and the polysilicon layer 18 is formed thinner than the metal layer 19. For example, the thickness of the polysilicon layer 18 is 10% to 30% and the thickness of the metal layer 19 is 90% to 70% with respect to the total thickness of the gate electrode 15. Specifically, the thickness of the polysilicon layer 18 is 0.05 μm to 0.15 μm (preferably about 0.1 μm), and the thickness of the metal layer 19 is about 0.45 μm to 0.35 μm. (Preferably about 0.4 μm).

  In order to form the gate electrode 15 having such a stacked structure of the polysilicon layer 18 and the metal layer 19, for example, after depositing polysilicon on the SiC epitaxial layer 9 by a plasma CVD method or the like, an evaporation method, A metal material is deposited by plasma CVD, sputtering, or the like. Next, the deposited polysilicon and metal material are collectively patterned into the same shape. Thereby, the gate electrode 15 composed of the metal layer 19 and the polysilicon layer 18 is obtained.

Further, an interlayer film 20 made of an insulating material such as silicon oxide is formed so as to cover the gate electrode 15. In the interlayer film 20, a contact hole 21 is selectively formed in the central region of the p-type well 10. The contact hole 21 is formed in a region where a part of the p ⁺ type well contact region 14 and the surrounding n ⁺ type source region 13 can be selectively exposed.

A source pad 5 is formed so as to enter the contact hole 21. Source pad 5 is electrically connected to n ⁺ type source region 13 and p ⁺ type well contact region 14. Therefore, the n ⁺ -type source region 13 has the same potential as the source pad 5. Further, since the p-type well 10 is connected to the source pad 5 through the p ⁺ -type well contact region 14, it has the same potential as the source pad 5. On the other hand, the gate pad 7 (see FIG. 1A) is connected to the gate electrode 15 at a position not shown. As a result, the gate electrode 15 has the same potential as the gate pad 7.

According to this semiconductor device 1, by continuing the state in which no voltage is applied to the gate pad 7 (off control), the gap between the n ⁺ -type source region 13 and the SiC epitaxial layer 9 as the n-type drain region is It is electrically isolated by the p-type well 10 region. That is, a channel is not formed between the source and the drain, and the switch is turned off. On the other hand, by applying a voltage equal to or higher than the threshold voltage _Vth to the gate pad 7 with a drain voltage applied between the n ⁺ -type source region 13 and the SiC epitaxial layer 9 as the n-type drain region (ON control). ), A channel is formed in the channel formation region 17. This corresponds to a switch-on state.

In this semiconductor device 1, since the metal layer 19 is included in the gate electrode 15, the sheet resistance of the gate electrode 15 can be reduced as compared with the case where a gate electrode made of only polysilicon is used. As a result, the switching speed of the semiconductor device 1 can be improved and the switching loss can be reduced.
A polysilicon layer 18 is formed so as to cover the entire region on the gate insulating film 16. Therefore, the gate insulating film 16 can be protected by the polysilicon layer 18 when the metal layer 19 is formed by vapor deposition, plasma CVD, sputtering, or the like. Thereby, the metal plasma constituting the metal layer 19 can be prevented from directly colliding with the gate insulating film 16. As a result, it is possible to prevent plasma damage from occurring in the gate insulating film 16. That is, it is possible to prevent the occurrence of plasma damage in the portion of the gate insulating film 16 on the channel formation region 17. Therefore, characteristics of the semiconductor device 1 (for example, the threshold voltage _Vth ) can be prevented from changing with respect to the design specifications. As a result, a highly reliable semiconductor device 1 can be provided. Moreover, since the polysilicon layer 18 and the metal layer 19 can be formed by batch patterning, the manufacturing process can be simplified. Further, the threshold voltage _Vth of the semiconductor device 1 can be designed with a polysilicon work function. Therefore, the threshold voltage _Vth can be designed under the same conditions as in the case of a conventional gate electrode made of only polysilicon.

Further, when the semiconductor device 1 is an n-channel MISFET as in this embodiment, the gate electrode 15 made only of p-type polysilicon has an advantage that the threshold voltage _Vth can be increased. Has the disadvantage of being expensive. Therefore, according to the semiconductor device 1, the combined use of the p-type polysilicon layer 18 and the metal layer 19 makes use of the advantages of the p-type polysilicon, and compensates for the disadvantages of the p-type polysilicon with the metal layer 19 having a low sheet resistance. be able to.

Further, the proportion of the metal layer 19 in the gate electrode 15 is increased by forming the polysilicon layer 18 thinner than the metal layer 19. Thereby, the above effect of reducing the sheet resistance of the gate electrode 15 can be more effectively expressed.
FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. In FIG. 3, parts corresponding to the respective parts shown in FIG. 2 are denoted by the same reference numerals as those given to the respective parts, and description thereof is omitted.

  The gate electrode 15 in the semiconductor device 1 of the first embodiment includes a polysilicon layer 18 that covers the entire region on the gate insulating film 16 and a metal layer 19 laminated on the polysilicon layer 18. The gate electrode 32 in the semiconductor device 31 of the second embodiment includes a polysilicon layer 33 that selectively covers a region on the gate insulating film 16 and a metal layer 34 stacked on the polysilicon layer 33. The thickness of the polysilicon layer 33 is preferably the same as the thickness of the polysilicon layer 18 of the first embodiment.

The polysilicon layer 33 is disposed on the channel formation region 17 of each unit cell so that the gate insulating film 16 is exposed in a region between the adjacent unit cells 11 (p-type well 10). In this structure, a recess 35 sandwiched between adjacent polysilicon layers 33 is formed on a region between the unit cells 11 of the gate insulating film 16. In this embodiment, portions of the polysilicon layer 33 on the channel forming regions 17 extend in parallel with each other along the surface of the SiC epitaxial layer 9. Further, the portion of the polysilicon layer 33 on each channel formation region 17 may have an overlap portion that selectively covers the n ⁺ -type source region 13 and / or the region between adjacent unit cells 11. . Further, the end portion (region on the n ⁺ -type source region 13) of the gate insulating film 16 on the opposite side of the concave portion 35 may be exposed with respect to the portion on each channel forming region 17 of the polysilicon layer 33. A recess 36 sandwiched between the polysilicon layer 33 and the interlayer film 20 is formed at the end of the gate insulating film 16.

The metal layer 34 is formed so as to cover the polysilicon layer 33, and a part thereof is embedded in the recesses 35 and 36. Moreover, it is preferable that the metal layer 34 consists of the same material as the metal layer 19 of 1st Embodiment mentioned above.
In order to form the gate electrode 32 having the laminated structure of the polysilicon layer 33 and the metal layer 34, for example, polysilicon is deposited on the SiC epitaxial layer 9 by a plasma CVD method or the like, and then polysilicon is deposited. Patterning is selectively performed in a predetermined shape. As a result, a polysilicon layer 33 is formed on the channel formation region 17 of each unit cell 11. Next, a metal material is deposited so as to cover the polysilicon layer 33 by vapor deposition, plasma CVD, sputtering, or the like. Next, the deposited metal material is patterned. Thereby, the gate electrode 32 composed of the metal layer 34 and the polysilicon layer 33 is obtained.

According to the semiconductor device 31, the proportion of the metal layer 34 in the gate electrode 32 can be increased by the amount embedded in the recesses 35 and 36 as compared with the gate electrode 15 in the first embodiment. Therefore, the sheet resistance of the gate electrode 32 can be further reduced.
Further, the polysilicon layer 33 is disposed so as to cover the region on the channel formation region 17 of the gate insulating film 16. Therefore, it is possible to prevent the occurrence of plasma damage in the portion of the gate insulating film 16 on the channel formation region 17. Thereby, the characteristics (for example, threshold voltage _Vth ) of the semiconductor device 31 can be prevented from fluctuating with respect to the design specifications. As a result, a highly reliable semiconductor device 31 can be provided. Further, the threshold voltage _Vth of the semiconductor device 31 can be designed with a polysilicon work function. Therefore, the threshold voltage _Vth can be designed under the same conditions as in the case of a conventional gate electrode made of only polysilicon.

Of course, the same effect as the semiconductor device 1 of the first embodiment can also be achieved.
4A and 4B are schematic plan views of the semiconductor device according to the third embodiment of the present invention. FIG. 4A is an overall view, and FIG. Each internal enlarged view is shown.
The semiconductor device includes a power MISFET element using SiC. For example, the length in the vertical direction on the paper surface of FIG. 1 is about 1 mm.

  As shown in FIG. 4A, the semiconductor device 51 is disposed in the center of an SiC substrate 52 as an example of the SiC semiconductor layer of the present invention, and has an active region 53 that functions as a field effect transistor, and an active region 53. And an outer peripheral region 54 surrounding the outer periphery. For example, the source pad 55 made of aluminum is formed so as to cover almost the entire active region 53. In this embodiment, the source pad 55 has a square shape in plan view. A removal region 56 surrounding the central region of the source pad 55 is formed along the outer peripheral region 54 at the peripheral edge of the source pad 55. A part of the removal region 56 is selectively depressed toward the central region of the source pad 55. A gate pad 57 is installed in this recess. For example, the gate finger 58 made of aluminum extends from the gate pad 57 along the outer peripheral region 54 over the entire removal region 56. In this embodiment, the pair of gate fingers 58 are formed symmetrically with respect to the gate pad 57.

  As shown in FIG. 4B, a gate trench 59 is formed in the SiC substrate 52 immediately below the source pad 55 and the like. The gate trench 59 is formed across the active region 53 and the outer peripheral region 54. The gate trenches 59 are formed in a lattice shape in the active region 53, and are formed in a stripe shape drawn out from each end of the active trench 60 to the outer peripheral region 54, and used as a gate of the MISFET. 60, and a contact trench 61 serving as a contact with a gate electrode 67 (described later). The contact trench 61 is formed by an extension of the active trench 60. Note that the patterns of the active trench 60 and the contact trench 61 are not limited to these shapes. For example, the active trench 60 may have a stripe shape, a honeycomb shape, or the like. Further, the contact trench 61 may have a lattice shape, a honeycomb shape, or the like.

The active region 53 is further divided into a plurality of unit cells 62 by the active trench 60. In the active region 53, a plurality of unit cells 62 are regularly arranged in a matrix (matrix). On the upper surface of each unit cell 62, a p ⁺ type channel contact layer 63 is formed in the central region, and an n ⁺ type source layer 64 is formed so as to surround the p ⁺ type channel contact layer 63. The n ⁺ -type source layer 64 forms the side surface of each unit cell 62 (the side surface of the active trench 60).

  In the outer peripheral region 54, the gate fingers 58 are laid along the direction crossing the striped contact trench 61. In this embodiment, the gate finger 58 is laid in a region inside the longitudinal end portion of the contact trench 61 (the end opposite to the active trench 60), and the contact trench 61 has the end portion of the gate finger 58 as a gate finger. It protrudes outside 58. In a region further outside the terminal portion, the SiC substrate 52 is formed with a low step portion 65 dug down over the entire circumference of the outer peripheral region 54.

Next, basic sectional structures of the active region 53 and the outer peripheral region 54 of the semiconductor device 51 will be described.
5A, 5B, and 5C are cross-sectional views of a semiconductor device according to the third embodiment of the present invention, and FIG. 5A is a cross-sectional line Va-Va in FIG. FIG. 5B is a cross-sectional view seen from the cutting plane line Vb-Vb in FIG. 4B, and FIG. 5C is a cross-sectional view viewed from the cutting plane line Vc-Vc in FIG. Cross-sectional views are shown respectively.

As described above, the semiconductor device 51 includes the SiC substrate 52. In this embodiment, the SiC substrate 52 is an n-type (for example, an n ⁺ type having a concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ ) as the first conductivity type, and the drain region ( It functions as a drift layer.
A p-type channel layer 66 is formed on the surface side of SiC substrate 52 in active region 53. In the p-type channel layer 66, an n ⁺ -type source layer 64 and a p ⁺ -type channel contact layer 63 surrounded by the n ⁺ -type source layer 64 are formed. N ⁺ type source layer 64 and p ⁺ type channel contact layer 63 are both exposed on the surface of SiC substrate 52.

On the surface side of SiC substrate 52, a gate trench 59 that penetrates n ⁺ -type source layer 64 and p-type channel layer 66 and reaches SiC substrate 52 as a drain region is formed. The gate trench 59 divides the p-type channel layer 66 into a plurality of unit cells 62 arranged in a lattice, for example.
A gate electrode 67 is embedded in the gate trench 59, and a gate insulating film 68 is interposed between the gate electrode 67 and the SiC substrate 52.

In the active region 53, the gate electrode 67 extends between the n ⁺ -type source layer 64 and the SiC substrate 52 as the drain region, and is an inversion layer (on the side of the active trench 60) on the surface of the p-type channel layer 66 (side surface of the active trench 60). Channel) formation. In other words, the semiconductor device 51 has a so-called trench gate type MISFET.
The gate electrode 67 is embedded in the gate trench 59 (the active trench 60) up to the surface of the SiC substrate 52 in the active region 53, for example, as shown by hatching in FIG. 4B. Thereby, the gate electrode 67 is also formed in a lattice shape, and the upper surface of each unit cell 62 is exposed without being covered with the gate electrode 67. On the other hand, outer peripheral region 54 has an overlap portion 69 formed so as to cover the surface of SiC substrate 52 from the open end of gate trench 59 (contact trench 61). In this embodiment, the overlap portion 69 is formed so as to cross the stripe-shaped contact trench 61 along the gate finger 58.

  The gate electrode 67 includes a polysilicon layer 70 and a metal layer 71 that are stacked in this order from the side surface and the bottom surface side of the gate trench 59 via the gate insulating film 68. The polysilicon layer 70 may be made of, for example, p-type polysilicon, and the metal layer 71 may be made of, for example, aluminum (Al), molybdenum (Mo), titanium nitride (TiN), copper (Cu), tungsten (W ) Etc. Among these, copper (Cu) and tungsten (W) are preferable. Since copper (Cu) and tungsten (W) are excellent in step coverage, the gate trench 59 can be satisfactorily backfilled with the metal layer 71 when the buried gate electrode 67 is formed in the gate trench 59.

  The polysilicon layer 70 is formed so as to cover the entire inner surface of the gate trench 59 along the side surface and the bottom surface of the gate trench 59. Further, the polysilicon layer 70 may cover the surface of the SiC substrate 52 in the outer peripheral region 54 as in this embodiment. As a result, a space 72 surrounded by the polysilicon layer 70 is formed in the gate trench 59. Metal layer 71 is formed so as to fill this space 72 and to cover the surface of SiC substrate 52 from the open end of gate trench 59 in outer peripheral region 54. That is, the metal layer 71 forms an overlap portion 69 of the gate electrode 67 in the outer peripheral region 54. Since the polysilicon layer 70 covers the entire inner surface of the gate trench 59, the contact between the metal layer 71 and the gate insulating film 68 is prevented over the entire portion between the metal layer 71 and the gate insulating film 68. Yes.

  In this embodiment, the polysilicon layer 70 has a uniform thickness. For example, the thickness of the polysilicon layer 70 is 5% to 20% with respect to the width of the gate trench 59. Specifically, the width of the gate trench 59 is 1.3 μm to 1.0 μm (preferably 0.6 μm), and the thickness of the polysilicon layer 70 is 0.015 μm to 0.2 μm (preferably 0.8 μm). About 1 μm). Thereby, the polysilicon layer 70 is made thinner than the thickness of the metal layer 71 in the width direction of the gate trench 59.

  In order to form the gate electrode 67 having such a stacked structure of the polysilicon layer 70 and the metal layer 71, for example, a polycrystal is formed on the SiC substrate 52 by plasma CVD or the like so as to cover the entire inner surface of the gate trench 59. After depositing silicon, a metal material is deposited by vapor deposition, plasma CVD, sputtering, or the like. Next, the portion of the deposited polysilicon and metal material on the active region 53 is selectively removed by etch back. Thereby, a gate electrode 67 composed of the polysilicon layer 70 and the metal layer 71 is obtained.

An interlayer film 73 made of, for example, silicon oxide is formed on the surface of SiC substrate 52. In the interlayer film 73, a contact hole 74 is selectively formed in the central region of the p-type channel layer 66 in the active region 53. This contact hole 74 is formed in a region where a part of the p ⁺ type channel contact layer 63 and the surrounding n ⁺ type source layer 64 can be selectively exposed. As shown in FIG. 4B, a contact hole 75 is selectively formed in the interlayer film 73 in the outer peripheral region 54 immediately below the gate finger 58. In this embodiment, the contact hole 75 is formed in a straight line surrounding the active region 53 along the outer peripheral region 54 at the center in the width direction of the gate finger 58.

On the interlayer film 73, a source pad 55 and a gate finger 58 (gate pad 57) are formed. The source pad 55 enters all the contact holes 74 at once and is connected to the n ⁺ -type source layer 64 and the p ⁺ -type channel contact layer 63 in each unit cell 62. Therefore, the n ⁺ -type source layer 64 has the same potential as the source pad 55. Further, since the p-type channel layer 66 is connected to the source pad 55 through the p ⁺ -type channel contact layer 63, it has the same potential as the source pad 55. The gate finger 58 enters the contact hole 75 and is connected to the overlap portion 69 of the gate electrode 67 as a contact portion 76. Therefore, since the gate electrode 67 embedded in the active trench 60 is connected to the gate finger 58 via the overlap portion 69, it has the same potential as the gate finger 58 (gate pad 57).

According to this semiconductor device 51, by continuing the state in which no voltage is applied to the gate pad 57 (off control), the gap between the n ⁺ -type source layer 64 and the SiC substrate 52 as the n-type drain region is p. It is electrically insulated by the mold channel layer 66. That is, a channel is not formed between the source and the drain, and the switch is turned off. On the other hand, by applying a voltage equal to or higher than the threshold voltage _Vth to the gate pad 57 in a state where a drain voltage is applied between the n ⁺ -type source layer 64 and the SiC substrate 52 as the n-type drain region (ON control). A channel is formed on the side surface of the gate trench 59 of the p-type channel layer 66. This corresponds to a switch-on state.

In the semiconductor device 51, since the metal layer 71 is included in the gate electrode 67, the sheet resistance of the gate electrode 67 can be reduced as compared with the case where a gate electrode made of only polysilicon is used. As a result, the switching speed of the semiconductor device 51 can be improved and the switching loss can be reduced.
A polysilicon layer 70 is formed so as to cover the entire inner surface of the gate trench 59. Therefore, when forming the metal layer 71 by vapor deposition, plasma CVD, sputtering, or the like, the gate insulating film 68 in the gate trench 59 can be protected by the polysilicon layer 70. Thereby, the metal plasma constituting the metal layer 71 can be prevented from directly colliding with the gate insulating film 68. As a result, plasma damage can be prevented from occurring in the gate insulating film 68. That is, it is possible to prevent the occurrence of plasma damage in the portion of the gate insulating film 68 on the p-type channel layer 66. Therefore, characteristics of the semiconductor device 51 (for example, the threshold voltage _Vth ) can be prevented from changing with respect to the design specification. As a result, a highly reliable semiconductor device 51 can be provided. In addition, since the polysilicon layer 70 and the metal layer 71 can be formed by batch patterning (etch back), the manufacturing process can be simplified. Further, the threshold voltage _Vth of the semiconductor device 51 can be designed with the work function of polysilicon. Therefore, the threshold voltage _Vth can be designed under the same conditions as in the case of a conventional gate electrode made of only polysilicon.

Further, the gate electrode 67 made of only p-type polysilicon has an advantage that the threshold voltage _Vth can be lowered, but conversely has a disadvantage that the sheet resistance is high. Therefore, according to the semiconductor device 51, by using the p-type polysilicon layer 70 and the metal layer 71 in combination, the disadvantage of the p-type polysilicon is compensated by the metal layer 71 having a low sheet resistance while taking advantage of the p-type polysilicon. be able to.

Further, the proportion of the metal layer 71 in the gate electrode 67 is increased by forming the polysilicon layer 70 thinner than the metal layer 71. As a result, the above effect of reducing the sheet resistance of the gate electrode 67 can be more effectively exhibited.
Furthermore, since the contact portion 76 of the overlap portion 69 with the gate finger 58 is the metal layer 71, a current can be favorably passed from the gate finger 58 to the gate electrode 67.

6A, 6B, and 6C are schematic cross-sectional views of a semiconductor device according to the fourth embodiment of the present invention. 6 (a), (b), and (c), parts corresponding to those shown in FIGS. 5 (a), (b), and (c) are denoted by the same reference numerals as those given to those parts. Description of these parts is omitted.
The gate electrode 67 in the semiconductor device 51 of the third embodiment described above includes a polysilicon layer 70 that covers the entire inner surface of the gate trench 59 along the side surface and the bottom surface of the gate trench 59, and a space 72 inside the polysilicon layer 70. And a metal layer 71 embedded in the substrate. The gate electrode 82 in the semiconductor device 81 of the fourth embodiment includes a polysilicon layer 83 that is selectively formed on the entire side surface of the gate trench 59 so that the bottom surface of the gate trench 59 is exposed, and the polysilicon layer 83. And a metal layer 84 embedded in the space 85 inside. The thickness of the polysilicon layer 83 is preferably the same as the thickness of the polysilicon layer 70 of the third embodiment.

The metal layer 84 is buried in a space 85 surrounded by the polysilicon layer 83 so as to be in contact with a portion of the gate insulating film 68 on the bottom surface of the gate trench 59. The metal layer 84 is preferably made of the same material as the metal layer 71 of the third embodiment described above.
In order to form gate electrode 82 having such a laminated structure of polysilicon layer 83 and metal layer 84, for example, polycrystal is formed on SiC substrate 52 by plasma CVD or the like so as to cover the entire inner surface of gate trench 59. After the silicon is deposited, the portion of the polysilicon gate trench 59 on the bottom surface is selectively removed by etching. Next, a metal material is deposited by vapor deposition, plasma CVD, sputtering, or the like. Next, portions of the deposited polysilicon and metal material on the active region are selectively removed by etch back. Thereby, a gate electrode 82 composed of the polysilicon layer 83 and the metal layer 84 is obtained.

According to this semiconductor device 81, compared with the gate electrode 67 in the third embodiment described above, the portion on the bottom surface of the gate trench 59 of the polysilicon layer 83 is replaced with the metal layer 84. The ratio of the metal layer 84 can be increased. Therefore, the sheet resistance of the gate electrode 82 can be further reduced.
Further, the polysilicon layer 83 is disposed so as to cover the region on the p-type channel layer 66 of the gate insulating film 68. Therefore, it is possible to prevent the occurrence of plasma damage in the portion of the gate insulating film 68 on the p-type channel layer 66. Thereby, the characteristics (for example, the threshold voltage _Vth ) of the semiconductor device 81 can be prevented from fluctuating with respect to the design specifications. As a result, a highly reliable semiconductor device 81 can be provided. Further, the threshold voltage _Vth of the semiconductor device 81 can be designed with the work function of polysilicon. Therefore, the threshold voltage _Vth can be designed under the same conditions as in the case of a conventional gate electrode made of only polysilicon.

Of course, the same effect as the semiconductor device 81 of the third embodiment can also be achieved.
7A and 7B are schematic cross-sectional views of a semiconductor device according to the fifth embodiment of the present invention. In FIG. 7A, parts corresponding to the parts shown in FIG. 3 are given the same reference numerals as those given to the parts, and the description of those parts is omitted. Further, in FIG. 7B, parts corresponding to the respective parts shown in FIG. 6A are denoted by the same reference numerals as those given to the respective parts, and description thereof will be omitted. .

First, as shown in FIG. 7A, the semiconductor device 41 further includes a source trench 42 formed in the inner region of each unit cell 11. In this embodiment, the source trench 42 penetrates the p-type well 10 from the surface of the SiC epitaxial layer 9 and reaches the SiC epitaxial layer 9 as a drain region in the central portion of each unit cell 11.
A p-type source breakdown voltage holding region 43 is formed around the source trench 42. The source breakdown voltage holding region 43 is formed so as to reach the p-type well 10 from the bottom surface of the source trench 42 through its edge portion. A p ⁺ type well contact region 44 is formed on the surface of the source breakdown voltage holding region 43 so as to be exposed at the bottom surface of each source trench 42. The p ⁺ type well contact region 44 is electrically connected to the p type well 10 via the source breakdown voltage holding region 43. The source pad 5 is formed so as to enter the source trench 42. Thus, the source pad 5 is electrically connected to the n ⁺ type source region 13 on the side surface of the source trench 42 and electrically connected to the p ⁺ type well contact region 44 on the bottom surface of the source trench 42.

  7B, the semiconductor device 45 similarly further includes a source trench 46 formed in the inner region of each unit cell 62. In this embodiment, the source trench 46 penetrates the p-type channel layer 66 from the surface of the SiC substrate 52 and reaches the SiC substrate 52 as a drain region at the center of each unit cell 62. The depth of the source trench 46 is the same as the depth of the gate trench 59, for example.

A p-type source breakdown voltage holding region 47 is formed around the source trench 46. The source breakdown voltage holding region 47 is formed so as to reach the p-type channel layer 66 from the bottom surface of the source trench 46 through its edge portion. A p ⁺ -type channel contact layer 48 is formed on the surface portion of the source breakdown voltage holding region 47 so as to be exposed at the bottom surface of each source trench 46. The p ⁺ type channel contact layer 48 is electrically connected to the p type channel layer 66 through the source breakdown voltage holding region 47. The source pad 55 is formed so as to enter the source trench 46. As a result, the source pad 55 is electrically connected to the n ⁺ -type source layer 64 on the side surface of the source trench 46 and electrically connected to the p ⁺ -type channel contact layer 48 on the bottom surface of the source trench 46.

Also by the semiconductor devices 41 and 45 of the fifth embodiment, the same effect as that of the above-described embodiment can be achieved.
8A and 8B are schematic cross-sectional views of the semiconductor device according to the sixth embodiment of the present invention. In FIG. 8A, parts corresponding to the parts shown in FIG. 3 are given the same reference numerals as those given to the parts, and the description of those parts is omitted. Further, in FIG. 8B, parts corresponding to the respective parts shown in FIG. 6A are denoted by the same reference numerals as those given to the respective parts, and description of those parts is omitted. .

  First, as shown in FIG. 8A, the semiconductor device 91 further includes a source trench 92 formed in the inner region of each unit cell 11. The source trench 92 has an upper trench 93 having a depth from the surface of the SiC epitaxial layer 9 to the p-type well 10 and a width narrower than the upper trench 93, and extends from the p-type well 10 to the SiC epitaxial layer 9 as a drain region. A deep lower trench 94. Thus, the source trench 92 has a two-stage structure in which the side surface of the upper layer trench 93 extends one step outward from the side surface of the lower layer trench 94.

The p-type well 10 is exposed in a ring shape at the step portion between the upper layer trench 93 and the lower layer trench 94, and the p ⁺ type well contact region 95 is formed in the exposed portion.
A p-type source breakdown voltage holding region 96 is formed around the source trench 92. The source breakdown voltage holding region 96 is formed so as to reach the p-type well 10 from the bottom surface of the lower trench 94 through its edge. The source pad 5 is formed so as to enter the source trench 92. As a result, the source pad 5 is electrically connected to the n ⁺ type source region 13 on the side surface of the upper layer trench 93, and is electrically connected to the p ⁺ type well contact region 95 on the bottom surface of the upper layer trench 93 and the side surface of the lower layer trench 94. Connected.

  Further, as shown in FIG. 8B, the semiconductor device 97 similarly further includes a source trench 98 formed in the inner region of each unit cell 62. The source trench 98 has an upper trench 99 having a depth from the surface of the SiC substrate 52 to the p-type channel layer 66 and a width narrower than the upper trench 99, and extends from the p-type channel layer 66 to the SiC substrate 52 as a drain region. And a lower trench 100 having a depth. As a result, the source trench 98 has a two-stage structure in which the side surface of the upper layer trench 99 extends one step outward from the side surface of the lower layer trench 100.

A p-type channel layer 66 is exposed in a ring shape at a step portion between the upper trench 99 and the lower trench 100, and a p ⁺ -type channel contact layer 101 is formed in the exposed portion.
A p-type source breakdown voltage holding region 102 is formed around the source trench 98. The source breakdown voltage holding region 102 is formed so as to reach the p-type channel layer 66 from the bottom surface of the lower trench 100 through its edge portion. The source pad 55 is formed so as to enter the source trench 98. As a result, the source pad 55 is electrically connected to the n ⁺ type source layer 64 at the side surface of the upper layer trench 99, and is electrically connected to the p ⁺ type channel contact layer 101 at the bottom surface of the upper layer trench 99 and the side surface of the lower layer trench 100. Connected.

The semiconductor devices 91 and 97 according to the sixth embodiment can achieve the same effects as those of the above-described embodiment.
FIGS. 9A and 9B are schematic cross-sectional views of a semiconductor device according to the seventh embodiment of the present invention. In FIG. 9A, parts corresponding to the parts shown in FIG. 3 are denoted by the same reference numerals as those given to the respective parts, and description thereof will be omitted. Further, in FIG. 9B, parts corresponding to the parts shown in FIG. 6A are denoted by the same reference numerals as those given to those parts, and the description of those parts is omitted. .

  First, as shown in FIG. 9A, the semiconductor device 111 further includes a p-type pillar layer 112 formed in the SiC epitaxial layer 9 as a drain region. The p-type pillar layer 112 is formed in the inner region of the p-type well 10 of each unit cell 11. In this embodiment, the p-type pillar layer 112 is formed in a substantially central region of the p-type well 10, for example, similar to the p-type well 10 (in the layout of FIG. 1B, a square in plan view). The p-type pillar layer 112 is formed so as to continue to the p-type well 10, and extends toward the back surface of the SiC epitaxial layer 9 to a position deeper than the p-type well 10 in the SiC epitaxial layer 9 as a drain region. Yes. That is, the p-type pillar layer 112 is formed in a substantially columnar shape (substantially a square columnar shape in the layout of FIG. 1B). Thereby, the SiC epitaxial layer 9 includes a p-type pillar layer 112 arranged at an appropriate pitch, and an SiC epitaxial layer 9 as an n-type drain region sandwiched between the p-type pillar layers 112 adjacent to each other. The SiC epitaxial layers 9 are alternately arranged in a direction along the surface.

  As shown in FIG. 9B, in the semiconductor device 113, a p-type pillar layer 114 is formed in the SiC substrate 52 as a drain region. The p-type pillar layer 114 is formed in an inner region of the p-type channel layer 66 of each unit cell 62. More specifically, in this embodiment, the p-type pillar layer 114 is similar to the p-type channel layer 66 in a substantially central region of the p-type channel layer 66 (in plan view in the layout of FIG. 4B). (Rectangle). The p-type pillar layer 114 is formed to be continuous with the p-type channel layer 66, and extends toward the back surface of the SiC substrate 52 to a position deeper than the p-type channel layer 66 in the SiC substrate 52 as a drain region. Yes. That is, the p-type pillar layer 114 is formed in a substantially columnar shape (substantially a square columnar shape in the layout of FIG. 4B). Thereby, the SiC substrate 52 includes the p-type pillar layers 114 arranged at an appropriate pitch and the SiC substrate 52 as an n-type drain region sandwiched between the p-type pillar layers 114 adjacent to each other. They are alternately arranged in the direction along the surface of the substrate 52.

Also by the semiconductor devices 111 and 113 of the seventh embodiment, the same effect as that of the above-described embodiment can be achieved.
10A and 10B are schematic cross-sectional views of a semiconductor device according to the eighth embodiment of the present invention. In FIG. 10 (a), parts corresponding to the respective parts shown in FIG. 3 are denoted by the same reference numerals as those given to the respective parts, and description thereof will be omitted. Further, in FIG. 10B, the same reference numerals as those given to the respective parts shown in FIG. 6A are assigned to the parts corresponding to the respective parts shown in FIG. 6A, and description thereof will be omitted. .

  First, as shown in FIG. 10A, the semiconductor device 121 further includes a p-type floating layer 122 formed in the SiC epitaxial layer 9 as a drain region. The p-type floating layer 122 is formed in the inner region of the p-type well 10 of each unit cell 11. In this embodiment, the p-type floating layer 122 is disposed at a distance from the p-type well 10 just below the central region of the p-type well 10. Thereby, the p-type floating layer 122 is insulated from the p-type well 10.

  As shown in FIG. 10B, the semiconductor device 123 further includes a p-type floating layer 124 formed in the SiC substrate 52 as a drain region. The p-type floating layer 124 is formed in the inner region of the p-type channel layer 66 of each unit cell 62. In this embodiment, the p-type floating layer 124 is disposed at a distance from the p-type channel layer 66 immediately below the central region of the p-type channel layer 66. Thereby, the p-type floating layer 124 is insulated from the p-type channel layer 66.

Also by the semiconductor devices 121 and 123 of the eighth embodiment, the same effect as that of the above-described embodiment can be achieved.
Next, an arrangement pattern of the plurality of unit cells 11 and 62 will be described with reference to FIGS. The arrangement pattern of the plurality of unit cells 11 and 62 is not limited to these. 11 to 14 exemplify the arrangement pattern of the unit cells 62 in the description of the arrangement pattern, and parts corresponding to the respective parts shown in FIG. 4B are denoted by the same reference numerals. Show.

  In the above description, as shown in FIG. 11, the square unit cells 11 and 62 are regularly arranged in a matrix (matrix). Each unit cell 11, 62 may be formed in a rectangular shape having a long side and a short side, for example, as shown in FIG. In this case, the unit cells 11 and 62 may be regularly arranged in a matrix (matrix). Each unit cell 11, 62 may be formed in a hexagonal shape (for example, a regular hexagonal shape). The arrangement pattern of the plurality of unit cells 11 and 62 may be honeycomb. In other words, the plurality of unit cells 11 and 62 may be arranged in a zigzag pattern in which the adjacent unit cells 11 and 62 are staggered. This staggered arrangement may be applied to square unit cells 11 and 62 as shown in FIG.

  15A and 15B are schematic cross-sectional views of the semiconductor device according to the ninth embodiment of the present invention. In FIG. 15 (a), parts corresponding to the respective parts shown in FIG. 3 are denoted by the same reference numerals as those given to the respective parts, and description thereof will be omitted. Further, in FIG. 15B, parts corresponding to the respective parts shown in FIG. 6A are denoted by the same reference numerals as those given to the respective parts, and description thereof will be omitted. . FIGS. 16 to 19 are diagrams for explaining the layout of the unit cells 11 and 62 in FIGS. 15A and 15B, and illustrate the arrangement pattern of the unit cells 62. FIG.

First, as shown in FIG. 15A, the semiconductor device 131 further includes a p ⁻ type relaxation layer 133 that is selectively formed in a lattice-like n ⁻ type epiline 132 that partitions each unit cell 11. The p ⁻ type relaxation layer 133 includes a first portion 134 disposed at the intersection of the n ⁻ type epiline 132.
p ^- a first portion 134 of the type relaxation layer 133, n ^- width wider than type epitaxial lines 132, n ^- are formed so as to cross the type epitaxial lines 132 in the width direction. In this embodiment, the first portion 134 is formed in a larger shape than the intersecting portion so as to overlap the unit cell 11 (p-type well 10) surrounding the intersecting portion of the n ⁻ type epiline 132 in plan view. Yes.

As shown in FIG. 15B, the semiconductor device 135 further includes a p ⁻ type relaxation layer 136 selectively formed in a lattice-like gate trench 59 (contact trench 61) that partitions each unit cell 62. Including. The p ⁻ type relaxation layer 136 includes a first portion 137 disposed at the intersection of the gate trench 59.
The first portion 137 of the p ⁻ type relaxation layer 136 has a width wider than that of the gate trench 59 and is formed so as to cross the gate trench 59 in the width direction. In this embodiment, the first portion 137 is formed in a shape larger than the intersecting portion so as to overlap the unit cell 62 (p-type channel layer 66) surrounding the intersecting portion of the gate trench 59 in plan view. .

The p ⁻ type relaxation layers 133 and 136 of this embodiment have different positions and shapes each time the arrangement patterns of the unit cells 11 and 62 are different. For example, in the arrangement patterns shown in FIGS. As shown in FIG.
Also by the semiconductor devices 121 and 123 of the ninth embodiment, the same operational effects as those of the above-described embodiments can be achieved.

  20A and 20B are schematic cross-sectional views of the semiconductor device according to the tenth embodiment of the present invention. FIGS. 21A and 21B are schematic cross-sectional views of the semiconductor device according to the tenth embodiment of the present invention. 20 (a) and 20 (b), portions corresponding to the respective portions shown in FIG. 3 and FIG. 15 (a) are denoted by the same reference numerals as those denoted for the respective portions, and those portions are described. Description is omitted. 21 (a) and 21 (b), parts corresponding to those shown in FIGS. 6 (a) and 15 (b) are given the same reference numerals as those given to the respective parts. Description of these portions is omitted. FIGS. 22 to 25 are diagrams for explaining the layout of the unit cells 11 and 62 in FIGS. 20A, 20B, and 21A, 21B. FIG. Is illustrated.

First, as shown in FIGS. 20A and 20B, the p ⁻ type relaxation layer 133 of the semiconductor device 141 further includes a second portion 142 disposed over the entire n ⁻ type epiline 132. That is, the p ⁻ type relaxation layer 133 is also formed as the second portion 142 in the linear portion of the n ⁻ type epiline 132.
The second portion 142 of the p ⁻ type relaxation layer 133 is formed along the n ⁻ type epiline 132 with a width narrower than that of the n ⁻ type epiline 132. In this embodiment, the second portion 142 is formed at an interval from each p-type well 10 of the plurality of unit cells 11 adjacent to each other. By providing a space between the second portion 142 and the p-type well 10, a path for a drain current flowing through the n ⁻ -type epiline 132 along the side surface of each p-type well 10 when the semiconductor device 141 is turned on is secured. Can do. Therefore, an increase in on-resistance can be suppressed and a favorable transistor operation can be performed. The second portion 142 is formed shallower than the first portion 134.

21A and 21B, the p ⁻ type relaxation layer 136 of the semiconductor device 143 further includes a second portion 144 arranged over the entire gate trench 59. That is, the p ⁻ type relaxation layer 136 is also formed as the second portion 144 in the straight portion of the gate trench 59.
The second portion 144 of the p ⁻ type relaxation layer 136 is formed along the gate trench 59 with a width narrower than that of the gate trench 59. In this embodiment, the second portion 144 is formed with a space from each p-type channel layer 66 of the plurality of unit cells 62 adjacent to each other. By providing a space between the second portion 144 and the p-type channel layer 66, a path for drain current flowing along the side surface of the gate trench 59 of each p-type channel layer 66 when the semiconductor device 143 is turned on is secured. Can do. Therefore, an increase in on-resistance can be suppressed and a favorable transistor operation can be performed. The second portion 144 is formed shallower than the first portion 137.

The p ⁻ type relaxation layers 133 and 136 of this embodiment have different positions and shapes each time the arrangement patterns of the unit cells 11 and 62 are different. For example, in the arrangement patterns shown in FIGS. As shown in FIG.
The semiconductor devices 141 and 143 of the ninth embodiment can achieve the same functions and effects as those of the previous embodiments.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, a configuration in which the conductivity type of each semiconductor portion of each semiconductor device described above is inverted may be employed. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.

Further, in the gate electrodes 15, 32, 67, 82, a polysilicon carbide layer may be used instead of the polysilicon layer.
Further, all of the gate electrodes 15, 32, 67, 82 may be made of metal.
The semiconductor device of the present invention is a power module used in an inverter circuit constituting a drive circuit for driving an electric motor used as a power source for an electric vehicle (including a hybrid vehicle), a train, an industrial robot, etc., for example. Can be incorporated into. It can also be incorporated into a power module used in an inverter circuit that converts electric power generated by a solar cell, wind power generator, or other power generation device (especially an in-house power generation device) to match the power of a commercial power source.

In addition, features grasped from the disclosure of the above-described embodiments can be combined with each other even in different embodiments. Moreover, the components represented in each embodiment can be combined within the scope of the present invention.
In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Active area | region 3 Peripheral area | region 8 SiC substrate 9 SiC epitaxial layer 10 P-type well 13 n ⁺ type | mold source region 15 Gate electrode 16 Gate insulating film 18 Polysilicon layer 19 Metal layer 31 Semiconductor device 32 Gate electrode 33 Polysilicon layer 34 Metal layer 41 Semiconductor device 45 Semiconductor device 51 Semiconductor device 52 SiC substrate 53 Active region 54 Peripheral region 58 Gate finger 59 Gate trench 60 Active trench 61 Contact trench 64 n ⁺ type source layer 66 p type channel layer 67 Gate electrode 68 Gate insulation Film 69 Overlap part 70 Polysilicon layer 71 Metal layer 72 Space 73 Interlayer film 76 Contact part 81 Semiconductor device 82 Gate electrode 83 Polysilicon layer 84 Metal layer 85 Space 91 Semiconductor Device 97 semiconductor device 111 a semiconductor device 113 a semiconductor device 121 a semiconductor device 123 a semiconductor device 131 a semiconductor device 135 a semiconductor device 141 a semiconductor device 143 a semiconductor device

Claims (21)

A SiC semiconductor layer;
A gate insulating film formed in contact with the SiC semiconductor layer;
A gate electrode disposed on the gate insulating film and controlling the formation of a channel in the SiC semiconductor layer;
The gate electrode includes a metal part in its entirety or in part.   2. The semiconductor device according to claim 1, wherein the gate electrode includes a polysilicon portion disposed between the metal portion constituting the part of the gate electrode and the gate insulating film.   The semiconductor device according to claim 2, wherein the polysilicon portion is selectively formed on the gate insulating film.   The semiconductor device according to claim 3, wherein the polysilicon portion is formed on a portion of the SiC semiconductor layer where the channel is formed via the gate insulating film.   The semiconductor device according to claim 2, wherein the polysilicon portion is formed so as to cover the entire region on the gate insulating film.   The semiconductor device according to claim 2, wherein the polysilicon portion is made of p-type polysilicon. The polysilicon part and the metal part are a polysilicon layer and a metal layer laminated in this order from the SiC semiconductor layer side,
The semiconductor device according to claim 2, wherein the polysilicon layer is thinner than the metal layer.   The semiconductor device according to claim 1, wherein the metal part is made of copper (Cu) or tungsten (W).   2. The semiconductor device according to claim 1, wherein the gate electrode includes a polysilicon carbide portion disposed between the metal portion constituting a part of the gate electrode and the gate insulating film.   The semiconductor device according to claim 9, wherein the polysilicon carbide portion is selectively formed on the gate insulating film. A first conductivity type SiC semiconductor layer functioning as a drain region;
A second conductivity type well selectively disposed on the SiC semiconductor layer so as to be exposed on the surface side of the SiC semiconductor layer;
A source region of a first conductivity type disposed in the well and surrounded by the well;
A gate electrode that is disposed between the source region and the SiC semiconductor layer as the drain region and controls the formation of a channel on the surface of the well;
A gate insulating film disposed between the gate electrode and the surface of the SiC semiconductor layer;
The gate electrode includes a polysilicon layer and a metal layer stacked in this order from the surface side of the SiC semiconductor layer.   The semiconductor device according to claim 11, wherein the polysilicon layer is selectively formed on a portion of the well where the channel is formed via the gate insulating film.   The semiconductor device according to claim 11, wherein the polysilicon layer is formed so as to cover an entire region on the gate insulating film.   The semiconductor device according to claim 11, wherein a plurality of the wells are arranged in a lattice pattern. A SiC semiconductor layer in which a gate trench is formed;
A source layer of a first conductivity type disposed so as to be exposed on a surface side of the SiC semiconductor layer and forming a part of a side surface of the gate trench;
A channel layer of a second conductivity type disposed on the back side of the SiC semiconductor layer with respect to the source layer so as to be in contact with the source layer and forming a part of the side surface of the gate trench;
A drain layer of a first conductivity type disposed on the back side of the SiC semiconductor layer with respect to the channel layer so as to be in contact with the channel layer and forming the bottom surface of the gate trench;
A gate insulating film formed on the side surface and the bottom surface of the gate trench;
A gate electrode embedded in the gate trench and controlling the formation of a channel on the side surface of the gate trench of the channel layer;
The gate electrode includes a polysilicon layer and a metal layer stacked in this order from the side surface and / or the bottom surface side of the gate trench. The polysilicon layer is selectively formed on the entire side surface of the gate trench;
The semiconductor device according to claim 15, wherein the metal layer is embedded in a space surrounded by the polysilicon layer so as to contact a portion of the gate insulating film on the bottom surface of the gate trench. The polysilicon layer is formed so as to cover the entire inner surface of the gate trench, following the side surface and the bottom surface of the gate trench,
The semiconductor device according to claim 15, wherein the metal layer is embedded in a space surrounded by the polysilicon layer. The SiC semiconductor layer includes an active region in which the channel is formed, and an outer peripheral region surrounding the active region,
The gate trench is formed across the active region and the outer peripheral region,
The gate electrode is formed so as to cover the surface of the SiC semiconductor layer from the opening end of the gate trench in the outer peripheral region, and has an overlap portion made of the metal layer,
18. The semiconductor device according to claim 15, wherein the semiconductor device includes a gate finger disposed so as to surround the active region along the outer peripheral region and electrically connected to the overlap portion of the gate electrode. The semiconductor device according to item. The gate trench is formed in a lattice shape in the active region, and is formed in a stripe shape drawn from the end of the lattice trench in the outer peripheral region,
The semiconductor device according to claim 18, wherein the gate finger is laid along a direction crossing the stripe-shaped trench. The semiconductor device further includes an interlayer film formed on the surface of the SiC semiconductor layer so as to cover the gate electrode,
The semiconductor device according to claim 18, wherein the gate finger includes a contact portion that penetrates the interlayer film and contacts the gate electrode at a center in a width direction thereof.   21. The semiconductor device according to claim 20, wherein the contact portion is formed in a straight line surrounding the active region along the outer peripheral region.

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