JP2016015353A - Semiconductor manufacturing apparatus, semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor manufacturing apparatus, semiconductor device and semiconductor device manufacturing method Download PDF

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JP2016015353A
JP2016015353A JP2012254384A JP2012254384A JP2016015353A JP 2016015353 A JP2016015353 A JP 2016015353A JP 2012254384 A JP2012254384 A JP 2012254384A JP 2012254384 A JP2012254384 A JP 2012254384A JP 2016015353 A JP2016015353 A JP 2016015353A
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substrate
tray
heater
layer
semiconductor
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憲 佐藤
Ken Sato
憲 佐藤
博一 後藤
Hiroichi Goto
博一 後藤
洋志 鹿内
Hiroshi Shikauchi
洋志 鹿内
慶太郎 土屋
Keitaro Tsuchiya
慶太郎 土屋
篠宮　勝
Masaru Shinomiya
勝 篠宮
和徳 萩本
Kazunori Hagimoto
和徳 萩本
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Sanken Electric Co Ltd
Shin Etsu Handotai Co Ltd
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Sanken Electric Co Ltd
Shin Etsu Handotai Co Ltd
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Priority to JP2012254384A priority Critical patent/JP2016015353A/en
Priority to PCT/JP2013/006135 priority patent/WO2014080566A1/en
Priority to TW102139354A priority patent/TW201428994A/en
Publication of JP2016015353A publication Critical patent/JP2016015353A/en
Pending legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C23C16/303—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/10—Heating of the reaction chamber or the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing apparatus, a semiconductor device and a semiconductor device manufacturing method, which can restrict a temperature distribution occurring in a substrate at the time of forming an epitaxial growth layer.SOLUTION: A semiconductor manufacturing apparatus according to the present embodiment comprises a tray 12 installed in a chamber and a heater 20 for heating the tray 12 from the undersurface side, and heats a substrate 110 arranged on the tray 12 by the heater 20 via the tray 12 to form an electron supply layer 123 composed of a nitride-based compound semiconductor on the substrate 110. The semiconductor manufacturing apparatus is composed in a manner capable of increasing when forming an epitaxial growth layer 123, a quantity of heat applied from the heater 20 to the tray 12 at a portion having a wider gap between an undersurface of the substrate 110 and a top face of the tray 12 in comparison of a portion having a narrower gap between the undersurface of the substrate 110 and the top face of the tray 12.

Description

本発明は、チャンバ内に設置されたトレイと、トレイを下面側から加熱するヒータと、を備え、トレイ上に配置された基板をヒータでトレイを介して加熱して、基板上に窒化物系化合物半導体で構成されるエピタキシャル成長層を形成する半導体製造装置、半導体装置、および、半導体装置の製造方法に関する。   The present invention includes a tray installed in a chamber and a heater that heats the tray from the lower surface side, and the substrate disposed on the tray is heated via the tray with the heater to form a nitride system on the substrate. The present invention relates to a semiconductor manufacturing apparatus, a semiconductor device, and a manufacturing method of a semiconductor device that form an epitaxial growth layer composed of a compound semiconductor.

窒化ガリウム系化合物半導体は、例えばＳｉＣやＳｉ、あるいはサファイアといった材料から構成される基板上にエピタキシャル成長させて形成されるのが一般的である。しかし、窒化ガリウム系化合物半導体と格子整合する基板がなく、さらに窒化ガリウム系化合物半導体と基板との線膨張係数も大きく異なることから、反り等が発生し、基板に温度分布が発生するという問題を抱えている。例えば、窒化ガリウム系化合物半導体の結晶成長方法としては、有機金属化学気相成長法（ＭＯＣＶＤ）や分子線エピタキシャル成長法（ＭＢＥ）等が一般的であるが、これらの方法で結晶成長させる場合、トレイ上に基板を配置し、ヒータの熱でトレイを介して基板を加熱する。このとき、トレイ本体は、ヒータと熱電対や放射温度計等による温度制御法によって均一な温度制御がなされているが、基板と結晶層との間の応力によって反りが生じ、トレイから基板の一部が浮き上がり、基板表面温度が均一でなくなることがある。   The gallium nitride compound semiconductor is generally formed by epitaxial growth on a substrate made of a material such as SiC, Si, or sapphire. However, there is no substrate that is lattice-matched with the gallium nitride compound semiconductor, and the linear expansion coefficients of the gallium nitride compound semiconductor and the substrate are greatly different, which causes warpage and temperature distribution on the substrate. I have it. For example, as a crystal growth method for a gallium nitride-based compound semiconductor, a metal organic chemical vapor deposition method (MOCVD), a molecular beam epitaxial growth method (MBE), or the like is generally used. A board | substrate is arrange | positioned on top and a board | substrate is heated through a tray with the heat of a heater. At this time, the tray body is uniformly controlled by a temperature control method using a heater, a thermocouple, a radiation thermometer, etc., but warpage occurs due to the stress between the substrate and the crystal layer, and the tray main body is The part may float up and the substrate surface temperature may not be uniform.

そこで、特許文献１では、基板の反りのデータを温度制御にフィードバックし、歩留まりの少ないエピタキシャルウエハを形成する対策が提案されている。   Therefore, Patent Document 1 proposes a countermeasure for forming an epitaxial wafer with a low yield by feeding back substrate warpage data to temperature control.

特開２００６−１５６４５４号公報JP 2006-156454 A

ところで、このような従来の半導体装置の製造では、基板とエピタキシャル成長層の線膨張係数の違いによって基板に反りが生じる。そして、この反りによって、基板と基板を配置しているトレイとの間で隙間が大きくなることで、基板温度が不均一になる、すなわち、基板の面内温度分布が大きく不均一となる。このため、基板が常温に戻ったときに各層の面内均一性に悪影響を与えることが懸念される。   By the way, in the manufacture of such a conventional semiconductor device, the substrate is warped due to the difference in linear expansion coefficient between the substrate and the epitaxial growth layer. This warpage increases the gap between the substrate and the tray on which the substrate is placed, resulting in nonuniform substrate temperature, that is, large in-plane temperature distribution of the substrate. For this reason, there is a concern that the in-plane uniformity of each layer is adversely affected when the substrate returns to room temperature.

従って、各層の形成では基板の温度分布を小さくすること、すなわちこの反りを抑えることは重要であり、特にエピタキシャル成長層の形成時には各層の面内の厚みを実質的に均一化するためにも重要である。   Therefore, in forming each layer, it is important to reduce the temperature distribution of the substrate, that is, to suppress this warp. In particular, when forming an epitaxial growth layer, it is also important to make the in-plane thickness of each layer substantially uniform. is there.

特許文献１では、サファイア基板上に発光デバイスを設けたものであり、基板に生じる反りをモニタすることは記載されているが、デバイスに対してどのように制御するかは記載されていない。   In Patent Document 1, a light emitting device is provided on a sapphire substrate, and it is described that the warpage generated on the substrate is monitored, but it is not described how to control the device.

本発明は上記課題に鑑みてなされたものであり、エピタキシャル成長層の形成時に基板に生じる温度分布を小さくすることができる半導体製造装置、半導体装置、および、半導体装置の製造方法を提供することを課題とする。   The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor manufacturing apparatus, a semiconductor device, and a semiconductor device manufacturing method capable of reducing the temperature distribution generated in the substrate during the formation of the epitaxial growth layer. And

上記課題を解決するために、本発明に係る半導体製造装置は、チャンバ内に設置されたトレイと、前記トレイを下面側から加熱するヒータと、を備え、前記トレイ上に配置された基板を前記ヒータで前記トレイを介して加熱して、前記基板上に窒化物系化合物半導体で構成されるエピタキシャル成長層を形成する半導体製造装置であって、前記エピタキシャル成長層を形成する際に、前記基板の下面と前記トレイの上面との間隔が広い部分では、前記基板の下面と前記トレイの上面との間隔が狭い部分に比べ、前記ヒータから前記トレイに与えられる熱量を高くすることが可能な構成にされていることを特徴とする。   In order to solve the above problems, a semiconductor manufacturing apparatus according to the present invention includes a tray installed in a chamber, and a heater that heats the tray from the lower surface side, and the substrate disposed on the tray A semiconductor manufacturing apparatus for forming an epitaxial growth layer composed of a nitride-based compound semiconductor on the substrate by heating through the tray with a heater, and when forming the epitaxial growth layer, a lower surface of the substrate In a portion where the distance between the upper surface of the tray is wide and the portion where the distance between the lower surface of the substrate and the upper surface of the tray is narrow, the amount of heat given from the heater to the tray can be increased. It is characterized by being.

また、本発明に係る半導体装置は、請求項１に記載の半導体製造装置を用いて製造された半導体装置であって、前記基板はシリコン系基板であり、前記基板上に第１の窒化物系化合物半導体で構成される電子走行層の上に形成されていて、前記第１の窒化物系化合物半導体と異なる組成式を有する第２の窒化物系化合物半導体で構成される電子供給層を前記エピタキシャル成長層として備えることを特徴とする。   A semiconductor device according to the present invention is a semiconductor device manufactured using the semiconductor manufacturing apparatus according to claim 1, wherein the substrate is a silicon-based substrate, and a first nitride-based substrate is formed on the substrate. Epitaxial growth of an electron supply layer made of a second nitride compound semiconductor formed on an electron transit layer made of a compound semiconductor and having a composition formula different from that of the first nitride compound semiconductor It is provided as a layer.

また、本発明に係る半導体装置の製造方法は、請求項１に記載の半導体製造装置を用いた半導体装置の製造方法であって、前記基板としてシリコン系基板を用い、前記基板上に第１の窒化物系化合物半導体で構成される電子走行層を形成し、前記電子走行層上に、前記第１窒化物系化合物半導体と異なる組成式を有する第２の窒化物系化合物半導体で構成される電子供給層を前記エピタキシャル成長層として形成することを特徴とする。   A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to claim 1, wherein a silicon-based substrate is used as the substrate, and the first is formed on the substrate. An electron transit layer composed of a nitride compound semiconductor is formed, and an electron composed of a second nitride compound semiconductor having a composition formula different from that of the first nitride compound semiconductor is formed on the electron transit layer. The supply layer is formed as the epitaxial growth layer.

本発明によれば、エピタキシャル成長層の形成時に基板に生じる温度分布を小さくすることができる半導体製造装置、半導体装置、および、半導体装置の製造方法を提供することができる。   According to the present invention, it is possible to provide a semiconductor manufacturing apparatus, a semiconductor device, and a semiconductor device manufacturing method capable of reducing the temperature distribution generated in the substrate when the epitaxial growth layer is formed.

第１実施形態に係る半導体製造装置の構成を示す模式的な正面図である。It is a typical front view showing the composition of the semiconductor manufacturing device concerning a 1st embodiment. 第１実施形態で、基板上に電子走行層まで形成したことを示す模式的な側面図である。It is a typical side view which shows having formed to the electron transit layer on the board | substrate in 1st Embodiment. 第１実施形態で、基板上に電子供給層まで形成したことを示す模式的な側面図である。It is a typical side view which shows having formed even the electron supply layer on the board | substrate in 1st Embodiment. 第１実施形態で、チャンバから基板を取り出して常温になった状態を示す模式的な側面図である。It is a typical side view which shows the state which took out the board | substrate from the chamber and became normal temperature in 1st Embodiment. 第１実施形態で、基板の電子供給層上に電極を形成したことを示す模式的な側面図である。It is a typical side view which shows having formed the electrode on the electron supply layer of a board | substrate in 1st Embodiment. 第１実施形態で、電子供給層上に電極を形成した後に個々の半導体装置に分割したことを示す模式的な側面図である。It is a typical side view showing having divided into individual semiconductor devices, after forming an electrode on an electron supply layer in a 1st embodiment. 第２実施形態で、トレイを加熱するヒータの構成を示す模式的な側面図である。In 2nd Embodiment, it is a typical side view which shows the structure of the heater which heats a tray.

以下、半導体装置がパワーデバイス用のＨＥＭＴである例を挙げ、添付図面を参照しつつ、本発明の実施の形態について説明する。また、第２実施形態では第１実施形態と同一の構成要素には同じ符号を付してその説明を省略する。また、以下の説明で、基板上に形成する、という表現は、基板上に別の層を介して形成することも含めて表現している。例えば、基板上に電子走行層を形成する、とは、基板にバッファ層を形成しバッファ層の上に電子走行層を形成することも含めて表現している。   Hereinafter, an example in which a semiconductor device is a HEMT for a power device will be described, and an embodiment of the present invention will be described with reference to the accompanying drawings. Moreover, in 2nd Embodiment, the same code | symbol is attached | subjected to the component same as 1st Embodiment, and the description is abbreviate | omitted. Further, in the following description, the expression “formed on the substrate” includes expression formed on the substrate via another layer. For example, the formation of an electron transit layer on a substrate includes the formation of a buffer layer on the substrate and the formation of an electron transit layer on the buffer layer.

[第１実施形態]
まず、第１実施形態について説明する。図１は、本実施形態に係る半導体製造装置の構成を示す模式的な正面図である。図２は、本実施形態で基板上に電子走行層まで形成したことを示す模式的な側面図、図３は、本実施形態で基板上に電子供給層まで形成したことを示す模式的な側面図、図４は、本実施形態でチャンバから基板を取り出して常温になった状態を示す模式的な側面図である。図５は、図４に示した状態で電子供給層上に電極を形成したことを示す模式的な側面図である。図６は、図５に示した状態の後に個々の半導体装置に分割したことを示す模式的な側面図である。 [First embodiment]
First, the first embodiment will be described. FIG. 1 is a schematic front view showing the configuration of the semiconductor manufacturing apparatus according to the present embodiment. FIG. 2 is a schematic side view showing that the electron transit layer is formed on the substrate in this embodiment, and FIG. 3 is a schematic side view showing that the electron supply layer is formed on the substrate in this embodiment. 4 and 4 are schematic side views showing a state where the substrate is taken out of the chamber and brought to room temperature in the present embodiment. FIG. 5 is a schematic side view showing that an electrode is formed on the electron supply layer in the state shown in FIG. FIG. 6 is a schematic side view showing that the semiconductor device is divided into individual semiconductor devices after the state shown in FIG.

（半導体製造装置）
本実施形態に係る半導体製造装置１０は、図１に示すように、チャンバ（炉）１１と、チャンバ１１内に設置されたトレイ１２と、チャンバ１１に接続されたガス供給源１４および排気装置１５と、トレイ１２を下面側から加熱するヒータ２０と、を備えている。 (Semiconductor manufacturing equipment)
As shown in FIG. 1, the semiconductor manufacturing apparatus 10 according to the present embodiment includes a chamber (furnace) 11, a tray 12 installed in the chamber 11, a gas supply source 14 and an exhaust device 15 connected to the chamber 11. And a heater 20 for heating the tray 12 from the lower surface side.

図２、図３に示すように、ヒータ２０は、トレイ１２の中央部１２ｍの下方に位置する第１ヒータ２０ｍと、トレイ１２の周辺部１２ｅの下方に位置する第２ヒータ２０ｅと、で構成されている。そして、電子走行層（第１のエピタキシャル成長層）１２２および電子供給層（第２のエピタキシャル成長層）１２３を形成する際に中央部１２ｍの温度が周辺部１２ｅの温度に比べて高くなるように、第１ヒータ２０ｍおよび第２ヒータ２０ｅのトレイ１２との間隔が調整可能となっている。   As shown in FIGS. 2 and 3, the heater 20 includes a first heater 20 m positioned below the central portion 12 m of the tray 12 and a second heater 20 e positioned below the peripheral portion 12 e of the tray 12. Has been. Then, when forming the electron transit layer (first epitaxial growth layer) 122 and the electron supply layer (second epitaxial growth layer) 123, the temperature of the central portion 12m is set higher than the temperature of the peripheral portion 12e. The distance between the tray 12 of the first heater 20m and the second heater 20e can be adjusted.

本実施形態では、図２、図３に示すように、第２ヒータ２０ｅは、第１ヒータ２０ｍに比べてトレイ１２との間隔ｄｓが広いように配置されている。すなわち、第２ヒータ２０ｅとトレイ１２の周辺部１２ｅの下面との間隔ｄｓは、第１ヒータ２０ｍとトレイ１２の中央部１２ｍの下面との間隔ｄｍに比べて広い。従って、第１ヒータ２０ｍと第２ヒータ２０ｅとで仕様が同じで発熱量も同じであっても、第１ヒータ２０ｍによってトレイ１２の中央部１２ｍに伝えられる単位時間あたりの熱量は、第２ヒータ２０ｅによって周辺部１２ｅに伝えられる単位時間あたりの熱量よりも高い。   In the present embodiment, as shown in FIGS. 2 and 3, the second heater 20e is arranged so that the distance ds from the tray 12 is wider than the first heater 20m. That is, the distance ds between the second heater 20e and the lower surface of the peripheral portion 12e of the tray 12 is wider than the distance dm between the first heater 20m and the lower surface of the central portion 12m of the tray 12. Therefore, even if the first heater 20m and the second heater 20e have the same specifications and the same calorific value, the amount of heat per unit time transmitted to the central portion 12m of the tray 12 by the first heater 20m is the second heater. The amount of heat per unit time transmitted to the peripheral portion 12e by 20e is higher.

そして、第１ヒータ２０ｍおよび第２ヒータ２０ｅの通電によって、トレイ１２を介して基板１１０が加熱されたときの中央部１２ｍおよび周辺部１２ｅの温度がそれぞれ設定温度になるように、間隔ｄｍ、ｄｓを予め調整することが可能である。この設定温度は、バッファ層１２１、電子走行層１２２および電子供給層１２３の形成によって生じる後述の第１中間体１４０や第２中間体１５０に生じる反りが比較的抑えられ（すなわち温度分布が小さくされ）、かつ、第２中間体１５０を常温に戻したときに第２中間体１５０が実質的に平坦になっているように、基板１１０の平面寸法、厚みおよび材質、バッファ層１２１、電子走行層１２２および電子供給層１２３の厚みや組成などを考慮して決定される。   The intervals dm, ds are set so that the temperatures of the central portion 12m and the peripheral portion 12e when the substrate 110 is heated via the tray 12 by the energization of the first heater 20m and the second heater 20e become the set temperatures, respectively. Can be adjusted in advance. In this set temperature, warpage generated in the first intermediate body 140 and the second intermediate body 150 which will be described later due to the formation of the buffer layer 121, the electron transit layer 122, and the electron supply layer 123 is relatively suppressed (that is, the temperature distribution is reduced). And the planar dimensions, thickness and material of the substrate 110, the buffer layer 121, and the electron transit layer so that the second intermediate 150 is substantially flat when the second intermediate 150 is returned to room temperature. 122 and the thickness and composition of the electron supply layer 123 are determined.

（半導体装置）
半導体製造装置１０を用いて製造された半導体装置１３６は、図６に示すように、シリコン系基板からなる基板１１０と、基板１１０上に順次形成されたバッファ層１２１、電子走行層１２２（第１のエピタキシャル成長層、チャネル層）および電子供給層１２３（第２のエピタキシャル成長層、バリア層）と、電子供給層１２３上に形成されたソース電極１３１、ゲート電極１３２およびドレイン電極１３３と、を有する。 (Semiconductor device)
As shown in FIG. 6, a semiconductor device 136 manufactured using the semiconductor manufacturing apparatus 10 includes a substrate 110 made of a silicon-based substrate, a buffer layer 121 formed on the substrate 110 in sequence, and an electron transit layer 122 (first And an electron supply layer 123 (second epitaxial growth layer, barrier layer), and a source electrode 131, a gate electrode 132, and a drain electrode 133 formed on the electron supply layer 123.

バッファ層１２１は、例えばＡｌＮとＧａＮが交互に積層されて構成される。電子走行層１２２は、第１の窒化物系化合物半導体（ＧａＮ）で構成される。そして、電子供給層１２３は、第１の窒化物系化合物半導体と異なる組成式を有する第２の窒化物系化合物半導体（ＡｌＧａＮ）で構成されている。   The buffer layer 121 is configured by alternately laminating AlN and GaN, for example. The electron transit layer 122 is composed of a first nitride compound semiconductor (GaN). The electron supply layer 123 is composed of a second nitride compound semiconductor (AlGaN) having a composition formula different from that of the first nitride compound semiconductor.

（半導体装置の製造方法）
半導体装置１３６を製造するには、本実施形態ではＭＯＣＶＤ法で以下のようにして製造する。 (Method for manufacturing semiconductor device)
In the present embodiment, the semiconductor device 136 is manufactured by the MOCVD method as follows.

まず、シリコンまたはＳｉＣ等のシリコン系基板を基板１１０としてトレイ１２上に載置し、チャンバ１１内を真空吸引して所定の真空度に到達させる。また、第１ヒータ２０ｍおよび第２ヒータ２０ｅの通電によって、トレイ１２の中央部１２ｍと周辺部１２ｅとがそれぞれ設定温度に到達して中央部１２ｍと周辺部１２ｅとの温度差が所定温度差となることによって、電子供給層１２３を形成するときの基板中央部１１０ｍと基板周辺部１１０ｅの温度が実質的に均一な温度になるように、間隔ｄｍ、ｄｓを予め調整しておく。   First, a silicon-based substrate such as silicon or SiC is placed on the tray 12 as the substrate 110, and the inside of the chamber 11 is vacuumed to reach a predetermined degree of vacuum. Further, when the first heater 20m and the second heater 20e are energized, the central portion 12m and the peripheral portion 12e of the tray 12 reach the set temperature, respectively, and the temperature difference between the central portion 12m and the peripheral portion 12e becomes a predetermined temperature difference. Thus, the distances dm and ds are adjusted in advance so that the temperatures of the substrate central portion 110m and the substrate peripheral portion 110e when the electron supply layer 123 is formed are substantially uniform.

そして、第１ヒータ２０ｍ、第２ヒータ２０ｅに通電させ、トレイ１２を介して基板１１０を加熱する。第１ヒータ２０ｍおよび第２ヒータ２０ｅによってトレイ１２の中央部１２ｍおよび周辺部１２ｅが上記の設定温度に到達した後、図２に示すように、基板１１０上にバッファ層１２１、電子走行層（第１のエピタキシャル成長層）１２２を順次形成してなる、製造途中段階の第１中間体１４０が形成される。バッファ層１２１および電子走行層１２２は基板１１１に比べて小さい格子定数を有し、かつ基板１１１に比べて大きい線膨張係数を有する。従って、第１中間体１４０は中央部がやや浮き上がった形状となる。   Then, the first heater 20m and the second heater 20e are energized to heat the substrate 110 through the tray 12. After the central portion 12m and the peripheral portion 12e of the tray 12 reach the above set temperature by the first heater 20m and the second heater 20e, as shown in FIG. 2, the buffer layer 121 and the electron transit layer (first layer) are formed on the substrate 110. 1 epitaxial growth layer) 122 is sequentially formed, and a first intermediate 140 in the middle of manufacturing is formed. The buffer layer 121 and the electron transit layer 122 have a lattice constant smaller than that of the substrate 111 and have a larger linear expansion coefficient than that of the substrate 111. Accordingly, the first intermediate body 140 has a shape in which the central portion is slightly raised.

ここで、本実施形態では、ヒータ２０（第１ヒータ２０ｍおよび第２ヒータ２０ｅ）の加熱によって、第１中間体中央部１４０ｍが第１ヒータ２０ｍから単位時間あたりに受ける熱量は、第１中間体周辺部１４０ｅが第２ヒータ２０ｅから単位時間あたりに受ける熱量よりも高くされた状態で成膜している。従って、この成膜後（バッファ層１２１および電子走行層１２２の成膜後）の第１中間体中央部１４０ｍと第１中間体周辺部１４０ｅとの温度差、すなわち第１中間体１４０に生じる温度分布は、トレイ底での単位時間あたりに受ける熱量がトレイ底面で均一とされた従来に比べて小さいので、第１中間体１４０の反りは従来に比べて小さい。   Here, in the present embodiment, the amount of heat that the first intermediate body 140m receives from the first heater 20m per unit time due to the heating of the heater 20 (the first heater 20m and the second heater 20e) is the first intermediate body. The film is formed in a state where the peripheral portion 140e is higher than the amount of heat received per unit time from the second heater 20e. Therefore, the temperature difference between the first intermediate central portion 140m and the first intermediate peripheral portion 140e after the film formation (after the buffer layer 121 and the electron transit layer 122 are formed), that is, the temperature generated in the first intermediate 140. Since the amount of heat received per unit time at the bottom of the tray is smaller than that of the conventional case where the distribution is uniform on the bottom surface of the tray, the warp of the first intermediate 140 is smaller than that of the conventional case.

電子走行層１２２の形成後、図３に示すように、電子供給層（第２のエピタキシャル成長層）１２３をＭＯＣＶＤ法で成膜して第２中間体１５０を形成する。なお、電子供給層１２３の膜厚はバッファ層１２１や電子走行層１２２に比べて薄いので、反り具合は図２に示した状態（電子走行層１２２を形成した直後）と同程度である。   After the formation of the electron transit layer 122, as shown in FIG. 3, an electron supply layer (second epitaxial growth layer) 123 is formed by the MOCVD method to form the second intermediate 150. In addition, since the film thickness of the electron supply layer 123 is thinner than the buffer layer 121 and the electron transit layer 122, the degree of warping is almost the same as that shown in FIG. 2 (immediately after the electron transit layer 122 is formed).

その後、チャンバ１１から第２中間体１５０を取り出し、室温にまで自然冷却させる（図４参照）。ここで、トレイ１２の中央部１２ｍおよび周辺部１２ｅが上記の設定温度に到達するように第１ヒータ２０ｍおよび第２ヒータ２０ｅの位置が調整されていることにより、第２中間体１５０は室温状態では平坦となる。   Then, the 2nd intermediate body 150 is taken out from the chamber 11, and is naturally cooled to room temperature (refer FIG. 4). Here, the positions of the first heater 20m and the second heater 20e are adjusted so that the central portion 12m and the peripheral portion 12e of the tray 12 reach the set temperature, so that the second intermediate 150 is in a room temperature state. Then it becomes flat.

その後、図５に示すように、第２中間体１５０上にソース電極１３１、ゲート電極１３２およびドレイン電極１３３などを形成し、更に複数に分割することで、複数の個別の半導体装置１３６を得る（図６参照）。   After that, as shown in FIG. 5, a source electrode 131, a gate electrode 132, a drain electrode 133, and the like are formed on the second intermediate 150 and further divided into a plurality of parts to obtain a plurality of individual semiconductor devices 136 ( (See FIG. 6).

以上説明したように、本実施形態によれば、第１ヒータ２０ｍおよび第２ヒータ２０ｅの加熱によって、第１中間体周辺部１４０ｅと第１中間体中央部１４０ｍとがそれぞれ設定温度（第１中間体周辺部１４０ｅが第１中間体中央部１４０ｍよりも低い温度）にされた状態で成膜を開始している。従って、電子走行層（第１のエピタキシャル成長層）１２２の成膜後での第１中間体中央部１４０ｍと第１中間体周辺部１４０ｅとの温度差、すなわち第１中間体１４０に生じる温度分布は、従来に比べて小さい。   As described above, according to this embodiment, the first intermediate body peripheral portion 140e and the first intermediate body central portion 140m are set to the set temperatures (first intermediate temperature) by the heating of the first heater 20m and the second heater 20e. The film formation is started in a state in which the body peripheral portion 140e is set to a temperature lower than that of the first intermediate central portion 140m. Therefore, the temperature difference between the first intermediate central portion 140m and the first intermediate peripheral portion 140e after the formation of the electron transit layer (first epitaxial growth layer) 122, that is, the temperature distribution generated in the first intermediate 140 is as follows. Small compared to the conventional.

よって、第２中間体１５０が常温に戻ったときにおける電子供給層１２３（第２のエピタキシャル成長層）の面内均一性を大幅に改善することができる。従って、電子供給層１２３（第２のエピタキシャル成長層）の組成（混晶比）、膜厚、結晶性などのばらつきを低減することができ、デバイスの順方向特性、しきい値などが揃った半導体装置１３６（エピタキシャルウエハ）が得られ、半導体装置１３６の製造における歩留まりを大幅に向上させることができる。なお、電子走行層１２２の形成直後で第１中間体１４０の温度が均一になるように上記設定温度を調整してこの歩留まりを極めて高くすることも可能である。   Therefore, the in-plane uniformity of the electron supply layer 123 (second epitaxial growth layer) when the second intermediate 150 returns to room temperature can be greatly improved. Therefore, variations in the composition (mixed crystal ratio), film thickness, crystallinity, and the like of the electron supply layer 123 (second epitaxial growth layer) can be reduced, and the semiconductor has a uniform forward characteristic, threshold value, and the like. A device 136 (epitaxial wafer) is obtained, and the yield in manufacturing the semiconductor device 136 can be significantly improved. Note that it is possible to increase the yield by adjusting the set temperature so that the temperature of the first intermediate 140 becomes uniform immediately after the formation of the electron transit layer 122.

また、トレイ１２に対する第１ヒータ２０ｍおよび第２ヒータ２０ｅの位置（間隔）を、予め調整しておくことで上記効果を得ることが可能である。従って、半導体装置１３６の製造途中で第１ヒータ２０ｍおよび第２ヒータ２０ｅの出力（発熱量）を変更できない半導体製造装置１０であっても、半導体製造装置１０の基板配置位置での観察（in-situ観察）を行って予め電子供給層１２３の反りおよび温度分布を把握しておき、それに合わせてトレイ１２の温度分布が設定分布となるように第１ヒータ２０ｍおよび第２ヒータ２０ｅの位置設定（トレイ１２との間隔の設定）を行うことで、上記効果を奏することができる。   Further, the above-described effects can be obtained by adjusting the positions (intervals) of the first heater 20m and the second heater 20e with respect to the tray 12 in advance. Therefore, even in the semiconductor manufacturing apparatus 10 in which the outputs (heat generation amounts) of the first heater 20m and the second heater 20e cannot be changed during the manufacturing of the semiconductor device 136, the observation (in− The position of the first heater 20m and the second heater 20e is set so that the temperature distribution of the tray 12 becomes the set distribution in accordance with the warp and temperature distribution of the electron supply layer 123 by performing in situ observation). The above effect can be obtained by setting the interval with the tray 12.

なお、本実施形態では、半導体装置１３６の製造途中で第１ヒータ２０ｍおよび第２ヒータ２０ｅの出力や位置を変更できない半導体製造装置１０の例で説明したが、変更できる例（いわゆる独立ゾーン制御が可能な例）の半導体製造装置であってもよい。これにより、各層の成長時の反り形状に対応させて温度分布を適宜変更することで、反りの影響を抑えて各層を成長させることができ、半導体装置１３６の製造における歩留まりを更に向上させることができる。   In the present embodiment, the example of the semiconductor manufacturing apparatus 10 in which the outputs and positions of the first heater 20m and the second heater 20e cannot be changed during the manufacturing of the semiconductor device 136 has been described. The semiconductor manufacturing apparatus of a possible example) may be used. Accordingly, by appropriately changing the temperature distribution in accordance with the warp shape during the growth of each layer, each layer can be grown while suppressing the influence of the warp, and the yield in manufacturing the semiconductor device 136 can be further improved. it can.

また、本実施形態では、第１ヒータ２０ｍおよび第２ヒータ２０ｅの両者の発熱量が調整可能である例で説明したが、どちらか一方が調整可能であっても、トレイ１２の中央部１２ｍの温度を周辺部１２ｅの温度に比べて高くすることが可能である。   Further, in the present embodiment, the example in which the heat generation amounts of both the first heater 20m and the second heater 20e can be adjusted has been described, but even if one of them is adjustable, the central portion 12m of the tray 12 can be adjusted. The temperature can be made higher than the temperature of the peripheral portion 12e.

また、本実施形態では、第１ヒータ２０ｍからトレイ１２の中央部１２ｍに与える単位時間あたりの熱量が、第２ヒータ２０ｅからトレイ１２の周辺部１２ｅに与える単位時間あたりの熱量よりも高い例で説明したが、電子供給層１２３の成膜時に基板１１０の反りを従来よりも抑えることができるように第１ヒータ２０ｍおよび第２ヒータ２０ｅからトレイ１２に熱量を与えることができれば良く、本発明は単位時間あたりの熱量の高低に限定するものではない。   In the present embodiment, the amount of heat per unit time given from the first heater 20m to the central portion 12m of the tray 12 is higher than the amount of heat per unit time given from the second heater 20e to the peripheral portion 12e of the tray 12. As described above, it is sufficient that the amount of heat can be applied to the tray 12 from the first heater 20m and the second heater 20e so that the warpage of the substrate 110 can be suppressed more than before when the electron supply layer 123 is formed. It is not limited to the amount of heat per unit time.

［第２実施形態］
次に、第２実施形態について説明する。図７は、本実施形態で、トレイを加熱するヒータの構成を示す模式的な側面図である。本実施形態では、第１実施形態に比べ、ヒータ２２０の構成が異なる。本実施形態では、ヒータ２２０は、トレイ１２の中央部１２ｍの下方に位置する第１ヒータ２２０ｍと、トレイ１２の周辺部１２ｅの下方に位置する第２ヒータ２２０ｅと、で構成されている。 [Second Embodiment]
Next, a second embodiment will be described. FIG. 7 is a schematic side view showing a configuration of a heater for heating the tray in the present embodiment. In the present embodiment, the configuration of the heater 220 is different from that in the first embodiment. In the present embodiment, the heater 220 includes a first heater 220m located below the central portion 12m of the tray 12 and a second heater 220e located below the peripheral portion 12e of the tray 12.

第１ヒータ２２０ｍおよび第２ヒータ２２０ｅは、通電量が互いに異なるように設定することが可能である。本実施形態では、第１ヒータ２２０ｍおよび第２ヒータ２２０ｅの通電によって、トレイ１２を介して基板１１０が加熱されたときの中央部１２ｍおよび周辺部１２ｅの温度が設定温度になるように、通電量を予め設定しておく。   The first heater 220m and the second heater 220e can be set to have different energization amounts. In the present embodiment, the energization amount is such that the temperature of the central portion 12m and the peripheral portion 12e when the substrate 110 is heated via the tray 12 becomes the set temperature by energization of the first heater 220m and the second heater 220e. Is set in advance.

本実施形態により、第１ヒータ２２０ｍとトレイ１２の中央部１２ｍとの間隔ｄｍ、および、第２ヒータ２２０ｅとトレイ１２の周辺部１２ｅとの間隔ｄｓを同一にしても、第１実施形態と同様の効果を奏することができる。   According to this embodiment, even if the distance dm between the first heater 220m and the central portion 12m of the tray 12 and the distance ds between the second heater 220e and the peripheral portion 12e of the tray 12 are the same, the same as in the first embodiment. The effect of can be produced.

また、第１実施形態と同様、半導体装置の製造途中で第１ヒータ２２０ｍおよび第２ヒータ２２０ｅの出力や位置を変更できる場合には、各層の成長時の反り形状に対応させて温度分布を適宜変更することで、反りの影響を抑えて各層を成長させることができ、半導体装置の製造における歩留まりを更に向上させることができる。   Similarly to the first embodiment, when the output and position of the first heater 220m and the second heater 220e can be changed during the manufacturing of the semiconductor device, the temperature distribution is appropriately set corresponding to the warp shape during the growth of each layer. By changing, each layer can be grown while suppressing the influence of warpage, and the yield in manufacturing the semiconductor device can be further improved.

以上、本発明の実施の形態を説明したが、上記実施形態は、本発明の技術的思想を具体化するための例示であって、構成部品の材質、形状、構造、配置等を上記のものに特定するものではない。本発明は、要旨を逸脱しない範囲内で種々変更して実施できる。また、図面は模式的なものであり、寸法比などは現実のものとは異なることに留意すべきである。従って、具体的な寸法比などは以下の説明を参酌して判断すべきものである。又、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。   The embodiment of the present invention has been described above, but the above embodiment is an example for embodying the technical idea of the present invention, and the material, shape, structure, arrangement, etc. of the component parts are as described above. It is not something specific. The present invention can be implemented with various modifications without departing from the scope of the invention. In addition, it should be noted that the drawings are schematic and the dimensional ratios and the like are different from actual ones. Therefore, specific dimensional ratios and the like should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

以上のように、本発明に係る半導体製造装置、半導体装置、および、半導体装置の製造方法では、トレイ上に配置された基板にエピタキシャル成長層を形成する際に、トレイの上面と基板の下面との間隔が広い部分では、トレイの上面と基板の下面との間隔が狭い部分に比べ、ヒータからトレイに与えられる熱量を高くすることが可能なので、エピタキシャル成長層の形成時に基板に生じる温度分布を小さくすることができる半導体製造装置、半導体装置、および、半導体装置の製造方法として用いるのに好適である。   As described above, in the semiconductor manufacturing apparatus, the semiconductor device, and the manufacturing method of the semiconductor device according to the present invention, when the epitaxial growth layer is formed on the substrate disposed on the tray, the upper surface of the tray and the lower surface of the substrate are Compared with the part where the distance between the upper surface of the tray and the lower surface of the substrate is narrow, the amount of heat applied from the heater to the tray can be increased in the part where the distance is wide, so the temperature distribution generated in the substrate during the formation of the epitaxial growth layer is reduced. It is suitable for use as a semiconductor manufacturing apparatus, a semiconductor device, and a method for manufacturing a semiconductor device.

１０ 半導体製造装置
１１ チャンバ
１２ トレイ
１２ｅ 周辺部
１２ｍ 中央部
２０ ヒータ
２０ｅ 第２ヒータ
２０ｍ 第１ヒータ
１１０ 基板（基板、シリコン系基板）
１２２ 電子走行層（エピタキシャル成長層、第１のエピタキシャル成長層）
１２３ 電子供給層（エピタキシャル成長層、第２のエピタキシャル成長層）
１３６ 半導体装置
ｄｓ 間隔
ｄｍ 間隔 DESCRIPTION OF SYMBOLS 10 Semiconductor manufacturing apparatus 11 Chamber 12 Tray 12e Peripheral part 12m Center part 20 Heater 20e 2nd heater 20m 1st heater 110 Substrate (substrate, silicon system substrate)
122 Electron transit layer (epitaxial growth layer, first epitaxial growth layer)
123 Electron supply layer (epitaxial growth layer, second epitaxial growth layer)
136 Semiconductor device ds interval dm interval

Claims (5)

チャンバ内に設置されたトレイと、前記トレイを下面側から加熱するヒータと、を備え、前記トレイ上に配置された基板を前記ヒータで前記トレイを介して加熱して、前記基板上に窒化物系化合物半導体で構成されるエピタキシャル成長層を形成する半導体製造装置であって、
前記エピタキシャル成長層を形成する際に、前記基板の下面と前記トレイの上面との間隔が広い部分では、前記基板の下面と前記トレイの上面との間隔が狭い部分に比べ、前記ヒータから前記トレイに与えられる熱量を高くすることが可能な構成にされていることを特徴とする半導体製造装置。 A tray installed in the chamber; and a heater for heating the tray from the lower surface side. The substrate disposed on the tray is heated via the tray by the heater, and nitride is formed on the substrate. A semiconductor manufacturing apparatus for forming an epitaxial growth layer composed of a compound semiconductor,
When the epitaxial growth layer is formed, the portion from which the lower surface of the substrate and the upper surface of the tray have a large distance from the heater to the tray compared to the portion where the distance between the lower surface of the substrate and the upper surface of the tray is narrow. A semiconductor manufacturing apparatus characterized in that the amount of heat applied can be increased. 前記ヒータは、前記トレイの中央部の下方に位置する第１ヒータと、前記トレイの周辺部の下方に位置する第２ヒータと、で構成され、
前記エピタキシャル成長層として電子供給層を形成する際に前記中央部の温度が前記周辺部に比べて高くなるように、前記第１ヒータおよび前記第２ヒータの少なくとも一方から前記トレイに与える熱量が調整可能であることを特徴とする請求項１に記載の半導体製造装置。 The heater is composed of a first heater located below the central portion of the tray, and a second heater located below the peripheral portion of the tray,
The amount of heat applied to the tray from at least one of the first heater and the second heater can be adjusted so that the temperature of the central portion is higher than that of the peripheral portion when the electron supply layer is formed as the epitaxial growth layer. The semiconductor manufacturing apparatus according to claim 1, wherein: 前記基板としてシリコン系基板を前記トレイに配置し、前記基板上に第１の窒化物系化合物半導体で構成される電子走行層を第１の前記エピタキシャル成長層として形成し、前記第１の窒化物系化合物半導体と異なる組成式を有する第２の窒化物系化合物半導体で構成される電子供給層を第２の前記エピタキシャル成長層として前記電子走行層上に形成するに際し、
前記周辺部の温度が前記中央部の温度に比べて高くなるように、前記第１ヒータおよび前記第２ヒータの少なくとも一方から前記トレイに与える熱量が調整可能とされていることを特徴とする請求項２に記載の半導体製造装置。 A silicon-based substrate is disposed on the tray as the substrate, an electron transit layer composed of a first nitride-based compound semiconductor is formed on the substrate as the first epitaxial growth layer, and the first nitride-based layer is formed. In forming an electron supply layer composed of a second nitride-based compound semiconductor having a composition formula different from that of the compound semiconductor on the electron transit layer as the second epitaxial growth layer,
The amount of heat applied to the tray from at least one of the first heater and the second heater can be adjusted so that the temperature of the peripheral portion is higher than the temperature of the central portion. Item 3. The semiconductor manufacturing apparatus according to Item 2. 請求項１に記載の半導体製造装置を用いて製造された半導体装置であって、
前記基板はシリコン系基板であり、
前記基板上に第１の窒化物系化合物半導体で構成される電子走行層の上に形成されていて、前記第１の窒化物系化合物半導体と異なる組成式を有する第２の窒化物系化合物半導体で構成される電子供給層を前記エピタキシャル成長層として備えることを特徴とする半導体装置。 A semiconductor device manufactured using the semiconductor manufacturing apparatus according to claim 1,
The substrate is a silicon-based substrate;
A second nitride compound semiconductor formed on the substrate on an electron transit layer composed of a first nitride compound semiconductor and having a composition formula different from that of the first nitride compound semiconductor A semiconductor device comprising: an electron supply layer comprising: 請求項１に記載の半導体製造装置を用いた半導体装置の製造方法であって、
前記基板としてシリコン系基板を用い、
前記基板上に第１の窒化物系化合物半導体で構成される電子走行層を形成し、
前記電子走行層上に、前記第１窒化物系化合物半導体と異なる組成式を有する第２の窒化物系化合物半導体で構成される電子供給層を前記エピタキシャル成長層として形成することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to claim 1,
Using a silicon-based substrate as the substrate,
Forming an electron transit layer composed of a first nitride-based compound semiconductor on the substrate;
A semiconductor device characterized in that an electron supply layer made of a second nitride compound semiconductor having a composition formula different from that of the first nitride compound semiconductor is formed on the electron transit layer as the epitaxial growth layer. Manufacturing method.
JP2012254384A 2012-11-20 2012-11-20 Semiconductor manufacturing apparatus, semiconductor device and semiconductor device manufacturing method Pending JP2016015353A (en)

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