JP6138974B2 - Semiconductor substrate - Google Patents

Description

  The present invention relates to a semiconductor substrate.

  Nitride semiconductors such as GaN and AlGaN are power switching devices that operate at high temperatures, taking advantage of high breakdown voltage, high saturation drift velocity, chemical and thermal stability, and large band gap. The device is expected to be used for a device capable of light emission, a blue or green light emitting device, and the like. However, a single crystal GaN substrate or a single crystal AlN substrate used as a nitride semiconductor base substrate is expensive, and it is expected that the price will be higher if an attempt is made to increase the substrate diameter. Therefore, there is a need for a technique for forming a nitride semiconductor using a Si substrate that can be expected to be inexpensive. Since the crystal structure of a nitride semiconductor such as GaN or AlGaN is a wurtzite type belonging to the hexagonal system, when the nitride semiconductor is epitaxially grown on the Si substrate, the Si (111) plane is selected as the crystal growth plane.

  Patent Document 1 discloses a semiconductor electronic device having a high breakdown voltage and a small warpage. The semiconductor electronic device includes a substrate, a buffer layer formed on the substrate, an intervening layer formed between the substrate and the buffer layer, and a nitride compound semiconductor formed on the buffer layer. And a layer. The buffer layer includes a first semiconductor layer made of a nitride compound semiconductor having a smaller lattice constant and a larger thermal expansion coefficient than the substrate, and a nitride system having a smaller lattice constant than the first semiconductor layer and a larger thermal expansion coefficient than the substrate. A nitride compound having two or more composite layers alternately laminated with a second semiconductor layer made of a compound semiconductor, and the intervening layer has a lattice constant smaller than that of the first semiconductor layer and a thermal expansion coefficient larger than that of the substrate Made of semiconductor. The buffer layer is formed such that the thickness of each first semiconductor layer or each second semiconductor layer decreases in the stacking direction.

  Non-Patent Document 1 discloses that an AlGaN / GaN multilayer structure is used when epitaxially growing a GaN crystal having a Si (111) plane, and there is a description that the multilayer structure relieves tensile strain.

JP 2009-188252 A

Seong-Hwan Jang et al., `` High-quality GaN / Si (111) epitaxial layers grown with various AlGaN / GaN superlattices as intermediate layer by MOCVD '', Journal of Crystal Growth, Vol.253, pp. 64-70, 2003

When epitaxially growing a nitride semiconductor such as GaN or AlGaN on the Si (111) surface, the difference in lattice constant (lattice mismatch) between the lattice constant of Si and the epitaxial growth layer GaN or AlGaN is large. The problem is that the difference between the thermal expansion coefficient and the thermal expansion coefficient of GaN or AlGaN is large. That is, the thermal expansion coefficient of Si is 2.6 × 10 ⁻⁶ / ° C., whereas the thermal expansion coefficient of GaN is as large as 5.6 × 10 ⁻⁶ / ° C. As a result, when the GaN crystal is epitaxially grown on the Si substrate and then the Si substrate and the GaN crystal are cooled, the GaN crystal contracts more than the Si substrate, and the substrate may be warped or the GaN crystal may be cracked. .

  In order to solve the above problems, in a first aspect of the present invention, a base substrate, a first crystal layer, a second crystal layer, and a functional layer are provided, and the base substrate and the first crystal layer are provided. The second crystal layer and the functional layer are arranged in the order of the base substrate, the first crystal layer, the second crystal layer, and the functional layer, and the first crystal layer and the second crystal layer are latticed. The thermal expansion coefficient of the functional layer is larger than the thermal expansion coefficient of the base substrate, the lattice constant of the first crystal layer is smaller than the lattice constant of the second crystal layer, When a cross-sectional TEM image is observed including the first interface where the first crystal layer and the second crystal layer are in contact with each other and the second interface of the second crystal layer located on the functional layer side in the same field of view, The area of the first moire image observed including the first interface is the first moire image. Providing smaller semiconductor substrate than the area of the second moiré image observed contain a surface.

The base substrate is made of silicon, the first crystal layer is made of Al _x Ga _1-x N, the second crystal layer is made of Al _y Ga _1-y N, and x and y are 0 ≦ y <x ≦ It is preferable to have a relationship of 1. It is preferable that the second crystal layer is a crystal grown under the condition that the surface roughness of the second crystal layer is larger than the surface roughness when the first crystal layer is crystal-grown. The first stress due to the difference between the thermal expansion coefficient of the base substrate and the thermal expansion coefficient of the functional layer may be generated in the functional layer due to a decrease in temperature. In the second crystal layer, a second stress resulting from a difference between a lattice constant of the first crystal layer and a lattice constant of the second crystal layer may be generated in a direction opposite to the direction of the first stress. .

  The base substrate, the first crystal layer, the second crystal layer, and the functional layer, the third crystal layer, and the fourth crystal layer may further include a third crystal layer and a fourth crystal layer. Are arranged in the order of the base substrate, the first crystal layer, the second crystal layer, the third crystal layer, the fourth crystal layer, and the functional layer, and the second crystal layer and the third crystal layer Are formed in contact with each other, and the third crystal layer and the fourth crystal layer are in contact with each other in lattice matching or pseudo-lattice matching, and the lattice constant of the third crystal layer is greater than the lattice constant of the fourth crystal layer. A cross-sectional TEM image including the second interface where the second crystal layer and the third crystal layer are in contact with each other and the third interface where the third crystal layer and the fourth crystal layer are in contact with each other in the same field of view. Area of the third moiré image observed including the third interface It may be less than the area of the second moiré image. In the fourth crystal layer, a third stress resulting from a difference between a lattice constant of the third crystal layer and a lattice constant of the fourth crystal layer may be generated in a direction opposite to the direction of the first stress. .

  In the second aspect of the present invention, the step of epitaxially growing the first crystal layer on the base substrate and the step of epitaxially growing the second crystal layer in contact with the first crystal layer and lattice-matching or pseudo-lattice-matching And a step of epitaxially growing a functional layer on the second crystal layer, wherein the thermal expansion coefficient of the functional layer is larger than the thermal expansion coefficient of the base substrate. The lattice constant of the first crystal layer is smaller than the lattice constant of the second crystal layer, and the first interface where the first crystal layer and the second crystal layer are in contact with each other and the first layer located on the functional layer side When a cross-sectional TEM image is observed including the second interface of the two crystal layers in the same field of view, the area of the first moire image observed including the first interface is observed including the second interface. Ru Providing smaller semiconductor substrate than the area of the 2 moire images. That is, in the first aspect, each of the first crystal layer, the second crystal layer, and the functional layer may be formed by an epitaxial growth method.

  In a third aspect of the present invention, a base substrate, a first crystal layer, a second crystal layer, and a functional layer, the base substrate, the first crystal layer, the second crystal layer, and the The functional layer is arranged in the order of the base substrate, the first crystal layer, the second crystal layer, and the functional layer, and the first crystal layer and the second crystal layer are in contact with each other in lattice matching or pseudo-lattice matching. The thermal expansion coefficient of the functional layer is smaller than the thermal expansion coefficient of the base substrate, and the lattice constant of the first crystal layer is larger than the lattice constant of the second crystal layer, and the first crystal layer and the second crystal When a cross-sectional TEM image is observed including the first interface where the layers are in contact with each other and the second interface of the second crystal layer located on the functional layer side in the same field of view, it is observed including the first interface. A second area in which the area of the first moire image is observed including the second interface; Providing smaller semiconductor substrate than the area of the array images.

  The base substrate, the first crystal layer, the second crystal layer, and the functional layer, the third crystal layer, and the fourth crystal layer may further include a third crystal layer and a fourth crystal layer. Are arranged in the order of the base substrate, the first crystal layer, the second crystal layer, the third crystal layer, the fourth crystal layer, and the functional layer, and the second crystal layer and the third crystal layer Are formed in contact with each other, and the third crystal layer and the fourth crystal layer are in contact with each other in lattice matching or pseudo-lattice matching, and the lattice constant of the third crystal layer is greater than the lattice constant of the fourth crystal layer. A cross-sectional TEM image including the second interface where the second crystal layer and the third crystal layer are in contact with each other and the third interface where the third crystal layer and the fourth crystal layer are in contact with each other in the same field of view. Area of the third moiré image observed including the third interface It may be less than the area of the second moiré image.

  In the fourth aspect of the present invention, the step of epitaxially growing the first crystal layer on the base substrate and the step of epitaxially growing the second crystal layer in contact with the first crystal layer and lattice-matching or pseudo-lattice matching And a step of epitaxially growing a functional layer on the second crystal layer, wherein the thermal expansion coefficient of the functional layer is smaller than the thermal expansion coefficient of the base substrate. The lattice constant of the first crystal layer is larger than the lattice constant of the second crystal layer, and the first interface where the first crystal layer and the second crystal layer are in contact with each other and the first layer located on the functional layer side When a cross-sectional TEM image is observed including the second interface of the two crystal layers in the same field of view, the area of the first moire image observed including the first interface is observed including the second interface. Ru Providing smaller semiconductor substrate than the area of the 2 moire images. That is, in the third aspect, each of the first crystal layer, the second crystal layer, and the functional layer may be formed by an epitaxial growth method.

  In this specification, the lattice constant of the first crystal layer refers to the lattice constant at 20 ° C. of the first crystal layer obtained by growing only the first crystal layer on the substrate in lattice matching. . The same applies to the lattice constants of the second crystal layer, the third crystal layer, the fourth crystal layer, and the functional layer. In this specification, the thermal expansion coefficient of the functional layer refers to the thermal expansion coefficient of the functional layer at 20 ° C. The same applies to the thermal expansion coefficients of the first crystal layer, the second crystal layer, the third crystal layer, and the fourth crystal layer. In this specification, “pseudo-lattice matching” is not perfect lattice matching, but is in contact with each other within a range where the difference in lattice constant between two semiconductors in contact with each other is small and defects due to lattice mismatch are not significant. A state in which two semiconductors can be stacked. At this time, the crystal lattice difference of each semiconductor is deformed within a range that can be elastically deformed, so that the difference in the lattice constant is absorbed. For example, the stacked state of Ge and GaAs is called pseudo lattice matching.

An example of a cross section of a semiconductor substrate 100 is shown. An example of a cross section of a semiconductor substrate 200 is shown. 2 shows a cross-sectional TEM photograph of the semiconductor substrate of Example 1. The cross-sectional TEM photograph which observed the semiconductor substrate of Example 1 inclining 5 degree | times is shown. (A)-(c) shows the curvature of the board | substrate at the time of making it grow epitaxially by changing growth temperature.

  Hereinafter, the present invention will be described through embodiments of the invention. FIG. 1 shows an example of a cross section of a semiconductor substrate 100. The semiconductor substrate 100 includes a base substrate 102, a first crystal layer 104, a second crystal layer 106, and a functional layer 108.

  The base substrate 102 is a support substrate that supports an epitaxial growth layer formed thereon. Examples of the base substrate 102 include a Si substrate. Examples of the Si substrate include a silicon wafer whose bulk as a whole is made of Si and an SOI (Silicon on Insulator) substrate whose surface is Si. The surface of the base substrate 102 is a flat surface without warping when a crystal layer is not formed on the surface.

The first crystal layer 104 and the second crystal layer 106 are nitride semiconductor crystals formed on the base substrate 102. The first crystal layer 104 and the second crystal layer 106 may be formed by epitaxial growth. Examples of the first crystal layer 104 include AlN and AlGaN. Examples of the second crystal layer 106 include AlGaN or GaN. The first crystal layer 104 and the second crystal layer 106 function as a stress control layer. Preferably, the first crystal layer 104 is made of Al _x Ga _1-x N, the second crystal layer 106 is made of Al _y Ga _1-y N, and x and y have a relationship of 0 ≦ y <x ≦ 1. .

  An example of the functional layer 108 is a nitride semiconductor crystal formed on the base substrate 102. The functional layer 108 is formed on the base substrate 102 with the first crystal layer 104 and the second crystal layer 106 interposed therebetween. The material of the functional layer 108 is arbitrary. The functional layer 108 may be formed by epitaxial growth. Examples of the functional layer 108 include AlGaN or GaN. A semiconductor device can be formed using the functional layer 108 as an active layer.

  The base substrate 102, the first crystal layer 104, the second crystal layer 106, and the functional layer 108 are arranged in the order of the base substrate 102, the first crystal layer 104, the second crystal layer 106, and the functional layer 108. An arbitrary layer may be interposed between the base substrate 102 and the first crystal layer 104. Further, an arbitrary layer may be interposed between the second crystal layer 106 and the functional layer 108. The first crystal layer 104 and the second crystal layer 106 are in contact with each other by lattice matching or pseudo-lattice matching. A first interface 110 is formed at the interface where the first crystal layer 104 and the second crystal layer 106 are in contact with each other, and a second interface 112 is formed at the interface of the second crystal layer 106 located on the functional layer 108 side. .

  The thermal expansion coefficient of the functional layer 108 is larger than the thermal expansion coefficient of the base substrate 102. When the functional layer 108 is epitaxially grown by MOCVD, it is generally grown at a temperature of about 700 ° C. or higher. When the temperature of the semiconductor substrate 100 is lowered after the functional layer 108 is grown, the thermal contraction of the functional layer 108 becomes larger than the thermal contraction of the base substrate 102, and the first stress 114, which is a tensile stress, is applied to the functional layer 108. Occur. As a result, the first warp occurs in the semiconductor substrate 100. Since the first stress 114 is a tensile stress, the first warp has a shape bulging downward from the functional layer 108 toward the base substrate 102. Note that the vertical direction here refers to the case where the functional layer 108 is on the top and the base substrate 102 is on the bottom. Hereinafter, when simply referred to as “upper” or “lower”, the same applies. The first warp is a virtual warp when the semiconductor substrate 100 is warped only by the first stress 114, and is different from the warp that occurs in the actual semiconductor substrate 100. The maximum value of the displacement from the flat surface is given as the first warp magnitude (first warp amount). If the amount of warpage swollen downward takes a positive value, the first amount of warpage is a positive value.

  The lattice constant of the first crystal layer 104 is smaller than the lattice constant of the second crystal layer 106. When the second crystal layer 106 is epitaxially grown by lattice matching or pseudo-lattice matching on the first crystal layer 104, the constituent atoms of the second crystal layer 106 at the first interface 110 are spaced apart from the lattice of the first crystal layer 104. It is formed to be the same as the constant. However, since the lattice constant of the second crystal layer 106 is larger than the lattice constant of the first crystal layer 104, the distance between the constituent atoms of the second crystal layer 106 increases as the distance from the first interface 110 into the bulk of the second crystal layer 106 increases. It coincides with the lattice constant of the two-crystal layer 106. That is, a force for increasing the constituent atomic spacing acts at least in the vicinity of the first interface 110 of the second crystal layer 106, and a second stress 116, which is a compressive stress, is generated in the second crystal layer 106. As a result, a second warp occurs in the semiconductor substrate 100. Since the second stress 116 is a compressive stress, the second warp has a shape bulging upward from the base substrate 102 toward the functional layer 108. The second warp is a virtual warp when the semiconductor substrate 100 is warped only by the second stress 116, and is different from the warp that occurs in the actual semiconductor substrate 100. The maximum value of the displacement from the flat surface can be given as the second warp magnitude (second warp amount). Since the second warp is the reverse direction of the first warp, the second warp amount is a negative value.

  When a cross-sectional TEM image is observed including the first interface 110 and the second interface 112 in the same field of view, the area of the first moire image 118 observed including the first interface 110 is the second interface 112. It is smaller than the area of the second moire image 120 to be observed. In general, when a defect such as misfit dislocation occurs at the interface, the lattice position at the interface changes, and when this is observed with a TEM image, it is observed as a moire image. That is, as the area of the moire image is larger, more dislocations such as misfit are present, so it can be estimated that stress relaxation occurs at the interface in the region where the area of the moire image is observed. That is, the second interface 112 is more stress relieved than the first interface 110.

  The actual amount of warpage generated in the semiconductor substrate 100 is given by the sum of the amounts of warpage generated from the stresses in the crystal layers formed on the semiconductor substrate 100. In general, since the thermal stress of the functional layer 108 is larger than other stresses, the warpage amount of the semiconductor substrate 100 takes a positive value. The warp amount of the crystal layer formed between the base substrate 102 and the first crystal layer 104 and the warp amount of the crystal layer formed between the second crystal layer 106 and the functional layer 108 are either positive or negative. Although the actual warpage amount varies depending on whether the first warpage is taken, at least the first warpage amount by the functional layer 108 is a positive value and the second warpage amount by the second crystal layer 106 is a negative value. The amount of warpage of the entire 100 is reduced. As a result, cracking and peeling of the functional layer 108 can be suppressed.

  When the base substrate 102 is made of Si and the first crystal layer 104 is made of a Group 3-5 compound semiconductor such as AlN or AlGaN, the lattice constant difference between the base substrate 102 and the first crystal layer 104 is large. The first crystal layer 104 is formed on the base substrate 102 in a state where the lattice is sufficiently relaxed. In such a case, since the interface between the base substrate 102 and the first crystal layer 104 is sufficiently lattice-relaxed, the amount of warpage of the first crystal layer 104 due to the lattice constant difference is very small. In addition, since the thickness of the first crystal layer 104 is generally thinner than the thickness of the functional layer 108, the warp amount of the first crystal layer 104 due to the difference in thermal expansion coefficient between the base substrate 102 and the first crystal layer 104 is It is smaller than the first warp amount generated in the functional layer 108. That is, the first crystal layer 104 does not generate a large amount of warpage, and the effect of the invention of suppressing the cracking and peeling of the functional layer 108 by reducing the amount of warpage of the entire semiconductor substrate 100 is not lost. An arbitrary crystal layer such as a buffer layer can be formed between the base substrate 102 and the first crystal layer 104. When the buffer layer is similar to the first crystal layer 104 described above, As in the case of the single crystal layer 104, a large warp does not occur in the buffer layer. Therefore, the buffer layer does not lose the effect of the invention described above.

  The crystal layer formed between the second crystal layer 106 and the functional layer 108 and in contact with the second interface 112 of the second crystal layer 106 is determined by the lattice constant of the second crystal layer 106. When the crystal layer has a large lattice constant, a compressive stress in the same direction as the second stress 116 is generated in the crystal layer, and the amount of warpage becomes a negative value, so that the first amount of warp by the functional layer 108 is reduced. Can work in any direction. However, when the crystal has a lattice constant smaller than that of the second crystal layer 106, tensile stress in the same direction as the first stress 114 is generated in the crystal layer, and the warpage amount of the semiconductor substrate 100 is reduced. It is not preferable because it acts in the direction of increasing.

  However, even if the lattice constant of the crystal layer formed in contact with the second interface 112 is smaller than the lattice constant of the second crystal layer 106 and generates a tensile stress, the second interface 112 is not the first interface. Since the stress is relieved more than 110, the absolute value of the amount of warpage due to the crystal layer formed in contact with the second interface 112 is smaller than the absolute value of the second amount of warpage due to the second crystal layer 106. As a result, the sum of the warpage amount of the crystal layer formed in contact with the second interface 112 and the second warpage amount by the second crystal layer 106 becomes a negative value, and the warpage amount of the entire semiconductor substrate 100 can be reduced.

  As described above, the first crystal layer 104 and the second crystal layer 106 function as a stress control layer. Even when a plurality of first crystal layers 104 and second crystal layers 106 are formed to enhance the stress control effect, the number of layers to be stacked can be reduced. The moire image can be observed by TEM with the substrate tilted. The tilt angle of the substrate is in the range of 0.2 to 7 degrees. The tilt angle is adjusted so that the moire image is clearly observed, and the moire image is observed with the cross-sectional TEM photograph observed in such a state.

  Note that a functional layer 108 having a thermal expansion coefficient smaller than that of the base substrate 102 may be selected. In this case, the crystal layer material is selected so that the lattice constant of the first crystal layer 104 is larger than the lattice constant of the second crystal layer 106. In this case, in the functional layer 108, a compressive stress due to a difference between the thermal expansion coefficient of the base substrate 102 and the thermal expansion coefficient of the functional layer 108 is generated due to a decrease in temperature, and the first crystalline layer 106 has a first stress. A tensile stress is generated due to the difference between the lattice constant of the crystal layer 104 and the lattice constant of the second crystal layer 106.

When the base substrate 102 is made of Si and the functional layer 108 is GaN, since the first stress 114 generated in the functional layer 108 is a tensile stress, a compressive stress may be generated as the second stress 116. In the case of AlGaN, the larger the Al composition ratio, the smaller the lattice constant. Therefore, when the base substrate 102 is Si, the first crystal layer 104 is made of Al _x Ga _1-x N, and the second crystal layer 106 is Al _y Ga _{1. -YN} , and x and y preferably have a relationship of 0≤y <x≤1. When the base substrate 102 is Si, the first crystal layer 104 and the second crystal layer 106 can be AlN and AlGaN, respectively.

  Note that the amount of misfit dislocations at the second interface 112 can be controlled by the surface state of the second crystal layer 106. For example, the second crystal layer 106 can be grown under the condition that the surface roughness of the second crystal layer 106 is larger than the surface roughness when the first crystal layer 104 is grown. Thereby, the misfit dislocation at the second interface 112 can be made larger than the misfit dislocation at the first interface 110. For example, the second crystal layer 106 may be a crystal grown under the condition that the grain size of the second crystal layer 106 is smaller than the grain size when the first crystal layer 104 is crystal-grown. The surface roughness or grain size of the first crystal layer 104 and the second crystal layer 106 can be controlled by the growth temperature. The higher the growth temperature, the greater the surface roughness. Alternatively, it can be controlled by the V / III ratio, which is the ratio of the Group V material to the Group III material. The smaller the V / III ratio, the greater the surface roughness.

  FIG. 2 shows a cross-sectional example of the semiconductor substrate 200. The semiconductor substrate 200 exemplifies a configuration further including a third crystal layer 204 and a fourth crystal layer 206 in addition to members constituting the semiconductor substrate 100. The third crystal layer 204 and the fourth crystal layer 206 have the same configuration as the first crystal layer 104 and the second crystal layer 106, and function as a stress control layer. Other configurations are the same as those of the semiconductor substrate 100.

  That is, the base substrate 102, the first crystal layer 104, the second crystal layer 106 and the functional layer 108, and the third crystal layer 204 and the fourth crystal layer 206 are combined into the base substrate 102, the first crystal layer 104, and the second crystal layer. The layer 106, the third crystal layer 204, the fourth crystal layer 206, and the functional layer 108 are arranged in this order. The second crystal layer 106 and the third crystal layer 204 are formed in contact with each other. The third crystal layer 204 and the fourth crystal layer 206 are in contact with each other by lattice matching or pseudo-lattice matching, and the lattice constant of the third crystal layer 204 is smaller than the lattice constant of the fourth crystal layer 206. A cross-sectional TEM image including the second interface 112 where the second crystal layer 106 and the third crystal layer 204 are in contact with each other and the third interface 208 where the third crystal layer 204 and the fourth crystal layer 206 are in contact with each other in the same field of view. When observed, the area of the third moire image 210 observed including the third interface 208 is smaller than the area of the second moire image 120.

  Since the thermal expansion coefficient of the functional layer 108 is larger than the thermal expansion coefficient of the base substrate 102 and the lattice constant of the third crystal layer 204 is smaller than the lattice constant of the fourth crystal layer 206, the fourth crystal layer 206 includes A third stress 224 (compressive stress) resulting from the difference between the lattice constant of the third crystal layer 204 and the lattice constant of the fourth crystal layer 206 is generated in a direction opposite to the direction of the first stress 114 (tensile stress). That is, the functional layer 108 generates a positive first warp amount, the second crystal layer 106 generates a negative second warp amount, and the fourth crystal layer 206 has a negative value due to the third stress 224. A third amount of warpage of the value is generated. Note that the bonding at the second interface 112 between the second crystal layer 106 and the third crystal layer 204 generates a tensile stress in the third crystal layer 204 and causes a positive amount of warpage. Since the relaxation is greater than the stress relaxation at the first interface 110 or the stress relaxation at the third interface 208, the absolute value of the warpage amount by the third crystal layer 204 is the warpage amount by the second crystal layer 106 or the warpage amount by the fourth crystal layer 206. Smaller than. As described above, the first crystal layer 104 and the second crystal layer 106 function as stress control layers, and the third crystal layer 204 and the fourth crystal layer 206 also function as stress control layers. The amount of warpage of the entire semiconductor substrate 100 can be reduced.

  Note that the first crystal layer 104 and the third crystal layer 204 can be the same, and the second crystal layer 106 and the fourth crystal layer 206 can be the same. The thermal expansion coefficient of the functional layer 108 may be smaller than the thermal expansion coefficient of the base substrate 102, and the lattice constant of the third crystal layer 204 may be larger than the lattice constant of the fourth crystal layer 206. In this case, in the functional layer 108, compressive stress due to the difference between the thermal expansion coefficient of the base substrate 102 and the thermal expansion coefficient of the functional layer 108 is generated due to a decrease in temperature. A tensile stress is generated due to the difference between the lattice constant of the crystal layer 204 and the lattice constant of the fourth crystal layer 206. The first crystal layer 104 and the second crystal layer 106 may be graded layers whose composition changes gently.

  A 2-inch Si substrate having a main surface of (111) surface was prepared. This substrate was etched with hydrofluoric acid to remove the silicon oxide film on the main surface of the substrate. Next, this substrate is carried into a growth furnace, and the temperature of the substrate is raised to 1130 ° C. while introducing hydrogen into the furnace, thereby removing a thin silicon oxide film newly formed on the substrate surface after etching with hydrofluoric acid. Went.

Next, by sequentially supplying raw materials on the Si substrate under the conditions shown in Table 1, a semiconductor substrate having a crystal stacked structure shown in Table 1 was produced. In this laminated structure, in order to clearly show the effect of the present invention, the thickness of the functional layer is made thinner than the thickness used for a normal element. Thus, the influence on the warpage of the substrate due to the difference in thermal expansion coefficient between the functional layer and the Si substrate is reduced, and the effect of the stress control layer according to the present invention is relatively clearly shown.

As raw materials, trimethylgallium (TMG), trimethylaluminum (TMA), and ammonia (NH ₃ ) were used. The pressure in the growth furnace was kept at 30 kPa. Hydrogen was used as a raw material carrier gas. The growth of each layer was performed while controlling the supply amount of each raw material and the substrate temperature. Table 1 shows the difference between the Al composition and the V / III ratio. The Al composition changes the flow rate ratio of TMG and TMA, and the V / III ratio changes the ratio of the flow rate of ammonia and the flow rate of TMG and TMA. Was controlled.

  FIG. 3 is a cross-sectional TEM photograph of the semiconductor substrate formed as described above. A sample for a cross-sectional TEM photograph was produced by cutting the substrate along a plane parallel to the (10-10) plane of the semiconductor crystal. An ion beam processing method was used for cutting. The thickness of the cut sample was 100 nm. FIG. 4 is a cross-sectional TEM photograph of this semiconductor substrate (cut out sample) observed by tilting by 5 degrees. That is, the electron beam was irradiated from a direction inclined by 5 ° from the direction perpendicular to the (10-10) plane to the (0001) plane direction. The acceleration voltage of the electron beam was 300 kV. The irradiation current value was about 400 pA. The transmission electron beam was detected with an imaging plate, and a cross-sectional TEM photograph was obtained. The cross-sectional TEM photograph was taken so as to include the first interface and the second interface in the same field of view, and to include a range of 600 nm width in the direction parallel to the substrate surface (lateral direction in the photograph of FIG. 4).

  By tilting by 5 degrees, a striped moire image can be observed in a region including the interface between the AlN layer and the lower AlGaN layer. In FIG. 4, the portion of the moire image is surrounded by a broken line. Generation of a striped moire image indicates that crystals having different lattice constants are close to each other in the vicinity of the interface between the crystal layers. That is, the crystal grows discontinuously at the interface where moire is generated. In other words, it grows while relaxing the lattice.

  The evaluation of the moire area is a range including the first interface and the second interface in the same field of view in a cross section passing through the center of the plane parallel to the laminated structure of the semiconductor crystal and in a direction parallel to the substrate surface (in FIG. This is done for a range of 600 nm width in the photo (lateral direction). In FIG. 4, the area near the AlN / AlGaN interface on the (substrate side) has a larger area where moire fringes are generated than near the AlGaN / AlN interface on the (substrate side). That is, there are more bonds in the vicinity of the (substrate side) AlN / AlGaN interface than in the vicinity of the (substrate side) AlGaN / AlN interface. As a result, the stress generated due to the difference in lattice constant is larger for the AlN / AlGaN stacked pair that sandwiches the interface with less lattice relaxation (substrate side) than the AlGaN / AlN stacked pair that sandwiches the lattice relaxed interface (substrate side). growing.

  (Substrate side) The warp generated in the substrate due to the stress generated by the AlGaN / AlN stacked pair is the same as the direction of the warp generated by the difference in thermal expansion coefficient between the functional layer and the Si substrate. (Substrate side) AlN / AlGaN The warp generated by the stacked pair is the opposite. As described above, since the stress generated due to the lattice constant difference is larger in the (substrate side) AlN / AlGaN stacked pair than in the (substrate side) AlGaN / AlN stacked pair, the stress relaxation layer shown in Table 1 is It acts to reduce the warpage caused by the difference in thermal expansion coefficient between the functional layer and the Si substrate, and suppresses the generation of cracks.

  FIG. 5 shows a photograph of the appearance of a substrate epitaxially grown by changing the growth temperature of the AlGaN layer of the stress control layer. A striped pattern in which horizontal lines with a width of 2 mm are arranged with a period of 4 mm is arranged on the back side of the substrate so that the warp of the substrate can be visually recognized, and the striped pattern is photographed from above obliquely so that the striped pattern is reflected on the substrate. The warpage of the substrate can be recognized by the difference in the width of the stripe pattern reflected on the substrate. The substrates (a), (b), and (c) are based on the structure and manufacturing conditions shown in Table 1, and the growth temperature of AlGaN of the stress control layer is only (a) 900 ° C., (b) 1000 ° C., ( c) 1130 ° C.

  (A) has the narrowest stripe pattern width, and the stripe pattern width increases in the order of (b) and (c). In (a) and (b), the substrate is convex, and the degree of warpage is larger in (a) than in (b). (C) is substantially flat. That is, with the stress control layer according to the present invention, the substrate is warped in the direction opposite to the warp caused by the difference in thermal expansion coefficient between the Si substrate and the functional layer, and the degree thereof can be controlled. By applying this invention, it is possible to control the warpage of the substrate caused by the difference in thermal expansion coefficient between the functional layer and the substrate, and to suppress the occurrence of cracks.

  The execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, and method shown in the claims, the description, and the drawings is particularly “before”, “prior”, etc. It should be noted that it can be implemented in any order unless explicitly stated and the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor substrate, 102 ... Base substrate, 104 ... First crystal layer, 106 ... Second crystal layer, 108 ... Functional layer, 110 ... First interface, 112 ... Second interface, 114 ... First stress, 116 ... First 2 stress, 118 ... first moire image, 120 ... second moire image, 200 ... semiconductor substrate, 204 ... third crystal layer, 206 ... fourth crystal layer, 208 ... third interface, 210 ... third moire image, 224 ... Third stress.

Claims (4)

A base substrate made of silicon , a first crystal layer, a second crystal layer, a third crystal layer, a fourth crystal layer, and a functional layer;
The base substrate, the first crystal layer, the second crystal layer, and the functional layer, and the third crystal layer and the fourth crystal layer are the base substrate, the first crystal layer, and the second crystal layer. , The third crystal layer, the fourth crystal layer, and the functional layer are arranged in this order,
The first crystal layer and the second crystal layer are in contact with each other in lattice matching or pseudo-lattice matching;
The second crystal layer and the third crystal layer are in contact with each other;
The third crystal layer and the fourth crystal layer are in contact with each other in lattice matching or pseudo-lattice matching;
A thermal expansion coefficient of the functional layer is larger than a thermal expansion coefficient of the base substrate;
A lattice constant of the first crystal layer is smaller than a lattice constant of the second crystal layer;
A lattice constant of the third crystal layer is smaller than a lattice constant of the fourth crystal layer;
The first and the first interface crystal layer and the second crystal layer is in contact with each other, and the second interface the second crystal layer and the third crystal layer that Sessu each other, the third crystal layer and the fourth crystal When a cross-sectional TEM image is observed including the third interface where the layers are in contact with each other in the same field of view, the area of the first moire image observed including the first interface is observed including the second interface. The area of the third moire image that is smaller than the area of the second moire image and is observed including the third interface is smaller than the area of the second moire image. The first crystal layer is made of Al _x Ga _1-x N;
The second crystal layer is made of Al _y Ga _1-y N;
The semiconductor substrate according to claim 1, wherein x and y have a relationship of 0 ≦ y <x ≦ 1. The crystal growth of the second crystal layer is performed under a condition that the surface roughness of the second crystal layer is larger than the surface roughness when the first crystal layer is crystal-grown. 2. The semiconductor substrate according to 2. The semiconductor substrate according to any one of claims 1 to 3, wherein each of the first crystal layer, the second crystal layer, and the functional layer is formed by an epitaxial growth method.