JP2015535991A5 - - Google Patents

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Publication number
JP2015535991A5
JP2015535991A5 JP2015533265A JP2015533265A JP2015535991A5 JP 2015535991 A5 JP2015535991 A5 JP 2015535991A5 JP 2015533265 A JP2015533265 A JP 2015533265A JP 2015533265 A JP2015533265 A JP 2015533265A JP 2015535991 A5 JP2015535991 A5 JP 2015535991A5
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JP
Japan
Prior art keywords
interface unit
network interface
transaction
context array
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015533265A
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English (en)
Japanese (ja)
Other versions
JP6144348B2 (ja
JP2015535991A (ja
Filing date
Publication date
Priority claimed from US13/626,758 external-priority patent/US9471538B2/en
Priority claimed from US13/626,766 external-priority patent/US9225665B2/en
Application filed filed Critical
Priority claimed from PCT/US2013/061295 external-priority patent/WO2014052261A1/en
Publication of JP2015535991A publication Critical patent/JP2015535991A/ja
Publication of JP2015535991A5 publication Critical patent/JP2015535991A5/ja
Application granted granted Critical
Publication of JP6144348B2 publication Critical patent/JP6144348B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2015533265A 2012-09-25 2013-09-24 チップソケットプロトコル上のネットワーク Active JP6144348B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13/626,758 2012-09-25
US13/626,758 US9471538B2 (en) 2012-09-25 2012-09-25 Network on a chip socket protocol
US13/626,766 US9225665B2 (en) 2012-09-25 2012-09-25 Network on a chip socket protocol
US13/626,766 2012-09-25
PCT/US2013/061295 WO2014052261A1 (en) 2012-09-25 2013-09-24 Network on a chip socket protocol

Publications (3)

Publication Number Publication Date
JP2015535991A JP2015535991A (ja) 2015-12-17
JP2015535991A5 true JP2015535991A5 (enExample) 2017-01-26
JP6144348B2 JP6144348B2 (ja) 2017-06-07

Family

ID=50388890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015533265A Active JP6144348B2 (ja) 2012-09-25 2013-09-24 チップソケットプロトコル上のネットワーク

Country Status (6)

Country Link
EP (2) EP4123468A1 (enExample)
JP (1) JP6144348B2 (enExample)
KR (1) KR101690568B1 (enExample)
CN (1) CN104685480B (enExample)
IN (1) IN2015MN00441A (enExample)
WO (1) WO2014052261A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2529217A (en) * 2014-08-14 2016-02-17 Advanced Risc Mach Ltd Transmission control checking for interconnect circuitry
US11436185B2 (en) * 2019-11-15 2022-09-06 Arteris, Inc. System and method for transaction broadcast in a network on chip
WO2022141322A1 (zh) * 2020-12-30 2022-07-07 华为技术有限公司 一种片上系统及相关方法
CN117389931B (zh) * 2023-12-12 2024-05-03 芯动微电子科技(武汉)有限公司 适用于总线访问gpu核内存储器的协议转换模块及方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6477646B1 (en) * 1999-07-08 2002-11-05 Broadcom Corporation Security chip architecture and implementations for cryptography acceleration
US6826191B1 (en) * 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US8087064B1 (en) * 2000-08-31 2011-12-27 Verizon Communications Inc. Security extensions using at least a portion of layer 2 information or bits in the place of layer 2 information
WO2002069575A1 (en) * 2001-02-28 2002-09-06 Gotham Networks, Inc. Methods and apparatus for network routing device
US7277449B2 (en) * 2002-07-29 2007-10-02 Freescale Semiconductor, Inc. On chip network
US6996651B2 (en) * 2002-07-29 2006-02-07 Freescale Semiconductor, Inc. On chip network with memory device address decoding
US6671275B1 (en) * 2002-08-02 2003-12-30 Foundry Networks, Inc. Cross-point switch with deadlock prevention
WO2004034676A1 (en) * 2002-10-08 2004-04-22 Koninklijke Philips Electronics N.V. Integrated circuit and method for establishing transactions
US7181556B2 (en) * 2003-12-23 2007-02-20 Arm Limited Transaction request servicing mechanism
CN100520752C (zh) * 2004-03-26 2009-07-29 皇家飞利浦电子股份有限公司 数据处理系统和用于事务中止的方法
US7716409B2 (en) * 2004-04-27 2010-05-11 Intel Corporation Globally unique transaction identifiers
WO2007033363A2 (en) * 2005-09-13 2007-03-22 Ist International, Inc. System and method for providing packet connectivity between heterogeneous networks
CN101379841A (zh) * 2005-09-13 2009-03-04 Ist国际公司 为提供异种网络之间的小包连通性和组分和小包之系统和方法
US20070245033A1 (en) * 2006-04-14 2007-10-18 Microsoft Corporation Link layer discovery and diagnostics
EP2054807A2 (en) * 2006-08-08 2009-05-06 Koninklijke Philips Electronics N.V. Electronic device and method of controlling a communication
GB2450148A (en) * 2007-06-14 2008-12-17 Advanced Risc Mach Ltd Controlling write transactions between initiators and recipients via interconnect logic
US8285912B2 (en) * 2009-08-07 2012-10-09 Arm Limited Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure
FR2951342B1 (fr) * 2009-10-13 2017-01-27 Arteris Inc Reseau sur puce a latence nulle
EP2333830B1 (en) * 2009-12-07 2014-09-03 STMicroelectronics (Research & Development) Limited a package comprising a first and a second die coupled by a multiplexed bus
EP2388707B1 (en) * 2010-05-20 2014-03-26 STMicroelectronics (Grenoble 2) SAS Interconnection method and device, for example for systems-on-chip
WO2011148925A1 (ja) * 2010-05-24 2011-12-01 日本電気株式会社 半導体装置とネットワークルーティング方法とシステム
FR2961048B1 (fr) * 2010-06-03 2013-04-26 Arteris Inc Reseau sur puce avec caracteristiques de qualite-de-service
EP2444903A1 (en) * 2010-09-29 2012-04-25 STMicroelectronics (Grenoble 2) SAS A transaction reordering arrangement

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