JP2015534271A - CMOS image sensor column sharing pixel unit and pixel array - Google Patents

Abstract

The present invention discloses a column sharing pixel unit and a pixel array of a CMOS image sensor. The MOS image sensor column sharing pixel unit and the CMOS image sensor pixel array have two column pixels as one set of pixel units, and the two pixels share a selection transistor, a source follower transistor, a reset transistor, and a floating active region in the column. A plurality of sets of pixel units are arranged so as to form a two-dimensional pixel array in the vertical and horizontal directions, and are connected by two layers of metal lines in the two-dimensional pixel array. The function of collecting image information is realized by using only the metal wire of the first layer and the metal wire of the first layer as the control line of the device, and a metal wire of a higher layer than the second layer is used as the device. Without using control lines, the media height on the photodiode Si surface is effectively reduced, and more light is incident on the photodiode. In Rukoto, by increasing the light use efficiency and the conversion gain of the small-area image sensor, it is possible to improve the sensitivity, it is possible to improve the image quality of the small area pixel image sensor effectively. [Selection] Figure 4

Description

  This application is filed with the Chinese Patent Office on September 24, 2012, and the priority of the Chinese patent application with the application number 201210359161.6 and the title of the invention as "column sharing pixel unit and pixel array of CMOS image sensor" The entire content of which is claimed and incorporated herein by reference.

  The present invention relates to a CMOS image sensor, and more particularly to a column sharing pixel unit and a pixel unit of a CMOS image sensor.

  Currently, image sensors are widely used in digital cameras, mobile phones, medical devices, automobiles, and other applications. In particular, due to the rapid progress of CMOS (complementary metal oxide semiconductor) image sensors, people's demand for low output, small size, high resolution image sensors is increasing.

  The arrangement method of the pixel structure of the CMOS image sensor in the prior art takes 4T2S (four transistors, two pixels sharing) as an example, and it depends on the structural characteristics of the pixel itself. Metal, second layer metal, and third metal layer need to be interconnected as an element, and multiple rows or columns of first layers between adjacent rows of pixels or between adjacent columns of pixels, respectively Metal, second layer metal or third layer metal wire is required. In addition, the parasitic capacitance of the metal connecting the floating active region and the gate of the source follower transistor increases.

  The prior art described above includes at least the following drawbacks.

  Since the photosensitive area of the small pixel sensor is small and the sensitivity is low, information transmission under dark light is not clear enough. In particular, when the first layer metal, the second layer metal, and the third metal layer are interconnected as an element, the height of the medium on the surface of the photodiode Si (silicon) is relatively high. The metal wire obstructs part of the light incident on the. Moreover, the metal line connecting the floating active region and the gate of the source follower transistor is close to the power supply metal line, the parasitic capacitance of the floating active region is increased, and the width (conversion gain) for converting the signal electrons into the signal voltage is not increased. .

  An object of the present invention is to provide a column sharing pixel unit and a pixel array of a small area CMOS image sensor with high sensitivity.

  The object of the present invention is realized by the following technical technique.

  In the column sharing pixel unit of the CMOS image sensor of the present invention, one pixel includes a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, a floating active region, and a metal line. Two column pixels are used as one set of pixel units, and the two pixels share a selection transistor, a source follower transistor, a reset transistor, and a floating active region in the column.

  The CMOS image sensor pixel array of the present invention includes a plurality of sets of column sharing pixel units of the CMOS image sensor, and the plurality of sets of pixel units are arranged to form a two-dimensional pixel array in the vertical and horizontal directions. The pixel array is connected by two layers of metal lines including a zeroth layer metal line and a first layer metal line.

  As can be seen from the above-described technical technique provided by the present invention, the column image sharing pixel unit and the CMOS image sensor pixel array of the CMOS image sensor of the present invention have two column pixels as one set of pixel units, and the two pixels are in a column. Share a selection transistor, a source follower transistor, a reset transistor, and a floating active region, and arrange a plurality of sets of pixel units so as to form a two-dimensional pixel array in the vertical and horizontal directions. 2 layers of metal lines are connected, and the metal lines use only the 0th layer metal lines and the 1st layer metal lines as element control lines to realize the function of collecting image information. The height of the medium on the surface of the photodiode Si can be reduced without using a metal wire of a higher layer than the second layer as an element control line. Effectively lowered, is incident more light on the photodiode. Therefore, in the column sharing pixel unit structure of the CMOS image sensor of the present invention, the sensitivity can be improved by increasing the light utilization efficiency and the conversion gain of the small area image sensor, so that the image quality of the small area pixel image sensor is effectively improved. Can be increased.

It is the circuit schematic diagram of the 4T2S structure which consists of two pixels in the specific Example 1 of the column sharing pixel unit of the CMOS image sensor of this invention. FIG. 4 is a schematic layout diagram of a 4T2S structure including two pixels in a specific example 1 of the column sharing pixel unit of the CMOS image sensor of the present invention. It is the circuit schematic diagram of the 4 * 4 pixel array in the specific Example 1 of the column sharing pixel unit and pixel array of the CMOS image sensor of this invention. FIG. 3 is a layout schematic diagram of a 4 × 4 pixel array in a specific example 1 of the column sharing pixel unit and the pixel array of the CMOS image sensor of the present invention. It is the circuit schematic diagram of the 4T2S structure which consists of two pixels in the specific Example 2 of the column sharing pixel unit of the CMOS image sensor of this invention. It is the layout schematic of the 4 * 4 pixel array in the specific Example 2 of the column sharing pixel unit and pixel array of the CMOS image sensor of this invention.

  The technical methods in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It will be appreciated that the described embodiments are merely some of the embodiments of the present invention and not all embodiments. All other embodiments obtained based on the embodiments of the present invention on the premise that those skilled in the art do not spend creative efforts are all included in the protection scope of the present invention.

  Preferred embodiments of the column sharing pixel unit of the CMOS image sensor of the present invention are as shown in FIGS.

  One pixel includes a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, a floating active region, and a metal line, and two column pixels are used as one set of pixel units. Two pixels share a selection transistor, a source follower transistor, a reset transistor, and a floating active region in the column.

  The floating active region and the gate of the source follower transistor are connected by a first-layer metal line in the column direction, and this metal line is separated from the power supply metal line.

  The CMOS image sensor pixel array of the present invention includes a plurality of sets of column sharing pixel units of the CMOS image sensor, and the plurality of sets of pixel units are arranged to form a two-dimensional pixel array in the vertical and horizontal directions. The pixel array is connected by two layers of metal lines including a zeroth layer metal line and a first layer metal line.

  In the two-dimensional pixel array, a power supply line and a column signal output line between pixels in the same column in the column direction are connected by a metal line of the first layer.

  In the two-dimensional pixel array, the transistor element control lines between the same row pixels in the row direction are connected by the 0th layer metal line.

  The present invention solves the problem that the sensitivity of a small area pixel of a conventional image sensor is low, and uses only the metal wire of the 0th layer and the metal wire of the 1st layer as element control lines. This function realizes the function to collect image information, and without using a metal wire of a higher layer than the second layer as an element control line, the height of the medium on the surface of the photodiode Si is lowered and more light is emitted. Can be incident on the photodiode. The metal line connecting the floating active region to the gate of the source follower transistor is separated from the power supply metal line, so that the parasitic capacitance of the floating active region is reduced, so that the width for converting the signal electrons into the signal voltage is increased. Therefore, in the CMOS image sensor column sharing pixel unit and the CMOS image sensor pixel array structure of the present invention, the sensitivity can be improved by increasing the light utilization efficiency and the conversion gain in the small area image sensor. The image quality of the image sensor can be improved effectively.

Example 1

  As shown in the schematic circuit diagram of FIG. 1, the column sharing pixel unit of the CMOS image sensor employs a 4T2S structure, which includes two pixels, and these two pixels are arranged in the same column in an up-and-down structure method.

  In FIG. 1, reference numerals 101 and 201 denote two pixel photodiodes, and reference numerals 102 and 202 denote two charge transfer transistors. Reference numeral 103 denotes a reset transistor, 104 denotes a source follower transistor, 105 denotes a selection transistor, and 106 denotes a column signal output line. Two of these pixels include the reset transistor 103, the source follower transistor 104, the selection transistor 105, and the column signal output line 106. Sharing. An FD (Floating Diffusion) is a floating active area, and two pixels share the FD. The transistor control line SX is connected to the gate of the selection transistor 105, the control line TX1 is connected to the gate of the transfer transistor 102, the control line RX is connected to the gate of the reset transistor 103, and the control line TX2 is connected to the gate of the transfer transistor 202. Connected to. The column signal output line 106 is connected to the source of the source follower transistor 104. Vdd is a power supply voltage and is connected to the drain of the reset transistor 103 and the drain of the selection transistor 105.

  FIG. 2 is a layout schematic diagram corresponding to the circuit schematic diagram shown in FIG.

  In FIG. 2, transistor element control lines SX, TX1, RX, TX2 are connected by a metal wire of the 0th layer, and the power supply control line Vdd and the column signal output line 106 are connected by a metal wire of the first layer. The metal element control lines SX, TX1, RX and TX2 in the 0th layer are in contact with the gate polysilicons 105, 102, 103 and 202 through the contact holes 0, respectively, and the metal power supply control lines in the 1st layer The Vdd and the drain of 105 and the drain of 103 are in contact with each other via a contact hole 1, and between the metal column signal output lines 106 and 104 of the first layer are connected via a contact hole 1. Contact each other. The floating active region FD and the gate polysilicon of 104 are contacted through the contact hole 1 using the first layer metal line.

  The two pixels described above are described as one set of units. In this embodiment, a plurality of sets of pixel units are arranged as a two-dimensional pixel array in the vertical and horizontal directions, and a 4 × 4 pixel array is used. It is shown schematically as an example. The column sharing pixel unit structure and the two-dimensional pixel array structure of the high-sensitivity small-area CMOS image sensor of the present invention include, but are not limited to, a 4 × 4 pixel array, and can be applied to other pixel arrays of various sizes. Can do.

  FIG. 3 is a circuit schematic diagram of a 4 × 4 pixel array. A schematic layout corresponding to the pixel array circuit diagram shown in FIG. 3 is as shown in FIG.

  In the pixel arrays shown in FIGS. 3 and 4, reference numerals 111, 121, 131, and 141 denote photodiodes of the pixels in the first row, and 211, 221, 231, and 241 denote photodiodes of the pixels in the second row. , 321, 331, and 341 are photodiodes of pixels in the third row, and 411, 421, 431, and 441 are photodiodes of pixels in the fourth row. The pixel element control line SX1 is connected to the gate polysilicon of the selection transistors 115, 125, 135, and 145 in the same row, and the pixel element control line TX1 is connected to the gate polysilicon of the charge transfer transistors 112, 122, 132, and 142 in the same row. The pixel element control line RX1 is connected to the gate polysilicon of the reset transistors 113, 123, 133, and 143 in the same row, and the pixel element control line TX2 is connected to the gate polysilicon of the charge transfer transistors 212, 222, 232, and 242 in the same row. Each set of pixel units FD is connected to the corresponding gate polysilicon of the source follower transistors 114, 124, 134, 144. The pixel element control line SX3 is connected to the gate polysilicon of the selection transistors 315, 325, 335, and 345 in the same row, and the pixel element control line TX3 is connected to the gate polysilicon of the charge transfer transistors 312, 322, 332, and 342 in the same row. The pixel element control line RX3 is connected to the gate polysilicon of the reset transistors 313, 323, 333, and 343 in the same row, and the TX4 of the pixel element is connected to the gate polysilicon of the charge transfer transistors 412, 422, 432, and 442 in the same row. The pixel units FD of each set are connected to the gate polysilicon of the corresponding source follower transistors 314, 324, 334, 344, respectively. Reference numerals 16, 26, 36, and 46 denote column signal output lines for the pixels of the first column, the second column, the third column, and the fourth column, respectively, which are connected to the sources of the source follower transistors of the corresponding column pixels. Vdd is a power supply metal line.

  In the pixel array, pixel element control lines SX1, TX1, RX1, TX2, SX3, TX3, RX3, and TX4 in the same row are connected by a metal line of the 0th layer. The signal output lines 16, 26, 36, 46 in the same column are connected by a first layer metal line, the power supply line Vdd is connected by a first layer metal line, and the FD of each set of pixel units is a corresponding source. The first layer metal line is connected to the gate of the follower transistor.

Example 2

  In another example for realizing the embodiment of the present invention, as shown in the circuit schematic diagram of FIG. 5, the column sharing pixel unit of the CMOS image sensor adopts a 4T2S structure, and includes two pixels. The pixels are arranged in the same row in an up-and-down structure method. 101 'and 201' are two pixel photodiodes, respectively, and 102 'and 202' are two pixel charge transfer transistors, respectively. 103 ′ is a reset transistor, 104 ′ is a source follower transistor, 105 ′ is a selection transistor, and 106 ′ is a column signal output line. Of these, two pixels are the reset transistor 103 ′ and the source follower transistor 104. ', The selection transistor 105' and the column signal output line 106 'are shared. FD ′ (Floating Diffusion) is a floating active region, and two pixels share FD ′. The transistor control line SX ′ is connected to the gate of the selection transistor 105 ′, the control line TX1 ′ is connected to the gate of the transfer transistor 102 ′, the control line RX ′ is connected to the gate of the reset transistor 103 ′, and the control line TX2 ′ Is connected to the gate of the transfer transistor 202 '. The column signal output line 106 'is connected to the source of the source follower transistor 104'. Vdd 'is a power supply voltage and is connected to the drain of the reset transistor 103' and the drain of the selection transistor 105 '.

  The two pixels described above are described as one set of units. In this embodiment, a plurality of sets of pixel units are arranged as a two-dimensional pixel array in the vertical and horizontal directions, and a 4 × 4 pixel array is used. It is shown schematically as an example. The column sharing pixel unit structure and the two-dimensional pixel array structure of the high-sensitivity small-area CMOS image sensor of the present invention include, but are not limited to, a 4 × 4 pixel array, and can be applied to other pixel arrays of various sizes. Can do.

  In the pixel array shown in FIG. 6, 111 ′, 121 ′, 131 ′, 141 ′ are photodiodes of the pixels in the first row, and 211 ′, 221 ′, 231 ′, 241 ′ are the photos of the pixels in the second row. 311 ′, 321 ′, 331 ′, and 341 ′ are photodiodes of the pixels in the third row, and 411 ′, 421 ′, 431 ′, and 441 ′ are photodiodes of the pixels in the fourth row. The pixel element control line SX1 ′ is connected to the gate polysilicon of the selection transistors 115 ′, 125 ′, 135 ′, and 145 ′ in the same row, and the pixel element control line TX1 ′ is the charge transfer transistors 112 ′, 122 ′, and 132 ′ in the same row. , 142 ′, the pixel element control line RX1 ′ is connected to the reset transistors 113 ′, 123 ′, 133 ′, 143 ′ of the same row, and the pixel element control line TX2 ′ of the same row. Connected to the gate polysilicon of the charge transfer transistors 212 ', 222', 232 ', 242', each set of pixel units FD 'has a corresponding gate poly of the source follower transistors 114', 124 ', 134', 144 '. Connected to silicon. The pixel element control line SX3 ′ is connected to the gate polysilicon of the selection transistors 315 ′, 325 ′, 335 ′, and 345 ′ in the same row, and the pixel element control line TX3 ′ is the charge transfer transistors 312 ′, 322 ′, and 332 ′ in the same row. 342 ′ is connected to the gate polysilicon of the pixel element, the pixel element control line RX3 ′ is connected to the gate polysilicon of the reset transistors 313 ′, 323 ′, 333 ′, and 343 ′ of the same row, and the TX4 ′ of the pixel element is the charge of the same row. Each set of pixel units FD ′ is connected to the gate polysilicon of the transfer transistors 412 ′, 422 ′, 432 ′, 442 ′, and the gate polysilicon of the corresponding source follower transistors 314 ′, 324 ′, 334 ′, 344 ′. Connected to. Reference numerals 16 ', 26', 36 ', and 46' denote column signal output lines for the pixels of the first column, the second column, the third column, and the fourth column, respectively, and the source of the source follower transistor of the corresponding column pixel. Connected. Vdd 'is a power supply metal line.

  In the CMOS image sensor column sharing pixel unit and the CMOS image sensor pixel array of the two embodiments of the present invention, a pixel structure arranged in an up-and-down structure method is adopted, and a connection method of transistors and floating nodes in the pixel structure is adopted. By improving, the metal line realizes a function of collecting image information by using only the metal line of the 0th layer and the metal line of the 1st layer as the control line of the element. Without using higher-layer metal lines as element control lines, the number of layers used for metal lines is reduced, the medium height on the surface of the photodiode Si is effectively lowered, and more light is emitted from the photodiode. Increasing the light utilization efficiency.

  It should be particularly noted that the use of the 0th layer metal line and the first layer metal line is not the only embodiment for implementing the present invention, but the first layer metal line and the second layer metal line. This means that the advantages of the pixel structure of the present invention may be realized by using metal lines of other layers or other metal lines. The use of the metal lines of the Nth layer and the (N + 1) th layer may be determined according to the design situation of a specific pixel, both of which reduce the number of layers used for the metal lines proposed in the present invention, The effect of increasing the light utilization efficiency by reducing the height of the medium can be realized. Since the design method that is the core of the pixel structure for changing the layer hierarchy of the metal lines is similar to the first embodiment and the second embodiment, it will not be described separately here.

  In addition, the metal line connecting the floating active region of the column sharing pixel unit of the CMOS image sensor of the present invention to the gate of the source follower transistor is separated from the power supply metal line, thereby reducing the parasitic capacitance of the floating active region. Is converted into a signal voltage.

  Therefore, in the CMOS image sensor column sharing pixel unit and the CMOS image sensor pixel array structure of the present invention, the sensitivity can be improved by increasing the light use efficiency and conversion gain of the small area pixel sensor. The image quality of the sensor can be improved effectively.

  The above is only a preferred specific embodiment of the present invention, and the protection scope of the present invention is not limited to this. Any change or replacement readily conceivable by those skilled in the art within the technical scope disclosed in the present invention shall fall within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (4)

One pixel is a column sharing pixel unit of a CMOS image sensor including a photodiode, a charge transfer transistor, a selection transistor, a source follower transistor, a reset transistor, a floating active region, and a metal line,
Column sharing of a CMOS image sensor, wherein two column pixels are used as one set of pixel units, and the two pixels share a selection transistor, a source follower transistor, a reset transistor, and a floating active region in the column. Pixel unit. 2. The floating active region and the gate of the source follower transistor are connected by a first layer metal line in a column direction, and the metal line is separated from a metal line of a power source. CMOS image sensor column-sharing pixel unit. A plurality of column-sharing pixel units of the CMOS image sensor according to claim 1 or 2 are included, the plurality of sets of pixel units are arranged to form a two-dimensional pixel array in the vertical and horizontal directions, and the two-dimensional pixel array A CMOS image sensor pixel array comprising: a second metal line including a zeroth layer metal line and a first layer metal line. In the two-dimensional pixel array, a power line and a column signal output line between pixels in the same column in the column direction are connected by a metal line of the first layer,
4. The CMOS image sensor pixel array according to claim 3, wherein in the two-dimensional pixel array, transistor element control lines between the same row pixels in the row direction are connected by a metal line of the 0th layer.

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