JP2015511427A5 - - Google Patents

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Publication number
JP2015511427A5
JP2015511427A5 JP2014553393A JP2014553393A JP2015511427A5 JP 2015511427 A5 JP2015511427 A5 JP 2015511427A5 JP 2014553393 A JP2014553393 A JP 2014553393A JP 2014553393 A JP2014553393 A JP 2014553393A JP 2015511427 A5 JP2015511427 A5 JP 2015511427A5
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JP
Japan
Prior art keywords
delay line
delay
power
difference
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2014553393A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015511427A (ja
Filing date
Publication date
Priority claimed from US13/368,906 external-priority patent/US8680908B2/en
Application filed filed Critical
Publication of JP2015511427A publication Critical patent/JP2015511427A/ja
Publication of JP2015511427A5 publication Critical patent/JP2015511427A5/ja
Pending legal-status Critical Current

Links

JP2014553393A 2012-01-18 2013-01-17 オンチップ粗遅延較正 Pending JP2015511427A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261587705P 2012-01-18 2012-01-18
US61/587,705 2012-01-18
US13/368,906 US8680908B2 (en) 2012-01-18 2012-02-08 On-chip coarse delay calibration
US13/368,906 2012-03-08
PCT/US2013/021836 WO2013109688A1 (en) 2012-01-18 2013-01-17 On-chip coarse delay calibration

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2018072371A Division JP2018152567A (ja) 2012-01-18 2018-04-04 オンチップ粗遅延較正

Publications (2)

Publication Number Publication Date
JP2015511427A JP2015511427A (ja) 2015-04-16
JP2015511427A5 true JP2015511427A5 (enExample) 2016-02-12

Family

ID=48779550

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2014553393A Pending JP2015511427A (ja) 2012-01-18 2013-01-17 オンチップ粗遅延較正
JP2018072371A Pending JP2018152567A (ja) 2012-01-18 2018-04-04 オンチップ粗遅延較正

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2018072371A Pending JP2018152567A (ja) 2012-01-18 2018-04-04 オンチップ粗遅延較正

Country Status (6)

Country Link
US (1) US8680908B2 (enExample)
EP (1) EP2805416A1 (enExample)
JP (2) JP2015511427A (enExample)
KR (1) KR20140123956A (enExample)
CN (1) CN104054263B (enExample)
WO (1) WO2013109688A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140266290A1 (en) * 2013-03-14 2014-09-18 Bhavin Odedara Process detection circuit
CN104378088B (zh) * 2013-08-15 2017-06-09 瑞昱半导体股份有限公司 延迟时间差检测及调整装置与方法
US9503090B2 (en) 2014-08-19 2016-11-22 International Business Machines Corporation High speed level translator

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05199088A (ja) * 1991-02-25 1993-08-06 Toshiba Corp 遅延回路
US5796682A (en) * 1995-10-30 1998-08-18 Motorola, Inc. Method for measuring time and structure therefor
US6166821A (en) * 1998-10-02 2000-12-26 Electronics For Imaging, Inc. Self calibrating pulse width modulator for use in electrostatic printing applications
US7595686B2 (en) 2001-11-09 2009-09-29 The Regents Of The University Of Colorado Digital controller for high-frequency switching power supplies
US7315270B2 (en) 2005-03-04 2008-01-01 The Regents Of The University Of Colorado Differential delay-line analog-to-digital converter
JP2007110686A (ja) * 2005-09-14 2007-04-26 Advantest Corp デジタル回路、半導体デバイス及びクロック調整方法
CN1862273B (zh) * 2006-01-09 2010-04-21 北京大学深圳研究生院 一种测试时钟信号抖动的片上系统
US7750706B1 (en) * 2006-07-21 2010-07-06 Marvell International Ltd. Circuits, architectures, apparatuses, systems, and methods for low voltage clock delay generation
JP4271244B2 (ja) 2007-03-26 2009-06-03 株式会社半導体理工学研究センター アナログ・デジタル（ａｄ）変換器及びアナログ・デジタル変換方法
JP2011169594A (ja) * 2008-06-13 2011-09-01 Advantest Corp マルチストローブ回路およびそのキャリブレーション方法および試験装置
US8228106B2 (en) * 2010-01-29 2012-07-24 Intel Mobile Communications GmbH On-chip self calibrating delay monitoring circuitry
US20130002274A1 (en) * 2010-03-29 2013-01-03 Nec Corporation Aging degradation diagnosis circuit and aging degradation diagnosis method for semiconductor integrated circuit

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