JP2015508982A5 - - Google Patents

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Publication number
JP2015508982A5
JP2015508982A5 JP2014560053A JP2014560053A JP2015508982A5 JP 2015508982 A5 JP2015508982 A5 JP 2015508982A5 JP 2014560053 A JP2014560053 A JP 2014560053A JP 2014560053 A JP2014560053 A JP 2014560053A JP 2015508982 A5 JP2015508982 A5 JP 2015508982A5
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JP
Japan
Prior art keywords
frequency
oscillator
enabled
transmitter
receiver
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Application number
JP2014560053A
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English (en)
Japanese (ja)
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JP2015508982A (ja
JP5951808B2 (ja
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Publication date
Priority claimed from US13/765,992 external-priority patent/US9143085B2/en
Application filed filed Critical
Publication of JP2015508982A publication Critical patent/JP2015508982A/ja
Publication of JP2015508982A5 publication Critical patent/JP2015508982A5/ja
Application granted granted Critical
Publication of JP5951808B2 publication Critical patent/JP5951808B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2014560053A 2012-03-01 2013-02-28 無線装置のための時分割複信モードでの周波数合成器アーキテクチャー Expired - Fee Related JP5951808B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261605285P 2012-03-01 2012-03-01
US61/605,285 2012-03-01
US13/765,992 US9143085B2 (en) 2012-03-01 2013-02-13 Frequency synthesizer architecture in a time-division duplex mode for a wireless device
US13/765,992 2013-02-13
PCT/US2013/028398 WO2013130866A2 (en) 2012-03-01 2013-02-28 Frequency synthesizer architecture in a time-division duplex mode for a wireless device

Publications (3)

Publication Number Publication Date
JP2015508982A JP2015508982A (ja) 2015-03-23
JP2015508982A5 true JP2015508982A5 (enExample) 2015-12-24
JP5951808B2 JP5951808B2 (ja) 2016-07-13

Family

ID=49042789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014560053A Expired - Fee Related JP5951808B2 (ja) 2012-03-01 2013-02-28 無線装置のための時分割複信モードでの周波数合成器アーキテクチャー

Country Status (6)

Country Link
US (1) US9143085B2 (enExample)
EP (1) EP2820765B1 (enExample)
JP (1) JP5951808B2 (enExample)
KR (1) KR101669208B1 (enExample)
CN (1) CN104160631B (enExample)
WO (1) WO2013130866A2 (enExample)

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US20250080097A1 (en) * 2023-08-31 2025-03-06 Samsung Electronics Co., Ltd. Calibrated delay lines for generation of accurate and programmable phase delays between outputs of frequency dividers

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