JP2015507743A5 - - Google Patents

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Publication number
JP2015507743A5
JP2015507743A5 JP2014550289A JP2014550289A JP2015507743A5 JP 2015507743 A5 JP2015507743 A5 JP 2015507743A5 JP 2014550289 A JP2014550289 A JP 2014550289A JP 2014550289 A JP2014550289 A JP 2014550289A JP 2015507743 A5 JP2015507743 A5 JP 2015507743A5
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JP
Japan
Prior art keywords
test
vector
processor
input
data
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Pending
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JP2014550289A
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English (en)
Japanese (ja)
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JP2015507743A (ja
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Priority claimed from US13/338,581 external-priority patent/US8719649B2/en
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Publication of JP2015507743A publication Critical patent/JP2015507743A/ja
Publication of JP2015507743A5 publication Critical patent/JP2015507743A5/ja
Pending legal-status Critical Current

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JP2014550289A 2011-12-28 2012-10-25 Ｊｔａｇシステムの遅延スケジューリングの方法および装置 Pending JP2015507743A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/338,581 US8719649B2 (en) 2009-03-04 2011-12-28 Method and apparatus for deferred scheduling for JTAG systems
US13/338,581 2011-12-28
PCT/US2012/061824 WO2013101336A1 (en) 2011-12-28 2012-10-25 Method and apparatus for deferred scheduling for jtag systems

Publications (2)

Publication Number Publication Date
JP2015507743A JP2015507743A (ja) 2015-03-12
JP2015507743A5 true JP2015507743A5 (cg-RX-API-DMAC10.html) 2016-02-25

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Application Number Title Priority Date Filing Date
JP2014550289A Pending JP2015507743A (ja) 2011-12-28 2012-10-25 Ｊｔａｇシステムの遅延スケジューリングの方法および装置

Country Status (6)

Country Link
US (1) US8719649B2 (cg-RX-API-DMAC10.html)
EP (1) EP2798360A1 (cg-RX-API-DMAC10.html)
JP (1) JP2015507743A (cg-RX-API-DMAC10.html)
KR (1) KR101545109B1 (cg-RX-API-DMAC10.html)
CN (1) CN104185795A (cg-RX-API-DMAC10.html)
WO (1) WO2013101336A1 (cg-RX-API-DMAC10.html)

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US12067091B2 (en) * 2020-12-22 2024-08-20 Synopsys, Inc. Hardware-based obfuscation of digital data
CN113312735B (zh) * 2021-05-19 2022-06-03 太原理工大学 一种城市供水管网dma分区方法
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CN114036885B (zh) * 2021-11-08 2025-09-30 上海兆芯集成电路股份有限公司 内建自测试的方法及互连接口
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