JP2015233089A - Epitaxial wafer for compound semiconductor element and compound semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer for a compound semiconductor element and a compound semiconductor element, which can make electron mobility of a high electron mobility transistor part comparable with at least a stand-alone high electron mobility transistor.SOLUTION: In an epitaxial wafer 100 for a compound semiconductor element in which a high electron mobility transistor structure 300 and a hetero bipolar transistor structure 400 are layered on a substrate 200, the high electron mobility transistor structure 300 has a sub-collector layer 401 having a concentration of an n-type impurity of not less than 1.0×10cmand not more than 3.0×10cm.

Description

  The present invention relates to an epitaxial wafer for a compound semiconductor device, and a compound semiconductor device, in which a high electron mobility transistor (HEMT) structure and a hetero bipolar transistor (HBT) structure are stacked on a substrate. .

  Hetero bipolar transistors are capable of ultra-high speed operation with low distortion, and are mainly used as power amplifiers (PAs) in transmitters such as mobile phones and wireless local area networks (LANs). .

  BiHEMT (or BiFET) is a combination of this heterobipolar transistor and a high electron mobility transistor (see, for example, Patent Document 1), whereby a part of a peripheral circuit of a power amplifier composed of a heterobipolar transistor is integrated. It is possible to reduce the size of the module and shorten the transmission path (reduction of transmission loss), so that it is possible to secure advantages such as improved module characteristics. Become.

  The BiHEMT basically has a multilayer structure in which a high electron mobility transistor structure is formed on a substrate made of a compound semiconductor, and a heterobipolar transistor structure is formed on the high electron mobility transistor structure.

  The reason why the high electron mobility transistor structure is formed on the lower layer side, that is, the substrate side than the heterobipolar transistor structure is that the high electron mobility transistor requires a high-performance high-resistance buffer layer. This is because it is more advantageous to form the high electron mobility transistor structure on the substrate side than the heterobipolar transistor structure.

  In many cases, the heterobipolar transistor structure is formed on the lower layer side than the high electron mobility transistor structure. In this case, however, the high resistance buffer layer essential for the high electron mobility transistor is epitaxially grown to a considerable thickness. Because it is necessary, it is disadvantageous in price compared with the former structure.

  The structure and material of the high electron mobility transistor structure and the heterobipolar transistor structure in BiHEMT are basically the same as the conventional single unit of the high electron mobility transistor and the heterobipolar transistor. The product is only laminated.

  In order to separate the high electron mobility transistor structure from the heterobipolar transistor structure, an isolation layer made of InGaP that is easy to selectively etch, or AlAs that is slightly inferior in selectivity but can be easily epitaxially grown is used. ing.

  High electron mobility transistor structure and heterobipolar transistor structure stacked on the same substrate cannot be used at the same place as high electron mobility transistor part or heterobipolar transistor part at the same time. Excluding etc., it will be used exclusively so that only one of them is used.

  The high electron mobility transistor structure includes at least a buffer layer for preventing current leakage and buffering strain, a first electron supply layer for supplying electrons, a channel layer for traveling electrons, A second electron supply layer for supplying electrons, a Schottky layer for making contact with the Schottky electrode and ensuring a withstand voltage, and a metal that is added (doped) with n-type carriers in a high concentration and becomes an electrode And a contact layer for reducing the contact resistance with the substrate are sequentially laminated on the substrate.

  On the contact layer, a high electron mobility transistor structure and a heterobipolar transistor structure are separated, and an isolation layer made of InGaP or AlAs is formed.

  Further, the heterobipolar transistor structure includes at least a subcollector layer for extracting current to the outside, a collector layer for collecting electrons, a base layer for controlling the flow of electrons, and an emitter for emitting electrons. A layer and an emitter contact layer for injecting current from the outside are sequentially stacked on the separation layer.

  These thin film multilayer structures should be formed by methods such as metal organic vapor phase epitaxy (MOVPE) or metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Can do.

  The metalorganic vapor phase epitaxy method is a method of epitaxially growing a thin film crystal on a substrate by gasifying and supplying a solid or liquid organometallic raw material and performing thermal decomposition or chemical reaction on the substrate that has been heated. The molecular beam growth method is a method in which each constituent element of a thin film crystal is evaporated from a separate crucible in an ultra vacuum and supplied onto a substrate heated in the form of a molecular beam, and a thin film crystal is epitaxially grown thereon. is there.

  However, since the molecular beam growth method requires ultra-vacuum, it is not good at phosphorus-based epitaxial growth with a high vapor pressure. In the case of BiHEMT, the metal organic vapor phase growth method is exclusively employed.

  By these methods, an epitaxial wafer for a compound semiconductor device in which a thin film multilayer structure is epitaxially grown on a substrate is completed, and subsequent pattern formation, etching, electrodes (emitter electrode, base electrode, collector electrode, source electrode, gate electrode, And a drain electrode) formation, protective film formation, packaging, and other processing steps complete a compound semiconductor device using BiHEMT.

  As described above, in the case of a general BiHEMT, the lower half of the compound semiconductor device epitaxial wafer has a high electron mobility transistor structure and the upper half has a heterobipolar transistor structure. Since it cannot be produced in the same place as the heterobipolar transistor part, it is used exclusively.

  Moreover, although this is also common, the area of the heterobipolar transistor part which becomes a power amplifier is large, and the area of the high electron mobility transistor part used for peripheral circuits such as a bias circuit is small.

  An insulating region is formed as necessary. As a method therefor, there are a method in which ions are implanted to increase the resistance, or a trench is dug by etching.

JP 2009-081284 A

  As described above, BiHEMT is expected to improve electrical characteristics by reducing the size of the module and shortening the transmission path, compared to a module manufactured by combining conventional high electron mobility transistors and heterobipolar transistors. .

  However, the high electron mobility transistor portion of BiHEMT has a problem that the electron mobility is deteriorated (decreased) as compared with a single high electron mobility transistor. For example, a multiband type in which a filter needs to be switched depending on a band. In a power amplifier, it cannot be used as a high-performance power switch for switching an output destination, and is limited to use as a control circuit exclusively.

  Accordingly, an object of the present invention is to provide an epitaxial wafer for a compound semiconductor device and a compound semiconductor device capable of making the electron mobility of a high electron mobility transistor portion at least comparable to that of a single high electron mobility transistor. There is.

The present invention devised to achieve this object is an epitaxial wafer for a compound semiconductor device in which a high electron mobility transistor structure and a heterobipolar transistor structure are laminated on a substrate, wherein the high electron mobility transistor structure is , An epitaxial wafer for a compound semiconductor device having a subcollector layer having an n-type impurity concentration of 1.0 × 10 ¹⁸ cm ⁻³ or more and 3.0 × 10 ¹⁸ cm ⁻³ or less.

  The n-type impurity may be any one of Si, S, or Ge.

  Moreover, this invention is the compound semiconductor element produced using the said epitaxial wafer for compound semiconductor elements.

  According to the present invention, it is possible to provide an epitaxial wafer for a compound semiconductor device and a compound semiconductor device capable of making the electron mobility of the high electron mobility transistor portion at least as high as that of a single high electron mobility transistor. it can.

It is the schematic which shows the structure of the epitaxial wafer for compound semiconductor elements which concerns on this invention. It is the schematic which shows the structure of the compound semiconductor element which concerns on this invention. It is a figure which shows the relationship between the density | concentration of the n-type impurity in a subcollector layer, and the electron mobility of a high electron mobility transistor part.

  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

  As shown in FIG. 1, an epitaxial wafer 100 for a compound semiconductor device according to a preferred embodiment of the present invention is formed by laminating a high electron mobility transistor structure 300 and a heterobipolar transistor structure 400 on a substrate 200.

The high electron mobility transistor structure 300 is formed on a substrate 200 made of semi-insulating GaAs and a buffer layer 301 made of undoped GaAs and having a thickness of 500 nm, and an n-type impurity formed on the buffer layer 301. A first electron supply layer 302 having a thickness of 30 nm and made of n-type Al _x Ga _1-x As (x = 0.3) containing Si, and an undoped layer formed on the first electron supply layer 302 A first spacer layer 303 made of type Al _x Ga _1-x As (x = 0.3) and having a thickness of 10 nm, and an undoped In _x Ga _1-x formed on the first spacer layer 303 and as (x = 0.18) channel layer 304 a thickness of 15nm made of, undoped _{Al x Ga 1-x as (} x = 0.3) having a thickness of conjunction is formed on the channel layer 304 A second spacer layer 305 of 0 nm, the n-type _{Al x Ga 1-x As (} x = 0.48) having a thickness of containing Si as n-type impurity while being formed on the second spacer layer 305 A 30-nm second electron supply layer 306 and a Schottky layer formed on the second electron supply layer 306 and made of undoped Al _x Ga _1-x As (x = 0.3) have a thickness of 30 nm And a contact layer 308 formed on the Schottky layer 307 and made of n-type GaAs containing Si as an n-type impurity and having a thickness of 600 nm.

  When the layers constituting the high electron mobility transistor structure 300 are epitaxially grown, a group III source gas, a group V source gas, and a dopant source gas are supplied onto the substrate 200 together with a carrier gas, and the growth temperature is set to 580 ° C. or higher and 750 ° C. It is preferable to perform epitaxial growth in order by metal organic vapor phase epitaxy, with a growth temperature of 6666 Pa or less, a V / III ratio of 10 or more and 300 or less.

The heterobipolar transistor structure 400 is formed on the high electron mobility transistor structure 300 and sandwiches a separation layer 500 made of undoped In _x Ga _x-1 P (x = 0.48) and having a thickness of 10 nm. A sub-collector layer 401 having a thickness of 500 nm and made of n-type GaAs containing Si as an n-type impurity and an n-type impurity formed on the sub-collector layer 401 and containing Si as an n-type impurity. A collector layer 402 made of GaAs having a thickness of 700 nm, a base layer 403 having a thickness of 120 nm made of p-type GaAs containing C as a p-type impurity and formed on the collector layer 402, and formed on the base layer 403. And an n-type In _x Ga _x-1 P (x = 0.48) element containing Si as an n-type impurity and having a thickness of 40 nm The emitter contact layer 405 is formed on the emitter layer 404 and made of n-type GaAs containing Si as an n-type impurity and has a thickness of 100 nm. The emitter contact layer 405 is formed on the emitter contact layer 405 and is n-type. A non-alloy contact layer 406 having a thickness of 100 nm and made of n-type In _x Ga _x-1 As (0 <x <1) containing Si as an impurity.

  Since the isolation layer 500 needs to be epitaxially grown at a temperature lower than that of the contact layer 308 below it, it is preferable to epitaxially grow the isolation layer 500 by providing a temperature interval after the contact layer 308 is epitaxially grown.

Specifically, after the contact layer 308 is epitaxially grown, the temperature is lowered while supplying a carrier gas and arsine (AsH ₃ ), and then the group V source gas is switched from arsine to phosphine (PH ₃ ), and the growth temperature is 550 ° C. Hereinafter, it is preferable that the growth pressure is 6666 Pa, the V / III ratio is 10 or more and 300 or less, and epitaxial growth is performed by metal organic vapor phase epitaxy.

  When the layers constituting the heterobipolar transistor structure 400 are epitaxially grown, the temperature is raised while supplying a carrier gas and phosphine, and then the phosphine is switched to arsine to reduce the electron mobility in the high electron mobility transistor structure 300. In order not to invite, the growth temperature is 400 ° C. or higher and 580 ° C. or lower, which is lower than the growth temperature of the high electron mobility transistor structure 300, the growth pressure is 6666 Pa, the V / III ratio is 1 or higher and 75 or lower. It is preferable to perform epitaxial growth in order.

  The compound semiconductor device epitaxial wafer 100 obtained through these film forming steps is subjected to several processing steps, and as shown in FIG. 2, an emitter electrode 601, a base electrode 602, a collector electrode 603, a source electrode 604, a gate By forming the electrode 605 and the drain electrode 606, the compound semiconductor element 600 including the high electron mobility transistor portion 700 and the heterobipolar transistor portion 800 can be manufactured.

  Note that an insulating region 900 is formed between the high electron mobility transistor portion 700 and the heterobipolar transistor portion 800.

In the epitaxial wafer 100 for a compound semiconductor device according to the present embodiment, the high electron mobility transistor structure 300 has an n-type impurity concentration of 1.0 × 10 ¹⁸ cm ⁻³ or more and 3.0 × 10 ¹⁸ cm ^{−. The} subcollector layer 401 is ³ or less.

  Thereby, when the compound semiconductor element 600 is manufactured using the epitaxial wafer 100 for compound semiconductor elements, the electron mobility of the high electron mobility transistor portion 700 is at least comparable to that of a single high electron mobility transistor. It becomes possible.

On the other hand, when the concentration of the n-type impurity in the subcollector layer 401 is less than 1.0 × 10 ¹⁸ cm ⁻³ , the heterobipolar transistor portion 800 is increased due to an increase in resistance accompanying a decrease in carrier concentration in the subcollector layer 401. This increases the on-resistance and exceeds the practical range. Further, if the concentration of the n-type impurity in the subcollector layer 401 is more than 3.0 × 10 ¹⁸ cm ⁻³ , the electron mobility in the high electron mobility transistor portion 700 is lowered.

That is, by setting the concentration of the n-type impurity in the subcollector layer 401 to 1.0 × 10 ¹⁸ cm ⁻³ or more and 3.0 × 10 ¹⁸ cm ⁻³ or less, if the performance is the same as the conventional one, the improvement in characteristics can be achieved. Since the compound semiconductor element 600 is used for downsizing, it is advantageous in a high-functional portable terminal such as a smart phone that has a large number of functions and therefore must accommodate a large number of devices.

  In the embodiments described so far, the example in which the n-type impurity of the subcollector layer is Si has been described. However, any other group IV element, that is, S or Ge may be used. .

These n-type impurities are difficult to be added at a high concentration of 3.0 × 10 ¹⁸ cm ⁻³ or more, and the concentration is inevitably necessary unless overdoping is performed so as to enter the antisite or the lattice. It is within the range of 1.0 × 10 ¹⁸ cm ⁻³ or more and 3.0 × 10 ¹⁸ cm ⁻³ or less, and the above effect can be achieved.

  On the other hand, group VI elements such as Se and Te have a negative doping characteristic with respect to temperature, so that the concentration can be increased only at a low temperature, and at a high temperature when other layers are epitaxially grown. Since diffusion occurs, it is not practical.

  Hereinafter, the reason for the numerical limitation according to the present invention will be described.

First, by a metal organic chemical vapor deposition method, a buffer layer made of undoped GaAs with a thickness of 500 nm and an n-type Al _x Ga _1-x As containing Si as an n-type impurity are formed on a substrate made of semi-insulating GaAs. A first electron supply layer having a thickness of 30 nm made of (x = 0.3) and a first spacer layer having a thickness of 10 nm made of undoped Al _x Ga _1-x As (x = 0.3) And a channel layer made of undoped In _x Ga _1-x As (x = 0.18) having a thickness of 15 nm and a thickness made of undoped Al _x Ga _1-x As (x = 0.3). A 10 nm second spacer layer; a 30 nm thick second electron supply layer comprising n-type Al _x Ga _1-x As (x = 0.48) containing Si as an n-type impurity; and undoped Al _{x Ga 1-x As (x} = 0.3) having a thickness of the 30nm of shea And Ttoki layer was laminated thickness and 600nm of the contact layer made of n-type GaAs containing Si as n-type impurity, in this order to form a high electron mobility transistor structure.

Next, an n-type separation layer made of undoped In _x Ga _x-1 P (x = 0.48) is sandwiched on the high electron mobility transistor structure by metal organic vapor phase epitaxy. A sub-collector layer with a thickness of 500 nm made of n-type GaAs containing Si as an impurity, a collector layer with a thickness of 700 nm made of n-type GaAs containing Si as an n-type impurity, and a p-type containing carbon as a p-type impurity. A base layer made of GaAs having a thickness of 120 nm, an emitter layer made of n-type In _x Ga _x-1 P (x = 0.48) containing Si as an n-type impurity, and an n-type impurity an emitter contact layer thickness of n-type GaAs is 100nm containing Si, n-type in _x containing Si as n-type impurity _{Ga x-1 as (0 <} x <1) is 100nm thick consisting Non'aro Forming a hetero bipolar transistor structure by laminating a contact layer, in this order.

At this time, the concentration of the n-type impurity in the subcollector layer is 1.0 ×, which is a lower limit value that does not increase the on-resistance of the heterobipolar transistor portion due to an increase in resistance accompanying a decrease in carrier concentration in the subcollector layer. Change from 10 ¹⁸ cm ⁻³ to 2.0 × 10 ¹⁸ cm ⁻³ , 3.0 × 10 ¹⁸ cm ⁻³ , 4.0 × 10 ¹⁸ cm ⁻³ , 5.0 × 10 ¹⁸ cm ^−3. Thus, a plurality of epitaxial wafers for compound semiconductor elements were produced, and the epitaxial wafers for compound semiconductor elements were processed into compound semiconductor elements through several processing steps.

  About these compound semiconductor elements, the electron mobility of the high electron mobility transistor part was measured. The result is shown in FIG.

As can be seen from FIG. 3, when the concentration of the n-type impurity in the subcollector layer exceeds 3.0 × 10 ¹⁸ cm ⁻³ , the decrease in electron mobility in the high electron mobility transistor portion becomes significant.

From the above results, in the present invention, the concentration of the n-type impurity in the subcollector layer is defined to be 1.0 × 10 ¹⁸ cm ⁻³ or more and 3.0 × 10 ¹⁸ cm ⁻³ or less.

100 epitaxial wafer for compound semiconductor device 200 substrate 300 high electron mobility transistor structure 301 buffer layer 302 first electron supply layer 303 first spacer layer 304 channel layer 305 second spacer layer 306 second electron supply layer 307 shot Key layer 308 Contact layer 400 Hetero bipolar transistor structure 401 Sub-collector layer 402 Collector layer 403 Base layer 404 Emitter layer 405 Emitter contact layer 406 Non-alloy contact layer 500 Separation layer 600 Compound semiconductor device 601 Emitter electrode 602 Base electrode 603 Collector electrode 604 Source Electrode 605 Gate electrode 606 Drain electrode 700 High electron mobility transistor portion 800 Hetero bipolar transistor portion 900 Insulating region

Claims (3)

In an epitaxial wafer for compound semiconductor devices in which a high electron mobility transistor structure and a heterobipolar transistor structure are stacked on a substrate,
The high electron mobility transistor structure includes a sub-collector layer having an n-type impurity concentration of 1.0 × 10 ¹⁸ cm ⁻³ or more and 3.0 × 10 ¹⁸ cm ⁻³ or less. Epitaxial wafer for compound semiconductor devices.   The epitaxial wafer for a compound semiconductor device according to claim 1, wherein the n-type impurity is any one of Si, S, and Ge.   A compound semiconductor device produced using the compound semiconductor device epitaxial wafer according to claim 1.

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