JP2015207745A - Print wiring plate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable suppression of warp of a print wiring plate at one side of which a conductor pattern is buried.SOLUTION: A print wiring plate 10 has a first interlayer resin insulating layer 30, a first conductor layer 30 which is buried at the first face F1 side of the first interlayer resin insulating layer 20 and whose uppermost face is exposed, a second conductor layer 50 formed on the second face F2 of the first interlayer resin insulating layer 20, a first via conductor 25a which is provided to penetrate through the first interlayer resin insulating layer 20 and electrically connects the first conductor layer 30 and the second conductor layer 50, a second interlayer resin insulating layer 40 laminated on the first interlayer resin insulating layer 20 and the second conductor layer 50 at the second face F2 side, and a second via conductor 45a which is provided to penetrate through the second interlayer resin insulating layer 40 and a third conductor layer 60 formed on the second interlayer resin insulating layer 40, and filled with metal for electrically connecting the second conductor layer 50 and the third conductor layer 60. The thermal expansion coefficient of the first interlayer resin insulating layer 20 is larger than the thermal expansion coefficient of the second interlayer resin insulating layer 40.

Description

  The present invention relates to a printed wiring board, and more particularly to a printed wiring board in which a part of a conductor wiring layer is embedded in an interlayer resin insulating layer.

  In recent years, the demand for thin electronic devices has increased, and accordingly, wiring boards used in electronic devices are also required to be thinner. Conventionally, a wiring board in which an insulating layer and a conductor layer are sequentially laminated only on one side of a support (carrier) has been proposed as a response to the demand for thinning. According to such a structure, it is not necessary to provide an insulating material (core substrate) having appropriate rigidity at the center in the stacking direction, and the support can be removed in the manufacturing process after use, so that it is thin. A wiring board is formed. For example, in Patent Document 1, a metal layer is attached to one side of a resin film, and after the metal layer is patterned into a predetermined pattern, an insulating sheet is pressure-bonded onto the metal layer, whereby the metal layer is formed. A method of manufacturing a wiring board is disclosed in which the resin film is embedded in an insulating sheet and then the resin film is peeled off from the insulating sheet.

  In Patent Document 2, a conductor pattern is formed on a release layer provided on a copper foil, the conductor pattern is embedded in the vicinity of the surface of the insulating material, and a conductor pattern is also formed on the surface opposite to the insulating material. A wiring board is disclosed in which a copper foil is removed and completed after being formed or after the lamination and patterning of an insulating material and a metal layer are further repeated a predetermined number of times.

Japanese Patent Laid-Open No. 10-173316 JP 2004-318044 A

  Unlike the wiring board formed by laminating a conductor layer and an insulating layer on both sides of the core substrate, the wiring board disclosed in Patent Document 1 and Patent Document 2 has a conductor layer embedded in one side of the insulating layer, Other conductor layers and insulating layers are laminated only on the other side of the insulating layer (hereinafter, the wiring board formed in this way is also simply referred to as a coreless substrate). For this reason, both sides of the wiring board are likely to have an asymmetric structure, and the printed wiring board is likely to be warped. If the printed wiring board is warped, connection failure may occur between the printed wiring board and the electronic component, or connection reliability may be reduced. In the wiring board disclosed in Patent Document 2, warping is suppressed by attaching a reinforcing material to an insulating material. However, when such a reinforcing material is used, the material cost and processing cost of the printed wiring board are reduced. Get higher.

  An object of the present invention is to provide a printed wiring board in which warpage due to a temperature change is suppressed even when a conductor pattern is embedded on one side. And by suppressing such warpage, it is possible to suppress poor connection with electronic components without requiring additional reinforcing materials and processes, and to obtain high connection reliability with electronic components. It is to provide a wiring board.

  The printed wiring board of the present invention is embedded in a first interlayer resin insulation layer having a first surface and a second surface opposite to the first surface, and the first interlayer resin insulation layer on the first surface side. The first conductor layer exposed at the top surface, the second conductor layer formed on the first interlayer resin insulation layer on the second surface side, and the first interlayer resin insulation layer, A first via conductor that electrically connects the first conductor layer and the second conductor layer; a first interlayer resin insulating layer on the second surface side; and a second interlayer laminated on the second conductor layer A resin insulation layer; a third conductor layer formed on the second interlayer resin insulation layer; and the second interlayer resin insulation layer, the second conductor layer and the third conductor layer provided through the second interlayer resin insulation layer. Interlayer resin insulation layers and conductor layers, which are provided with second via conductors filled with electrically connecting metals, are alternately laminated. The thermal expansion coefficient of the first interlayer resin insulation layer is greater than the thermal expansion coefficient of the second interlayer resin insulation layer.

  According to the printed wiring board of the present invention, the imbalance of the action on the warp of the printed wiring board between the expansion and contraction on the first conductor layer side and the expansion and contraction on the second conductor layer side during heating and cooling is alleviated, and the temperature Warpage of the printed wiring board due to changes is suppressed. As a result, connection failures with electronic components are suppressed and connection reliability is increased.

Sectional drawing of one Example of the printed wiring board of one Embodiment of this invention. Sectional drawing which is another Example of the printed wiring board of one Embodiment of this invention, Comprising: The example which changes the weight ratio of an inorganic fiber, without changing the thickness of an interlayer resin insulation layer. Sectional drawing which is another Example of the printed wiring board of one Embodiment of this invention, Comprising: The example which changes the material of the resin component of an interlayer resin insulation layer. Sectional drawing of the printed wiring board of other embodiment of this invention. Explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Explanatory drawing of each process of the manufacturing method of the printed wiring board shown by FIG. Sectional drawing of the printed wiring board by a prior art. Explanatory drawing which shows the state which the curvature has produced in the printed wiring board by the prior art shown by FIG. 6A.

  Next, a printed wiring board according to an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, a printed wiring board 10 according to an embodiment of the present invention (hereinafter, the printed wiring board is also simply referred to as a wiring board) has a first surface F1 and a first surface F1 opposite to the first surface F1. A first interlayer resin insulation layer 20 having two surfaces F2, a first conductor layer 30 embedded in the first interlayer resin insulation layer 20 on the first surface F1 side and exposed at the uppermost surface, and a first interlayer resin. The second conductor layer 50 formed on the second surface F2 of the insulating layer 20 and the second interlayer resin insulation laminated on the second surface F2 and the second conductor layer 50 of the first interlayer resin insulating layer 20 A layer 40 and a third conductor layer 60 formed on the second interlayer resin insulation layer 40 are provided. Further, the wiring board 10 of the present embodiment is provided through the first interlayer resin insulation layer 20, and a first via conductor 25a that electrically connects the first conductor layer 30 and the second conductor layer 50; A second via conductor (45a) is provided to penetrate the second interlayer resin insulation layer (40) and electrically connect the second conductor layer (50) and the third conductor layer (60).

  The wiring board 10 according to the present embodiment is characterized in that the thermal expansion coefficient of the first interlayer resin insulation layer 20 is configured to be larger than the thermal expansion coefficient of the second interlayer resin insulation layer 40. The operation will be described below. FIG. 6A shows a printed wiring board 90 formed in the structure of a conventional coreless substrate. A conductive layer 92b, an insulating layer 91b, and a conductive layer 92c are sequentially stacked on the other side of the insulating layer 91a in which the conductive layer 92a is embedded on one side, and solder is formed on the surfaces of the conductive layers 92a and 92c. Resists 94a and 94b are respectively formed. The insulating layer 91a and the insulating layer 91b are made of the same material made of an insulating resin 912 impregnated with inorganic fibers 911 and inorganic fibers 911 such as glass fibers, respectively, and are formed to have substantially the same thickness. The via conductor 93a connects the conductor layer 92a and the conductor layer 92b, and the via conductor 93b connects the conductor layer 92b and the conductor layer 92c.

  The printed wiring board 90 shown in FIG. 6A is likely to have an asymmetric structure on both sides of the printed wiring board depending on whether or not the conductor layers 92a and 92c are embedded in the insulating layers 91a and 91b. The strain due to heat is also easy to accumulate. For example, as described in detail later, the conductor layer 92a is embedded in the insulating layer 91a, whereas the conductor layer 92c is formed on the surface of the insulating layer 91b. Is formed thicker than the solder resist 94a. Further, a large electronic component (for example, a semiconductor device) is generally connected at a narrow pitch to the exposed surface of a conductor layer embedded in an insulating layer such as the conductor layer 92a. Since the solder resist 94a where the electronic component is mounted is provided with a large opening 95 as shown in FIG. 6A, the area of the solder resist 94a is likely to be smaller than the area of the solder resist 94b. For this reason, the volume of the solder resist 94a tends to be smaller than the volume of the solder resist 94b. Therefore, the thermal expansion or thermal contraction when the printed wiring board 90 is heated or cooled is larger on the conductor layer 92c side than on the conductor layer 92a side, and the expansion / shrinkage on the conductor layer 92c side is printed. This strongly acts on the bending of the wiring board 90. For this reason, for example, when the printed wiring board 90 is heated at the time of mounting an electronic component or the like, as shown in FIG. 6B, a warp that protrudes toward the conductor layer 92c is likely to occur.

  When the printed wiring board 90 is warped, as shown in FIG. 6B, the gap between the electrode 110 of the electronic component 100 mounted on the printed wiring board 90 and the conductor pattern 921 of the conductor layer 92a to which the electrode 110 is connected. Some of them may not come into contact even with a bonding material such as solder 120. Further, when the printed wiring board 90 is cooled, a reverse warp, that is, a convex warp on the conductor layer 92a side occurs, so that a temperature change during use causes a connection between the electronic component 100 and the printed wiring board 90. Stress can occur repeatedly, resulting in poor connection reliability.

  As described above, the wiring board 10 of the present embodiment is configured such that the thermal expansion coefficient of the first interlayer resin insulation layer 20 is larger than the thermal expansion coefficient of the second interlayer resin insulation layer 40, so that the ambient temperature Warpage of the wiring board 10 caused by the change is suppressed. That is, in the wiring board 10 of the present embodiment, as described above, the expansion / contraction on the first conductor layer 30 side is more bent than the expansion / contraction on the third conductor layer 60 side when heated or cooled. Even in the structure that acts strongly, the thermal expansion coefficient of the first interlayer resin insulation layer 20 is larger than the thermal expansion coefficient of the second interlayer resin insulation layer 40, and therefore the first conductor layer 30 side rather than the third conductor layer 60 side. In this case, the amount of expansion / contraction during heating or cooling increases, and the imbalance of the action of the wiring board 10 on the first conductor layer 30 side and the third conductor layer 60 side is alleviated. As a result, warping of the wiring board 10 due to temperature change is suppressed. As a result, connection failure between the wiring board 10 and the electronic component 88 (see FIG. 5H) is suppressed, and connection reliability with the electronic component 88 is increased.

  As shown in FIG. 1, the wiring board 10 of the present embodiment has a surface on the surface of the first pattern 30 a that is a part of the first conductor layer 30 and a side where the first conductor layer 30 is embedded. A first solder resist 35 is formed on a part of the surface of the first interlayer resin insulation layer 20. The second solder resist 55 is formed on the surface of the third conductor layer 60 and on the portion of the surface of the second interlayer resin insulation layer 40 where the third conductor layer 60 is not formed.

  Generally, the solder resist is provided for the purpose of ensuring the insulation of the surface of the conductor layer exposed on the surface of the insulating layer. For this reason, in the wiring board 10 shown in FIG. 1, the first solder resist 35 is on the surface of the first conductor layer 30 and the second solder resist 55 is on the surface of the third conductor layer 60. It is formed to have a thickness. As a result, as shown in FIG. 1, the first solder resist 35 provided on the surface of the first interlayer resin insulation layer 20 in which the first conductor layer 30 is embedded has the third conductor layer 60 on the surface. It is thinner than the second solder resist 55 formed on the surface of the second interlayer resin insulation layer 40 formed thereon. For this reason, when the temperature around the wiring board 10 changes, the expansion / contraction of the second solder resist 55 acts more strongly on the bending of the wiring board 10 than the expansion / contraction of the first solder resist 35. Further, as shown in FIG. 1, in this embodiment, the surface of the second pattern 30b of the first conductor layer 30 and the surface of the first interlayer resin insulation layer 20 around the second pattern 30b are electronic components. Since it corresponds to the mounting area 88 (see FIG. 5H), the first solder resist 35 is not formed. For this reason, when the temperature around the wiring board 10 changes, the second solder resist 55 expands and contracts more than the first solder resist 35. However, in this embodiment, since the thermal expansion coefficient of the first interlayer resin insulation layer 20 is larger than the thermal expansion coefficient of the second interlayer resin insulation layer 40, the first and second solder resists 35 are similar to the above-described relaxation action. , 55 can reduce the imbalance of the action on the warp of the wiring board 10 due to the expansion / contraction of 55, and the difference between the expansion / contraction amounts can be offset. As a result, warping of the wiring board 10 due to temperature change is suppressed. As a result, connection failure between the wiring board 10 and the electronic component 88 (see FIG. 5H) is suppressed, and connection reliability with the electronic component 88 is increased.

  In the present embodiment, the first interlayer resin insulation layer 20 includes inorganic fibers 21 and an insulating resin 22 impregnated in the inorganic fibers 21 as shown in FIG. Similarly, the second interlayer resin insulation layer 40 includes inorganic fibers 41 and an insulating resin 42 impregnated in the inorganic fibers 41. The material of the inorganic fibers 21 and 41 is not particularly limited, but a material having a smaller coefficient of thermal expansion than the insulating resins 22 and 42 is preferable. For example, glass cloth is used. Also, the material of the insulating resins 22 and 42 is not particularly limited. For example, an epoxy resin, a polyester resin, a bismaleimide triazine resin (BT resin), an imide resin (polyimide), a phenol resin, and an allylated phenylene ether resin (A -PPE resin) and the like, and preferably an epoxy resin is used.

  Insulating resins 22 and 42 may be added with a sub-material (not shown) such as a particulate filler in addition to the main material of the resin material as described above. The filler material is selected from, for example, silica, alumina, silicon nitride, and the like, and preferably silica is used. However, the filler material is not limited to these, and other materials may be used. Thus, the thermal expansion coefficient of the 1st and 2nd interlayer resin insulation layers 20 and 40 may be adjusted by adding a filler and adjusting the addition amount.

  The first and second interlayer resin insulation layers 20 and 40 may not include the inorganic fibers 21 and 41.

  In one example of the present embodiment shown in FIG. 1, the amount of the insulating resin 22 included in the first interlayer resin insulating layer 20 is larger than the amount of the insulating resin 42 included in the second interlayer resin insulating layer 40. There have been many. That is, the weight ratio of the inorganic fibers 21 to the entire first interlayer resin insulation layer 20 is made smaller than the weight ratio of the inorganic fibers 41 to the entire second interlayer resin insulation layer 40. As a result, the first interlayer resin insulation layer 20 is thicker than the second interlayer resin insulation layer 40. When the inorganic fibers 21 and 41 are formed of a material having a lower coefficient of thermal expansion than the insulating resins 22 and 42, the weight ratio of the inorganic fibers 21 to the entire first interlayer resin insulating layer 20 is thus the inorganic fibers 41. By making it smaller than the weight ratio of the second interlayer resin insulation layer 40 as a whole, the thermal expansion coefficient of the first interlayer resin insulation layer 20 can be larger than the thermal expansion coefficient of the second interlayer resin insulation layer 40.

  In the example shown in FIG. 1, the inorganic fibers 21 constituting the first interlayer resin insulation layer 20 and the inorganic fibers 41 constituting the second interlayer resin insulation layer 40 may be made of the same material or different materials. It may be configured. Similarly, the insulating resin 22 and the insulating resin 42 may be made of the same material or different materials. For example, even when the insulating resin 22 is made of a material having a smaller coefficient of thermal expansion than the material of the insulating resin 42, the weight ratio of the inorganic fibers 21 to the entire first interlayer resin insulating layer 20 is the first of the inorganic fibers 41. The thermal expansion coefficient of the first interlayer resin insulation layer 20 is made smaller than the weight ratio with respect to the entire two interlayer resin insulation layer 40 so that the thermal expansion coefficient of the first interlayer resin insulation layer 20 is larger than that of the second interlayer resin insulation layer 40. Just do it.

  The amount of the insulating resins 22 and 42 impregnated in the inorganic fibers 21 and 41 is the same as that of the insulating resins 22 and 42 when the first and second interlayer resin insulating layers 20 and 40 are manufactured. It can be adjusted by the time to be immersed in the bath containing the solution. The longer the inorganic fibers 21 and 41 are immersed in the tank in which the solution of the insulating resins 22 and 42 is placed, the more the amount of the insulating resins 22 and 42 impregnated in the inorganic fibers 21 and 41 increases. The method of impregnating the inorganic resins 21 and 41 with the insulating resin 22 and 42 and the method of adjusting the amount of impregnation are not limited to this, and other methods may be used. For example, the impregnation amount may be increased by impregnating the inorganic fibers 21 and 41 with the insulating resins 22 and 42 and then drying them first, and then impregnating the insulating resin one or more times. .

  In order to make the thermal expansion coefficient of the first interlayer resin insulation layer 20 larger than the thermal expansion coefficient of the second interlayer resin insulation layer 40, as described above, the insulating resin simply impregnated in the inorganic fibers 21 and 41 is used. The method of adjusting the amounts of 22 and 42 is preferable in that it is not necessary to prepare various inorganic fibers and insulating resin materials as the constituent materials of the first and second interlayer resin insulating layers 20 and 40. However, the thermal expansion coefficient of the first interlayer resin insulation layer 20 and / or the second interlayer resin insulation layer 40 may be adjusted by using any method without being limited to such a method. Below are some examples.

  FIG. 2 shows a wiring board 10 of another example of the present embodiment. In the wiring board 10 shown in FIG. 2, the inorganic fibers 21 of the first interlayer resin insulation layer 20 are made of the same material as the inorganic fibers 41 of the second interlayer resin insulation layer 40, but in a smaller amount than the inorganic fibers 41. Has been. In the example shown in FIG. 2, the first interlayer resin insulation layer 20 and the second interlayer resin insulation layer 40 are formed to have the same thickness. By doing so, as in the example shown in FIG. 1, the weight ratio of the inorganic fibers 21 to the entire first interlayer resin insulation layer 20 is smaller than the weight ratio of the inorganic fibers 41 to the entire second interlayer resin insulation layer 40. Become. For this reason, when the inorganic fibers 21 and 41 are formed of a material having a lower thermal expansion coefficient than the insulating resins 22 and 42, the thermal expansion coefficient of the first interlayer resin insulating layer 20 is the same as that of the second interlayer resin insulating layer 40. It becomes larger than the thermal expansion coefficient.

  Further, by appropriately adjusting the difference between the amount of the inorganic fibers 21 and the amount of the inorganic fibers 41, the first interlayer resin insulation layer 20 is the same as the second interlayer resin insulation layer 40 as shown in FIG. It can also be made thick. Furthermore, the thermal expansion coefficient of the first interlayer resin insulation layer 20 can be made larger than that of the second interlayer resin insulation layer 40 while the first interlayer resin insulation layer 20 is made thinner than the second interlayer resin insulation layer 40. It is. Needless to say, the first interlayer resin insulation layer 20 may be formed thicker than the second interlayer resin insulation layer 40.

  In the description of another example of the wiring board 10 of the present embodiment shown in FIG. 2, the inorganic fiber 21 of the first interlayer resin insulation layer 20 is the same material as the inorganic fiber 41 of the second interlayer resin insulation layer 40. However, the material constituting the first and second interlayer resin insulation layers 20 and 40 is not limited to such a condition, and any material may be used. For example, even when the inorganic fiber 21 is made of a material having a smaller coefficient of thermal expansion than the material of the inorganic fiber 41, the amount of the inorganic fiber 21 is still smaller than the amount of the inorganic fiber 41, and the first interlayer resin What is necessary is just to be comprised so that the thermal expansion coefficient of the insulating layer 20 may become larger than the thermal expansion coefficient of the 2nd interlayer resin insulation layer 40. FIG.

  FIG. 3 shows a wiring board 10 of still another example of the present embodiment. In the wiring board 10 shown in FIG. 3, the insulating resin 22 a of the first interlayer resin insulating layer 20 is made of a material having a higher coefficient of thermal expansion than the insulating resin 42 a of the second interlayer resin insulating layer 40. For this reason, the thermal expansion coefficient of the first interlayer resin insulation layer 20 can be larger than the thermal expansion coefficient of the second interlayer resin insulation layer 40. In the wiring board 10 shown in FIG. 3, the first interlayer resin insulation layer 20 and the second interlayer resin insulation layer 40 are formed to have the same thickness, but the first interlayer resin insulation layer 20 and the second interlayer resin insulation layer are formed. The layer 40 may be formed to have a different thickness.

  In the example shown in FIG. 3, the insulating resin 22a of the first interlayer resin insulating layer 20 is made of a material having a larger coefficient of thermal expansion than the insulating resin 42a of the second interlayer resin insulating layer 40. In place of or in addition to the insulating resins 22a and 42a, the inorganic fiber 21 of the first interlayer resin insulating layer 20 has a higher thermal expansion coefficient than the material of the inorganic fiber 41 of the second interlayer resin insulating layer 40. It may be constituted by.

  The method for making the coefficient of thermal expansion of the first interlayer resin insulation layer 20 larger than the coefficient of thermal expansion of the second interlayer resin insulation layer 40 is not limited to the method illustrated in FIGS. Can be used.

  The first conductor layer 30 of the wiring board 10 of the present embodiment can be formed from any conductive material. A copper electroplating film formed by electroplating that can form a thick film in a short time is preferable. Similarly, the second and third conductor layers 50 and 60 can be formed of any conductive material. Preferably, the second and third conductor layers 50 and 60 are made of copper, and copper foil, an electroless plating film formed by electroless plating, and an electroplating film formed by electroplating (all shown). 3). However, the second and third conductor layers 50 and 60 are not limited to such a configuration, and may be formed of a single layer or four or more layers, and are formed by a method other than plating, such as a sputtering method. A sputtered film may be included, and a nickel foil or the like may be included.

  In the present embodiment, as shown in FIG. 1, the first and second via conductors 25a and 45a are respectively connected to the conduction holes 25b and 45b provided in the first and second interlayer resin insulation layers 20 and 40, respectively. It is comprised by the metal film formed in an inner surface. In the example shown in FIG. 1, the conduction holes 25b and 45b are completely filled with the metal film. However, the present invention is not limited to this, and the conduction holes 25b and 45b may not be completely filled.

In the present embodiment, as shown in FIG. 1, the first and second via conductors 25a and 45a each have a via diameter that decreases from the third conductor layer 60 side toward the first conductor layer 30 side. For this reason, the size of the cross section of the first and second via conductors 25a, 45a perpendicular to the stacking direction of the wiring board 10 is reduced toward the first surface F1 of the first interlayer resin insulation layer 20. When the wiring board 10 is, for example, a coreless substrate, the conductor layer and the insulating layer are sequentially laminated only on the surface of the first interlayer resin insulation layer 20 opposite to the side where the first conductor layer 30 is embedded, and the third conductor Since the conduction holes 25b and 45b are provided by irradiating, for example, a CO ₂ laser from the side where the layer 60 is formed, the first and second via conductors 25a and 45a have the shapes shown in FIG. It is easy to become. However, the shape of the first and second via conductors 25a and 45a is not limited to this, and may be the same size on the first conductor layer 30 side and the third conductor layer 60 side, for example. The diameter may be increased from the three conductor layer 60 side toward the first conductor layer 30 side.

  In the present embodiment, as shown in FIG. 1, the surface of the third conductor layer 60 is covered with the second solder resist 55 except for the portion on the second via conductor 45a. However, the present invention is not limited to this, and a larger portion of the third conductor layer 60 may be exposed without being covered with the second solder resist 55. Similarly, not only the second pattern 30 b but also the surface of all the first conductor layers 30 including the first pattern 30 a may be exposed from the first solder resist 35 on the first conductor layer 30 side.

The materials of the first and second solder resists 35 and 55 are not particularly limited as long as they have good solder heat resistance and insulating properties, but are preferably formed of an epoxy resin or an acrylic resin. It is formed of a material containing 40 to 70% by weight of an inorganic filler such as SiO ₂ . Note that the first solder resist 35 and the second solder resist 55 may be formed of different materials.

  Next, a printed wiring board according to another embodiment of the present invention will be described with reference to FIG. The same components as those of the embodiment of the present invention described above are denoted by the same reference numerals as those shown in FIG. 1, and detailed description thereof is omitted. As shown in FIG. 4, the printed wiring board 11 according to another embodiment of the present invention includes a third interlayer resin insulation layer 70 and a fourth interlayer resin layer 50 between the second conductor layer 50 and the second interlayer resin insulation layer 40. It differs from the wiring board 10 of one embodiment shown in FIG. 1 described above in that the conductor layer 75 is provided. In the wiring board 11 of the present embodiment, the first conductor layer 30 and the third conductor layer 60 are electrically connected to each other through the third interlayer resin insulation layer 70 in cooperation with the first and second via conductors 25a and 45a. A third via conductor 78 is also provided for connection.

  The other part of the wiring board 11 of this embodiment is comprised similarly to the wiring board 10 of one above-mentioned embodiment. That is, also in the wiring board 11 of this embodiment, the first interlayer resin insulation layer 20 is configured to have a higher thermal expansion coefficient than the second interlayer resin insulation layer 40. Therefore, similarly to the wiring board 10 of one embodiment, the imbalance of the action with respect to the warp of the wiring board 11 on the first conductor layer 30 side and the third conductor layer 60 side when the ambient temperature changes is alleviated. As a result, warping of the wiring board 11 due to temperature change is suppressed. As a result, connection failure between the wiring board 11 and the electronic component 88 (see FIG. 5H) is suppressed, and connection reliability with the electronic component 88 is increased.

  As a method for adjusting the coefficient of thermal expansion of the first and second interlayer resin insulation layers 20 and 40 of the wiring board 11 of the present embodiment, any method can be used as in the above-described one example. That is, as shown in FIGS. 1 to 3, the impregnation amount of the insulating resins 22 and 42 into the inorganic fibers 21 and 41 may be adjusted, and the amount of the inorganic fibers 21 and 41 may be adjusted. Alternatively, the inorganic fibers 21 and the inorganic fibers 41 may be formed of materials having different coefficients of thermal expansion, and / or the insulating resin 22 and the insulating resin 42 may be formed of materials having different coefficients of thermal expansion. Good. Therefore, even if the thickness of the 1st interlayer resin insulation layer 20 and the thickness of the 2nd interlayer resin insulation layer 40 are the same, either one may be thicker than the other.

  The coefficient of thermal expansion and thickness of the third interlayer resin insulation layer 70 and the constituent materials such as the inorganic fibers 71 and the insulating resin 72 are not particularly limited. In short, the warpage of the wiring board 11 due to the change in ambient temperature is suppressed by making the thermal expansion coefficient of the first interlayer resin insulation layer 20 larger than the thermal expansion coefficient of the second interlayer resin insulation layer 40. I just need it. However, the difference between the coefficient of thermal expansion of the first interlayer resin insulation layer 20 and the coefficient of thermal expansion of the second interlayer resin insulation layer 40 can effectively contribute to the suppression of the warp of the wiring board 11, so that the third interlayer resin The thermal expansion coefficient of the resin insulating layer 70 is preferably a magnitude between the thermal expansion coefficient of the first interlayer resin insulating layer 20 and the thermal expansion coefficient of the second interlayer resin insulating layer 40. The material of the fourth conductor layer 75 can be formed by the same material and method as those of the second and third conductor layers 50 and 60.

  In FIG. 4, the third interlayer resin insulation layer 70 and the fourth conductor layer 75 are sequentially laminated between the second conductor layer 50 and the second interlayer resin insulation layer 40 from the second conductor layer 50 side. It is shown as However, the third interlayer resin insulation layer 70 and the fourth conductor layer 75 are arranged between the first interlayer resin insulation layer 20 and the second conductor layer 50 from the first interlayer resin insulation layer 20 side to the fourth conductor layer 75, Next, the third interlayer resin insulation layer 70 may be laminated in this order. Further, in addition to the third interlayer resin insulation layer 70 and the fourth conductor layer 75, one set or a plurality of sets of interlayer resin insulation layers and conductor layers are formed as the second conductor layer 50 and the second interlayer resin insulation layer. 40 and / or between the first interlayer resin insulation layer 20 and the second conductor layer 50.

  Next, a method for manufacturing the wiring board 10 according to an embodiment of the present invention will be described with reference to FIGS. 5A to 5H, in order to facilitate understanding of the manufacturing process of the wiring board 10, the manufacturing of the wiring board 10 is performed in the direction rotated by 180 ° with the rotation axis in the direction perpendicular to the drawing from the direction shown in FIG. 1. The state during the process is shown.

  In the method of manufacturing the wiring board 10 of one embodiment, first, as shown in FIG. 5A, a carrier 80 and a first metal foil 81 with a carrier copper foil 80a are prepared as starting materials. The first metal foil 81 with the carrier copper foil 80a is laminated with the carrier copper foil 80a side facing the carrier 80 side, and is joined by being pressurized and heated. The carrier 80 is preferably made of a semi-cured prepreg material made of a material in which a core material such as glass fiber is impregnated with an insulating resin such as epoxy, but is not limited thereto. May be used. Although the material of the 1st metal foil 81 will not be specifically limited if the below-mentioned 1st conductor layer 30 (refer FIG. 5B) can be formed on the surface, Preferably copper foil or nickel foil is used. The first metal foil 81 is, for example, a metal foil having a thickness of 2 to 6 μm, preferably 5 μm. The carrier copper foil 80a is, for example, a copper foil having a thickness of 15 to 30 μm, preferably 18 μm. However, the thickness of the 1st metal foil 81 and the carrier copper foil 80a is not limited to these, You may be made into other thickness.

  The carrier copper foil 80a and the first metal foil 81 are bonded to each other by, for example, a thermoplastic adhesive (not shown) on substantially the entire attachment surface. However, the carrier copper foil 80a and the first metal foil 81 are not limited to this, and the adhesive or It may be joined by ultrasonic connection.

  In the example shown in FIG. 5A, an example is shown in which the first metal foil 81 to which the carrier copper foil 80a has already been bonded is bonded to the carrier 80 made of a single prepreg material, but is limited to such a configuration. Instead, for example, a double-sided copper clad laminate may be used for the carrier 80, and the single first metal foil 81 may be bonded to each of the copper foils bonded to both surfaces with an adhesive or the like.

  5A to 5D show an example of a manufacturing method in which the first metal foil 81 is bonded to both sides of the carrier 80 and the wiring board 10 is formed on each side. If the wiring boards 10 are formed on both sides of the carrier 80 as described above, it is preferable in that two wiring boards 10 are manufactured at a time. However, the wiring board 10 may be formed only on one surface of the carrier 80, or wiring boards having different circuit patterns may be formed on both sides. Since the following description about the manufacturing method of the wiring board 10 is demonstrated with reference to FIG. 5A-5F by which the example in which the same circuit pattern is formed in both surfaces is shown, only one surface is demonstrated and the other surface side And the reference numerals on the other side in each drawing are omitted.

  Next, as shown in FIG. 5B, the first conductor layer 30 is formed on the first metal foil 81. Although the formation method of the 1st conductor layer 30 is not specifically limited, For example, an electroplating method is used. Specifically, first, a plating resist film (not shown) is formed on a predetermined region other than a portion where first and second patterns 30a and 30b (see FIG. 5H) described later are formed on the first metal foil 81. Is formed. Subsequently, an electroplating film is formed on the first metal foil 81 on which the plating resist film is not formed, for example, by electroplating using the first metal foil 81 as a seed layer. Thereafter, the plating resist film is removed. As a result, the first conductor layer 30 is formed on the first metal foil 81 as shown in FIG. 5B. The first conductor layer 30 is preferably an electroplated film made of copper.

  Next, as shown in FIG. 5C, a semi-cured first interlayer resin insulation layer 20 is laminated on the first metal foil 81 and the first conductor layer 30, and further on the first interlayer resin insulation layer 20. A second metal foil 501 is laminated on the substrate. Thereafter, the second metal foil 501 and the first interlayer resin insulation layer 20 are pressed toward the carrier 80 side and further heated. As a result, the first interlayer resin insulation layer 20 is completely cured, and simultaneously joined to the first metal foil 81, the first conductor layer 30, and the second metal foil 501. In FIG. 5C, the first interlayer resin insulation layer 20 is composed of inorganic fibers 21 and an insulating resin 22, but the first interlayer resin insulation layer 20 does not include the inorganic fibers 21 and is an insulating resin. 22 may be comprised.

Next, as shown in FIG. 5D, a conduction hole 25 b that penetrates through the second metal foil 501 and the first interlayer resin insulation layer 20 and exposes the first conductor layer 30 is formed. Specifically, laser light is irradiated from a surface side of the second metal foil 501 to a predetermined position on the second metal foil 501 using a CO ₂ laser. As a result, a conduction hole 25b is formed as shown in FIG. 5D. After the formation of the conduction hole 25b, desmearing is preferably performed on the conduction hole 25b. Further, the surface of the second metal foil 501 may be blackened before the laser light irradiation so that the absorption efficiency of the laser light is increased.

  Next, as shown in FIG. 5E, a first metal film 502 is formed on the second metal foil 501 and in the conduction hole 25b. The first metal film 502 is preferably formed by electroless plating. When formed by electroless plating, the first metal film 502 is preferably formed to a thickness of 0.3 to 1 μm. In another preferred example, the first metal film 502 is formed by a sputtering method. When formed by sputtering, the first metal film 502 is preferably formed to a thickness of 0.05 to 0.2 μm. The material of the first metal film 502 is not particularly limited, but is preferably made of copper. However, the method and material for forming the first metal film 502 are not limited to these, and other methods and materials may be used.

  Subsequently, a second metal film 503 is formed on the first metal film 502. The method for forming the second metal film 503 is not particularly limited, but it is preferably formed by electroplating in that a thick film can be formed in a short time. When formed by electroplating, first, a plating resist film 82 is formed on the first metal film 502. The plating resist film 82 is formed on the first metal film 502 in a region excluding at least the conductive hole 25b and a portion where the predetermined pattern of the second conductor layer 50 (see FIG. 5F) is provided. Subsequently, a second metal film 503 is formed on the first metal film 502 not covered with the plating resist film 82 by electroplating. As a result, as shown in FIG. 5E, the conduction hole 25b is filled with the second metal film 503, and the first via conductor 25a composed of the first and second metal films 502 and 503 is formed.

  Next, a part of the first metal film 502 and the second metal foil 501 covered with the plating resist film 82 is removed. Specifically, first, the plating resist film 82 is peeled off. Subsequently, the first metal film 502 exposed by peeling the plating resist film 82 and the second metal foil 501 below the first metal film 502 are removed. As a result, as shown in FIG. 5F, the second metal foil 501, the first metal film 502, and the second metal film are formed on the surface of the first interlayer resin insulation layer 20 on the side where the first conductor layer 30 is not embedded. A second conductor layer 50 having a pattern 50a made of 503 is formed.

  Next, as shown in FIG. 5G, a second interlayer resin insulation layer 40 and a third conductor layer 60 are sequentially formed on the second conductor layer 50 and the first interlayer resin insulation layer 20, and the second A via conductor 45 a is formed in the second interlayer resin insulation layer 40. The second interlayer resin insulation layer 40, the third conductor layer 60, and the second via conductor 45a repeat the steps shown in FIGS. 5C to 5F, thereby repeating the first interlayer resin insulation layer 20, the second conductor layer 50, and the second via conductor 45a. Each may be formed in the same manner as the one via conductor 25a.

  Subsequently, the carrier 80, the carrier copper foil 80a, and the first metal foil 81 are removed. Specifically, first, for example, in the state where the wiring board 10 in the intermediate process is heated and the thermoplastic adhesive (not shown) that joins the carrier copper foil 80a and the first metal foil 81 is softened. Are separated. Alternatively, as described above, when both are bonded by an adhesive or ultrasonic connection in the blank portion near the outer periphery, the carrier copper foil 80a, the first metal foil 81, and The carrier copper foil 80a and the carrier 80 and the first metal foil 81 may be separated by cutting the carrier 80 together with the first interlayer resin insulation layer 20 and the like and cutting the joint portion. Thereafter, first metal foil 81 is removed by, for example, etching.

  5C to 5F are repeated one or more times to obtain three or more interlayer resin insulation layers and four like the wiring board 11 of the other embodiment shown in FIG. A wiring board having the above conductor layers and via conductors penetrating each interlayer resin insulating layer can be formed.

  Next, as shown in FIG. 5H, on the surface of a part of the first conductor layer 30 and on the part of the surface of the first interlayer resin insulation layer 20 on the first conductor layer 30 side, A solder resist 35 is formed. The second solder resist 55 is formed on the surface of the third conductor layer 60 and on the portion of the surface of the second interlayer resin insulation layer 40 where the third conductor layer 60 is not formed. In FIG. 5H, the in-process product of the wiring board 10 shown in FIG. 5G is rotated by 180 ° about the axis perpendicular to the drawing so as to be consistent with FIG. 1 showing the completed state. A plate 10 is shown.

  The first and second solder resists 35 and 55 are, for example, a layer made of a photosensitive epoxy material or the like on the entire surface of the first interlayer resin insulation layer 20 on the first conductor layer 30 side, and the second interlayer resin insulation layer 40. After being formed on the entire surface on the third conductor layer 60 side, a layer made of an epoxy material or the like at an upper portion of a predetermined portion where the first and second solder resists 35 and 55 are provided is exposed, and an unexposed portion of the epoxy material It is formed by being removed by development. However, the present invention is not limited to this, and the first and second solder resists 35 and 55 may be screen printing or the like using a mask having an opening corresponding to a portion where the first and second solder resists 35 and 55 are provided. It may be provided by the method. Further, the first and second solder resists 35 and 55 are, for example, a layer made of a non-photosensitive epoxy material or the like on the entire surface of the first interlayer resin insulating layer 20 on the first conductor layer 30 side and the second interlayer resin. After being formed on the entire surface of the insulating layer 40 on the third conductor layer 60 side, a portion that does not require the formation of a solder resist may be removed by laser.

  As shown in FIG. 5H, among the patterns formed on the first conductor layer 30, the second pattern 30 b to which the electrodes of the electronic component 88 mounted on the wiring board 10 are connected covers the first solder resist 35. Instead, it is exposed in the opening formed in the first solder resist 35. On the other hand, the surface of the third conductor layer 60 is covered with the second solder resist 55 except for the portion on the second via conductor 45a. However, the pattern of the first conductor layer 30 other than the second pattern 30b, for example, the first pattern 30a and the surface of the first interlayer resin insulation layer 20 around the first pattern 30a are covered with the first solder resist 35. It may be exposed without. Further, a larger portion of the surface of the third conductor layer 60 may be exposed without being covered with the second solder resist 55.

  Further, the surface of the first and third conductor layers 30 and 60 exposed without being covered with the solder resist 35 and the second solder resist 55 is made of, for example, Ni / Au, Ni / Pd / Au, or Sn. A corrosion resistant layer (not shown) may be formed. Further, a corrosion-resistant layer made of an organic protective film (OSP) may be formed by immersion in a liquid protective material or spraying of the protective material, or a solder coat layer (not shown) may be formed. Good.

  The wiring board 10 of one embodiment shown in FIG. 1 is completed through the steps shown in FIGS. 5A to 5H. As shown in FIG. 5H, for example, even if the electronic component 88 is mounted on the first conductor layer 30 embedded on the first surface F1 side of the first interlayer resin insulation layer 20 in the completed wiring board 10. Good.

  The manufacturing method of the wiring board 10 of one embodiment is not limited to the method described with reference to FIGS. 5A to 5H, and the conditions, order, and the like can be arbitrarily changed. Moreover, a specific process may be abbreviate | omitted and another process may be added.

10, 11 Printed wiring board 20 First interlayer resin insulation layer 21 Inorganic fibers 22, 22a Insulating resin 25a First via conductor 30 First conductor layer 30a First pattern 30b Second pattern 35 First solder resist 40 Second interlayer resin Insulating layer 41 Inorganic fiber 42, 42a Insulating resin 45a Second via conductor 50 Second conductor layer 55 Second solder resist 60 Third conductor layer 70 Third interlayer resin insulating layer 75 Fourth conductor layer F1 First interlayer resin insulating layer First surface F2 of the second surface of the first interlayer resin insulation layer

Claims (7)

A first interlayer resin insulation layer having a first surface and a second surface opposite to the first surface;
A first conductor layer embedded in the first interlayer resin insulation layer on the first surface side and having the uppermost surface exposed;
A second conductor layer formed on the first interlayer resin insulation layer on the second surface side;
A first via conductor provided through the first interlayer resin insulation layer and electrically connecting the first conductor layer and the second conductor layer;
A second interlayer resin insulation layer laminated on the first interlayer resin insulation layer on the second surface side and the second conductor layer;
A third conductor layer formed on the second interlayer resin insulation layer;
A second via conductor that is provided through the second interlayer resin insulation layer and is filled with a metal that electrically connects the second conductor layer and the third conductor layer;
A printed wiring board comprising an interlayer resin insulation layer and a conductor layer alternately laminated,
The thermal expansion coefficient of the first interlayer resin insulation layer is greater than the thermal expansion coefficient of the second interlayer resin insulation layer. The printed wiring board according to claim 1,
The thickness of the first interlayer resin insulation layer is greater than the thickness of the second interlayer resin insulation layer. The printed wiring board according to claim 1 or 2,
The first and second interlayer resin insulation layers include at least inorganic fibers and a resin impregnated in the inorganic fibers,
The weight ratio of the inorganic fibers contained in the first interlayer resin insulation layer to the whole first interlayer resin insulation layer is the weight ratio of the inorganic fibers contained in the second interlayer resin insulation layer to the whole second interlayer resin insulation layer. Less than weight ratio. The printed wiring board according to claim 1, further comprising:
A first solder resist formed on the first conductor layer and the first interlayer resin insulation layer; and a second solder resist formed on the third conductor layer and the third interlayer resin insulation layer. And the thickness of the first solder resist is smaller than the thickness of the second solder resist. The printed wiring board according to claim 4,
The first and second solder resists are formed by containing 40 to 70% by weight of an inorganic filler in an epoxy resin. The printed wiring board according to any one of claims 1 to 5,
The cross-sectional size of the first and second via conductors decreases toward the first surface of the first interlayer resin insulation layer. The printed wiring board according to any one of claims 1 to 6,
An electronic component is mounted on the first surface side of the first interlayer resin insulation layer.

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