JP2015204869A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent fraudulent conduct of replacing a sub ROM by making it not easy to detect measures against fraudulence.SOLUTION: The game machine includes: a main control board 50 for controlling the progress of a game, a first sub control board 80 for performing AT lotteries, and a second sub control board 90 for controlling the output of presentations. The first sub control board 80 stores presentation data and sends the presentation data to the second sub control board 90 as authentication data. The second sub control board 90 stores in advance an offset value and control information corresponding to the offset value that can be calculated form the authentication data sent from the first sub control board 80, receives the authentication data from the first sub control board 80, calculates the offset value and control information corresponding to the offset value on the basis of the authentication data, determines whether or not the offset value is correct, and performs abnormality detection processing upon a necessary condition that the offset value is determined as not correct.

Description

  The present invention relates to a gaming machine such as a slot machine, and more particularly to a technique for preventing a so-called sub ROM exchange goto action.

Among conventional gaming machines, for example, a slot machine includes a main (main) control board and a sub (sub) control board, both of which are electrically connected by a harness or the like, from the main control board to the sub control board. Sending information.
The main control board performs lottery drawing, reel stop control, and the like, and the sub-control board performs effect control and further AT (assist time) lottery.

  Here, the AT winning probability greatly affects the appearance of the slot machine. Therefore, it is necessary to prevent a go-to action for illegally replacing the ROM (referred to as “sub-ROM”) of the sub-control board, that is, unauthorized alteration of programs and data related to AT lottery.

In the prior art, a technique is known in which a gate device is provided in a harness or a terminal portion that connects a main control board and a sub control board, and this gate device is controlled by a sub ROM exchange detection device (for example, Patent Document 1). reference).
In the technique of Patent Document 1, the sub ROM exchange detection device stores the contents of the sub ROM of the sub control board in advance. Then, the sub ROM and the sub ROM data stored in the gate device are collated, and if the result of the collation is illegal, control is performed so that no signal is transmitted from the main control board to the sub control board. It is.

JP 2005-287911 A

However, in the above-described conventional technology, when a new gate device that is not found in a conventional gaming machine is provided between the main control board and the sub control board, a fraud countermeasure device is attached at first glance from the appearance. There is a problem that it will be understood.
Further, if a gate device is provided separately, the number of parts increases accordingly, and there is a problem that the cost increases.
The problem to be solved by the present invention is to prevent a sub ROM replacement goat action while preventing an anti-fraud measure from being easily seen from the appearance.

The present invention solves the above problems by the following means.
The present invention
Main control means for controlling the progress of the game;
Sub-control means for receiving information from the main control means and controlling effects based on the received information,
The sub-control means includes
First sub-control means for performing a predetermined lottery regarding the output of the production;
Second sub-control means for controlling the output of the performance,
The first sub-control means stores production data,
The first sub control means transmits at least a part of the effect data as authentication data to the second sub control means,
The second sub-control unit stores in advance an offset value that can be calculated from the authentication data transmitted from the first sub-control unit and control information corresponding to the offset value,
The second sub-control unit receives the authentication data transmitted from the first sub-control unit, calculates an offset value and control information corresponding to the offset value based on the authentication data, and the offset value is It is characterized by determining whether or not it is correct and executing a predetermined abnormality detection process on the condition that it is determined that the offset value is not correct.

  According to the present invention, the correct offset value and the control information corresponding to the offset value are stored in the second sub-control unit even if the sub-ROM exchange goto action on the first sub-control unit side is performed. If the received authentication data is calculated and collated, data match / mismatch can be found. Thereby, abnormality detection processing can be performed.

It is a block diagram which shows the outline of control of the slot machine (game machine) in this embodiment. It is a figure explaining the memory content of the memory of a 1st sub control board, and creation of the authentication data to transmit. It is a figure which shows the authentication data transmitted from a 1st sub control board. It is a figure explaining the calculation to an offset value and control data from the authentication data received from the 1st sub control board. It is a figure explaining the memory content of the memory of the 2nd sub control board. It is a figure which shows a vector table. It is a flowchart which shows the main loop of a 1st sub control board. It is a flowchart which shows an interruption process. It is a flowchart which shows the data transmission from a 1st sub control board to a 2nd sub control board. It is a flowchart which shows the abnormality detection process in a 2nd sub control board. It is a flowchart which shows the checksum process by the side of the 1st sub control board.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an outline of control of the slot machine 10 (game machine) in the present embodiment. The slot machine 10 includes a main control board 50 and sub control boards (first sub control board 80 and second sub control board 90).
The main control board 50 includes an input port 51, an output port 52, a memory 53, a main CPU 54, and the like (it does not mean that only the components illustrated in FIG. 1 are included).

  The main control board 50 and a peripheral device for game progress such as the operation switch illustrated in FIG. 1 are electrically connected via an input port 51 or an output port 52. The input port 51 is a connection unit to which signals such as operation switches are input, and the output port 52 is a connection unit that transmits signals to peripheral devices such as the motor 32.

  In FIG. 1, the peripheral device for input is indicated by an arrow from the peripheral device toward the main control board 50, and the peripheral device for output is the main control board 50 (second sub-control board). 90 is the same as that shown in FIG.

  A memory (main memory) 53 temporarily stores a ROM (main ROM) for storing programs necessary for the progress of the game, various data, and the like, and data captured when the main CPU 54 performs various controls. It consists of RWM (Read Write Memory) to be stored. Further, a register provided in the main CPU 54 is also included in the memory 53.

  The main CPU 54 refers to a CPU provided on the main control board 50, and executes programs and calculations necessary for the progress of the game. Specifically, the lottery of the role, the drive control of the reel 31, and the winning Execute paying out.

  The sub control board includes a first sub control board 80 and a second sub control board 90 in the present embodiment. The sub-control board controls selection or output of effects (information) during the game and during the game standby.

The first sub control board 80 and the second sub control board 90 are control boards belonging to the lower level of the main control board 50. The main control board 50 and the first sub control board 80 are electrically connected, and the serial communication circuit in the main CPU 54 of the main control board 50 produces a one-way effect on the first sub control board 80. Necessary information (signal, data, control command, etc.) is transmitted.
The main control board 50 and the first sub control board 80 are not limited to being electrically connected but may be connected using optical communication means. Furthermore, both the electrical connection and the optical communication connection are not limited to serial communication, and may be parallel communication.

  Information transmitted from the main control board 50 to the first sub control board 80 includes, for example, information that a medal has been inserted (betted or stored), information that the start switch 41 has been operated, and a lottery result of a combination (Winning role) information, information indicating that the rotation of the reel 31 has started, information indicating that the stop switch 42 has been operated, information indicating that the reel 31 has been stopped, and the stop position (stop symbol) of each reel 31 Information, winning combination information, medal payout information (including automatic betting by replay winning), gaming state information, freeze information, and the like.

Further, the first sub control board 80 and the second sub control board 90 include a first sub CPU 84 provided in the first sub control board 80 and a second sub CPU 94 provided in the second sub control board 90. Two-way communication is performed by serial communication circuits provided respectively. That is, necessary information is transmitted from the first sub-control board 80 to the second sub-control board 90, and the second sub-control board 90 transmits necessary information to the first sub-control board 80.
Note that the connection between the first sub-control board 80 and the second sub-control board 90 is not limited to electrical connection, and may be optical communication connection as described above. Furthermore, both the electrical connection and the optical communication connection are not limited to serial communication, and may be parallel communication.

  In the example of FIG. 1, the peripheral device connected to the first sub control board 80 is not shown, but the production peripheral device connected to the first sub control board 80 is the input port 81 or the output port 82. It is electrically connected via. Similarly to the main control board 50, the first sub control board 80 includes a memory 83 and a first sub CPU 84.

A memory (sub-main memory) 83 is a ROM (sub-main ROM) for storing programs and various data when performing an AT (including sub-bonus) lottery as performance data, and the first sub CPU 84 It consists of a register provided in the RWM and the first sub CPU 84 for temporarily storing data and the like taken in when the production is controlled.
The first sub CPU 84 includes AT lottery means 85. The AT lottery means 85 executes a lottery concerning AT (subbonus) or the like based on the number of games, winning combination and the like according to a predetermined program.
Further, the first sub CPU 84 includes authentication data transmission means 86, and transmits authentication data to the second sub control board 90 at a predetermined timing, as will be described later.

The second sub control board 90 is a control board belonging to a lower level than the first sub control board 80. The first sub control board 80 may be referred to as a sub main board, and the second sub control board 90 may be referred to as a sub sub control board.
Similarly to the first sub control board 80, the second sub control board 90 includes a memory 93 and a second sub CPU 94. A memory (sub-sub memory) 93 is a ROM (sub-sub ROM) for storing effect data (effect patterns, etc.) output from the effect lamp 21, the speaker 22, and the image display device 23, and the second sub CPU 94 is used for various effects. Is composed of an RWM that temporarily stores data and the like that are fetched when outputting and a register provided in the second sub CPU 94.
The second sub CPU 84 determines and executes an effect according to a predetermined program.

In FIG. 1, a medal slot 43 is a part where a player actually inserts (cares) a medal. The medal inserted from the medal insertion slot 43 passes through the passage sensor 43a and the blocker 45 and is detected by the insertion sensor 44.
The insertion sensor 44 is composed of, for example, a pair of optical sensors, and determines whether or not the medal has passed correctly based on the on / off timing of the pair of optical sensors.

  The passage sensor 43a is a sensor that detects whether or not the inserted medal is a regular one, and determines whether to accept the inserted medal based on the detection result of the passage sensor 43a. When accepting the inserted medal, the medal is guided to the insertion sensor 44 side through the blocker 45. On the other hand, when the inserted medal is not accepted, the blocker 45 is driven to return the inserted medal from the payout port.

Further, as shown in FIG. 1, the main control board 50 includes a bet switch 40, a start switch 41, a (left, middle, right) stop switch 42, and a checkout switch 46 as operation switches operated by the player. It is connected to the.
The bet switch 40 is a switch operated by the player when betting a stored medal for the game.

The start switch 41 is a switch operated by the player when starting the reels 31 (all of left, middle and right).
Furthermore, three stop switches 42 are provided corresponding to the three (left, middle, and right) reels 31 and are operated by the player when the corresponding reels 31 are stopped.
Further, the settlement switch 46 is a switch operated by the player when paying out the bet medals at the end of the game.

The main CPU 54 of the main control means 50 includes setting change means 60 for changing / determining the set value.
Here, the set value determines the degree of the appearance (medal that can be acquired) (the player's advantage), and in this embodiment, there are six stages of setting 1 to setting 6.
Then, the higher the set value is, the higher the winning probability of the combination (particularly the special combination) is set, and the higher the advantage for the player is set.
Further, the higher the set value is, the higher the probability of shifting to the AT and the higher the advantage for the player.

In addition, instead of increasing the probability of shifting to the AT, or increasing the probability of shifting to the AT, for example, increasing the probability of adding the number of games or payouts during the AT, or the probability of continuing the AT May be high.
Further, the higher the set value is, the higher the expected value of the payout number with respect to the number of inserted medals may be.

  To set / change the set value, a power switch and a set key (not shown) are used. When the set value is confirmed, the main control board 50 stores the set value in a predetermined storage area of the memory 53. Further, the setting value information is transmitted from the main control board 50 to the first sub-control board 80 and stored in a predetermined storage area in the memory 83. The first sub control board 80 also shares the same set value as the set value stored in the memory 53 of the main control board 50. Then, a set value is also set on the first sub-control board 80 side, and AT lottery or the like is executed with a probability corresponding to the set value.

A motor 32 of the symbol display device 30 and the like are electrically connected to the output port 52 of the main control board 50.
The symbol display device 30 includes a reel 31 (three in this embodiment) that displays symbols, a motor 32 that drives each reel 31, and the like.
The motor 32 is for rotating the reels 31, is connected to the center of rotation of each reel 31, and is controlled by a reel control means 62 described later. Here, the reel 31 includes a left reel 31, a middle reel 31, and a right reel 31, and a stop switch 42 that is operated when the left reel 31 is stopped is the left stop switch 42, and when the middle reel 31 is stopped. The stop switch 42 to be operated is the middle stop switch 42, and the stop switch 42 to be operated when stopping the right reel 31 is the right stop switch 42.

  The reel 31 is ring-shaped, and a reel tape on which a plurality of types of symbols (designs constituting a combination of symbols corresponding to the combination) is attached is attached to the outer peripheral surface thereof. In this embodiment, for each reel 31, 21 symbol display areas are arranged at equal intervals (the number of symbol frames is 21), and a predetermined symbol is displayed in each symbol display area. The number of symbol frames is 20 in addition to 21.

  The medal payout device 35 is electrically connected to the main control board 50. The medal payout device 35 includes a hopper motor 36 that is driven when paying out a medal of a hopper serving as a medal storage unit from a payout port, and a payout sensor 37 for detecting a medal paid out from the hopper motor 36. .

A medal that is maintained and accepted from the medal slot 43 is formed so as to be accommodated in the hopper through a predetermined passage.
The payout sensor 37 determines whether or not the medal has been paid out correctly when the medal is paid out. For example, when the signal of the payout sensor 37 is OFF despite the hopper motor 36 being driven, it is determined that no medal has been paid out, and a hopper error (no medal) is detected. On the other hand, when the signal of the payout sensor 37 remains on, it is detected that a medal jam has occurred.

Further, a stored number display device 47 and a bet number display device 48 are provided as information display devices controlled on the main control board 50 side.
As described above, the information display device includes a device that is electrically connected to the main control board 50 and is directly controlled by the main control board 50 without being controlled by the sub control board.

The slot machine 10 has a function of electrically storing medals, and can store up to “50” (50 sheets). When it exceeds “50”, it is paid out from the medal payout device 35.
The stored number display device 47 is a device for displaying the number of stored medal at the present time in segments.
The bet number display device 48 is a device for displaying the number of medals bet at the present time, and in this embodiment, displays a number in the range of “0” to “3”.

An output peripheral device including the effect lamp 21, the speaker 22, and the image display device 23 is electrically connected to the output port 92 of the second sub-control board 90.
The effect lamp 21 is an LED or the like for effect of the slot machine 10, and lights up in a predetermined pattern when a predetermined condition is satisfied. Note that the effect lamp 21 is arranged on the inner peripheral side of each reel 31, and a back lamp for illuminating from behind the symbols displayed on the reels 31 (upper and lower symbols visible from the display window). Fluorescent lamps for illuminating symbols on the reel 31 and decorative lamps (not shown) that are arranged on the front surface of the casing of the slot machine 10 and blink when a winning combination is included.

The speaker 22 outputs a predetermined sound when a predetermined condition is satisfied in order to perform various effects during the game.
Furthermore, the image display device 23 is composed of a liquid crystal display, an organic EL display, a dot display, and the like, and during the game, various effect images (effects corresponding to the push order during AT, the lottery result of the role, etc.) , Game information (the number of games during AT, the number of acquired games, etc.), a menu screen, and the like are displayed.

  At the start of the game, the player operates the bet switch 40 to bet a medal stored in advance, or obtain a medal from the medal slot 43. When medals are stored before the game starts, a predetermined number of medals are bet by operating the bet switch 40 within the range of the stored number.

Further, regardless of whether or not there is storage, one bet is placed when one medal is maintained from the medal insertion slot 43 from the state where there is no bet medal, and three bets are placed when three medals are maintained.
When a bet is placed, the signal is input to the main control board 50. Further, when the start switch 41 is operated in a state where a bet is placed, the signal is transmitted to the main control board 50.

  When receiving the operation signal of the start switch 41, the main CPU 54 (reel control means 62) controls to drive all the motors 32 and rotate all the reels 31 (however, it is not rotated when the freeze is executed). In some cases). As the reel 31 is rotated by the motor 32 in this way, the symbols on the reel 31 are moved and displayed in the display window at a predetermined speed in the vertical direction (the direction in which the symbols move from the upper level to the lower level).

  Further, the role lottery means 61 of the main CPU 54 performs a lottery for a role when a signal indicating that the start switch 41 is operated is detected. The role lottery means 61 extracts a random value when the start switch 41 is operated, and determines which winning combination the random value corresponds to the winning lottery table, thereby determining the winning combination in the game. To do.

The combination lottery table defines the types of combinations to be selected and the winning probability of each combination. Each of the winning lottery tables has a predetermined range of lottery areas. The lottery area is divided into a winning area and a non-winning area for each winning combination, and the winning lottery has a preset winning probability. The predetermined ratio is set so as to be.
The combination lottery table is provided for each set value, and the combination lottery table corresponding to the set value stored in the memory 53 is used.

  The player presses the stop switch 42 when the operation acceptance of the stop switch 42 is enabled, so that the reel 31 corresponding to the stop switch 42 (for example, the left reel 31 corresponding to the left stop switch 42) is pressed. Stop rotation. When the stop switch 42 is operated, the signal is input to the main control board 50.

When the main CPU 54 (reel control means 62) receives this signal, the main CPU 54 (reel control means 62) corresponds to the stop switch 42 from the combination lottery result in the combination lottery means 61 and the position of the reel 31 at the moment when the stop switch 42 is operated. Drive control of the motor 32 is performed, and stop control of the reel 31 related to the motor 32 is performed.
When all the reels 31 are stopped, when a combination of symbols corresponding to any of the winning combinations stops on the active line (that is, when winning the winning combination), a medal corresponding to the winning combination is paid out. Is called.

  The winning determination means 63 of the main CPU 54 determines whether or not the combination of symbols corresponding to any of the combinations has stopped on the active line when all the reels 31 are stopped. The winning determination means 63 determines the symbol on the active line by detecting the number of steps of the motor 32, for example.

  The payout means 64 of the main CPU 54 determines that the combination of symbols corresponding to any of the combinations has stopped on the active line when all the reels 31 are stopped, and when the winning combination of the combination is won, In response, a predetermined number of medals are paid out to the player. The payout is added as the stored number, or when the stored number exceeds “50”, the medal is actually paid out from the payout opening. When actually paying out medals, the hopper motor 36 is driven and controlled to pay out a predetermined number of medals. At the time of paying out medals, the payout medal is detected by the payout sensor 37, and it is checked whether or not it has been paid out correctly.

  When a main lottery is performed by the main control unit 50 at the start of the game, information on the lottery result of the combination is transmitted from the main control unit 50 to the first sub-control unit 80. When the first sub control means 80 receives this information, it further transmits this information to the second sub control board 90. Therefore, at the start of the game, both the first sub control board 80 and the second sub control board 90 receive information on the lottery result of the combination.

  For each game, the first sub-control means 80 generates a software random number based on the winning lottery result (information on the winning lottery result transmitted from the main control board 50 side) by the winning lottery means 61 at the start of the game. Depending on the lottery used, a lottery is performed as to whether or not AT is executed. In addition, during AT precursor, AT preparation, etc., the number of AT games is drawn. In addition, during AT, a lottery is performed by adding the number of AT games. Further, during AT, a lottery such as whether or not to shift to a mode that is more advantageous to the player (for example, a special mode for adding the number of AT games) is performed. These lotteries are performed based on programs and data stored in the memory 83.

Note that a lottery such as an AT may be performed every game, or may be performed on the condition that a predetermined combination lottery result is obtained. Further, the AT lottery is not limited to when the game is started, but may be performed when all the reels 31 are stopped (when winning a winning combination) or when the game ends (when medals are paid out or medals are automatically inserted for replay). Good.
In addition, the AT is not limited to lottery, but for example, the number of games from the end of the previous AT to the next AT activation may be determined by lottery or the like.

  Furthermore, the second sub-control board 90 selects and outputs an effect by lottery using software random numbers based on the lottery result of the combination by the combination lottery means 61 at the start of the game for each game (described above). The output of the production from the production lamp 21, the speaker 22, and the image display device 23 is controlled).

Specifically, as the game progresses, at what timing (when the start switch 41 is operated, when each stop switch 42 is operated, etc.), what effect is output (how the lamp 21 is operated) Whether to turn on, blink, or turn off, what kind of sound is output from the speaker 22, what kind of image is displayed on the image display device 23, and the like. Then, an effect is output according to this selection.
Therefore, the production output from the production lamp 21, the speaker 22, and the image display device 23 is controlled on the second sub-control board 90 side, and the main control board 50 and the first sub-control board 80 side. It is not controlled by.

FIG. 2 is a diagram showing a part of the effect data stored in the memory 83 (sub main ROM) of the first sub control board 80.
In the example of FIG. 2, three addresses “7000000”, “7000001”, and “7000003”, and offset values and control data corresponding to the respective addresses are shown. In practice, however, millions of addresses and data for each address are stored. These data are presentation data (including those related to AT lottery) used in the first sub-control board 80.

In the example of FIG. 2, control data (both displayed in hexadecimal) corresponding to the offset value is stored in each address. For example, the address “7000000” stores control data (lower) corresponding to five offset values “00” to “05” (upper). For example, the control data corresponding to the offset value “00” is “ AA ".
In the example of FIG. 2, the display of the control data at addresses “7000001” and “7000003” is omitted, but actually, control data corresponding to each offset value is stored.
Further, in the example of FIG. 2, the offset value is displayed in the upper stage and the control data is displayed in the lower stage. However, only the control data is actually stored in the memory 83, and the first sub-control board 80 controls the control data. When the offset value corresponding to is specified, the count value of a counter described later is used.

  The first sub control board 80 transmits the authentication data to the second sub control board 90, but creates authentication data including the offset value shown in FIG. 2 and control data corresponding to the offset value. As shown in FIG. 2, the authentication data is a group of four (one set) data, which is “0x50VV”, “0x51WW”, “0x52XX”, and “0x53YY”, respectively. Here, “VV”, “WW”, “XX”, and “YY” are values calculated from the offset value and control data corresponding to the offset value.

  “0x50VV” to “0x53YY” are binary 16-bit data when used as authentication data to be transmitted to the second sub-control board 90. Here, when 16 bits of data are divided into upper 8 bits and lower 8 bits, the upper 8 bits represent “50” to “53”. That is, in “0x50VV”, the upper 8 bits are a bit value representing “50” in binary, that is, “01010000”. Similarly, the upper 8 bits of “0x51WW”, “0x52XX”, and “0x53YY” are “01010001”, “0101010010”, and “01010011”, respectively.

Furthermore, in the present embodiment, the most significant bit (eighth bit) of the lower 8 bits of the 16-bit authentication data is empty and always “0”. Note that these empty bits can also be used for checksum data to be described later.
Furthermore, the offset value is indicated by the first to seventh bits of “0x50VV”, the first to seventh bits of “0x51WW”, and the first to fifth bits of “0x52XX”.
Control data is indicated by the sixth bit of “0x52XX” and the first to seventh bits of “0x53YY”.

For example, when transmitting the offset value “00” of the address “7000000” and the control data “AA” corresponding to the offset value “00”, the authentication data is created as follows.
First, the offset value is replaced with binary 19 bits. Therefore, the offset value “00” is “0000000000000000000” in 19 bits. Similarly, the control data is replaced with binary 8 bits. Therefore, the control data “AA” (hexadecimal number) is “10101010”.

Then, the first to seventh bits of the 19-bit offset value are assigned to the lower 7 bits of “0x50VV”. Therefore, the 16-bit authentication data of “0x50VV” is
"01010000 100000000"
It becomes.
Next, the 8th to 14th bits of the 19-bit offset value are assigned to the 1st to 7th bits of “0x51WW”. Therefore, 16-bit authentication data of “0x51WW” is
"0101010001 00000000"
It becomes.

Further, the 15th to 19th bits of the 19-bit offset value are assigned to the 1st to 5th bits of “0x52XX”.
Furthermore, the most significant bit (8th bit) of the 8-bit control data is assigned to the 6th bit of “0x52XX”. In the example of FIG. 2, the 7th bit of “0x52XX” in the 16-bit authentication data is set to “0”. Therefore, the 16-bit authentication data “0x52XX” is
“010100010 00100000”
It becomes.

Also, the first to seventh bits of the 8-bit control data are assigned to the first to seventh bits of “0x53YY”. Therefore, the 16-bit authentication data “0x53YY” is
"01010011 00101010"
It becomes.

From the above,
0x50VV: 01010000 00000000
0x51WW: 01010001 00000
0x52XX: 01010010 00100000
0x53YY: 01010011 00101010
It becomes.
Therefore, the group of authentication data is transmitted to the second sub-control board 90.

In addition, “VV”, “WW”, “XX”, and “YY” of “0x50VV”, “0x51WW”, “0x52XX”, and “0x53YY” are the last 8 bits of the 16-bit authentication data. The value is represented in hexadecimal.
Therefore,
00000000 = 00
00100000 = 20
00101010 = 2A
It is. Therefore, as shown in FIG. 2, the offset value “00”, the control data “AA” “0x50VV”, “0x51WW”, “0x52XX”, and “0x53YY” are “0x5000”, “0x5100”, “0x5220” and “0x532A”.

Another example will be described.
The authentication data of the offset value “01” of the address “7000000” and the control data “BB” corresponding to the offset value “01” is as follows.
First, the offset value is “0000000000000000001” when it is replaced with 19 bits of binary number. Further, the control data “BB” (hexadecimal number) is “10111011” when it is replaced with binary 8 bits.

When the 1st to 7th bits of the 19-bit offset value are assigned to the lower 7 bits of “0x50VV”, the 16-bit authentication data of “0x50VV” is
"01010000 00000001"
It becomes.
Next, when the 8th to 14th bits of the 19-bit offset value are assigned to the 1st to 7th bits of “0x51WW”, the 16-bit authentication data of “0x51WW” is
"0101010001 00000000"
It becomes.

Further, the 15th to 19th bits of the 19-bit offset value are assigned to the 1st to 5th bits of “0x52XX”.
Furthermore, the 8th bit of the control data is assigned to the 6th bit of “0x52XX” (same as above, the 7th bit is set to “0” in the lower 8 bits). Therefore, the 16-bit authentication data “0x52XX” is
“010100010 00100000”
It becomes.

Also, the first to seventh bits of the control data are assigned to the first to seventh bits of “0x53YY”. Therefore, the 16-bit authentication data “0x53YY” is
"01010011 00111011"
It becomes.

From the above,
0x50VV: 01010000 00000001
0x51WW: 01010001 00000
0x52XX: 01010010 00100000
0x53YY: 01010011 00111011
It becomes.
Also,
VV = 01
WW = 00
XX = 20
YY = 3B
It becomes. Therefore, as shown in FIG. 2, the offset value “01”, “0x50VV”, “0x51WW”, “0x52XX”, and “0x53YY” indicating the control data “BB” are respectively “0x5001”, “0x5100”, “0x5220” and “0x533B”.

FIG. 3 is a diagram showing the authentication data created as described above.
The authentication data to be transmitted to the second sub-control board 90 includes four groups of “0x50VV” to “0x53YY”, and is transmitted continuously. For example, in “0x50VV”, the first 8 bits of 16-bit authentication data is identification information indicating “01110000”, that is, “50”. The second sub-control board 90 determines that it is “0x50” from the first half 8-bit data.
The first to seventh bits (A00 to A06) of “0, A06, A05, A04, A03, A02, A01, A00”, which are the last 8 bits of “0x50 VV”, are offset value data.

Furthermore, in “0x51WW”, the data of the first half of 16-bit authentication data is identification information indicating “01110001”, that is, “51”. The second sub-control board 90 determines that “0x51” from the first half 8-bit data.
Of the latter 8 bits of “0x51WW”, the 1st to 7th bits (A07 to A13) are offset value data.

  Furthermore, in “0x52XX”, of the 16-bit authentication data, the first-half 8-bit data is identification information indicating “01110010”, that is, “52”. The second sub-control board 90 determines that “0x52” from the first half 8-bit data.

Of the latter half 8 bit data of “0x52XX”, the first to fifth bits (A14 to A18) are offset value data. Further, “D07” of the sixth bit is control data.
Furthermore, in “0x53YY”, the first 8 bits of the 16-bit authentication data is identification information indicating “01110011”, that is, “53”. The second sub-control board 90 determines that it is “0x53” from the first half 8-bit data.
Of the latter 8 bits of “0x53YY”, the 1st to 7th bits (D00 to D06) are values indicating control data.

The first sub control board 80 first determines which offset value (and control data) to transmit based on a counter provided in the first sub control board 80.
When the first sub control board 80 transmits the authentication data, a second sub control board 90 described later returns a checksum indicating that the authentication data has been received to the first sub control board 80. When receiving the checksum, the first sub-control board 80 determines whether or not the checksum is correct. If the checksum is correct, the first sub-control board 80 increments the counter by “+1”. For example, when the counter value is “0”, authentication data is created to transmit the offset value “0” and its control data, and when the counter value is “1”, the offset value Creates authentication data in order to transmit “1” and its control data.

  In this embodiment, it is determined which data of the offset value should be substantially transmitted based on the counter value. However, the present invention is not limited to this, and the offset value already transmitted (or the checksum is correct). The determined offset value) may be stored.

  FIG. 4 is a diagram for explaining calculation on the second sub-control board 90 side that has received the authentication data. As described above and as shown in FIG. 4, the first sub control board 80 sequentially transmits four pieces of authentication data to the second sub control board 90 as a group of authentication data. By transmitting four pieces of one authentication data consisting of 16 bits, one set is transmitted.

As illustrated in FIG. 4, the second sub-control board 90 receives authentication data of “0x50VV”, “0x51WW”, “0x52XX”, and “0x53YY”. Thereby, on the second sub-control board 90 side,
“0, 1, 0, 1, 0, 0, 0, 0, 0, A06, A05, A04, A03, A02, A01, A00”
“0, 1, 0, 1, 0, 0, 0, 1, 0, A13, A12, A11, A10, A09, A08, A07”
“0, 1, 0, 1, 0, 0, 1, 0, 0, E01, D07, A18, A17, A16, A15, A14”
"0, 1, 0, 1, 0, 0, 1, 1, 0, D06, D05, D04, D03, D02, D01, D00"
Are received.

Next, the second sub CPU 94 of the second sub control board 90 creates an 19-bit offset value using the first to third authentication data among the four authentication data. In the present embodiment, the lower 7 bits (A06 to A00) of the first authentication data (0x50VV), the lower 7 bits (A13 to A07) of the second authentication data (0x51WW), and the third authentication data The lower 5 bits (A18 to A14) of (0x52XX) are combined, and 19-bit data consisting of A18 to A00 is calculated (created) as an offset value (see FIG. 4).
Further, the 6th bit (“D07”) of the third authentication data and the lower 7 bits (D06 to D00) of the fourth authentication data (0x53YY) are combined to calculate control data consisting of 8 bits ( create. This control data becomes the control data specified by the offset value.

The second sub control board 90 then associates the offset value stored in the memory 93 of the second sub control board 90 with the control data corresponding to the offset value, and determines whether the control data is correct.
FIG. 5 is a diagram showing an authentication data table stored in the memory 93 (sub-sub ROM) of the second sub-control board 90.
As shown in FIG. 5, the second sub-control board 90 stores in the memory 93 a data table including offset values and control data corresponding to the offset values.
The offset value is 19-bit data. The control data is 8-bit data.

  When receiving the authentication data, the second sub-control board 90 creates an 19-bit offset value as described above and stores the created offset value. When the authentication data is received next time, an offset value is created again from the authentication data, and the created offset value is compared with the stored offset value (offset value created from the previous authentication data). If the difference is “1” (if incremented by “1”), it is determined that the offset value created from the received authentication data is correct, and the stored offset value is updated.

  If control data is created from the authentication data received this time and it is determined that the offset value is correct, then the control data corresponding to (created) the offset value is stored in the control data ( It is determined whether or not it matches (the control data corresponding to the created offset value) (collation in the second sub-control board 90). Therefore, when it is determined that the offset value created from the received authentication data is correct (that is, “1” is incremented with respect to the stored previous offset value), the control data is collated.

When it is determined that the control data match as a result of the collation, the abnormality detection process is not performed. On the other hand, when it is determined that the control data do not match, the count value of the abnormality detection counter 95b is added.
Here, in the present embodiment, the first sub-control board 80 includes an offset value abnormality counter 95a and an abnormality detection counter 95b as abnormality detection counters as shown in FIG.

  When the count value of the abnormality detection counter 95b is added, it is next determined whether or not the count value of the abnormality detection counter 95b has reached a predetermined value. When it is determined that the count value of the abnormality detection counter 95b has reached a predetermined value, the process proceeds to processing for notifying abnormality. On the other hand, when it is determined that the count value of the abnormality detection counter 95b has not reached the predetermined value, the process returns to the process of receiving the authentication data from the first sub control board 80.

On the other hand, when an offset value is created from the authentication data and it is determined that the offset value is incorrect (not incremented by “1”), the offset value created from the authentication data received this time is the stored offset value. It is determined whether or not the same value as (previously created offset value).
If it is determined that they are not the same value, it means that the current offset value is shifted by “2” or more with respect to the previous offset value. In this case, the count value of the offset value abnormality counter 95a is added. .

  When the count value of the offset value abnormality counter 95a is added, it is next determined whether or not the count value of the offset value abnormality counter 95a has reached a predetermined value. When it is determined that the count value of the offset value abnormality counter 95a has reached a predetermined value, the count value of the abnormality detection counter 95b is added without checking the control data. When the count value of the abnormality detection counter 95b is added, the above-described processing is executed.

When it is determined that the offset value created from the authentication data received this time is the same as the stored offset value (previously created offset value), the number of consecutive times determined to be the same value is counted. Count value of this counter (this counter is provided on the second sub-control board 90) is added. Then, after adding the count value, it is determined whether or not the count value is “4”.
When it is determined that the count value is “4”, that is, when it is determined that the offset value is the same four times in succession, the count value of the abnormality detection counter 95b is added without performing collation.
On the other hand, when it is determined that the count value is “3” or less, the control data is collated.

FIG. 6 is a diagram illustrating an example of a vector table stored in the memory 83 of the first sub control board 80 and the memory 93 of the second sub control board 90.
If the program has a plurality of interrupt processes, a subroutine for each interrupt process is created in advance. The vector table is a data table indicating the correspondence between the type of interrupt processing and the address of the subroutine in order to specify which subroutine is called when an interrupt processing request is made.

  Here, as shown in FIG. 2, the vector table may have a data table structure composed of an address and data corresponding to the address (when a vector table program is included in a normal program). However, there may be a data table structure as shown in FIG.

  The vector table shown in FIG. 6 is originally used on the first sub control board 80 side. However, the same vector table as that stored in the memory 83 of the first sub control board 80 is also stored in the memory 93 of the second sub control board 90. Note that a vector table equivalent to the vector table stored in the memory 83 of the first sub control board 80 may be stored in the memory 93 of the second sub control board 90 as it is, or the memory 83 of the first sub control board 80 may be stored. A part of the vector table stored in the second sub-control board 90 may be stored in the memory 93.

  The first sub-control board 80 transmits vector table interrupt processing and address data (that is, the contents of the vector table) to the second sub-control board 90. The second sub-control board 90 refers to the vector table stored in the memory 93 and determines whether or not the received interrupt process and its address match. If it is determined that they do not match, a predetermined abnormality detection process similar to the above is executed.

As described above, in the present embodiment,
(1) The memory 83 of the first sub-control board 80 stores a data table that includes an address and its effect data, and the effect data includes control data corresponding to the offset value. The first sub-control board 80 creates a group of four continuous authentication data from the offset value and the control data, and transmits it to the second sub-control board 90.
The second sub-control board 90 includes a data table that stores offset values and control data corresponding to the offset values. When the second sub-control board 90 receives the group of authentication data, the second sub-control board 90 calculates an offset value (19 bits) and control data (8 bits), and determines whether the offset value is incremented by “1”. to decide. When it is determined that the offset value has been incremented by “1”, it is determined that the offset value is correct, and collation is performed to determine whether or not the control data corresponding to the offset value matches. When it is determined that they do not match, a predetermined abnormality detection process is executed.

(2) An equivalent vector table is stored in both the first sub-control board 80 and the second sub-control board 90, or a part of the vector table stored in the first sub-control board 80 is subjected to the second sub-control. This is stored in the substrate 90.
The first sub control board 80 transmits the interrupt processing of the vector table and the data of the address (address) to the second sub control board 90. When the second sub-control board 90 receives the data, the second sub-control board 90 refers to the stored vector table and determines whether or not the interrupt processing matches the address (address). When it is determined that they do not match, a predetermined abnormality detection process is executed.
That is, the data in the vector table is used as authentication data.

By executing the above two processes, it is determined whether or not the memory 83 of the first sub-control board 80, that is, the so-called sub-ROM has been illegally exchanged (sub-ROM exchange goto action).
In addition, although it is preferable to perform both (1) and (2) above, collation may be performed using only one of (1) and (2). As the number of verifications increases, the reliability for verification increases, but the processing time increases. If the number of verifications is small, the processing time can be shortened, but the reliability decreases accordingly.

Furthermore, if the vector table is tampered with, there is a possibility that the malicious program is started before the anti-counterfeiting program is started. In this case, the unauthorized program may be tampered with so as not to pass the unauthorized countermeasure program.
However, it is possible to detect that the malicious program is not activated by checking the correspondence of the processing using the vector table.

FIG. 7 is a flowchart showing a main loop of the first sub-control board 80 in the present embodiment.
The first sub-control board 80 repeatedly executes the main loop shown in FIG. 7 as information processing related to the presentation while the power is turned on.

  In FIG. 7, first, in step S11, the first sub-control board 80 clears the mounted watchdog timer. Next, the process proceeds to step S12, and operation processing (measurement) of the watch dog timer is started. The watchdog timer outputs a pulse for determining the runaway of the first sub CPU 84 and continues to count the number of outputs of this pulse. As will be described later, when the count value of the number of pulses reaches a predetermined value (for example, “10”) before the watchdog timer is cleared, it is determined that the first sub CPU 84 is running out of control, and the first The processing of the sub-control board 80 is shifted to processing at power-on.

  In step S13, interrupt processing is permitted. When interrupt processing is permitted in step S13, interrupt processing shown in FIG. 8 described later is performed. In this interruption process, the authentication data described above is transmitted to the second sub-control board 90.

  If interrupt processing is permitted during the main loop, the main loop is temporarily exited and predetermined interrupt processing (FIG. 8) is executed. After executing the interrupt process, the process returns to the main loop again. This process is performed periodically. The interval of the interrupt time is 1 ms in this embodiment. That is, the process shown in FIG. 8 to be described later is executed for each interrupt process at 1 ms intervals.

  In step S14, the first sub-control board 80 executes lamp / sound control. This processing is performed by, for example, controlling the speaker 22, effect lamp 21, specifically side lamps (LEDs that are provided on both sides of the housing of the slot machine 10 and are lit and blinking according to the gaming state, winning combination, etc. Etc.)), back lamps (lamps that illuminate symbols from behind the reels 31), reel fluorescent lamps (fluorescent lamps arranged on the top of the reels 31), lamps that light the effect buttons, and the like.

  Next, proceeding to step S15, the first sub-control board 80 performs image display monitoring. This processing includes error detection and error handling of the heat dissipating fan provided in the image display device 23, reset request check processing of the image display device 23 (for example, when returning from power interruption, etc.), processing based on a command of the first sub CPU 84 Etc.

In the next step S16, the first sub-control board 80 performs amplifier monitoring. The amplifier here refers to the amplifier of the speaker 22. The operational state of this amplifier is monitored.
In the next step S17, monitoring of the bus controller (for example, I2C bus controller) is executed. This processing is monitoring of information transmission between devices.

  In the next step S18, execution processing for each frame is performed. The processing executed on the first sub-control board 80 is framed, and is set to be executed sequentially in the order of determination one frame at a time. When proceeding to the frame-by-frame execution process, in the next step S19, the first sub-control board 80 clears the watchdog timer started in step S12. Therefore, at this time, the counted number of pulses is cleared.

In step S20, the first sub-control board 80 executes one command processing, that is, one instruction in one frame. At the timing of this one command process, four (a group) authentication data are created from the offset value and the control data, and transmitted to the second sub-control board 90.
If a power interruption occurs during the processing of one command, complete recovery processing is performed. In the complete recovery process, the process returns from the timing when the power interruption occurred during the processing of one command.
In addition, when power interruption occurs other than during command processing, normal return processing is performed. In the normal return process, the first sub CPU 84 and the RWM are initialized, and the process is executed from the beginning of the main loop.
As a result, in the complete recovery process, the first sub CPU 84 and the RWM are not initialized. Therefore, even if a power failure occurs during the generation of the authentication data, the authentication data based on the correct offset value and control data is generated. can do.

In the next step S21, the first sub-control board 80 executes processing to be performed in the remaining time after one command processing. For example, when one command processing is completed and processing that should be executed is completed, the processing stored in the buffer is performed next. Here, authentication data may be created using this remaining time. Further, the authentication data can be transmitted by either one command processing or remaining time processing. In particular, when the game is not being played (for example, during the demonstration screen display), since the processing is small (the remaining time is large), it is possible to take time to create and transmit the authentication data.
Further, in the remaining time processing, the counter is incremented by “+1” for every 1 ms interrupt until it reaches “+16”.

Next, the process proceeds to step S22, and it is determined whether or not the processing for all the one frame to be executed in step S18 has been executed. Here, it is determined whether or not the execution of one frame has been completed by detecting whether or not 16 ms has elapsed since the interruption was permitted in step S13. In the present embodiment, one frame processing is always completed when 16 ms elapses.
Specifically, in this embodiment, a counter that is “+1” is provided for each interrupt process (every 1 ms), and the counter value is added for each interrupt process (every 1 ms) in the remaining time process in step S21 described above. , Count until “+16”.

In step S22, when the counter value reaches “+16”, it is determined that the processing for all the frames has been completed, and the process returns to step S11 (the counter value is reset). On the other hand, when it is determined that the processing of all one frame has not been completed yet, the process returns to step S20 to execute an unprocessed command in one frame.
Note that the processing time from when the interrupt is permitted in step S13 to the determination in step S22 is less than 1 ms.

  FIG. 8 is a flowchart showing interrupt processing when interrupt is permitted in step S13 in FIG. When interruption is permitted in step S13, the process shown in FIG. 8 is executed every 1 ms. What is executed in this interrupt processing is processing such as transmission of authentication data shown in FIG. 3 and the like from the first sub-control board 80 to the second sub-control board 90.

  First, in step S31 of FIG. 8, the first sub control board 80 continues to determine whether or not a command, that is, a command including the authentication data described above can be transmitted to the second sub control board 90. When it is determined that transmission is possible, the process proceeds to a predetermined step according to the state of the first sub-control board 80 at that time. In the present embodiment, the states that can be transmitted include an idle state, a data transmission start wait state, a data transmission in progress, a reply wait state, a recovery start state, and a recovery wait state.

  If it is in the idle state, the process proceeds to step S32. If it is in the data transmission start waiting state, the process proceeds to step S41. If the data is being transmitted, the data continues to be transmitted. When it is in a reply waiting state, the process proceeds to step S51, when it is in a recovery start state, the process proceeds to step S61, and when it is in a recovery waiting state, the process proceeds to step S71.

  In the idle state, when the process proceeds to step S32, the first sub control board 80 determines whether or not it has an untransmitted command (authentication data or the like). If it is determined that there is an untransmitted command, the process proceeds to step S33, and if it is determined that there is no untransmitted command, the process according to this flowchart is terminated. In step S33, in order to register an untransmitted command, the read pointer of the storage area (buffer) in which the untransmitted command is stored is updated. Next, in step S34, a transmission request is made for the 0th byte (in the case of 16-bit authentication data, it indicates byte data consisting of the lower 8 bits) in the command to be transmitted. In this process, by determining the 0th byte of the command, it is determined whether or not transmission data is written in TDR (Transmit Data Register; 1-byte register in the present embodiment, the same applies hereinafter) described later. It is.

In step S35, it is determined whether the TDR is empty (empty), that is, whether transmission data is written (stored). If it is determined that the TDR is empty, the process proceeds to step S36, and data to be transmitted is written in the TDR (write process). Then, the process proceeds to step S37, interrupt permission for emptying transmission data is performed, and this flowchart is ended.
When data is written to the TDR, the data is automatically transmitted, and after transmission, the TDR data is automatically emptied (empty).

  On the other hand, if it is determined in step S35 that the data is not TDR empty, the data to be transmitted is already written in the TDR, so the process proceeds to step S38, and the state shifts to a data transmission start waiting state. That is, after the process according to this flowchart is completed, in the next interrupt process, when “Yes” is determined in step S31, the process proceeds to step S41.

  If “Yes” is determined in step S31 and it is determined that the data transmission start waiting state is set, the process proceeds to step S41, and similarly to step S35 described above, it is determined whether or not the TDR is empty. When it is determined in step S41 that the TDR is not empty (data to be transmitted has already been written), the processing according to this flowchart is terminated. On the other hand, when it is determined that the TDR is empty, the process proceeds to step S42, and writing (write processing) to the TDR is performed as in step S36. Next, the process proceeds to step S43, and interrupt permission for emptying the data to be transmitted is performed as in step S37. Then, the process proceeds to step S44 and shifts to data transmission. That is, at the time of the next interrupt process, if “Yes” is determined in step S31, “data transmission is in progress”.

If “Yes” in the step S31, it is determined that a reply is awaited, and the process proceeds to a step S51.
When the first sub-control board 80 transmits data, the first sub-control board 80 starts timing by a timer. In step S51, the first sub-control board 80 continues to determine whether or not the time measured by the timer has passed a predetermined waiting time. When it is determined that the predetermined waiting time has elapsed, the process proceeds to step S53, and retry processing, that is, data retransmission, is performed. When the process proceeds to the retry process in step S53, the process proceeds to step S81 in FIG.

  On the other hand, when it is determined in step S51 that the predetermined waiting time has not elapsed, the process proceeds to step S52 to determine whether or not a checksum error has occurred. Here, the checksum error corresponds to a case where the checksum is received and the received checksum is not a correct value. If the checksum has not been received yet, the checksum error in step S52 does not occur. If it is determined in step S52 that a checksum error has occurred, the process proceeds to step S53, and the process proceeds to retry processing. If it is determined that there is no checksum error, the process of this flowchart ends.

  In the example of the flowchart of FIG. 8, it is determined on the first sub control board 80 side whether or not a checksum error has occurred based on the checksum returned from the second sub control board 90. It is also possible to determine a checksum error on the sub control board 90 side.

For example, when receiving the checksum, the second sub-control board 90 may determine whether the check is correct by comparing with the checksum calculated on the second sub-control board 90 side. In this case, when the second sub-control board 90 determines that the checksum is normal, the second sub-control board 90 does not reply to the first sub-control board 80, and when it is determined that the checksum is abnormal, A reply (indicating that the checksum is abnormal) may be sent to the first sub-control board 80.
When the first sub control board 80 receives information indicating that the checksum is abnormal, it determines that the checksum is abnormal.

  In step S81, it is determined whether the number of retries (including the first transmission) is 3 or less. That is, the first sub-control board 80 counts the number of retries using a counter, and determines whether or not the number of retries is “3” or less. When it is determined that the number of retries is "3" or less, the process proceeds to step S82 and shifts to a recovery start state. That is, at the time of the next interrupt process, if “Yes” is determined in step S31, the processes after step S61 are performed.

  On the other hand, if it is determined in step S81 that the number of retries is not "3" or less, the process proceeds to step S83, where the first sub control board 80 determines that the transmitted data is abnormal, and the second sub control board 80 An initialization request is made to the control board 90. Then, the process proceeds to step S84 and shifts to the idle state. That is, at the time of the next interrupt process, if “Yes” is determined in step S31, the processes after step S32 are performed.

  If “Yes” in the step S31, and it is determined that the recovery is started, the process proceeds to a step S61. In step S61, it is determined whether or not the TDR is empty. When it is determined that the TDR is not empty (data to be transmitted is written), the processing according to this flowchart is terminated. On the other hand, when it is determined that the TDR is empty, the process proceeds to step S62, a recovery waiting time (50 ms) is set, and the timer starts counting. In the next step S63, data is written to the TDR (write process). And it progresses to step S64 and transfers to a recovery waiting state. That is, at the time of the next interrupt process, if “Yes” is determined in step S31, the processes after step S71 are performed.

  If “Yes” in step S31, the process proceeds to step S71 when it is determined that it is in a recovery waiting state. In step S71, registered data to be transmitted is set. In the next step S73, a transmission request for the 0th byte of the data set in step S72 is made. Then, the process proceeds to step S74 and shifts to a data transmission start waiting state. That is, at the time of the next interrupt process, if “Yes” is determined in step S31, the processes after step S41 are performed.

  FIG. 9 is a flowchart showing the authentication data transmission process by the first sub-control board 80. In FIG. 8, when data transmission is in progress, the processing of FIG. 9 is executed. The example in FIG. 9 shows an example in which authentication data including an offset value is transmitted.

9, in step S92, the offset value to be transmitted and the control data corresponding to the offset value are acquired from the effect data (address, offset value and control data corresponding to the address) shown in FIG. . As described above, the first sub-control board 80 includes a counter for determining which authentication value corresponding to which offset value has been transmitted to the second sub-control board 90, and based on this counter value, An offset value and control data to be transmitted are acquired. When the offset value and the control data are acquired, a group of authentication data is created as shown in FIG.
Further, the created 16-bit authentication data is written in the TDR immediately before transmission, as shown in FIG. In step S93, the authentication data is transmitted to the second sub-control board 90.

In step S94, it is determined whether or not the offset value of the transmitted authentication data is the final offset value. Whether or not the authentication data corresponding to the final offset value has been transmitted is determined based on the counter value. When it is determined that the final offset value has been transmitted, all offset values to be authenticated and control data corresponding to the offset value have been transmitted.
If it is determined that the final offset value has been transmitted, the process proceeds to step S96 to initialize the offset value to be transmitted. That is, the above-described counter (counter that counts the transmitted offset value) is cleared, and the processing according to this flowchart ends.

On the other hand, when it is determined in step S94 that it is not the final offset value, the process proceeds to step S95, the offset value to be transmitted is updated (that is, the counter is incremented by “1”), and the processing according to this flowchart is terminated.
As will be described later, in this embodiment, the offset value to be transmitted is stored using a counter. However, the present invention is not limited to this, and the offset value to be transmitted (transmitted) itself is stored. May be.

  Here, the order of the offset values to be transmitted is “0”, “1”, “2”,... In the order, and when the vector table data of FIG. Do in order. However, the present invention is not limited to this, and the order of offset values to be transmitted can be arbitrarily determined. For example, when the offset value is acquired in step S92, it may be determined randomly using a software random number. However, it is set so that the same offset value is not specified a plurality of times until transmission of offset values of all addresses is completed.

  As the method, it is possible to set so as not to generate the same software random number. In this case, the generated software random number is stored, and if the generated software random number is already generated, the software random number is set to be generated again. That is, the transmission order until the round of the offset value to be transmitted is arbitrary, but control is performed so that the same offset value is not transmitted repeatedly until the round of the round.

FIG. 10 is a flowchart showing a process of the second sub control board 90 when the authentication data is transmitted from the first sub control board 80, specifically, an abnormality detection process.
First, in step S <b> 111, the second sub control board 90 determines whether authentication data has been received from the first sub control board 80. If it is determined that the authentication data has been received, the process proceeds to step S112. If it is determined that the authentication data has not been received, the process proceeds to step S124.

  In step S112, an offset value and control data corresponding to the offset value are created from the received authentication data. As shown in FIG. 4, when four (a group) authentication data consisting of 16 bits is received, a 19-bit offset value and 8-bit control data for the offset value are created.

  In the next step S113, the second sub-control board 90 extracts or creates a checksum of the authentication data received in step S111 and returns it to the first sub-control board 80. The first sub-control board 80 receives the checksum by the process shown in FIG. 11 described later, and determines its value to determine whether or not the authentication data has been transmitted correctly. There are various ways of setting the checksum value. For example, among the 16-bit authentication data, for example, the value of the 8th bit, which is an empty bit in the above example, can be set as the checksum, For example, the sum of all 16-bit values is calculated, and the value is set as a chemsum for transmission. Further, it is possible to include checksum data in advance in the authentication data transmitted from the first sub-control board 80, extract the data, and send it back as a checksum.

In step S114, it is determined whether or not the received authentication data is the first authentication data. Here, “first authentication data” means that the authentication data is not received for the second time or later when the authentication data transmission is retried. That is, “Yes” is obtained in step S114 when the first authentication data is received without retry, and “No” is obtained in step S114 when the second and subsequent authentication data is received after the retry.
When it is determined in step S114 that the data is the first authentication data, the process proceeds to step S119, and when it is determined that the data is not the first authentication data, the process proceeds to step S115.

In step S115, it is determined whether or not the offset value created from the received authentication data is “+1” with respect to the offset value created from the previously received authentication data. In the present embodiment, as described above, the received offset value is set to be incremented by “1”.
When it is determined in step S115 that the offset value is “+1”, the process proceeds to step S119, and when it is determined that the offset value is not “+1”, the process proceeds to step S116.

  In step S116, it is determined whether or not the offset value created from the authentication data received this time is the same as the offset value created from the authentication data received last time. For example, when the offset value created from the authentication data received last time is “0A” and the offset value created from the authentication data received this time is “0A”, both values are the same value.

If it is determined in step S116 that the offset values are not the same value, the process proceeds to step S117. If it is determined that the offset values are the same value, the process proceeds to step S123.
In step S117, the value of the offset value abnormality counter 95a is set to “+1”. In step S118, it is determined whether the value of the offset value abnormality counter 95a has reached a predetermined upper limit value.

Here, the upper limit value is arbitrarily set, but is set to “2” in the present embodiment. However, the present invention is not limited to this, and the upper limit value can be variously set. For example, the upper limit value may be set to “1”, or may be set to “3” or more. When the upper limit value is set to “1”, some processing related to the abnormality is performed only when the count value of the offset value abnormality counter 95a becomes “+1”.
When it is determined in step S118 that the value of the offset value abnormality counter 95a has reached the upper limit value, the process proceeds to step S125, and when it is determined that the upper limit value has not been reached, the process proceeds to step S119.

  Note that “No” in step S115, that is, when the offset value is not “+1” and it is determined in step S116 that the offset value is not the previous value, the offset value is “2” or more with respect to the previous value. It is a different case. For example, the previous offset value is “1” and the current offset value is “3”.

  On the other hand, in step S116, it is determined that the offset value created based on the authentication data received this time is the same value as the offset value created based on the authentication data received last time. Judge whether or not. Here, in this embodiment, “4 continuous” is set, but any number of continuous may be set. If it is determined that the values are the same for four consecutive times, it is determined that the authentication data is abnormal, and the process proceeds to step S125. On the other hand, when it is determined that it is not yet 4 consecutive, the process proceeds to step S119.

  In the example of the flowchart of FIG. 10, when it is determined that the offset value is the same value for four consecutive times, the process proceeds to step S125, and a count value of an abnormality detection counter 95b described later is added. However, as described above, when it is determined that the offset value is the same value for four consecutive times, the initialization command is not received from the first sub-control board 80 (the first sub-control board 80 is If the number of retries exceeds 3, the initialization command is transmitted to the second sub-control board 90), and the possibility of fraud is high. Therefore, when “Yes” is determined in step S123, the process may proceed to step S127, which will be described later, and may be shifted to an abnormality notification process.

In step S119, data collation is started. As described above, whether or not the control data corresponding to the offset value matches (is the same as) the control data stored in the memory 93 (data table shown in FIG. 5) of the second sub-control board 90. Judging.
If it is determined that they match, it is determined that correct authentication data has been received from the first sub-control board 80, and the process proceeds to step S121. On the other hand, when it is determined that they do not match, it is determined that correct authentication data has not been received from the first sub-control board 80, and the process proceeds to step S125.

In step S121, it is determined whether or not all areas have been collated. Here, the whole area refers to all offset values and control data stored in the memory 93 of the second sub-control board 90 in FIG. If it is determined that all areas have been collated, the process proceeds to step S122. If it is determined that all areas have not been collated, the process returns to step S111.
In step S122, the count values of the offset value abnormality counter 95a and the abnormality detection counter 95b are cleared (set to “0”). Then, the process returns to step S111.

  On the other hand, when it is determined in step S111 that the authentication data has not been received from the first sub control board 80, the process proceeds to step S124. In step S124, it is determined whether or not authentication data has been received for a certain period (time). Here, the second sub-control board 90 includes a timer that starts timing from the time when the authentication data is received, and when it is determined that a predetermined time has elapsed since the last time when the authentication data was received, It is determined that the authentication data has not been received. When it is determined that the authentication data has not been received for a certain period, the process proceeds to step S125, and when it is determined that the certain period has not elapsed, the process returns to step S111 to continue timing. Note that returning to step S111, when it is determined that the authentication data has been received, the timer count that has started counting from the last reception of the authentication data is cleared.

  When the process proceeds from step S118, step S120, step S123, or step S124 to step S125, the second sub control board 90 increments the count value of the abnormality detection counter 95b by "+1". Then, the process proceeds to step S126, and the second sub-control board 90 determines whether or not the count value of the abnormality detection counter 95b has reached a predetermined upper limit value. Here, various values can be set as the “upper limit value”, for example, “3” can be set. Of course, this upper limit may be set to “1”. That is, when the value of the abnormality detection counter 95b becomes “+1”, the processing described later related to abnormality detection may be executed uniformly.

When it is determined that the value of the abnormality detection counter 95b has reached the upper limit value, the process proceeds to step S127, and when it is determined that the upper limit value has not been reached, the process returns to step S111.
In step S127, the second sub-control board 90 sets the abnormal state of the authentication data. Then, the process proceeds to the next step S128 to notify that the authentication data is abnormal. This notification is, for example, notification that the offset value and the control data corresponding to the offset value do not match, and notification is performed using at least one of the effect lamp 21, the speaker 22, or the image display device 23. And the process by this flowchart is complete | finished.

As is apparent from the processing shown in FIG. 10, the second sub-control board 90 has a case where the offset values are not in order (step S115) or when the same offset value is repeatedly received (steps S116 and S123). Then, the value of the offset value abnormality counter 95a is added, and when the count value reaches the upper limit value, the value of the abnormality detection counter 95b is set to “+1”. When the count value of the abnormality detection counter 95b reaches the upper limit value, abnormality notification is performed.
Accordingly, if both the upper limit value of the offset value abnormality detection counter 95a and the upper limit value of the abnormality detection counter 95b are set to “1”, an abnormality notification is made when either one of the values changes from “0” to “1”. It can be performed.

  On the other hand, if the upper limit value of the offset value abnormality detection counter 95a is set to “2” or more, it will not be detected as an abnormality only when the authentication data cannot be correctly received due to noise or the like once. can do. Similarly, if the upper limit value of the abnormality detection counter 95b is set to “2” or more, even if the authentication data is not received for a certain period of time, it can be prevented from being detected as an abnormality immediately.

As is apparent from FIG. 10, even if the offset value created from the authentication data received this time is the same as the offset value created from the authentication data received last time, it is not the same value for four consecutive times (in step S123). “No”), the process proceeds to step S119 to perform collation.
Even if the offset value exceeds “+1”, if the offset value abnormality counter 95a does not reach the upper limit value, the process proceeds to step S119 and collation is performed.

  Although not shown in the flowchart, the second sub-control board 90 includes a retry counter, and includes a counter that sets the count value to “+1” every time it is determined that the offset value is the same as the previous value. The authentication data is not always transmitted at a constant time interval, and may be transmitted after a busy state. Even in such a case, it is possible to correctly count how many times the authentication data is retried.

  In FIG. 8 described above, when the first sub control board 80 determines that the number of retries (including the first transmission) is 4 (step S81), the process proceeds to step S83, and the second sub control board 90 Make a request to initialize For this reason, normally, in FIG. 10, it is not determined that “the offset value is the same value four consecutive times” in step S123.

  However, there is a possibility that the program may be falsified so as not to perform the process (initialization request) in step S83. Even if such alteration is made, the second sub-control board 90 side determines whether or not the offset value is the same value for four consecutive times, so that the second sub-control board 90 side uniquely detects an abnormality. It becomes possible. When it is determined that the offset value is the same value for four consecutive times, the initialization command has not been received from the first sub control board 80, and therefore the first sub control board 80 has been tampered with. It can be judged that there is a high possibility.

FIG. 11 is a flowchart showing the checksum processing on the first sub control board 80 side.
In the flowchart of FIG. 11, the process of step S137 (determination of whether the waiting time has elapsed) corresponds to the process of step S51 of FIG. Steps S139 to S141 correspond to step S53 (retry processing) in FIG.

  First, in step S <b> 131, the first sub control board 80 transmits authentication data to the second sub control board 90. Next, proceeding to step S132, the first sub-control board 80 starts measuring the elapsed time (timer count) from when the authentication data was transmitted. Then, it waits for a checksum response from the second sub-control board 90.

  In step S133, the first sub control board 80 determines whether or not a checksum has been received. When it is determined that the checksum has been received, the process proceeds to step S134. When it is determined that the checksum has not been received, the process proceeds to step S137.

  In step S134, the timer count started in step S132 is cleared. In step S135, the received checksum is verified. In the next step S136, it is determined whether or not the received checksum is correct as a result of the collation in step S135. When it is determined that the received checksum is correct, the process according to this flowchart is terminated, and when it is determined that the checksum is not correct, the process proceeds to step S139.

  In step S133, it is determined that a checksum has not been received, and in step S137, it is determined whether a waiting time has elapsed. When it is determined that the waiting time has not elapsed, the process returns to step S133, and when it is determined that the waiting time has elapsed, the process proceeds to step S138.

  In step S138, the timer count started in step S132 is cleared as in step S134. Next, proceeding to step S139, it is determined whether or not the number of retries (including the first transmission in this embodiment) of the authentication data transmitted at step S131 is “3” or less. In the present embodiment, the upper limit value of the number of transmissions of the same authentication data is set to “3”, and retry is performed up to three times. However, if “3” is exceeded, it is determined that there is an abnormality. Therefore, when it is determined that the number of retries is “3” or less, the process proceeds to step S141, and the same authentication data is retransmitted. Then, the process returns to step S132.

  On the other hand, when it is determined that the number of retries exceeds “3”, the process proceeds to step S140, and a predetermined abnormality detection process is performed. For example, as shown in step S83 to step S84 in FIG. 8, an initialization request is issued to the second sub-control board 90, and control is performed to shift to the idle state. And the process by this flowchart is complete | finished.

Next, a process until an abnormality is detected when a sub ROM (memory 83) replacement operation is actually performed will be described.
(1) When the offset value stored in the memory 83 of the first sub-control board 80 is tampered with in FIG. 2, for example, the control data “BB” of the offset value “01” out of the address “70000000” is “ Assume that it has been rewritten to “AA”.
In this case, once authentication data is created,
0x50VV: 01010000 00000001
0x51WW: 01010001 00000
0x52XX: 01010010 00100000
0x53YY: 01010011 00101010
It becomes.
Then, these authentication data are transmitted to the second sub control board 90.

  However, when a 19-bit offset value is created by the second sub-control board 90, the offset value created from the authentication data is “1”, and the control data is “AA”. However, since the control data corresponding to the offset value “1” is “BB” in the memory 93 of the second sub-control board 90, there is a mismatch when the control data is collated. In S120, it is determined that there is no matching.

(2) When the program is altered so that only the same group of authentication data is repeatedly transmitted In FIG. 2, it is assumed that control data of an offset value other than the offset value “00” has been altered, for example. Further, if authentication data other than the offset value “00” is transmitted to the second sub-control board 90, tampering is detected, so that only the authentication data with the offset value “00” is repeatedly transmitted. Is assumed to have been tampered with.
Specifically, only “0x5000”, “0x5100”, “0x5220”, and “0x532A” that are authentication data of the offset value “00” and the control data “AA” shown in FIG. 2 are continuously transmitted. Is the case.

  In such a case, the offset value is determined as the previous value in the process of step S116 in FIG. If it is determined that the offset values are the same for four consecutive times, the process after step S125 is performed, so that an abnormality notification can be finally performed.

(3) When the transmission program is falsified so that the falsified offset value is skipped and transmitted In FIG. 2, it is assumed that the control data “BB” having the offset value “01” has been falsified.
In this case, after transmitting the authentication data related to the control data “AA” having the offset value “00”, the authentication data related to the control data “BB” having the offset value “01” is not transmitted, and the offset value “02” is transmitted. It is conceivable to transmit authentication data related to the control data “CC”. That is, the authentication data related to the control data “BB” having the offset value “01” is skipped.

  In such a case, when the second sub control board 90 creates an offset value from the authentication data related to the control data “CC” having the offset value “02”, the control data “AA” having the offset value “00” received last time is created. Therefore, the offset value abnormality counter 95a is incremented by "+1" in step S117. Therefore, it is finally possible to notify the abnormality.

Note that the offset value deviation (jump) can be set as “how many times the number of verifications is generated, abnormality notification is performed” or the like. Furthermore, by combining with the count value of the timer, for example, it is possible to make a setting such as notifying abnormality when the offset value is shifted (flyed) twice within 60 minutes. Alternatively, if the offset value is deviated twice (flies) during one round, it is possible to notify the abnormality.
Furthermore, if a deviation (jump) occurs in a specific offset value during the previous round, and a deviation (jump) occurs in the same offset value during the next round, it is possible to report an abnormality at that point. It is.

  When the second sub control board 90 detects an abnormality (step S126 and subsequent steps in FIG. 10), various processes can be executed. For example, it is possible to perform control so that authentication data and other commands from the first sub-control board 80 are not accepted after the abnormal state is set or after the abnormality is notified.

  Here, as a sub ROM exchange goto action, there is a possibility that the program may be falsified so as to forcibly transmit an abnormality release command to the second sub control board 90 after transmission of unauthorized authentication data. However, the second sub-control board 90 may be set so as not to receive such a command after the abnormal state is set.

Moreover, the cancellation | release after abnormality notification is set, for example to power interruption or RAM (above-mentioned RWM) clear, and unless these are performed, the cancellation | release of abnormality notification is set as impossible.
When a power interruption occurs during verification of authentication data, it is stored to what time the verification has been completed, and the control is performed so that the verification is started after the interruption.

As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, For example, the following various changes are possible.
(1) In this embodiment, a group of four authentication data (16 bits each) is transmitted as authentication data, and a 19-bit offset value and 8-bit control data are created. For example, when the address becomes large, there is a method of using the offset value without using the address. However, the address itself and 16-bit data may be transmitted, the same data may be stored on the second sub-control board 90 side, and both may be simply verified.
Further, the number of groups of authentication data for one offset value and control data is four in the embodiment, but may be 1 to 3, or 5 or more.

(2) As shown in FIG. 1, the effect lamp 21 and the speaker 22 are electrically connected to the second sub-control board 90 in the same manner as the image display device 23. However, the present invention is not limited to this, and the effect lamp 21 and the speaker 22 may be electrically connected to the first sub-control board 80. Then, there is a method in which the second sub control board 90 is an image control board (a control board specialized for image control).
Although not shown in FIG. 1, when the image display device 23 is controlled, an image control CPU, an image controller IC, a character ROM (for storing character image data), A video RAM (VRAM) or the like is mounted.

(3) In addition to the data shown in the embodiment, the effect data that needs to be verified includes, for example, a function pointer table, an AT lottery data table, and the like. Here, the “function pointer table” is a table in which an address is assigned to each function (function executed on a program) and the address is stored. When calling a function, a pointer is specified and the function pointed to by the pointer is executed.
In the case of having a function that affects the appearance, the function pointer table (address and function corresponding to the address) is used as authentication data, and the second sub-control board 90 side (at least a part used for authentication) And storing the data in the function pointer table from the first sub-control board 80 as authentication data to the second sub-control board 90 for verification.

  (4) In the present embodiment, the main control board 50, the first sub control board 80, and the second sub control board 90 are illustrated as physically separate bodies, but the present invention is not limited thereto, and the first sub control is not limited thereto. The present invention can also be applied to the case where the function of the substrate 80 (first sub control means) and the function of the second sub control board 90 (second sub control means) are mounted on one sub control board. In such a case, depending on the capacity, both the main sub ROM (corresponding to the memory 83) and the sub sub ROM (corresponding to the memory 93) are mounted on the sub control board, or one sub sub ROM is mounted. ROM is mounted.

  (5) Furthermore, the present invention can also be applied to a case where the main control board 50, the first sub control board 80, and the second sub control board 90 are all mounted on one control board. is there. In this case, the main CPU 54 and the first sub CPU 84 are not limited to one-way communication, and bidirectional communication is also possible.

  (6) In the present embodiment, the first sub-control board 80 and the second sub-control board 90 are capable of bidirectional communication. However, if the specification does not transmit other commands (information) such as a checksum from the second sub-control board 90 to the first sub-control board 80, the first sub-control board 80 to the second sub-control board 90 The communication may be a one-way communication from the first sub control board 80 to the second sub control board 90 in the same manner as the communication between the main control board 50 and the first sub control board 80.

  (7) The timing for transmitting the authentication data is not limited to that shown in the embodiment, and may be any of transmission during game and transmission during game standby. The authentication data may be transmitted mainly by a method of periodically transmitting the authentication data using a timer or during a demonstration screen display where no game is being performed. If the demonstration screen is being displayed, the CPU has more processing power than the game, so that a lot of authentication data can be transmitted.

  (8) When collating the authentication data, the second sub-control board 90 may store all of the effect data of the first sub-control board 80 or may store a part thereof. . In the case of storing a part, for example, an address range in which important data exists in FIG. 2 is set, and the offset value and control data of the range are stored in the second sub-control board 90. You can do it.

  (9) In the example of FIG. 10, it is determined whether or not the offset value is “+1” in step S115. If it is determined that the offset value is not “+1”, the process proceeds to step S116. When it is determined that the value is not +1 ”, the process immediately proceeds to the process of step S117 (addition of the offset value abnormality counter 95a), the process of step S125 (addition of the abnormality detection counter 95b), or the process of step S127 (abnormal state set). May be.

(10) In the present embodiment, the first sub control board 80 and the second sub control board 90 are shown as the sub control boards, but the number of sub control boards may be three or more. For example, it is possible to provide an accessory (movable object for production) in the gaming machine and to provide a sub control board (third sub control board) for controlling the operation of the accessory.
In such a case, the second sub control board 90 and the third sub control board are electrically or optically connected, or the first sub control board 80 and the third sub control board are electrically or optically connected. Connect. It is also possible to store authentication data (such as an offset value and control data) on the third sub-control board, and execute collation based on the authentication data transmitted from the first sub-control board 80.

  (11) In the present embodiment, the slot machine 10 is illustrated as an example of the gaming machine, but not limited to the slot machine, the main control board (means), the first sub control board (means), the second sub control board (means) ) Can be applied to various gaming machines (including pachinko gaming machines).

<Appendix>
Problems to be solved by the invention (original invention) according to the initial claims of the present application, means for solving the problems related to the original invention, and effects of the original invention are as follows.
(A) Problems to be solved by the original invention In the conventional technology, if a new gate device that is not found in previous gaming machines is provided between the main control board and the sub-control board, it is illegal at first glance. There is a problem that it is known that a countermeasure device is attached.
Further, if a gate device is provided separately, the number of parts increases accordingly, and there is a problem that the cost increases.
Therefore, the problem to be solved by the original invention is to prevent the sub ROM exchange go-to action while making it impossible to easily overlook fraud countermeasures from the appearance.

(B) Means for Solving the Problems Related to the Initial Invention (Note that the corresponding embodiment is described in parentheses)
The first solution is
Main control means (main control board 50) for controlling the progress of the game;
Sub-control means (first sub-control board 80 and second sub-control board 90) that receives information from the main control means and controls the production based on the received information,
The sub-control means includes
First sub-control means (first sub-control board 80) for performing a predetermined lottery (AT lottery etc.) relating to the output of the effect;
Second sub-control means (second sub-control board 90) for controlling the output of the performance,
The first sub-control means stores production data (16-bit data),
The first sub control means transmits at least a part of the effect data as authentication data to the second sub control means,
The second sub-control unit includes an offset value (19-bit offset value) that can be calculated from the authentication data transmitted from the first sub-control unit, and control information (8-bit control data) corresponding to the offset value. Is stored in advance,
The second sub-control unit receives the authentication data transmitted from the first sub-control unit, calculates an offset value and control information corresponding to the offset value based on the authentication data, and the offset value is Predetermined abnormality detection processing (addition of count value of offset value abnormality counter 95a, addition of count value of abnormality detection counter 95b, abnormality) Notification) is performed.

The second solving means is the first solving means,
The second sub-control means, when the number of times that the offset value and the control information are determined not to correspond correctly within a predetermined time or within a predetermined period becomes a predetermined number of times (related to the offset value not correctly incremented) When the authentication data is received once or a plurality of times and / or when the authentication data related to the same offset value is received once or a plurality of times (especially continuously), the predetermined abnormality detection process is executed. It is characterized by that.

(C) Effect of the Initial Invention According to the initial invention, even if the sub ROM exchange gotten action on the first sub control means side is performed, the second sub control means has the correct offset value and control information corresponding to the offset value. Therefore, if the received authentication data is calculated and collated, it is possible to find a match / mismatch of the data. Thereby, for example, abnormality detection processing such as abnormality notification can be performed.

Note that if the sub-ROMs of both the first sub-control unit and the second sub-control unit are illegally replaced, there is no effect.
But,
1) The sub ROM exchange goto action is mainly to replace the sub ROM of the first sub control means.
2) Goto understands that the second sub-control means stores the offset value that can be calculated from the production data (authentication data) of the first sub-control means and the control information corresponding to the offset value. Difficult,
3) The sub ROM data of the second sub control means is for image control, is more complicated than the sub ROM data of the first sub control means, and has a huge amount of data. The present invention is effective because it is difficult to find out in which part of the sub ROM of the control means the offset value and the control information corresponding to the offset value are stored.

10 Slot machines (gaming machines)
DESCRIPTION OF SYMBOLS 21 Effect lamp 22 Speaker 23 Image display device 30 Symbol display device 31 Reel 32 Motor 35 Medal paying device 36 Hopper motor 37 Payout sensor 40 Bet switch 41 Start switch 42 Stop switch 43 Medal insertion port 43a Passage sensor 44 Input sensor 45 Blocker 46 Settlement Switch 47 Storage number display device 48 Bet number display device 50 Main control board 51 Input port 52 Output port 53 Memory 54 Main CPU
60 Setting change means 61 Role lottery means 62 Reel control means 63 Winning judgment means 64 Payout means 80 First sub control board 81 Input port 82 Output port 83 Memory 84 First sub CPU
85 AT lottery means 86 Authentication data transmission means 90 Second sub control board 91 Input port 92 Output port 93 Memory 94 Second sub CPU
95 Abnormality detection means 95a Offset value abnormality counter 95b Abnormality detection counter

Claims (2)

Main control means for controlling the progress of the game;
Sub-control means for receiving information from the main control means and controlling effects based on the received information,
The sub-control means includes
First sub-control means for performing a predetermined lottery regarding the output of the production;
Second sub-control means for controlling the output of the performance,
The first sub-control means stores production data,
The first sub control means transmits at least a part of the effect data as authentication data to the second sub control means,
The second sub-control unit stores in advance an offset value that can be calculated from the authentication data transmitted from the first sub-control unit and control information corresponding to the offset value,
The second sub-control unit receives the authentication data transmitted from the first sub-control unit, calculates an offset value and control information corresponding to the offset value based on the authentication data, and the offset value is A gaming machine characterized by determining whether it is correct and executing a predetermined abnormality detection process on the condition that it is determined that the offset value is not correct. In claim 1,
The second sub-control means executes the predetermined abnormality detection process when the number of times that it is determined that the offset value and the control information do not correspond correctly within a predetermined time or within a predetermined period becomes the predetermined number of times. A gaming machine characterized by that.