JP2015185583A - Method for manufacturing fuse element, method for manufacturing semiconductor device and method for producing titanium silicide film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a method for manufacturing a fuse element and a method for manufacturing a semiconductor device, in which variations in the resistance value of a titanium silicide film can be reduced even when the titanium silicide film has a fine pattern; and a method for producing a titanium silicide film.SOLUTION: A method for producing a fuse element includes the steps of: forming a titanium film 109 on a non-doped fuse polysilicon film 51; subjecting the titanium film 109 and the fuse polysilicon film 51 to first heat treatment to form a titanium silicide film of a C49 phase on the fuse polysilicon film 51; and subjecting the titanium silicide film to second heat treatment to change the phase of the titanium silicide film from a C49 phase to a C54 phase.

Description

  The present invention relates to a fuse element manufacturing method, a semiconductor device manufacturing method, and a titanium silicide film manufacturing method.

  Conventionally, metal silicide is formed for the purpose of reducing the resistance of the source, drain, and gate electrode. For example, in Patent Document 1, a titanium (Ti) film is deposited on a source diffusion layer, a drain diffusion layer, and a gate electrode, and then this titanium film is reacted with the source diffusion layer, the drain diffusion layer, and the gate electrode, respectively. It is described that the titanium silicide film (C49 phase) is formed, and then the C49 phase is changed to the C54 phase to form the titanium silicide film (C54 phase). The titanium silicide film has a lower resistance in the C54 phase than in the C49 phase.

Japanese Patent No. 3234002

  By the way, a semiconductor device including an analog circuit often has a trimming circuit formed in order to adjust its resistance value and capacitance value. In many cases, a semiconductor device including a memory circuit such as a DRAM is provided with a redundant circuit for replacing a defective cell with a spare cell. By selectively cutting fuse elements included in the trimming circuit and redundant circuit during the manufacturing process of semiconductor devices and in the post-manufacturing process, analog characteristics are adjusted to desired values and yield reduction is suppressed. You can do it.

  For example, polysilicide is used for the fuse element. Silicide is a compound of metal and silicon. A fuse element using polysilicide is blown by passing a current. However, when the polysilicide has a high resistance, current does not flow easily, and the fusing is difficult. Therefore, in the fuse element using polysilicide, it is necessary to suppress the increase in resistance of the silicide.

However, with the miniaturization of semiconductor devices, miniaturization of fuse elements is also progressing. When the silicide is miniaturized, there is a problem that the variation in the resistance value of the silicide increases.
FIG. 16 is a result of an experiment conducted by the present inventor and is a diagram showing a relationship between the sheet resistance and the length (L) of the titanium silicide film. In FIG. 16, the horizontal axis represents the sheet resistance (Ω / □), and the vertical axis represents the cumulative frequency (%) of the sheet resistance. The shape of the titanium silicide film used in this experiment in plan view (hereinafter referred to as planar shape) is a rectangle, and the length (L) is three types of 0.7 μm, 4.2 μm, and 200 μm. Each titanium silicide has a width (W) of 0.35 μm.

As shown in FIG. 16, it was confirmed that the variation in sheet resistance of the titanium silicide film increases in the order of L = 200 μm, 4.2 μm, and 0.7 μm. In particular, the titanium silicide film of L = 0.7 μm (micropattern) has a large variation in sheet resistance, and the occurrence of outliers (ie, deviating from the standard value) was confirmed.
Although the reason (mechanism) that the outlier is generated in the finely patterned titanium silicide film is not clear, the present inventor thinks as follows.

  FIG. 17 is a schematic diagram showing an outlier generation mechanism considered by the present inventors. For example, the titanium silicide film (C54 phase) is formed by a step of forming a titanium film on silicon, a step of forming a titanium silicide film (C49 phase) by a first heat treatment, and a second heat treatment. Through a phase transition from C49 phase to C54 phase.

In the phase transition process from the C49 phase to the C54 phase, when the second heat treatment is started, nuclei of the C54 phase are generated in the C49 phase. Then, as the processing time of the second heat treatment elapses, the C49 phase around the C54 phase nucleus transitions to the C54 phase.
Here, as shown in FIG. 17A, since the titanium silicide film 300 having a large pattern (W: small, L: large) has a large area, a C54 phase nucleus 320 is present. On the other hand, as shown in FIG. 17B, the titanium silicide film 310 having a minute pattern (W: small, L: small) is divided into a pattern in which the C54 phase nucleus 320 is present and a pattern in which the C54 phase nucleus 320 is not present. A phase transition occurs in a pattern in which nuclei 320 exist, and no phase transition occurs in a pattern in which no nuclei exist. For these reasons, the present inventor believes that the variation in sheet resistance of the titanium silicide film increases as the pattern becomes smaller.

  Accordingly, the present invention has been made in view of such circumstances, and a method of manufacturing a heat treatment of a fuse element and a method of manufacturing a semiconductor device capable of reducing variation in the resistance value of the titanium silicide film even in the case of a minute pattern. Another object is to provide a method for manufacturing a titanium silicide film.

  In order to solve the above-described problem, a method for manufacturing a fuse element according to an aspect of the present invention includes a step of forming a titanium film on a non-doped fuse silicon film, and a first process for forming a titanium film and a fuse silicon film. Performing a heat treatment to form a C49 phase titanium silicide film on the fuse silicon film; and performing a second heat treatment on the titanium silicide film to cause the titanium silicide film to transition from the C49 phase to the C54 phase; It is characterized by having.

The manufacturing method of the semiconductor device which concerns on 1 aspect of this invention is equipped with the process of performing said manufacturing method of a fuse element, It is characterized by the above-mentioned.
A method for manufacturing a titanium silicide film according to one embodiment of the present invention includes a step of forming a titanium film over a non-doped silicon film, a first heat treatment on the titanium film and the silicon film, and a C49 phase on the silicon film. And a step of subjecting the titanium silicide film to a second heat treatment to cause the titanium silicide film to transition from the C49 phase to the C54 phase.

  A method of manufacturing a fuse element according to another aspect of the present invention includes a step of forming a titanium film on a non-doped fuse silicon film, and performing a first heat treatment on the titanium film and the fuse silicon film, Forming a titanium silicide film on the fuse silicon film; and subjecting the titanium silicide film to a second heat treatment at a temperature higher than that of the first heat treatment.

It is sectional drawing which shows the structural example of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment in process order. It is a figure which shows the cumulative frequency distribution of the sheet resistance of the titanium silicide film | membrane formed on the non-doped fuse polysilicon film according to the dose amount of Ar. It is a figure which shows the cumulative frequency distribution of the sheet resistance of the titanium silicide film | membrane formed on the non-doped fuse polysilicon film according to the dose amount of Ar. It is a figure which shows the cumulative frequency distribution of the sheet resistance of the titanium silicide film | membrane formed on the fuse polysilicon film doped with P + according to the dose amount of Ar. It is a figure which shows the cumulative frequency distribution of the sheet resistance of a titanium silicide film. It is a figure which shows the cumulative frequency distribution of the sheet resistance of a titanium silicide film. It is a figure which shows the cumulative frequency distribution of the sheet resistance of a titanium silicide film. It is a figure which shows the cumulative frequency distribution of the sheet resistance of a titanium silicide film. It is a figure which shows the relationship between the dispersion | variation in sheet resistance, and the implantation energy of Ar. It is a figure which shows the relationship between the dispersion | variation in sheet resistance, and the dose amount of Ar. It is a figure which shows the relationship between the sheet resistance and length (L) of a titanium silicide film. It is a schematic diagram which shows the generation | occurrence | production mechanism of an outlier.

Embodiments according to the present invention will be described below with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof is omitted.
<First Embodiment>
(Construction)
FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device according to an embodiment of the present invention. First, the structure of the semiconductor device 100 will be described.

  As shown in FIG. 1, the semiconductor device 100 includes a silicon (Si) substrate 1, a MOS transistor 10 formed in a transistor region of the silicon substrate 1, and a fuse element 50 formed in a fuse region of the silicon substrate 1. Is provided. In FIG. 1, one MOS transistor 10 and one fuse element 50 are shown, but for example, a plurality of MOS transistors 10 and fuse elements 50 are formed. The semiconductor device 100 is formed on the silicon substrate 1, an element isolation layer 3 formed on the silicon substrate 1, an interlayer insulating film 81 formed on the silicon substrate 1 and covering the MOS transistor 10 and the fuse element 50, and the silicon substrate 1. Contact electrodes 83 and 84 penetrating the interlayer insulating film 81 in the thickness direction, and wiring layers 93 and 94 formed on the interlayer insulating film 81.

  The element isolation layer 3 electrically isolates the transistor region and the fuse region of the silicon substrate 1. In the fuse region, the element isolation layer 3 is also formed between the silicon substrate 1 and the fuse element 50, and the fuse element 50 and the silicon substrate 1 are insulated by the element isolation layer 3. Further, the MOS transistor 10 and the wiring layer 93 are electrically connected by the contact electrode 83. Similarly, the fuse element 50 and the wiring layer 94 are electrically connected by the contact electrode 84.

  The MOS transistor 10 includes a gate insulating film 11 formed on the silicon substrate 1, a gate electrode 13 formed on the gate insulating film 11, a source layer 15 having an LDD structure formed on both sides of the gate electrode 13, and A drain layer 16, a sidewall 17 formed on the side surface of the gate electrode 13, and a titanium silicide (TiSi 2) film 22 formed on the gate electrode 13, the source layer 15, and the drain layer 16, respectively.

  The fuse element 50 includes a fuse polysilicon film 51 formed on the element isolation layer 3, a titanium silicide (TiSi 2) film 62 formed on the fuse polysilicon film 51, and a side formed on the side surface of the fuse element 50. And a wall 53. The fuse polysilicon film 51 is made of a non-doped polysilicon film and is patterned in the shape of a fuse element. The crystal structure of the titanium silicide film 62 formed on the fuse polysilicon film 51 and the crystal structure of the titanium silicide film 22 formed in the transistor region described above are low resistance C54 phase (face-centered oblique). Crystal). The C54 phase is formed by forming a high-resistance C49 phase (bottom orthorhombic crystal) and then phase-changing the C49 phase by heat treatment.

(Production method)
Next, a method for manufacturing the semiconductor device 100 shown in FIG. 1 will be described.
FIG. 2A to FIG. 5C are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. As shown in FIG. 2A, first, a silicon substrate 1 is prepared. Next, the element isolation layer 3 is formed on the silicon substrate 1 by, for example, LOCOS (local oxidation of silicon) method. The formation method of the element isolation layer 3 is not limited to the LOCOS method. The element isolation layer 3 may be formed by an STI (shallow trench isolation) method.

Next, a gate insulating film 11 is formed on the silicon substrate 1. A method for forming the gate insulating film 11 is, for example, thermal oxidation of a silicon substrate. Then, a non-doped polysilicon film is formed on the silicon substrate 1 so as to cover the gate insulating film 11. A method for forming the non-doped polysilicon film is, for example, a LPCVD (low pressure chemical vapor deposition) method. The film thickness of the non-doped polysilicon film is about 3500 mm, for example. The non-doped polysilicon film is an intrinsic silicon film that is not doped with an N-type impurity (that is, a donor) or a P-type impurity (that is, an acceptor). The impurity concentration in the non-doped polysilicon film is 1 × 10 ¹⁶ atoms / cm ³ or less.

Next, this non-doped polysilicon film is patterned by photolithography and dry etching. As a result, as shown in FIG. 2B, the fuse polysilicon film 51 is formed simultaneously with the formation of the gate electrode 13.
Next, as shown in FIG. 2C, a resist pattern 101 having a shape covering the fuse region and opening the transistor region is formed on the silicon substrate 1 by photolithography. Then, N-type impurities (or P-type impurities) are ion-implanted into the silicon substrate 1 using the resist pattern 101 as a mask. As a result, N-type impurities (or P-type impurities) are introduced into the gate electrode 13 and the silicon substrate 1 below both sides of the gate electrode 13 at low concentrations. Since the upper and side surfaces of the fuse polysilicon film 51 are covered with the resist pattern 101, no impurities are introduced into the fuse polysilicon film 51 and the non-doped state is maintained. After this ion implantation, the resist pattern 101 is removed.

Next, a silicon oxide film is formed on the silicon substrate 1 by a CVD method or the like, and this silicon oxide film is etched back. Thereby, as shown in FIG. 3A, the sidewall 17 is formed on the side surface of the gate electrode 13, and at the same time, the sidewall 53 is formed on the side surface of the fuse polysilicon film 51.
Next, a resist pattern 103 having a shape covering the fuse region and opening the transistor region is formed on the silicon substrate 1. Then, N-type impurities (or P-type impurities) are ion-implanted into the silicon substrate 1 using the resist pattern 103 as a mask. As a result, N-type impurities (or P-type impurities) are introduced at a high concentration into the gate electrode 13 and the silicon substrate 1 outside the sidewall 17 as viewed from the gate electrode 13. Since the upper and side surfaces of the fuse polysilicon film 51 are covered with the resist pattern 103, no impurities are introduced into the fuse polysilicon film 51 and the non-doped state is maintained. Thereafter, the resist pattern 103 is removed.

  Next, as shown in FIG. 3B, a salicide block (self-aligned silicide block) film 105 is formed on the silicon substrate 1. For example, the salicide block film 105 is a silicon oxide film and is formed by a CVD method. After the salicide block film 105 is formed, the silicon substrate 1 is subjected to heat treatment to activate the impurities already introduced into the silicon substrate 1 or the like. Thereby, as shown in FIG. 3B, the source layer 15 and the drain layer 16 having an LDD structure are formed. The impurity activation may be performed before the formation of the salicide block film 105, rather than after the formation of the salicide block film 105.

  Next, the salicide block film 105 is patterned by photolithography, and the silicon substrate 1 is selectively covered with the salicide block film 105 as shown in FIG. Here, the salicide block film 105 is left in a region where silicide is not formed in the salicide process described later, and the salicide block film 105 is removed from a region where silicide is formed.

Next, as shown in FIG. 4A, a resist pattern 107 having a shape that opens the fuse polysilicon film 51 and its peripheral region and covers other regions (including the transistor region) is formed on the silicon substrate 1. Form. Then, a rare gas element is ion-implanted into the fuse polysilicon film 51 using the resist pattern 107 as a mask. Thereby, at least the upper part of the fuse polysilicon film 51 is amorphized while maintaining the non-doped state of the fuse polysilicon film 51. For example, argon (Ar) is ion-implanted into the fuse polysilicon film 51 as a rare gas element. The Ar implantation conditions are an implantation energy (that is, acceleration energy) of 30 keV and a dose of 1 × 10 ¹⁴ atoms / cm ² or more. Thereafter, as shown in FIG. 4B, the resist pattern 107 is removed from the silicon substrate 1.

Next, as shown in FIG. 4C, a titanium (Ti) film 109 is formed on the silicon substrate 1. The thickness of the titanium film 109 is about 550 mm, for example, and the formation method is a sputtering method.
Next, the silicon substrate 1 on which the titanium film 109 is formed is subjected to a first heat treatment to expose silicon exposed from below the salicide block film 105 (that is, the gate electrode 13, the source layer 15, the drain layer 16, and the non-doped layer). The fuse polysilicon film 51) and the titanium film 109 are chemically reacted (salicide process). The treatment conditions for the first heat treatment are, for example, 600 ° C. or more and 700 ° C. or less and 40 seconds or more and 80 seconds or less in a nitrogen atmosphere.

As a result, as shown in FIG. 5A, the C49-phase titanium silicide (C49-TiSi ₂ ) film 21 is self-aligned on the gate electrode 13 in the transistor region, on the source layer 15 and on the drain layer 16, respectively. At the same time, a C49-phase titanium silicide (C49-TiSi ₂ ) film 61 is formed in a self-aligned manner on the fuse polysilicon film 51 in the fuse region.

  That is, in the transistor region, silicon (gate electrode 13, source layer 15 and drain layer 16) reacts with titanium film 109 to form C49 phase titanium silicide layer 21 across the boundary between silicon and titanium film 109. Is done. At the same time, in the fuse region, silicon (fuse polysilicon 51) and the titanium film 109 react to form a C49-phase titanium silicide layer 61 across the boundary between the silicon and the titanium film 109. . In other words, in the transistor region, the upper portion of silicon becomes the C49 phase titanium silicide layer 21, and at the same time, in the fuse region, the upper portion of silicon becomes the C49 phase titanium silicide layer 61.

After that, as shown in FIG. 5B, the titanium film remaining without reacting in the salicide process (unreacted titanium film) is removed by wet etching. For this wet etching, for example, an APM cleaning solution (NH ₄ OH / H ₂ O ₂ / H ₂ O) is used.
Next, the silicon substrate 1 from which the unreacted titanium film has been removed is subjected to a second heat treatment to change the phase of the titanium silicide film 21 in the transistor region from the C49 phase to the C54 phase, and at the same time, the titanium silicide film in the fuse region. 61 is changed from the C49 phase to the C54 phase. The treatment conditions for the second heat treatment are, for example, 800 ° C. or more and 900 ° C. or less and 40 seconds or more and 80 seconds or less in a nitrogen atmosphere. Note that the temperature of the second heat treatment is higher than the temperature of the first heat treatment.

As a result, as shown in FIG. 5C, the titanium silicide (C49-TiSi ₂ ) film 21 in the transistor region is changed to a C54 phase titanium silicide (C54-TiSi ₂ ) film 22. At the same time, the titanium silicide (C49-TiSi ₂ ) film 61 in the fuse region also changes to a C54 phase titanium silicide (C54-TiSi ₂ ) film 62. Here, the titanium silicide film 61 in the fuse region is made of a polysilicon film that is non-doped and at least the upper portion is made amorphous. Thereby, compared with the titanium silicide film 21 in the transistor region, the phase transition from the C49 phase to the C54 phase is promoted in the titanium silicide film 61 in the fuse region. Thereafter, the interlayer insulating film 81, the contact electrodes 83 and 84, and the wiring layers 93 and 94 shown in FIG. 1 are sequentially formed, and the semiconductor device 100 shown in FIG. 1 is completed.

  In this embodiment, the salicide block film 105 is removed from the silicon substrate 1 after the C49 phase titanium silicide films 21 and 61 are formed or after the C54 phase titanium silicide films 22 and 62 are formed. May be. Alternatively, the salicide block film 105 may be left on the silicon substrate 1 as it is. 5C and 1 show a case where the salicide block film 105 is removed from the silicon substrate 1 before the interlayer insulating film 81 is formed.

In addition, after the wiring layer 94 shown in FIG. 1 is formed, an arbitrary fuse element 50 is selected from the plurality of fuse elements 50. Then, a current is passed through the selected fuse element 50 to melt it. Thereby, the electrical characteristics of the semiconductor device 100 can be adjusted to a desired value. Alternatively, when a defective circuit, a defective cell, or the like exists in the semiconductor device 100, these can be replaced with a redundant circuit or a redundant cell.
In the first embodiment, the fuse polysilicon film 51 corresponds to the “fuse silicon film” of the present invention. Ar corresponds to the “rare gas element” of the present invention. Further, the resist patterns 101 and 103 correspond to the “protective film” of the present invention.

(Effect of 1st Embodiment)
The first embodiment of the present invention has the following effects.
(1) As described above, in the process of FIG. 4C, the titanium film 109 is formed on the fuse polysilicon film 51. In the step of FIG. 5A, the fuse polysilicon film 51 and the titanium film 109 are reacted by a first heat treatment to form a C49 phase titanium silicide film.

  Here, the fuse polysilicon film 51 that reacts with the titanium film 109 is non-doped, and at least the upper portion is amorphized, whereby the C49-phase titanium silicide film 61 that easily undergoes phase transition to the C54 phase. It is formed. The reason (mechanism) that the phase transition to the C54 phase easily proceeds by the non-doping and amorphization is not clear. The present inventor believes that the titanium silicide film 61 is formed in a film quality in which the C54 phase nuclei are likely to be generated (that is, the C54 phase nuclei density is likely to increase) by the above non-doping and amorphization. thinking. When the second heat treatment is performed on the titanium silicide film 61, a large number of C54 phase nuclei are generated in the film, and the C49 phase around the C54 phase nuclei changes to the C54 phase as the heat treatment time elapses. Eventually, the entire film is homogenized to the C54 phase. As a result, a C54 phase titanium silicide film 62 with low resistance and small variation in resistance value can be formed. In addition, this inventor conducted experiment and confirmed the effect of the variation reduction of this low resistance and resistance value. Experimental results are shown in the examples described later.

(2) Since the phase transition from the C49 phase to the C54 phase can be efficiently performed, the fuse polysilicon film 51 has a minute pattern (for example, the planar shape is rectangular, the length (L) is 0.7 μm, and the width ( Even if W) is 0.35 μm, etc., the C54 phase titanium silicide film 62 can be formed in each minute pattern. Thereby, since the fuse element can be blown with high reproducibility, it can contribute to the improvement of the yield of the semiconductor device.

(3) In the step shown in FIG. 4A, a rare gas element is ion-implanted into the fuse polysilicon film 51 in a state where the fuse polysilicon film 51 is exposed (that is, a state without a through film). At least the upper part of the fuse polysilicon film is amorphized. As will be described in the examples described later, it is possible to reduce variations in resistance values of the C54 phase titanium silicide film formed on the fuse polysilicon film by ion implantation of a rare gas element without a through film. It is.

Second Embodiment
In the first embodiment, as shown in FIG. 4A, Ar is ion-implanted into the fuse polysilicon film 51 in a state where the fuse polysilicon film 51 is exposed (that is, without a through film). Explained when to do. However, the present invention is not limited to this. A rare gas element may be ion-implanted into the fuse polysilicon film 51 in a state where the upper surface and side surfaces of the fuse polysilicon film 51 are covered with a through film (that is, a state with a through film).

(Production method)
6A to 6C are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.
In FIG. 6A, the process up to the step of forming the salicide block film 105 is the same as that of the first embodiment. In the second embodiment, after the salicide block film 105 is formed, as shown in FIG. 6B, the fuse polysilicon film 51 and its peripheral region are opened, and other regions (including transistor regions) are formed. A resist pattern 137 is formed on the silicon substrate 1 so as to cover the substrate. Then, a rare gas element is ion-implanted into the fuse polysilicon film 51 through the salicide block film 105 using the resist pattern 137 as a mask. That is, the salicide block film 105 is used as a through film, and a rare gas element is ion-implanted into the fuse polysilicon film 51 with the through film.

For example, when Ar is ion-implanted as a rare gas element, the implantation conditions are an implantation energy of 85 keV and a dose of 1 × 10 ¹⁴ atoms / cm ² or more. In the second embodiment, since Ar is ion-implanted into the fuse polysilicon film 51 through the salicide block film 105, the Ar implantation energy is set higher than in the first embodiment. The thickness of the salicide block film 105 is, for example, 500 mm. Even with such a method, at least the upper part of the fuse polysilicon film 51 can be made amorphous while maintaining the fuse polysilicon film 51 in a non-doped state. Thereafter, the resist pattern 137 is removed from the silicon substrate 1 as shown in FIG.

Next, as shown in FIG. 3C, the salicide block film 105 is patterned.
The subsequent steps are the same as in the first embodiment. That is, as shown in FIG. 4C, the titanium film 109 is formed. Then, by the first heat treatment, the C49 phase titanium silicide film 21 is formed in a self-aligned manner in the transistor region, and at the same time, the C49 phase titanium silicide film 61 is formed in a self-aligned manner in the fuse region.

Next, the unreacted titanium film is removed. Then, the C49 phase titanium silicide films 21 and 61 are phase-shifted to the C54 phase by the second heat treatment. Thereafter, the interlayer insulating film 81, the contact electrodes 83 and 84, and the wiring layers 93 and 94 shown in FIG. 1 are sequentially formed, and the semiconductor device 100 is completed.
In the second embodiment, the salicide block film 105 corresponds to the “through film” of the present invention. Other correspondences are the same as those in the first embodiment.

(Effect of 2nd Embodiment)
The second embodiment of the present invention has the same effects as the effects (1) and (2) of the first embodiment.
<Modification>
(1) In the first and second embodiments described above, Ar is exemplified as a rare gas element to be ion-implanted into the fuse silicon film. However, in the present invention, the rare gas element ion-implanted into the fuse silicon film is not limited to Ar. The rare gas element to be ion-implanted into the fuse silicon film may be, for example, neon (Ne), krypton (Kr), xenon (Xe), or the like. Also in this case, at least the upper part of the fuse silicon film can be made amorphous while maintaining the fuse silicon film in a non-doped state.

(2) In the second embodiment, the case where the upper surface and the side surface of the fuse polysilicon film 105 are covered with the salicide block film 105 is illustrated as a through film for ion implantation. However, in the present invention, when a rare gas element is ion-implanted into the fuse silicon film via the through film, the through film only needs to cover at least the upper surface of the fuse silicon film. That is, when a rare gas element is ion-implanted into the fuse silicon film through the through film, the side surface of the fuse silicon film may be exposed from the through film. Also in this case, at least the upper part of the fuse silicon film can be made amorphous while maintaining the fuse silicon film in a non-doped state.

(3) In the present invention, as shown in the first and second embodiments, it is preferable to execute a step of ion-implanting a rare gas element into the fuse silicon film. This is because the variation in resistance value of the titanium silicide film formed on the fuse silicon film can be remarkably reduced.
However, as shown in the examples described later, even when the Ar ion implantation step is omitted, if the fuse silicon film is non-doped, variation in the resistance value of the titanium silicide film can be reduced to some extent. Therefore, the step of ion-implanting a rare gas element into the fuse silicon film may be omitted, and an aspect in which this step is omitted is also included in the scope of the present invention.

Next, as an example of the present invention, an experiment conducted by the present inventor and its result will be described.
(1) Case without Through Film First, the result of an experiment in which Ar is ion-implanted without a through film into the fuse polysilicon film will be described. FIG. 7, FIG. 8, FIG. 10, and FIG. 11 described below are the results of experiments in which Ar ions were implanted without a through film. These were obtained by the following procedure. That is, a non-doped polysilicon film was patterned to form a fuse polysilicon film. Next, when ion-implanting Ar, ion implantation was performed on the fuse polysilicon film under a plurality of dose conditions. Then, a titanium film was formed on the fuse polysilicon film. Next, a first heat treatment was performed, followed by removal of the unreacted titanium film, and further a second heat treatment to form a titanium silicide film on the fuse polysilicon film. Thereafter, the sheet resistance of each formed titanium silicide film was measured. Through the above procedure, FIG. 7, FIG. 8, FIG. 10, and FIG. 11 were obtained.

FIG. 7 is a diagram showing the cumulative frequency distribution of sheet resistance according to the dose amount of Ar for a titanium silicide film (W / L = 0.35 μm / 0.7 μm) formed on a non-doped fuse polysilicon film. In FIG. 7, the horizontal axis represents the sheet resistance [Ω / □], and the vertical axis represents the cumulative frequency [%].
FIG. 8 is a diagram showing the cumulative frequency distribution of sheet resistance according to the dose amount of Ar for a titanium silicide film (W / L = 0.35 μm / 4.2 μm) formed on a non-doped fuse polysilicon film.

As shown in FIGS. 7 and 8, when Ar is ion-implanted into the non-doped fuse polysilicon film, the variation in sheet resistance is smaller than when Ar is not ion-implanted (that is, without Ar). confirmed. Further, as can be seen by comparing FIG. 7 and FIG. 8, it was confirmed that the variation in the sheet resistance of the titanium silicide film does not depend on the length (L).
FIGS. 9A and 9B show the cumulative frequency of sheet resistance of a titanium silicide film (W / L = 0.35 μm / 4.2 μm) formed on a fuse polysilicon film doped with phosphorus ions (P +). It is a figure which shows distribution according to the dose amount of Ar. FIG. 9B is an enlarged view showing the result surrounded by the frame line in FIG. 9A and 9B, the horizontal axis indicates the sheet resistance [Ω / □], and the vertical axis indicates the cumulative frequency [%]. FIGS. 9A and 9B are obtained by the following procedure.

  That is, a polysilicon film doped with an impurity P + was patterned to a width (W) of 0.35 μm and a length (L) of 4.2 μm to form a fuse polysilicon film. Next, when Ar is ion-implanted, ion implantation is performed on the fuse polysilicon film under a plurality of dose conditions. Subsequently, a titanium film is formed, and first and second heat treatments are sequentially applied to the titanium film. A silicide film was formed. When Ar is not ion-implanted (that is, without Ar), a titanium film is formed on a fuse polysilicon film doped with P + and not implanted with Ar, and first and second heat treatments are sequentially applied thereto. Thus, a titanium silicide film was formed. 9A and 9B were obtained by measuring the sheet resistance of each titanium silicide film.

As shown in FIGS. 9A and 9B, it is confirmed that when Ar is ion-implanted into the fuse polysilicon film doped with P +, the variation in sheet resistance is larger than when Ar is not implanted. did. In particular, when the dose amount of Ar was 5 × 10 ¹⁴ (5E + 14) or more, the variation in sheet resistance was large, and the occurrence of outliers was confirmed.
FIG. 10 shows the cumulative frequency distribution of the sheet resistance of the titanium silicide film (W / L = 0.35 μm / 3.5 μm) formed on the fuse polysilicon film according to the presence or absence of P + doping and the dose of Ar. It is a figure shown separately.

  As shown in FIG. 10, when P + is doped and Ar is not ion-implanted (ie, P + is present and Ar is not present), P + is not doped and Ar is not ion-implanted (ie, P + is absent and Ar is not present). Compared with, the sheet resistance variation of the titanium silicide film was large, and the occurrence of outliers was confirmed. In addition, this “no P +, no Ar” is more out of the sheet resistance variation of the titanium silicide film than the case where P + is not doped and Ar is ion-implanted (that is, no P +, Ar is present). It was confirmed that there were no liers. From the above, it has been confirmed that non-doping of the fuse polysilicon film is extremely important in reducing variation in the resistance value of the titanium silicide film.

Further, when Ar is ion-implanted into the non-doped fuse polysilicon film without the through film, the Ar implantation energy is 30 keV and the Ar dose is in the range of 3 × 10 ^{14 to} 7 × 10 ¹⁴ atoms / cm ² . Then, it was confirmed that variation in sheet resistance of the titanium silicide film can be reduced.
FIG. 11 shows the cumulative frequency distribution of the sheet resistance of the titanium silicide film (W / L = 0.35 μm / 3.5 μm) formed on the fuse polysilicon film according to the presence or absence of P + doping, and the Ar implantation energy. It is a figure shown separately. The two data “P + present, no Ar” and “P + absent, Ar absent” in FIG. 11 are the same data as in FIG. These two data are also shown in FIG. 11 for comparison with the other data shown in FIG.

As shown in FIG. 11, when Ar is ion-implanted into a non-doped fuse polysilicon film without a through film, the Ar dose is 5 × 10 ¹⁴ atoms / cm ² and the Ar implantation energy is 20 to 40 keV. If it was within the range, it was confirmed that no outlier was generated in the sheet resistance of the titanium silicide film.

(2) Case with Through Film Next, the result of an experiment in which Ar is ion-implanted with a through film into the fuse polysilicon film will be described. Note that FIGS. 12 and 13 shown below are obtained by the following procedure.
That is, a non-doped polysilicon film was patterned to form a fuse polysilicon film. Next, a through film (SiO ₂ film, 500 mm) was formed on the fuse polysilicon film. When Ar was ion-implanted, ion implantation was performed on the fuse polysilicon film under a plurality of dose conditions. Thereafter, the through film was removed, and a titanium film was formed on the fuse polysilicon film. Next, a first heat treatment was performed, followed by removal of the unreacted titanium film, and further a second heat treatment to form a titanium silicide film on the fuse polysilicon film. Thereafter, the sheet resistance of each formed titanium silicide film was measured. Through the above procedure, data shown in FIGS. 12 and 13 was obtained.

FIG. 12 shows the cumulative frequency distribution of the sheet resistance of the titanium silicide film (W / L = 0.35 μm / 3.5 μm) formed on the fuse polysilicon film according to the presence or absence of P + doping and the dose of Ar. It is a figure shown separately.
As shown in FIG. 12, the results with the through film were the same as those without the through film shown in FIG. That is, “P +, no Ar” had a larger variation in the sheet resistance of the titanium silicide film than “P + no, Ar”, confirming the occurrence of outliers. In addition, it was confirmed that “no P +, no Ar” was larger in variation in sheet resistance of the titanium silicide film than “no P +, Ar”, but no outlier was generated. When Ar is ion-implanted into a non-doped polysilicon film with a through film, the Ar implantation energy is 85 keV and the Ar dose is in the range of 6 × 10 ¹⁴ to 1 × 10 ¹⁵ atoms / cm ^2. If so, it was confirmed that no outlier was generated in the sheet resistance of the titanium silicide film.

FIG. 13 shows the cumulative frequency distribution of the sheet resistance of the titanium silicide film (W / L = 0.35 μm / 3.5 μm) formed on the fuse polysilicon film according to the presence or absence of P + doping and the Ar implantation energy. It is a figure shown separately. In the case with the through film, the same result as in the case without the through film shown in FIG. 11 was obtained.
That is, as shown in FIG. 13, when Ar is ion-implanted into a non-doped fuse polysilicon film with a through film, the Ar dose is 8 × 10 ¹⁴ atoms / cm ² and the Ar implantation energy is 75 to It was confirmed that the variation in sheet resistance of the titanium silicide film can be reduced within the range of 95 keV.

(3) Comparison with / without Through Film FIG. 14 is a diagram showing the relationship between variation in sheet resistance of the titanium silicide film and Ar implantation energy. The horizontal axis of FIG. 14 shows the Ar implantation energy, and the vertical axis shows the variation (standard deviation / average value) of the sheet resistance of the titanium silicide film. As shown in FIG. 14, it was confirmed that the variation in sheet resistance of the titanium silicide film without the through film does not depend on the implantation energy within the range of 20 to 35 keV. Similarly, it was confirmed that the variation in sheet resistance of the titanium silicide film with the through film was not dependent on the implantation energy within the range of 80 to 95 keV. Furthermore, it was confirmed that the sheet resistance variation of the titanium silicide film was smaller in the case without the through film than in the case with the through film.

FIG. 15 is a diagram showing the relationship between the variation in sheet resistance of the titanium silicide film and the dose of Ar. The horizontal axis of FIG. 15 indicates the dose amount of Ar, and the vertical axis indicates the variation in sheet resistance (standard deviation / average value) of the titanium silicide film. As shown in FIG. 15, the variation in the sheet resistance of the titanium silicide film without the through film is as follows when the dose amount of Ar is in the range of 3.0 × 10 ^{14 to} 5.0 × 10 ¹⁴ atoms / cm ² . It was confirmed that it did not depend on the dose. Similarly, regarding the variation in the sheet resistance of the titanium silicide film with the through film, the dose is reduced when the Ar dose is in the range of 6.0 × 10 ^{14 to} 1.0 × 10 ¹⁵ atoms / cm ^2. Confirmed that it does not depend.
From FIG. 14 and FIG. 15, it was confirmed that the sheet resistance variation of the titanium silicide film was smaller in the case without the through film than in the case with the through film.
[Others]
The present invention is not limited to the embodiments and modifications described above. Based on the knowledge of those skilled in the art, design changes or the like may be added to each embodiment or modification, and an aspect in which such changes or the like are added is also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Element isolation layer 10 MOS transistor 11 Gate insulating film 13 Gate electrode 15 Source layer 16 Drain layer 17 Side wall 21 Titanium silicide (C49-TiSi ₂ ) film 22 Titanium silicide (C54-TiSi ₂ ) film 50 Fuse element 51 Non-doped fuse polysilicon film 53 Side wall 61 Titanium silicide (C49-TiSi ₂ ) film 62 Titanium silicide (C54-TiSi ₂ ) film 81 Interlayer insulating film 83, 84 Contact electrodes 93, 94 Wiring layer 100 Semiconductor devices 101, 103, 107, 137 Resist pattern 105 Salicide block film 109 Titanium film

Claims (11)

Forming a titanium film on the non-doped fuse silicon film;
Subjecting the titanium film and the fuse silicon film to a first heat treatment to form a C49 phase titanium silicide film on the fuse silicon film;
Applying a second heat treatment to the titanium silicide film to cause the titanium silicide film to transition from the C49 phase to the C54 phase. Between the step of forming the fuse silicon film and the step of forming the titanium silicide film,
The method for manufacturing a fuse element according to claim 1, further comprising a step of ion-implanting a rare gas element into the fuse silicon film to amorphize at least an upper portion of the fuse silicon film. In the step of ion-implanting the rare gas element into the fuse silicon film,
The method for manufacturing a fuse element according to claim 2, wherein the rare gas element is ion-implanted into the fuse silicon film with the upper surface of the fuse silicon film exposed. In the step of ion-implanting the rare gas element into the fuse silicon film,
3. The method of manufacturing a fuse element according to claim 2, wherein the noble gas element is ion-implanted into the fuse silicon film in a state where at least an upper surface of the fuse silicon film is covered with a through film. Between the step of applying the first heat treatment and the step of applying the second heat treatment,
5. The fuse according to claim 1, further comprising: removing an unreacted titanium film that has not reacted with the fuse silicon film in the first heat treatment from the titanium silicide film. Device manufacturing method. In the step of ion-implanting the rare gas element into the fuse silicon film,
The method for manufacturing a fuse element according to any one of claims 1 to 5, wherein argon is used as the rare gas element, and an injection amount of the argon is set to 1 × 10 ¹⁴ atoms / cm ² or more.   The manufacturing method of a semiconductor device provided with the process of performing the manufacturing method of the fuse element as described in any one of Claims 1-6. A step of ion-implanting impurities toward the main surface side of the semiconductor substrate on which the fuse silicon film is formed between the start and end of the fuse manufacturing method,
8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of ion-implanting the impurity, the impurity is ion-implanted in a state where an upper surface and a side surface of the silicon film for fuse are covered with a protective film.   The method for manufacturing a semiconductor device according to claim 7, further comprising a step of flowing a current through a fuse element formed by executing the method for manufacturing the fuse element to melt the fuse element. Forming a titanium film on the non-doped silicon film;
Performing a first heat treatment on the titanium film and the silicon film to form a C49 phase titanium silicide film on the silicon film;
Applying a second heat treatment to the titanium silicide film to cause the titanium silicide film to transition from the C49 phase to the C54 phase. Forming a titanium film on the non-doped fuse silicon film;
Applying a first heat treatment to the titanium film and the fuse silicon film to form a titanium silicide film on the fuse silicon film;
Applying a second heat treatment to the titanium silicide film at a temperature higher than that of the first heat treatment.

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