JP2015180467A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of reducing the number of wires for connecting a group general control means with a group unit control means, and initializing the group general control means to restore a normal condition when a data transmission/reception failure occurs between the group general control means and the group unit control means.SOLUTION: The game machine includes game control means for generally controlling games and performance control means for performing performance of games in response to a command from the game control means. Initialization means comprises: first initialization means which initializes signal level control means by an initialization signal inputted to an initialization signal input terminal; and second initialization means which initializes the signal level control means by initialization instruction data written in an initialization instruction data storage region.

Description

The present invention relates to a gaming machine including a plurality of group unit control means for controlling the effect devices divided into groups and a group overall control means for controlling the plurality of group unit control means, and more particularly to an initialization method for the group unit control means.

As a gaming machine that can simplify the wiring between the sub relay board and the electrical decoration board, the top LED central board arranged in the center of the top electrical decoration area is serially connected to the sub relay board,
A gaming machine having a configuration in which a top LED right substrate disposed on the right side of the top illumination area and a top LED left substrate disposed on the left side of the top illumination area are separated from the top LED central substrate and connected by wiring. It has been. Thereby, the number of wirings from the sub relay board to the top illumination area can be reduced to simplify the wiring (for example, see Patent Document 1).

In addition, as a gaming machine that can reduce the number of signal lines and easily detect fraudulent activities, signal transmission between the main board and the sub board is performed by the I ² C bus method. Some boards and sub-boards are each provided with a bidirectional bus buffer. This bidirectional bus buffer is for bifurcating the two bidirectional serial lines (SDA, SCL) constituting the I ² C bus into two unidirectional serial lines, respectively. The bus buffer and the bidirectional bus buffer provided on the sub-board are connected by four serial lines so that the signal transmission directions of the one-way serial lines branched by them match each other ( For example, see Patent Document 2).

JP 2008-212271 A JP 2006-15036 A

In the gaming machine described in Patent Document 1, communication from the CPU 83 to the top LED substrate is performed by serial communication, but only data transmission in one direction from the CPU 83 to the top LED substrate is described.

For this reason, the gaming machine described in Patent Document 1 cannot guarantee that data is accurately transmitted from the CPU 83 to the top LED substrate. In particular, since gaming machines are often placed in an environment exposed to noise, decorative LEDs may not emit light as the game progresses under the influence of noise, which may reduce interest.

On the other hand, the gaming machine described in Patent Document 2 is configured to perform two-way communication between the main board and the sub board, but does not describe that data is correctly transmitted. .
For this reason, there is no guarantee that the gaming machine operates correctly. In addition, two data lines and one clock line are required for each of the upstream (from the main board to the sub board) and the down (from the sub board to the main board).
Wiring cannot be reduced sufficiently.

Further, since Patent Literature 1 and Patent Literature 2 do not disclose a technique for confirming the validity of data transmission / reception between substrates, a specific countermeasure is taken when an actual data transmission / reception failure occurs. I can't.

In addition to reducing the number of connection lines connecting the group overall control means and the group unit control means, the present invention causes a problem in data transmission / reception between the group overall control means and the group unit control means. An object of the present invention is to provide a gaming machine capable of initializing the group overall control means and returning it to a normal state.

A first invention is a game comprising game control means for comprehensively controlling a game, and effect control means for controlling a plurality of effect devices for effecting a game in response to a command from the game control means. In the machine, the plurality of effect devices are divided into a plurality of groups, group unit control means for controlling the effect devices belonging to the divided group is provided for each group, and the effect control means is provided for the plurality of groups. A group control unit configured to collectively control a unit control unit, a timing signal line for transmitting a timing signal from the group control unit to the group unit control unit, and the group control unit and the group unit control unit The group control unit and the group unit control unit are connected to each other by a data line that communicates data with each other. Data communication between the group overall control means and each group unit control means is enabled, and the group overall control means includes arithmetic processing means for performing arithmetic processing related to control of the rendering device, and the arithmetic processing means. And a data bus for exchanging data between the arithmetic processing means and the signal level control means, based on a command from the signal level control means for controlling the signal levels of the data line and the timing signal line. When,
And the signal level control means repeatedly sets the signal level of the timing signal line while setting the signal level of the data line to a signal level corresponding to transmission data based on a transmission command from the arithmetic processing means. A transmission unit that sequentially transmits data to the group unit control unit by changing, a response signal capturing unit that captures a response signal from the group unit control unit after data transmission by the transmission unit, and the response signal A determination unit that determines success or failure of data transmission by a response signal captured by the capture unit, an initialization unit that initializes the signal level control unit, and the initialization unit via the data bus An initialization instruction data storage area in which initialization instruction data for instructing initialization of the signal level control means is written; An initialization signal input instruction terminal that is provided separately from the data bus and receives an initialization signal that instructs the initialization means to initialize the signal level control means; and the group unit control means Comprises response signal output means for outputting the response signal to the group overall control means via the data line on which the transmission means has transmitted data, and the initialization signal input instruction terminal is the arithmetic processing means. The initialization signal is input without going through the data bus from a predetermined output port, and the initialization unit receives the initialization signal by inputting the initialization signal to the initialization signal input terminal. First initialization means for initializing the signal level control means, and the initialization instruction data is written in the initialization instruction data storage area, whereby the signal level control means Characterized in that it comprises a second initialization means for initializing, the.

According to a second aspect of the present invention, the group overall control means includes a plurality of the signal level control means, and the arithmetic processing means and the plurality of signal level control means are connected by the data bus, and the arithmetic processing means When the initialization signal output from is input to the initialization signal input terminal provided in the plurality of signal level control means and all of the plurality of signal level control means are initialized, each signal level Using the first initialization means provided in the control means,
When all the signal level control means are initialized and only some signal level control means are initialized among the plurality of signal level control means, the signal level control means provided in the part of the signal level control means By writing the initialization instruction data in the initialization instruction data storage area,
The partial signal level control means is initialized.

According to a third aspect of the present invention, the group overall control unit includes an abnormality detection unit that detects a signal level control unit in which an abnormality has occurred from the plurality of signal level control units based on a determination result of the determination unit. The signal level control means detected by the abnormality detection means is initialized using the second initialization means provided in the signal level control means.

According to a fourth aspect of the present invention, when the signal control unit is initialized, the group overall control unit instructs all group unit control units controlled by the signal level control unit to perform initialization. Features.

According to a fifth aspect of the present invention, the group of effect devices includes a group of light emitting devices that decorates a gaming machine by emitting light, and a group of movable devices that decorates a gaming machine by moving a movable member provided in the gaming machine. And the group unit control means includes: a light emitting group unit control means for controlling the group of the light emitting devices; and a movable group unit control means for controlling the group of the movable devices. Initializes all of the signal level control means provided in the group overall control means by means of first initialization means provided in each signal level control means when a predetermined condition is satisfied, and each signal level control means The group unit control means connected to the unit is instructed to initialize, and the light emitting group unit control means is the group overall control means. When the initialization is instructed, the output state of the light emitting device controlled by the light emitting group unit control unit is controlled so as not to output, and the movable group unit control unit is instructed to initialize by the group overall control unit. If the movable group unit control means controls the movable member to return the movable member to the initial position, the movable device performs an initial position operation, and the movable member is movable even while the movable member is returned to the initial position. A signal level control unit different from the signal level control unit connected to the group unit control unit starts transmission of light emission control data to the group unit control unit.

According to a sixth aspect of the present invention, the group of effect devices includes a group of light emitting devices that decorates a gaming machine by emitting light, and a group of movable devices that decorates a gaming machine by moving a movable member provided in the gaming machine. The group unit control means includes a light emission group unit control means for controlling the group of the light emitting devices, and a movable group unit control means for controlling the group of the movable devices, and the abnormality detection means is When the determination means determines that data transmission to the movable group unit control means has failed, an abnormality of the signal level control means connected to the movable group unit control means is detected, and the group overall control means The second initialization provided in the signal level control means includes the signal level control means in which the abnormality is detected by the abnormality detection means. The group unit control means connected to the signal level control means is instructed to initialize, and the light emission group unit control means is instructed to initialize from the group overall control means. The light emitting group unit control means controls the output state of the light emitting device to be in a non-output state, and when the movable group unit control means is instructed to initialize by the group overall control means, the movable group In order to return the movable member controlled by the unit control means to the initial position, the movable device performs the initial position operation, and even while the movable member is returned to the initial position, the movable group unit control means is connected. The signal level control means different from the signal level control means to be continued to transmit the light emission control data to the group unit control means. And features.

According to the first invention, the group overall control means transmits data to the group unit control means via one data line, and a response signal is also sent from the group unit control means to the group overall control means via the same data line. Since it is transmitted, the wiring between the substrates can be reduced. Further, since a response signal is transmitted from the group unit control means to the group overall control means via the data line, it is possible to confirm whether data transmission has been performed, thereby preventing malfunction.
Furthermore, immediately after data is transmitted from the group overall control means to the group unit control means, a response signal is transmitted from the group unit control means to the group overall control means, so that high-speed data communication is possible. Furthermore, the first initialization unit that does not pass through the data bus and the second initialization unit that passes through the data bus can be selectively used depending on the situation.

According to the second aspect of the invention, when all the group general control means are initialized, the initialization is performed using the first initialization means provided in each group general control means, so that the specific group general control means is identified. Compared with the case of using the second initialization means provided in the group overall control means, initialization can be performed at a higher speed. Also, when initializing a specific group overall control means, initialization is performed using the second initialization means provided in the specific group overall control means, so that initialization signal input terminals of all the group overall control means There is no need for a circuit for inputting an initialization signal individually. That is, in the second invention, the initialization of all the group overall control means is aimed at speeding up, and the initialization of the specific group overall control means is aimed at simplifying the circuit. This is effective when the number of group overall control means is large.

According to the third aspect of the invention, since only the group overall control means in which an abnormality is detected is initialized using the second initialization means provided in the group overall control means, the group overall control means in which no abnormality is detected is initialized. It does not have to be converted.

According to the fourth invention, when the group overall control means is initialized, the group unit control means controlled by the group overall control means can also be initialized, so that the gaming machine can be initialized reliably.

According to the fifth invention, since the light emitting device operates even when the movable member is being returned to the initial position immediately after the power is turned on, the time from when the power is turned on until the light emitting device is turned on is shortened. The time required for checking the light emitting device immediately after power-on can be reduced.

According to the sixth aspect of the invention, even if the time until the movable member returns to the initial position becomes long or the movable member is being returned to the initial position, the other group overall control means performs group unit control. Since the means is controlled, the light emitting device does not turn off. For this reason, even if abnormalities such as noise occur and the movable member frequently returns to the initial position, it is possible to suppress as much as possible that the board surface of the gaming machine becomes dark.

It is explanatory drawing of the game machine of 1st Embodiment of this invention. It is a front view of the game board of a 1st embodiment of the present invention. It is a block diagram which shows the structure of the game machine of 1st Embodiment of this invention. It is a block diagram which shows the structure of the presentation control apparatus of 1st Embodiment of this invention. It is explanatory drawing of the connection of the decoration control apparatus of 1st Embodiment of this invention. It is a block diagram of the decoration control apparatus of 1st Embodiment of this invention. 1 is a block diagram of an I ² CI / O expander according to a first embodiment of this invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device that controls the decoration device of the first embodiment of the present invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device that controls the accessory driving MOT and the accessory driving SOL of the first embodiment of the present invention. It is a circuit diagram of the connection line regarding the input / output of the relay board | substrate of 1st Embodiment of this invention. It is a circuit diagram of the connecting line regarding the input / output of the decoration control apparatus of 1st Embodiment of this invention. It is explanatory drawing of the slave address contained in the data output to the decoration control apparatus from the presentation control apparatus of 1st Embodiment of this invention. It is an explanatory view of I ² CI / O expander address table of the first embodiment of the present invention. It is a diagram for explaining the I ² CI / O Aix work register assigned to the output setting register provided in expander of the first embodiment of the present invention. It is explanatory drawing of the start condition and stop condition of the data which the master IC of 1st Embodiment of this invention outputs via the connection line SDA and the connection line SCL. It is a timing chart which the decoration control apparatus into which the data output from the master IC of 1st Embodiment of this invention was input outputs a reply signal. It is a timing chart of the signal level of the connection line SDA and the connection line SCL when the master IC of the first embodiment of the present invention outputs effect control data. When the master IC according to the first embodiment of the present invention designates the individual address of the slave and sets the effect control data in the decoration control device, it is exchanged between the master IC and the I ² CI / O expander. It is a figure explaining the format of data. When the master IC according to the first embodiment of the present invention designates the individual address of the slave and sets the effect control data in the decoration control device, it is exchanged between the master IC and the I ² CI / O expander. Specific numerical values are applied to the production control data. It is a figure explaining another form of presentation control data of a 1st embodiment of the present invention. FIG master IC of the first embodiment is to initialize the I ² CI / O expander, illustrating the data format of the initialization instruction data transmitted to I ² CI / O expander from the master IC of the present invention It is. It is a figure explaining the abnormality determination table of 1st Embodiment of this invention. It is a flowchart of the process by the presentation control apparatus of 1st Embodiment of this invention. It is a flowchart of the I ² C initial reset process of the first embodiment of the present invention. It is a flowchart of the slave reset process of 1st Embodiment of this invention. It is a flowchart of the light emission control slave output process of 1st Embodiment of this invention. It is a flowchart of the slave continuous processing of 1st Embodiment of this invention. It is a flowchart of an I ² C occasional reset process according to the first embodiment of the present invention. It is a flowchart of the timer interruption process performed when the timer interruption of 1st Embodiment of this invention generate | occur | produces. It is a flowchart of the slave single output process of 1st Embodiment of this invention. It is a figure which shows the connection form of the decoration control apparatus provided in the whole gaming machine of the 1st Embodiment of this invention. It is explanatory drawing of the connection of the presentation control apparatus and decoration control apparatus of 2nd Embodiment of this invention. It is explanatory drawing of the abnormality determination table of 2nd Embodiment of this invention. It is a flowchart of the I2C initial reset process of ^2nd Embodiment of this invention. It is a flowchart of an I ² C occasional reset process of the second embodiment of the present invention. It is a timing chart before and after initialization of the master IC by power-on according to the second embodiment of the present invention. It is a timing chart before and after initialization of the master IC in which the abnormality of the second embodiment of the present invention has occurred.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is an explanatory diagram of the gaming machine 1 according to the first embodiment of the present invention.

A front frame (game frame) 3 of the gaming machine 1 is assembled to a main body frame (outer frame) 2 via a hinge 4 so as to be openable and closable on the front surface of the gaming machine 1. A game board 10 (see FIG. 2) is accommodated on the front side of the front frame 3. Further, a glass frame 18 having a cover glass (transparent member) covering the front surface of the game board 10 is attached to the front frame 3.

A decorative member 9 that emits decorative light is provided around the cover glass of the glass frame 18. Inside the decorative member 9 is a decorative device 620 (see FIG. 3) made of a lamp, LED, or the like.
Is provided. The decoration device 620 emits light in a predetermined light emission mode, so that the decoration member 9 emits light in a predetermined light emission mode.

Speakers 30 that emit sound (for example, sound effects) are provided on the left and right sides of the glass frame 18. An illumination unit 11 is provided above the glass frame 18. Inside the lighting unit 11, the above-described decoration device 620 is provided.

On the right side of the lighting unit 11, an abnormality notification LED 29 for notifying that an abnormality has occurred in the gaming machine 1 is provided.

The open / close panel 20 below the front frame 3 is provided with an upper tray 21 for supplying game balls to a not-shown ball hitting device, and the fixed panel 22 is provided with an ashtray 15, a lower plate 23, an operation unit 24 of the hit ball launching device and the like. . The lower plate 23 has a lower plate ball removing mechanism 16 for discharging the game balls stored in the lower plate 23.
Is provided. A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

Further, when the player turns the operation unit 24, the hitting ball launching device launches a game ball supplied from the upper plate 21.

In addition, an effect button 1 for accepting an operation input from a player is provided on the upper edge of the upper plate 21.
7 is provided.

The display device 5 provided on the game board 10 when the player operates the effect button 17.
3 (see FIG. 2), it is possible to select an effect content of the special figure variation display game and produce an effect in which the player's operation is intervened in the special figure variation display game on the display device 53.

In addition, in the special figure variation display game, the launched game ball is awarded to the first start winning opening 45 (see FIG. 2) provided in the game board 10 or the second starting winning opening of the normal variation winning apparatus 36 (see FIG. 2). It starts when you do. In the special figure fluctuation display game, a plurality of pieces of identification information are variably displayed on the display device 53. Then, when the identification information that has been variably displayed is stopped and the result mode of the stopped identification information is a specific result mode, the state of the gaming machine 1 is advantageous to the player (a state where a privilege is granted) Transition to a special gaming state.

In the upper right portion of the upper plate 21, a ball lending button 26 that is operated when a player borrows a game ball and a discharge button 27 that is operated to discharge a prepaid card from a card unit (not shown) are provided. . Between these buttons 26 and 27, a balance display unit 28 for displaying the balance of the prepaid card is provided.

  FIG. 2 is a front view of the game board 10 according to the first embodiment of the present invention.

The gaming machine 1 shown in FIG. 1 fires a game ball in an internal game area 10a (bounces it) to play a game, and a game area 10a is provided on the back side of the cover glass of the glass frame 18. The game board 10 which comprises is installed.

The game board 10 includes a flat game board main body 10b (made of wood or synthetic resin) serving as a mounting base for various members, and the game area 10 surrounded by a guide rail 32 on the front surface of the game board main body 10b.
a. In addition, on the outside of the guide rail 32 on the front surface of the game board main body 10b,
Front structural members 33, 33,... Are attached. Then, a game ball (hit ball; game medium) is launched from the launching device into the game area 10a surrounded by the guide rail 32 to play a game.

A center case 51 that forms a window 52 serving as a display area for a special figure variation display game is attached to the approximate center of the game area 10a. Behind the window portion 52 formed in the center case 51, a display device 53 is provided as an effect display device capable of executing an effect of a special figure variable display game that displays a plurality of identification information in a variable manner. ing. The display device 53 includes:
For example, a display unit 53 a that includes a liquid crystal display and whose display contents can be changed is arranged so as to be visible from the front side of the game board 10 through the window 52 of the center case 51. Note that the display device 53 is not limited to a device including a liquid crystal display, and may include a display such as an EL or a CRT.

Near the upper end of the window 52 of the center case 51, a movable accessory 60 that can be operated based on the gaming state is attached.

In addition, the game board 10 is provided with a general map start gate 34, a general map storage display 47 for displaying the number of unprocessed times of the general map change display game, and a general map display 35 for displaying the general map change display game. ing. Further, in the game area 10a, a first start winning opening 45 forming a first start winning area,
An ordinary variable prize winning device 36 having a second start prize opening that forms a second start prize area is provided. When the game ball has won the first start winning opening 45, the first special figure variation display game is executed as an auxiliary game, and when the game ball has won the normal variation prize winning device 36, the second game is performed as an auxiliary game. A special figure variation display game is executed.

Further, the game board 10 is provided with a first special figure display 38 for displaying the first special figure fluctuation display game, and a second special figure display 39 for displaying the second special figure fluctuation display game. Yes. The first
First special figure memory display 4 for displaying the number of unprocessed special figure fluctuation display games (first special figure start memory)
8 and a second special figure memory display 49 for displaying the number of unprocessed times (second special figure start memory) of the second special figure fluctuation display game. It should be noted that the common figure memory display 47, the universal figure display 35, the first special figure display 38, the second special figure display 39, the first special figure storage display 48, and the second special figure storage display 49 are: Together with a game state display LED (not shown) representing the game state, it is integrally provided as a segment LED.

Furthermore, the game area 10a has an attacker-type opening / closing door 42a that can be opened by rotating in a direction in which the upper end side is tilted toward the front side, and the first special figure variation display game and the second special figure variation display game. As a result, the special variable winning device 42 for converting the closed state (a disadvantageous state for the player) from the closed state (a disadvantageous state for the player) to the open state (a state advantageous for the player), and the game balls that have not won the winning point etc. An out-hole 43 to be collected is provided. In addition, the game area 10a is provided with general winning holes 44, 44,..., A windmill 46 as a batting direction changing member, a number of obstacle nails (not shown), and the like.

A gate SW 34a (see FIG. 3) for detecting a game ball that has passed through the general chart start gate 34 is provided in the general chart start gate 34. Then, when the game ball that has been driven into the game area 10a passes through the usual figure start gate 34, a usual figure change display game is performed.

In addition, when the game ball passes through the general chart start gate 34 in a state in which the normal map change display game cannot be started, if the general chart start memory number is less than the upper limit number, the general chart start memory number is incremented by one. ,
One random number indicating whether or not the normal figure change display game is won is stored as a normal figure start memory.

The state in which the normal map variable display game cannot be started is, for example, a state in which the normal map variable display game has already been executed and the normal map variable display game has not ended, or the normal variable display game has been hit and the normal variable prize winning device This is a state where 36 is converted to an open state.

In addition, the starting memory | storage number of a common figure change display game is displayed on the common figure memory | storage display 47 provided with LED.

The normal map display game is executed by a general map display 35 provided on the game board 10. In addition, you may make it display a common figure change display game in a part of display area of the display apparatus 53, In this case, for example, a number, a symbol, a character design etc. are used as an identification design, and this identification design is predetermined. After the time variation display, the display is stopped.

If the stop display of the normal variation display game becomes a special result mode, the normal variation display game is a hit, and the opening / closing members 36a and 36a of the normal variation winning device 36 are set for a predetermined time (for example, 0).
.5 seconds) Thereby, it becomes easy to win a game ball in the normal variation winning device 36, and the start of the second special figure variation display game is facilitated.

The normal variation winning device 36 includes a pair of left and right opening / closing members 36 a and 36 a and is disposed below the first start winning port 45. The open / close members 36a, 36a always maintain a closed state (an unfavorable state for the player) with an interval of about the diameter of the game ball. When it becomes a mode (when a normal fluctuation display game is a win), it is opened in a reverse “C” shape by a solenoid (Fuden SOL 36b, see FIG. 3) as a driving device, and a normal fluctuation prize is won. The device 36 can be changed to a state in which a game ball easily flows into the device 36 (a state advantageous to the player).

In addition, the gaming machine 1 according to the present embodiment, based on the result form of the special figure variation display game, as a gaming state, a short-time operation state (second operation state) that shortens the variation display time of the special figure variation display game on the display device 53. ) Can be generated. At this time, the short operation state (second operation state) is a state in which the operation state of the normal variation winning device 36 is more likely to be an open state than the normal operation state (first operation state).

At this time, in the short operation state, the execution time of the above-mentioned general-purpose variable display game is controlled to be shorter than the long execution time in the normal operation state (for example, 10 seconds is 1 second). The number of times of opening of the normal variation winning device 36 is controlled to be substantially increased. Further, in the short-time operation state, when the normal variation winning game 36 is released as a result of the normal variation display game being won, the release time is controlled to be longer than the short release time of the normal operation state. (For example, 0.3 seconds is 1.8 seconds). In the short-time operation state,
The normal variation winning device 36 is not one time for one hit result of the normal variation display game,
Opened multiple times (for example, twice). Further, in the short-time operation state, the probability that the hit result of the normal-variable display game is higher than that in the normal operation state is controlled. That is, the number of times of opening of the normal variation winning device 36 is increased as compared to the normal operation state, and it becomes easier for the game ball to win the normal variation winning device 36, and the second special figure variation display game can be easily started.

A first start opening SW45a (see FIG. 3) is provided in the first start winning opening 45, and based on detecting a game ball by the first start opening SW45a, a first special figure variation display as an auxiliary game is provided. A starting right to start the game is generated. In addition, the normal variation winning device 36 is provided with a second start port SW36d (see FIG. 3), and this second start port SW3.
Based on the detection of the game ball by 6d, the right to start the second special figure variation display game as an auxiliary game is generated.

The right to start the first special figure variation display game is stored as a first start memory (special figure 1 start memory) within a predetermined upper limit number (for example, 4). The first start memory number is displayed on the first special figure memory display 48. The start right for starting the second special figure variation display game is stored as the second start memory (special figure 2 start memory) within a predetermined upper limit number (for example, 4). The second start memory number is displayed on the second special figure memory display 49.

When the first special figure variation display game can be started (the first start memory number and the second start memory number are 0) and the game ball wins the first start winning opening 45, the start right is generated. The random number extracted with is stored as the first start memory, the first start memory number is incremented by 1, and the first special figure variation display game is immediately started based on the first start memory, At this time, 1 is subtracted from the first start memory number.

In addition, since the second special figure fluctuation display game is executed in preference to the first special figure fluctuation display game, even if the first start memory number is not zero, if the second start memory number is zero, When the game ball wins the normal variation winning device 36 that forms the second start winning opening, the random number extracted with the start right is stored as the second start memory, and the second start memory number is incremented by one. At the same time, the second special figure variation display game is started based on the second start memory immediately after the execution of the first special figure variation display game being executed, and at this time, the second start memory number is decremented by one.

On the other hand, a state in which the first special figure fluctuation display game or the second special figure fluctuation display game cannot be started immediately, for example, the first special figure fluctuation display game or the second special figure fluctuation display game has already been performed, and the special figure fluctuation display. If a game ball is won in the first start winning opening 45 when the game is not finished or in a special game state, if the first start memory number is less than the upper limit number (for example, less than four) The first start memory number is incremented by 1, and one random number extracted at the timing when the game ball is won in the first start winning opening 45 is stored as the first start memory.

Similarly, in this case, when a game ball wins the normal variation winning device 36 that forms the second starting winning opening, if the second starting stored number is less than the upper limit number (for example, less than four), the second starting stored number is 1 is added, and one random number extracted at the timing when the game ball wins the second start winning opening is stored as the second start storage.

When the first special figure fluctuation display game or the second special figure fluctuation display game is ready to start, the first special figure fluctuation display game or the second special figure fluctuation display is based on the first start memory or the second start memory. The game starts. At this time, the first special figure fluctuation display game and the second special figure fluctuation display game are not executed simultaneously, and the second special figure fluctuation display game is executed with priority over the first special figure fluctuation display game. It is like that.

That is, when there is a first start memory and a second start memory, the second special figure variation display game is executed.

The first special figure change display game and the second special figure change display game as the auxiliary game are executed by the first special figure display 38 and the second special figure display 39 provided on the game board 10. After a plurality of pieces of identification information are variably displayed, a predetermined result mode is stopped and displayed. In addition, a special figure fluctuation display game is executed in which a plurality of types of identification information (for example, numbers, symbols, character designs, etc.) are variably displayed on the display device 53 corresponding to each special figure fluctuation display game. And as a result of this special figure fluctuation display game, the first special figure display 38 or the second special figure display 39
When the display mode becomes a special result mode, a special game state (so-called jackpot state) is set. Correspondingly, the display mode of the display device 53 is also a special result mode (for example, any one of the numbers in the flat order such as “7, 7, 7”). The game machine may not be provided with the first special figure display 38 and the second special figure display 39, and the special figure variation display game may be executed only by the display device 53.

In addition, the gaming machine 1 of the present embodiment can generate a probability variation state (second probability state) as a gaming state based on the result mode of the special figure variation display game. This probability variation state (second probability state)
Is a state in which the probability of a hit result in the special figure variation display game is higher than the normal probability state (first probability state). It should be noted that the first special figure fluctuation display game and the second special figure fluctuation regardless of whether the first special figure fluctuation display game or the second special figure fluctuation display game results in the result mode of the special figure fluctuation display game. Both display games are in a probable state. In addition, the probability variation state and the short-time operation state described above can be generated independently, and both can be generated simultaneously,
It is also possible to generate only one.

  FIG. 3 is a block diagram showing a configuration of the gaming machine 1 according to the first embodiment of the present invention.

The gaming machine 1 includes a game control device 500 that controls the game in an integrated manner, an effect control device 550 that controls the display device 53 and the speaker 30 to perform various effects, and a payout motor (not shown) for paying out game balls. A payout control device 580 for controlling is provided.

First, the game control device 500 will be described. In FIG. 4, the effect control device 550 will be described.

The game control device 500 includes a game microcomputer 501 and an input I / F (Interface) 5.
05, an output I / F (Interface) 506, and an external communication terminal 507.

The gaming microcomputer 501 includes a CPU 502 and a ROM (Read Only Memory).
) 503 and RAM (Random Access Memory) 504.

The CPU 502 is a main control device that controls the game in an integrated manner, and controls the game. RO
M503 stores invariant information (program, data, etc.) for game control. R
The AM 504 is used as a work area during game control.

The external communication terminal 507 connects the game control device 500 to an external device such as an inspection device that inspects the setting information of the game control device 500.

The CPU 502 receives various input devices (a first start port SW45a, a second start port SW36d, a general winning port SW44a, a gate SW34a, a count SW42d, via an input I / F 505).
Upon receiving detection signals from the glass frame opening SW 18a, the front frame opening SW 3a, the ball break SW 54, the vibration sensor 55, and the magnetic sensor 56), various processes such as a big hit lottery are performed.

The first start port SW 45 a is a switch that detects that a game ball has won the first start winning port 45. The second start port SW 36 d is a switch that detects that a game ball has won a second start winning port of the normal variation winning device 36.

The general winning openings SWa 44 a to 44 n are switches that detect that a game ball has won the general winning opening 44. The gate SW 34a is a switch that detects that a game ball has passed through the usual start gate 34.

The count SW 42d is a switch that detects that a game ball has won a special winning opening of the special variable winning device 42.

The glass frame opening SW 18a is a switch that detects that the glass frame 18 has been opened. The front frame opening SW 3a is a switch for detecting that the front frame 3 is opened.

The ball cut SW 54 is a switch that detects that the number of game balls stored in the gaming machine 1 and used for payout has become a predetermined number or less.

The vibration sensor 55 is a sensor that detects a vibration applied to the gaming machine 1 and detects a fraud that improperly acquires a gaming ball by applying a vibration to the gaming machine 1. The magnetic sensor 56 includes the first start winning port 45, the second starting winning port of the normal variation winning device 36, the general winning port 44, and the special variable winning device 4.
2 is a sensor that detects magnetic force and is provided in the vicinity of the two prize winning openings and the normal start gate 34.
The magnetic sensor 93 detects a fraud that brings a magnet close to each winning hole and guides a game ball launched to the gaming area 10a to each winning hole.

In addition, the CPU 502 receives the first special figure display 38, the first special figure storage display 48, the second special figure display 39, the second special figure storage display 49, and the common figure display via the output I / F 506. 35, Fudenden S
A command signal is transmitted to the OL 36b, the special winning opening SOL42b, the payout control device 580, and the effect control device 550 to control the game in an integrated manner.

The first special figure display 38 displays a first special figure fluctuation display game that is executed as an auxiliary game when a game ball wins the first start winning opening 45. The first special figure memory display 48 displays a first start memory number that is a right to start the first special figure variable display game stored within a predetermined upper limit number range.

The second special figure display 39 displays a second special figure fluctuation display game that is executed as an auxiliary game when a game ball wins a big winning opening of the normal fluctuation winning device 36. Second special figure memory display 4
In 9, a second start memory number that is a start right to start the second special figure variable display game stored within the range of the predetermined upper limit number is displayed.

The general map display 35 displays a general map change display game that is performed when the game ball passes the general map start gate 34.

The general electric power SOL 36b opens the opening and closing members 36a, 36a when the stop display of the general variable display game executed on the general display display 35 becomes a special result mode, and the normal variable prize winning device 36 is opened.
The second starting winning opening is made in a state where the game ball can easily win.

The special winning opening SOL42b opens the open / close door 42a of the special variable winning device 42 when the result of the first special figure fluctuation display game or the second special figure fluctuation display game becomes a special result mode and becomes a special game state. Then, the big winning opening is converted into a state in which the game ball is easy to win.

In addition, the game control device 500 outputs the gaming machine data to a game hall management device (not shown) via an external information terminal 508 and an information collection terminal device (not shown). The gaming hall management device is a computer that collects and manages gaming data of the gaming machines 1 installed in the gaming hall.

In addition, the payout control device 580 pays out the number of game balls corresponding to the winning winning opening when the gaming ball wins the general winning opening 44 or the big winning opening, or the ball lending button 26 is operated. When a payout command for paying out a predetermined number of game balls is received from the game control device 500, a payout motor (not shown) is controlled based on the received payout command. The payout command includes the number of game balls to be paid out.

The game control device 500 uses a change start command, a customer waiting demo command, a fanfare command, a probability information command, an error designation command, and the like as game data indicating the game situation via the output I / F 506, and the effect control device 550. Send to.

FIG. 4 is a block diagram showing a configuration of the effect control device 550 according to the first embodiment of the present invention.

The effect control device 550 determines the contents of the effect based on the game data (display control command) input from the game control device 500, controls the display device 53 and the speaker 30, and via the decoration control device 610. Decoration device 620, accessory drive SOL560 (solenoid)
, And the accessory driving MOT (motor) 561 is controlled. Although details will be described later, the decoration device 620, the accessory driving SOL 560, and the accessory driving MOT 561 (collectively referred to as a production device).
As a result, the game is produced. The effect control device 550 receives a signal indicating that the effect button 17 has been operated from the effect button 17.

The production control device 550 includes a CPU 551, a control ROM 552, a RAM 553, and an image ROM.
554, sound ROM 555, VDP 556, sound LSI 557, input / output I / F 558, power-on detection circuit 559, master IC 570, and NOR gate circuit 590.

The CPU 551 is connected to the game control device 500, receives a command signal from the game control device 500 as an interrupt signal (INT), and is a main control device that controls various effects based on the input command signal. In addition, an interrupt signal is input to the CPU 551 from a controller of the master IC 570 which will be described later, and an interrupt signal is input from the VDP 556.

When an interrupt signal is input to the CPU 551, the CPU 551 interrupts the process currently being executed and executes a process corresponding to the input interrupt signal.

The control ROM 552 stores invariant information (program, data, etc.) for effect control. The RAM 553 is used as a work area during production control.

The image ROM 554 stores image data to be displayed on the display device 53, and the image ROM
554 is connected to the VDP 556. The sound ROM 555 stores sound data output from the speaker 30, and the sound ROM 555 is connected to the sound LSI 557.

The VDP 556 is a processor that controls image output to the display device 53. Sound LSI5
Reference numeral 57 denotes a circuit that controls the sound output from the speaker 30.

Note that the VDP 556 includes synchronization signal generation means for generating a synchronization signal that is synchronized with a cycle (33 ms cycle) for updating an image displayed on the display device 53. Every time the synchronization signal is generated, the synchronization signal generation means inputs the generated synchronization signal to the CPU 551 as an interrupt signal.

The input / output I / F 558 is an interface connected to the effect button 17, the motor position detection sensor 510, and the NOR gate circuit 590, an operation signal from the effect button 17, and a motor position detection signal from the motor position detection sensor 510. Is transmitted to the CPU 551 and a reset signal from the CPU 551 is transmitted to the NOR gate circuit 590.

The effect button 17 is provided on the upper edge portion of the upper plate 21 and is operated by the player in an effect in the first special figure fluctuation display game or the second special figure fluctuation display game executed on the display device 53. .

The motor position detection sensor 510 outputs a motor position detection signal when it is detected that the rotation shaft of the accessory driving MOT 561 has rotated to the initial position.

Note that the NOR gate circuit 590 includes a RSE provided in the controller of the master IC 570.
Connected to the T terminal and other circuits that require initialization. Other circuits that require initialization include, for example, the VDP 556 and the sound LSI 557. These are the production control device 550.
When the power is turned on and started up, the CPU 551 initializes it.

The CPU 551, VDP 556, RAM 553, control ROM 552, sound LSI 557, and input / output I / F 558 are connected via a bus 563.

The power-on detection circuit 559 detects the master I when the production control device 550 is powered on.
A reset signal that initializes a register (not shown) of C570 to a default state (all 0s) is generated, and the generated reset signal is output to the NOR gate circuit 590.

The CPU 551 outputs a reset signal to the input / output I / F 558 via the bus 563 when a predetermined condition is satisfied, and the input / output I / F 558 outputs the input reset signal to NO.
Output to the R gate circuit 590.

Note that the reset signal input from the power-on detection circuit 559 to the NOR gate circuit 590 and the reset signal input from the CPU 551 to the NOR gate circuit 590 via the input / output I / F 558 are in a low level state in any case. Function as a signal to command resetting. Therefore, if at least one of the power-on detection circuit 559 and the CPU 551 outputs a reset signal to the NOR gate circuit 590, the reset signal is input to the master IC 570 via the NOR gate circuit 590.

As described above, since the NOR gate circuit 590 is connected to the master IC 570 and other circuits that require initialization, when a reset is input to the NOR gate circuit 590, the master IC 570 and the NOR gate circuit 590 are input to the NOR gate circuit 590. Other circuits that require initialization to be connected are initialized.

Note that when there is no other circuit that requires initialization, the NOR gate circuit 590 is connected only to the master IC 570.

  Next, the master IC 570 will be described.

Master IC 570 designates the address of decoration control device 610 of the rendering device to be controlled, and outputs the control content of the rendering device to decoration control device 610 at the designated address.

The master IC 570 includes a connection line Vcc, a connection line Vact, a connection line SDA, a connection line SCL,
And the relay board (decoration control device) 60 via the five connection lines of the connection line GND (see FIG. 5).
Connected to 0.

The connection line Vcc is a connection line for supplying logic power to the relay board 600 and the decoration control device 610. The connection line Vact is a connection line for supplying a power source for driving the effect device (for example, a power source for causing the LED to emit light). Connection line SDA is a connection line for communicating data between effect control device 550 and decoration control device 610.
It functions as a data line in this embodiment. The connection line SCL is a connection line for inputting and outputting a clock signal used for data communication through the connection line SDA, and functions as a timing signal line in the present embodiment. The connection line GND shown in FIG. 5 includes a connection line Vcc and a connection line V.
This is the ground of the power supplied by act.

The relay board 600 and the decoration control device 610 are connected to each other through the connection line Vcc, the connection line Vact, the connection line SDA, the connection line SCL, and the connection line GND, similarly to the master IC 570 and the relay board 600. The

Master IC 570 and decoration control device 610 are connected to each other by connection line SDA and connection SCL.
Line bi-directional communication.

When transmitting data to the relay board 600 and the decoration control device 610, the master IC 570 first changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. Thus, a start condition for starting data output to the decoration control device 610 is established (a start condition is issued to the decoration control device 610).

Thereafter, the master IC 570 changes the signal level of the connection line SCL to LOW, and connects the connection line SCL.
While the CL signal level is LOW, the signal level of the connection line SDA is set to the level of the first bit of the transmission data, and after a predetermined time, the signal level of the connection line SCL is changed from LOW to HIGH. When the signal level of the connection line SCL changes to HIGH, the decoration control device 610 takes in the signal level of the connection line SDA and recognizes it as the first bit of the transmission data. Next, the master IC 570 returns the signal level of the connection line SCL from HIGH to LOW.

When this procedure is executed once, 1-bit data is transmitted from the master IC 570 to the decoration control device 610. Finally, this procedure is repeated 8 times, so that all 8 bits, which are unit bits of transmission data, are master. The data is transmitted from the IC 570 to the decoration control device 610 (1 byte of data is transmitted).

Then, the master IC 570 completes the transmission of the last 8-bit data and then connects to the connection line SC.
When the signal level of L is returned from HIGH to LOW, the connection line SDA is released to enter a reception standby state in which it waits to receive a response signal from the decoration control device 610.

In the reception standby state, the decoration control device 610 returns a 1-bit response signal (ACK or NACK described later) to the master IC 570 via the connection line SDA. Next, master IC5
70 changes the signal level of the connection line SCL from LOW to HIGH to capture the level of the response signal, and after a predetermined time, changes the signal level of the connection line SCL from HIGH to LOW, the decoration control device 610 causes the connection line SDA to change. To release.

The master IC 570 alternately repeats the data transmission for 1 byte and the reception of the response signal for 1 bit, and continues until all the data to be output to the decoration control device 610 is output. When the output of the data to be output is completed, the master IC 570 connects the connection line S
The signal level of the connection line SDA is changed from LOW to H while the CL signal level is kept HIGH.
By changing to IGH, a stop condition for ending data output to the decoration control device 610 is satisfied (a stop condition is issued to the decoration control device 610).

The input BUF 571 is a storage device that temporarily stores data input from the decoration control device 610 via the connection line SDA.

Specifically, when the master IC 570 is set to the input mode, the data transmitted from the decoration control device 610 to the master IC 570 is temporarily stored in the input BUF 571 with noise removed by the filter 575A.

The output BUF 572 temporarily stores data to be output to the decoration control device 610 via the connection line SDA.

The reset REG 573 functions as an initialization instruction data storage area of this embodiment, and is connected to the bus 563 and receives a command from the CPU 551 and outputs a reset signal to the controller. The controller comprehensively controls the master IC 570 and executes various processes.

The transmission mode REG574 is a register for selecting whether the mode for transmitting data to the I ² CI / O expander 615 is the byte mode or the buffer mode.

In byte mode, the master IC 570 sends 1 data to the I ² CI / O expander 615.
In this mode, an ACK or NACK is received from the I ² CI / O expander 615 each time a byte is transmitted, and an interrupt signal is output from the master IC 570 to the CPU 551 when either ACK or NACK is received.

Buffer mode, master IC570 is, data of a plurality of bytes stored in the output BUF572, sends each byte to I ² CI / O expander 615, each of the transmission, I ²
In this mode, when an ACK or NACK is received from the CI / O expander 615 and an NACK is received, an interrupt signal is output to the CPU 551 at that time.

However, in the buffer mode, when an ACK is received, an interrupt signal is output to the CPU 551 only when transmission of all data stored in the output BUF 572 is completed,
The master IC 570 performs I ² CI in a state where untransmitted data remains in the output BUF 572.
When the ACK is received from the / O expander 615, the control for outputting the next data to be transmitted from the output BUF572 without outputting the interrupt signal to the CPU 551 and outputting the data to the I ² CI / O expander 615 is performed. Repeated.

The byte mode is used when the master IC 570 outputs initialization instruction data and movable control data described later to the I ² CI / O expander 615. The buffer mode is used when the master IC 570 outputs light emission control data to be described later to the I ² CI / O expander 615.

The status REG 579 is a register that identifies whether the response signal received by the master IC 570 from the I ² CI / O expander 615 is ACK or NACK. When the master IC 570 outputs an interrupt signal to the CPU 551, the master IC 570 sets the value of the status REG 579 corresponding to the response signal received from the I ² CI / O expander 615.

The filter 575A removes noise from data input from the connection line SDA. When the driver 576A outputs data from the connection line SDA, the driver 576A applies a voltage at which the transistor 578A can operate to the transistor 578A.

As shown in FIG. 9, a predetermined voltage is applied to the connection line SDA by the pull-up resistor R, and the connection line SDA is connected to the filter 575A and the transistor 578A.

The transistor 578A uses a field effect transistor (FET) to reduce power consumption. The gate of the transistor 578A is connected to the driver 576A, and the drain is a connection line SDA to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

If the voltage applied to the gate of the transistor 578A is smaller than a predetermined value for operating the transistor 578A, no current flows between the drain and the source.
As a result, the connection line SDA becomes HIGH level. on the other hand,
If the voltage applied to the gate of the transistor 578A is equal to or higher than a predetermined value for operating the transistor 578A, a current flows from the drain to which the predetermined voltage is applied to the grounded source, whereby the voltage of the connection line SDA is reduced. As a result, the connection line SDA is LOW.
Become a level.

Note that the transistor 578A has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. For this reason, the connection line SDA has a normal I ^2.
It is possible to pass a current of about 10 milliamperes that is much larger than the current value used when using the C bus, and the data transmission between the production control device 550 and the decoration control device 610 can withstand a failure due to noise. It has become.

When the driver 576A outputs data from the connection line SDA, the driver 576A
In order to pass a current between the drain and the source of A, a voltage with a value that allows the transistor 578A to operate is applied to the gate of the transistor 578A. Then, the driver 576A outputs data from the connection line SDA by setting the voltage of the connection line SDA to HIGH level or LOW level.

The filter 575B removes noise from data input from the connection line SCL.
When the driver 576B outputs data from the connection line SCL, the driver 576B
Is applied to the transistor 578B.

As shown in FIG. 9, a predetermined voltage is applied to the connection line SCL by the pull-up resistor R, and the connection line SDA is connected to the filter 575B and the transistor 578B.

The transistor 578B uses a field effect transistor (FET) to suppress power consumption, the gate of the transistor 578B is connected to the driver 576B, and the drain is a connection line SCL to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

If the voltage applied to the gate of the transistor 578B is smaller than a predetermined value for operating the transistor 578B, no current flows between the drain and the source.
As a result, the connection line SCL becomes HIGH level. on the other hand,
If the voltage applied to the gate of the transistor 578B is equal to or higher than a predetermined value for operating the transistor 578B, a current flows from the drain to which the predetermined voltage is applied to the grounded source, so that the voltage of the connection line SCL is reduced. As a result, the connection line SCL is LOW.
Become a level.

Note that the transistor 578B has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. Therefore, the connection line SCL has a normal I ^2.
It is possible to pass a current of about 10 milliamperes that is much larger than the current value used when using the C bus, and the data transmission between the production control device 550 and the decoration control device 610 can withstand a failure due to noise. It has become.

When the driver 576B outputs a clock signal from the connection line SCL, the driver 576B applies a voltage with a value that allows the transistor 578B to operate to the gate of the transistor 578B in order to cause a current to flow between the drain and the source of the transistor 578B. The driver 576B
A clock signal is output from the connection line SCL by repeatedly changing the voltage of the connection line SCL between a HIGH level and a LOW level.

The power-on reset circuit 577 inputs the BUF 571 for input and the output BUF when the power is turned on to the master IC 570 and the voltage in the power-on reset circuit 577 reaches a predetermined value.
A reset signal for setting the storage area such as 572 to the default state is output to the controller.

  Next, the relay board 600 and the decoration control device 610 will be described.

The relay board 600 is directly connected to the master IC 570 in the decoration control device 610, that is, located on the most upstream side.

The decoration device 620 is a light-emitting device that is controlled by an I ² CI / O expander 615 (described later in FIG. 6) provided in the decoration control device 610 and flashes light when an electric current is passed. Etc. The accessory driving solenoid (SOL) 560 is a device that reciprocates when an electric current flows. The accessory driving solenoid (SOL) 560 moves an accessory for decoration (not shown) arranged on the game board 10 to produce an effect. The accessory driving motor (MOT) 561 is a device that rotates when an electric current flows, and produces an effect by moving the movable accessory 60. Actuator drive solenoid (SOL
) 560 and character object drive motor (MOT) 561 also provided in the decorative controller 610 I ² CI
Controlled by the / O expander 615.

The accessory driving SOL 560 may move the movable accessory 60, or the accessory driving MOT5.
61 may move an unillustrated accessory.

Method for connecting effect control device 550 and relay board 600, and relay board 600 and relay board 6
The connection method with the decoration control device 610 other than 00 will be described in detail with reference to FIG. Decoration control device 6
10 will be described in detail with reference to FIGS.

FIG. 5 is an explanatory diagram of connections of the decoration control devices 610A to 610F according to the first embodiment of this invention. In addition, for convenience of explanation, one relay board 600 and six decoration control devices 610A to 610F are illustrated as the decoration control device 610, but actually, it is necessary to correspond to the specifications of the gaming machine. A large number of decoration control devices 610 are connected.

The production control device 550 includes a connection line Vcc, a connection line Vact, a connection line SDA, and a connection line SCL.
And the connection line GND (hereinafter, these five connection lines are referred to as one harness) and connected to the effect control device 550.

Two decoration control devices 610A and 610D are connected to the relay board 600 in parallel by harnesses.

The decoration control device 610B is connected to the decoration control device 610A via a harness, and the decoration control device 610C is connected to the decoration control device 610B via a harness.

On the other hand, a decoration control device 610E is connected to the decoration control device 610D via a harness,
The decoration control device 610F is connected to the decoration control device 610E via a harness.

Each decoration control device 610 includes a connector serving as an attachment port for connecting the harness to itself. Since this connector is common to each decoration control device 610, it is possible to prevent erroneous wiring in the connection order of the connection lines.

Here, an I ² CI / O expander 615 provided in the decoration control device 610 (described later in FIG. 6).
Describes a method of controlling the decoration device 620.

The effect control device 550 determines the output mode of the effect device based on the game data input from the game control device 500. Then, the production control device 550 produces production control data (production control) including the individual address of the decoration control device 610 to be controlled (the individual address of the I ² CI / O expander 615) so that the determined output mode is obtained. Information) is output to the relay board 600. At this time, the effect control data is output from the connection line SDA to all the decoration control devices 610 connected to the effect control device 550 via the relay board 600. For this reason,
The master IC 570 can control all the decoration control devices 610 connected to the master IC 570.

In the present embodiment, a light-emitting device such as an LED is illustrated as the rendering device, so the LED
The light emission mode corresponds to the output mode of the rendering device. In this case, LE is determined by the production control data.
The lighting / flashing / extinguishing of D is instructed, and at the same time, the flashing cycle and lighting brightness of the LED are instructed.

Each decoration control device 610 has a unique individual address set in advance, so that when the effect control data is input, the address included in the input effect control data matches the set individual address. It is determined whether or not. If it is determined that the address included in the input effect control data matches the set individual address, the I ² CI / O expander 615 of the decoration control device 610 captures the effect control data. Thus, the output mode of the corresponding decoration device 620 is controlled, and a response signal is output to the master IC 570 immediately after the 8th bit data is input.

Each decoration control device 610 includes I ^{2 of the} decoration control device 610 in addition to the individual address.
A reset address for initializing the CI / O expander 615 is set.
This reset address is an address provided in common to all the I ² CI / O expanders 615 and cannot be used as an individual address. Also,
The value of the reset address cannot be changed (details will be described later).

The effect control device 550 is a decoration control device 610 (more precisely, I ² C of the decoration control device 610).
When the I / O expander 615) is initialized, initialization instruction data including the common address for resetting is output to the relay board 600. At this time, the initialization instruction data effect control data is output from the connection line SDA to all the decoration control devices 610 connected to the effect control device 550 via the relay board 600.

Each decoration control device 610 has a preset common address for resetting, so it is determined whether or not the address included in the input data matches the preset common address for resetting. To do. If it is determined that the address included in the input data matches a preset common address for resetting, the decoration control device 610
The I ² CI / O expander 615 outputs a response signal to the master IC 570, captures the input data as initialization instruction data, and outputs the I ² CI / O expander 61.
5 Initialize itself.

Incidentally, the I ² CI / O expander 615 is initialized, the initialized I ² CI /
The rendering device controlled by the O expander 615 is turned off.

As described above, the decoration control device 610 performs control based on a command from the effect control device 550, and therefore, the master IC 570 of the effect control device 550 is the master of the relationship between the effect control device 550 and the decoration control device 610. I ² CI / O expander 615 of decoration control device 610
Is a slave.

Although the case where the decoration target of the decoration control device 610 is the decoration device 620 has been described with reference to FIG. 5, the control target of the decoration control device 610 may be the accessory driving SOL 560 or the accessory driving MOT 561. In this case, since the rendering device becomes a drive source such as a motor or a solenoid,
The operation mode of these drive sources corresponds to the output mode of the rendering device. In this case, activation / deactivation of the drive source is instructed by the effect control data, and the operation speed is also instructed at the same time.

  FIG. 6 is a block diagram of the decoration control device 610 according to the first embodiment of this invention.

In FIG. 6, the decoration control device 610 (the decoration control device 610 on the lower side in FIG. 6) including the decoration device 620 LED inside the decoration control device 610 and the decoration control device 610 connected to the external decoration device 620. (The decoration control device 610 in the center of FIG. 6) will be described.

First, the decoration control device 610 provided with LEDs inside the decoration control device 610 will be described.

The decoration control device 610 on the lower side of FIG. 6 includes an I ² CI / O expander 615 and LEDs (decoration device 20). The connection line SDA and the connection line SCL are branched into two in the decoration control device 610, and one is output to the next decoration control device 610 as it is. The other is I ² CI /
Connected to O expander 615.

Further, a decoration device 620 to be controlled is provided on the output side of the I ² CI / O expander 615.
Is connected. The output side of the I ² CI / O expander 615 has ports 0 to 0 described in FIG.
15. Furthermore, all the ports of the decoration control device 610 are connected to the internal LEDs via current limiting resistors R0 to R15 described later with reference to FIG. 8A. Note that the current control resistors R0 to R15 are also provided in the decoration control device 610.

As described above, the I ² CI / O expander 615 has an address included in the effect control data input from the effect control device 550 and an individual address set in the I ² CI / O expander 615. Only when they match, the decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data.

Note that the power supply Vled in the figure is a power supply (supplied by the connection line Vact described above with reference to FIG.
This corresponds to a power source for causing the LED to emit light.

  Next, the decoration control device 610 connected to the external decoration device 620 will be described.

The central decoration control device 610 in FIG. 6 includes an I ² CI / O expander 615 and an LED (decoration device 20), and allows current to flow through the LEDs provided on the decoration device substrate 625 connected to the outside of the decoration control device 610. The decoration control device 610 and the decoration device substrate 625 are connected to each other through a connection line for connecting the power supply voltage Vled to the LED of the decoration device substrate 625 and a connection wire grounded to the ground.

The decoration device substrate 625 does not include the I ² CI / O expander 615 but is a substrate including only LEDs. In this case, the current limiting resistor (FIG. 8A) connected to the LED provided on the decoration device board 625 is provided on the decoration device board 625, but the decoration control device provided with the I ² CI / O expander 615. 610 may be provided.

It should be noted that the number of connection lines for passing current to these LEDs to be passed from the decoration control device 610 to the decoration device substrate 625 is determined in accordance with the number of LEDs provided on the decoration device substrate 625. . For example, in the case where the decoration device substrate 625 includes two LEDs, I ² CI
Two control lines for connecting the port of the / O expander 615 and the corresponding LED;
At least one power supply line for supplying Vled is required.

And the I ² CI / O expander 615 provided in the central decoration control device 610 is also
The address included in the effect control data input from the effect control device 550 and the I ² CI
The decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data only when the individual address set in the / O expander 615 matches. To do. In this case, both the decoration device 620 provided in the central decoration control device 610 and the decoration device 620 provided on the decoration device substrate 625 are connected to the I ² CI /
Controlled by O expander 615.

In this way, the decoration device substrate 625 is provided, and a part of the decoration device (
LED) is separated, and even if the LEDs are arranged at remote locations, the common I ² C
It can be controlled by the I / O expander 615.

Note that the decoration control device 610 may connect and control the accessory driving SOL 560 and the accessory driving MOT 561 in place of the decoration device 620, but details will be described later with reference to FIG. 8B.

FIG. 7 is a block diagram of the I ² CI / O expander 615 according to the first embodiment of this invention.

The I ² CI / O expander 615 includes a transistor 630 connected to the connection line SDA,
A filter 631 connected to the connection line SDA, a driver 632 connected to the connection line SDA,
A filter 633 connected to the connection line SCL, a bus controller 634, an output setting register 635, an output controller 636, a driver 637 connected to each port 0-15 on the output side of the I ² CI / O expander 615, and each port 0 Transistor 63 connected to -15
8A to 638P and a reset signal generation circuit 639.

The filter 631 is connected to the connection line SDA, removes noise of data input from the connection line SDA, and outputs the data from which noise has been removed to the bus controller 634. When the driver 632 outputs a response signal from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

The transistor 630 uses a field effect transistor (FET) to suppress power consumption, the gate of the transistor 630 is connected to the driver 632, and a predetermined voltage is applied to the drain by a pull-up resistor R (see FIG. 4). Connected to the connected connection line SDA, and the source is grounded.

If the voltage applied to the gate of the transistor 630 is smaller than a predetermined value for operating the transistor 630, no current flows between the drain and the source. On the other hand, transistor 6
If the voltage applied to the gate of 30 is not less than a predetermined value for operating the transistor 630,
When a current flows from the drain to which a predetermined voltage is applied to the grounded source, the voltage of the connection line SDA decreases. Note that the transistor 630 has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source.

When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage of a value that allows the transistor 630 to operate to the gate of the transistor 630 so that a current flows between the drain and the source. To do. The driver 632 outputs data from the connection line SDA by repeatedly changing the voltage of the connection line SDA from HIGH to LOW.

The filter 633 is connected to the connection line SCL, removes noise of data input from the connection line SCL, and outputs the data from which noise has been removed to the bus controller 634.

In addition, the I ² CI / O expander 615, is set a unique address by the address setting terminals A0~A3 provided in the I ² CI / O expander 615 is input to the bus controller 634. Further, an address for resetting the I ² CI / O expander 615 is also set in advance.

In the bus controller 634, the address of data input from the connection line SDA is I ² CI.
It is determined whether or not the address matches the unique address set in the / O expander 615. If the address matches, the data is fetched as effect control data.

In addition, the bus controller 634 receives the address of data input from the connection line SDA as I
^It is determined whether or not it matches the reset address preset in the ² CI / O expander 615, and the address of the input data and the reset address preset in the I ² CI / O expander 615 Is matched as initialization instruction data, the I ² CI / O expander 615 is initialized.

In addition, the bus controller 634 changes the signal level of the SCL connection line from LOW to HIGH and takes in the 8th bit data, and then changes the signal level of the SCL connection line from HIGH to LOW. A response signal is output from the connection line SDA to the master IC 570. Furthermore, when it is confirmed that the signal level of the SCL connection line changes from LOW to HIGH, and the signal level of the SCL connection line changes from HIGH to LOW again, the connection line SDA
Is released. That is, the number of changes in the signal level of the SCL connection line from LOW to HIGH is 9
A response signal is output at the time of turning.

In the output setting register 635, the operation mode of the I ² CI / O expander 615 and the output state of the ports 0 to 15 are set. When the bus controller 634 fetches the initialization instruction data from the connection line SDA and the I ² CI / O expander 615 is initialized, the output setting register 635 causes a current to flow to all the ports 0 to 15. It is set to the initial state so that there is no.

The output controller 636 is based on the data set in the output setting register 635.
The output state of the effect device is actually controlled by flowing current through the port driver 637 to the effect devices connected to the ports 0 to 15. When the bus controller 634 fetches the effect control data from the connection line SDA, this output state is updated to the contents specified in the fetched effect control data.

When a current flows through a port, the driver 637 applies a voltage at which the transistors 638A to 638P connected to the port through which the current flows can operate.

The gates of the transistors 638A to 638P are connected to the driver 637, the drain is connected to the port terminal connected to the connection line to which the voltage for operating the rendering device is applied as shown in FIGS. 8A and 8B, and the source is grounded Has been.

The voltage applied to the gates of the transistors 638A to 638P is the transistor 638A to
If it is smaller than a predetermined value for operating 638P, no current flows between the drain and the source. On the other hand, if the voltage applied to the gates of 638A to 638P is equal to or higher than a predetermined value for operating the transistor 638, the power supply Vled shown in FIG. 8A or the power supply Vmot or the power supply Vsol shown in FIG. Current flows to the source grounded through the drain of the transistor 638, so that the output state of the effect device connected to the port terminal can be controlled.

Further, the I ² CI / O expander 615 of the decoration control device 610 can control all the rendering devices connected to the port terminals of the I ² CI / O expander 615 at the same time. ² One rendering device connected to the port terminal of the CI / O expander 615 can be controlled as one group.

Since the I ² CI / O expanders 615 included in each decoration control device 610 are assigned different individual addresses, the rendering device is divided into a plurality of groups. That is, the I ² CI / O expander 6 provided in each decoration control device 610.
15 is configured as a group unit control means capable of controlling the effect device in units of groups.

Therefore, the effect control device 550 that controls the decoration control device 610 functions as a group control unit that controls the group unit control unit.

The reset signal generation circuit 639 has a Vcc terminal connected to the connection line Vcc that supplies power to the I ² CI / O expander 615, and a RES that receives an external reset signal.
The ET terminal is connected.

The reset signal generation circuit 639 is powered on to the I ² CI / O expander 615,
When the voltage rises to a predetermined value, a reset signal is generated, and the generated reset signal is input to the bus controller 634, the output setting register 635, and the output controller 636.

When a reset signal of LOW level is input from the outside, the reset signal generation circuit 639 outputs a reset signal, so that the CPU 551 of the effect control device 550 outputs N
A reset signal may be input from the RESET terminal via the OR gate circuit 590. When the RESET terminal is not used, as shown in FIGS. 8A and 8B,
The T terminal may be pulled up to HIGH.

FIG. 8A is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 that controls the decoration device 620 according to the first embodiment of the present invention.

The I ² CI / O expander 615 has an NC terminal, a RESET terminal, and an SC as input terminals.
L terminal, SDA terminal, Vcc terminal, A0 to A3 terminal, and GND terminal are provided, and PORT0 to PORT15 are provided as output terminals.

A power source supplied to the I ² CI / O expander 615 is connected to the RESET terminal via a pull-up resistor R. For this reason, the voltage applied to the reset terminal is always HIG
H is maintained.

  The SCL terminal is connected to the connection line SCL, and the SDA terminal is connected to the connection line SDA.

A power supply supplied to the I ² CI / O expander 615 is connected to the Vcc terminal. Further, a capacitor CP for removing power supply noise is connected to the Vcc terminal.

The A0 to A3 terminals are terminals for setting unique addresses for the I ² CI / O expander 615. Note that the address of the normal I ² CI / O expander 615 is represented by 4 bits. When the power of the I ² CI / O expander 615 is applied to this terminal, “1” is displayed in the bus controller 634. When this terminal is connected to the ground, “0” is set in the bus controller 634.

Therefore, the address of the I ² CI / O expander 615 shown in FIG. 8A is “0100”.
The address of the I ² CI / O expander 615 shown in FIG. 8B is “0110”. The GND terminal is a terminal for grounding a voltage.

Each PORT0 terminal to PORT15 terminal is connected to each LED via current limiting resistors R0 to R15.
0 to a decoration device 620 composed of LEDs 15. One port may be connected to one port as in PORT0, but port 1 as in PORT1-15.
A plurality of LEDs may be connected to each.

One I ² CI / O expander 61 when one LED is provided for each port
5 can control a maximum of 16 LEDs. If the number of LEDs connected to each port is different, assuming that all LEDs connected in series to one port are one type of LED, one I ² CI / O expander is used. By 615, up to 16 kinds of LEDs can be controlled.

When a voltage is applied from the driver 637 to the gates of the transistors 638A to 638P (see FIG. 7) connected to the PORT0 terminal to the PORT15 terminal, a current flows from the drain to the source of the transistors 638A to 638P to which the voltage is applied. Is possible,
A current flows through the LEDs 0 to 15 connected to the PORT0 terminal to the PORT15 terminal, and the LEDs 0 to 15 are turned on.

On the other hand, if the driver 637 does not apply a voltage to the gates of the transistors 638A to 638P, no current flows through each LED0 to LED15, and each LED0 to LED15 is not lit.

Note that the PORT0 to PORT15 terminals of the I ² CI / O expander 615 have L
Since it is possible to connect a motor or solenoid instead of ED, I ² CI / O
A case where a motor or a solenoid is driven using the expander 615 will be described.

FIG. 8B illustrates the accessory driving MOT 561 and the accessory driving SOL 560 according to the first embodiment of this invention.
6 is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 for controlling the control.

The accessory driving MOT 561 is composed of a stepping motor, and rotates by sequentially applying a predetermined voltage to signal terminals of respective phases that drive the stepping motor. In this embodiment,
The signal terminal of each phase of the accessory driving MOT 561 is connected to the PORT0 terminal to the PORT3 terminal.

When a voltage is applied from the driver 637 to any one of the gates of the transistors 638A to 638D connected to the PORT0 terminal to the PORT3 terminal connected to the accessory driving MOT561, the transistors 638A to 638D to which the voltage is applied are applied. The current can flow from the drain to the source, the current flows to the accessory driving MOT 561 connected to the PORT0 terminal to the PORT3 terminal, and the accessory driving MOT561 is driven.

The connection lines connecting the PORT0 terminal to the PORT3 terminal and the accessory driving MOT 561 are branched, and one of the branched connection lines is connected to the power supplied to the accessory driving MOT 561 via the diode D and the Zener diode ZD. Connected.

The PORT terminal 15 is connected to the accessory driving SOL 560. Actor-driven SOL56
When a voltage is applied from the driver 637 to the gate of the transistor 638P connected to the PORT15 terminal connected to 0, a current can flow from the drain to the source of the transistor 638P to which the voltage is applied, A current flows through the accessory driving SOL 560 connected to the PORT 15 terminal, and the accessory driving SOL 560 is driven.

In FIG. 8B, with respect to I ² CI / O Aix although both character object drive MOT561 and character object drive SOL560 Panda 615 are connected, one I ² CI / O expander 615, the character object drive A configuration in which at least one of the MOT 561 and the accessory driving SOL 560 is connected may be used.

For example, a dedicated I ² CI / O expander 615 that controls only the stepping motor is provided, or an I ² CI / O that controls only the solenoid.
The expander 615 may be provided exclusively. With such a configuration, it is possible to control the rendering devices belonging to the same group at the same timing, and therefore it becomes possible to group and control only the rendering devices that require high-speed processing.

FIG. 9 is a circuit diagram of connection lines related to input / output of the relay board 600 according to the first embodiment of the present invention.

The relay board 600 includes an upstream connector 601, two downstream connectors 602A and 602B, and an I ² CI / O expander 615.

The upstream connector 601 is a connector connected to the master IC 570 upstream of the relay board 600, and the connectors 602 A and 602 B are connected to the decoration control device 610 downstream of the relay board 600.

In order to connect the connection line SDA to the two downstream connectors 602A and 602B, the internal connection line SDA911 extending from the upstream connector 601 branches at a branch 901 into a first connection line SDA921 and a second connection line SDA931. The first connection line SDA921 is connected to the downstream connector 602A, and the second connection line SDA931 is connected to the downstream connector 602B.

Similarly, the internal connection line SCL912 extending from the upstream connector 601 branches at a branch 902 into a first connection line SCL922 and a second connection line SCL932. The first connection line SCL922 is connected to the downstream connector 602A, and the second connection line SCL932 is connected to the downstream connector 602B.

In order to connect the connection line SDA to the I ² CI / O expander 615, the second connection line SDA
931 branches at a branch 903, and the branched second connection line SDA931 is connected to the SDA terminal shown in FIGS. 8A and 8 of the I ² CI / O expander 615. Also, connect the connection line SCL to I ²
In order to connect to the CI / O expander 615, the second connection line SCL932 is branched at the branch 904, and the branched second connection line SCL932 is an SCL terminal shown in FIGS. 8A and 8B of the I ² CI / O expander 615. Connected to.

Note that the I ² CI / O expander 615 is supplied with a voltage Vcc that is a power supply voltage of the I ² CI / O expander 615. Although not shown in FIG. 9, I ² CI /
From the O expander 615, signal lines (see FIG. 8A) of the ports 0 to 15 for driving the LEDs (decoration apparatus 200) provided on the relay substrate 600 are output.

The I ² CI / O expander 615 includes a second connection line SDA931 and a second connection line S.
Although the CL 932 is connected, the first connection line SDA921 and the first connection line SCL922 are connected.
May be connected.

I ² CI / O Aix input expander 615 via the connection line SDA signal is output via the connection line SDA upstream of the master IC570, and from the upstream of the master IC570 to I ² CI / O expander 615 of the relay board 600 The Zener diode ZD941 is connected to the internal connection line SDA911 in order to remove the noise of the generated signal.

Specifically, the internal connection line SDA911 branches at the branch 905, and the branched internal connection line SD.
A911 is connected to the cathode side of the Zener diode ZD941, and the Zener diode ZD94
The anode side of 941 is grounded.

For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA911 is released by the Zener diode ZD941.

Further, the upstream master IC 570 to the I ² CI / O expander 615 of the relay board 600
In order to remove noise from the signal input via the connection line SCL, the internal connection line SCL9
12 is connected to a Zener diode ZD942.

Specifically, the internal connection line SCL912 branches at a branch 906, and the branched internal connection line SC.
L912 is connected to the cathode side of the Zener diode ZD942, and the Zener diode ZD94
The anode side of 942 is grounded.

For this reason, a voltage (for example, a pulsed noise signal) applied to the internal connection line SCL912 is released by the Zener diode ZD942.

A signal output from the I ² CI / O expander 615 of the relay board 600 to the decoration control device 610 connected to the downstream connector 602A via the connection line SDA, and the downstream connector 602A
I ² CI / O expander 615 of relay board 600 from decoration control device 610 connected to
In order to remove noise from the signal input to the connection line SDA, the first connection line SDA9
A zener diode ZD943 is connected to 21.

Specifically, the first connection line SDA921 branches off at the branch 907, and the branched first connection line SD.
A921 is connected to the cathode side of Zener diode ZD943, and Zener diode ZD
The anode side of 943 is grounded.

Therefore, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA921 is released by the Zener diode ZD943.

Similarly to the Zener diode ZD943 connected to the first connection line SDA921, the Zener diode 945 is also connected to the second connection line SDA931.

The first connection line SCL922 is used to remove noise of a signal input from the I ² CI / O expander 615 of the relay board 600 to the decoration control device 610 connected to the downstream connector 602A via the connection line SCL. Is connected to a Zener diode ZD944.

Specifically, the first connection line SCL 922 branches at the branch 908, and the branched first connection line SC.
L922 is connected to the cathode side of the Zener diode ZD944 and the Zener diode ZD
The anode side of 944 is grounded.

For this reason, a voltage (for example, a pulse noise signal) of a predetermined level or higher applied to the internal connection line SCL922 is released by the Zener diode ZD944.

Similarly to the Zener diode ZD944 connected to the first connection line SCL922, the Zener diode ZD946 is also connected to the second connection line SCL932.

Further, the upstream connection line SDA connected to the master IC 570 and the decoration control device 610.
Pull-up resistor R95 for pulling up the voltage of the downstream connection line SDA connected to
1 is connected to the first connection line SDA921. Similarly, a pull-up resistor R952 for pulling up the voltage of the upstream connection line SCL connected to the master IC 570 and the downstream connection line SCL connected to the decoration control device 610 is provided in the first connection line SDA922. Connected.

Specifically, the first connection line SDA921 branches at the branch 909, and the branched first connection line SD.
A921 is connected to a pull-up resistor R951. Similarly, the first connection line SCL922 branches at a branch 910, and the branched first connection line SCL922 is connected to a pull-up resistor R952.

A pull-up resistor 951 that pulls up the voltages of the connection line SDA and the connection line SCL,
952 may not be provided in the relay board 600, may be provided in the master IC 570, or may be provided in the decoration control device 610 other than the relay board 600. In short, it may be anywhere as long as the voltage Vcc can be supplied to the drain terminals of the transistors that drive the connection line SDA and the connection line SCL.

Connection line Vcc for supplying a power supply voltage to the I ² CI / O expander 615 of the relay board 600
The internal connection line Vcc971 extending from the Vcc terminal of the upstream connector 601 connected to the internal connection line GND972 extending from the GND terminal of the upstream connector 601 and grounded,
They are connected via a smoothing capacitor C961 and a bypass capacitor 962.

The smoothing capacitor C961 is a capacitor for smoothing the voltage waveform of the power supply,
The bypass capacitor CP962 is a capacitor for removing noise from the power supply voltage.

For this reason, the power supply voltage supplied to the I ² CI / O expander 615 of the relay board 600 is smoothed by the smoothing capacitor C961, and noise is removed by the bypass capacitor 962, so that the I ² CI / O expander is removed. 615 is supplied.

Similarly, the internal connection line Vcc9 extending from the Vcc terminal of the downstream connectors 602A and 602B
73 and the internal connection line GND974 extending from the GND terminal are connected via a smoothing capacitor C961 and a bypass capacitor 962. As a result, the smoothed and noise-free voltage is applied to the connection line Vcc connected to the downstream decoration control device 610.

FIG. 10 is a circuit diagram of connection lines related to input / output of the decoration control device 610 according to the first embodiment of the present invention.

The decoration control device 610 includes an upstream connector 611, an I ² CI / O expander 615, and a downstream connector 612.

A bus is connected to the upstream connector 611 from the relay board 600 or the decoration control device 610 on the upstream side. The downstream connector 612 is connected to a bus connected to the decoration control device 610 on the downstream side.

The SDA terminal of the upstream connector 611 and the SDA terminal of the downstream connector 612 are connected by an internal connection line SDA1011. The SCL terminal of the upstream connector 611 and the SCL terminal of the downstream connector 612 are connected by an internal connection line SCL1012.

In order to connect the connection line SDA to the I ² CI / O expander 615, the internal connection line SDA
Reference numeral 1011 branches at the branch 1001, and the branched internal connection line SDA 1011 is connected to the SDA terminal shown in FIGS. 8A and 8 of the I ² CI / O expander 615. Connection line SCL
Are connected to the I ² CI / O expander 615, the internal connection line SCL1012 branches at the branch 1002, and the branched internal connection line SCL1012 is connected to the I ² CI / O expander 61.
5 is connected to the SCL terminal shown in FIGS. 8A and 8B.

Note that the I ² CI / O expander 615 is supplied with a voltage Vcc that is a power supply voltage of the I ² CI / O expander 615. Although not shown in FIG. 10, I ² CI
From the / O expander 615, an LED (decoration apparatus 20) related to the decoration control apparatus 610
The signal lines (see FIG. 8A) of the ports 0 to 15 that drive 0) are output.

The I ² CI / O expander 615 of the decoration control device 610 shown in FIG.
10 from the upstream decoration control device 610 or relay board 600 connected to the terminal 11 via the connection line SDA, and the decoration shown in FIG. 10 from the upstream decoration control device 610 or relay board 600 connected to the upstream connector 611. In order to remove noise from the signal input to the I ² CI / O expander 615 of the control device 610 via the connection line SDA, the internal connection line SDA101 is used.
1 is connected to a Zener diode ZD1041.

Specifically, the internal connection line SDA1011 branches at a branch 1003, the branched internal connection line SDA1011 is connected to the cathode side of the Zener diode ZD1041, and the anode side of the Zener diode ZD1041 is grounded.

For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA1011 is released by the Zener diode ZD1041.

Further, the upstream decoration control device 610 or the relay board 600 connected to the upstream connector 611.
To the I ² CI / O expander 615 of the decoration control device 610 shown in FIG.
Zener diode ZD942 is connected to the internal connection line SCL1012 in order to remove noise from the signal input through the internal connection line SCL1012.

Specifically, the internal connection line SCL1012 branches at a branch 1004, the branched internal connection line SCL1012 is connected to the cathode side of the Zener diode ZD1042, and the anode side of the Zener diode ZD1042 is grounded.

For this reason, a voltage (for example, a pulsed noise signal) applied to the internal connection line SCL 1012 at a predetermined level or more is released by the Zener diode ZD1042.

The I ² CI / O expander 615 of the decoration control device 610 shown in FIG.
10, a signal output via the connection line SDA to the downstream decoration control device 610 connected to 12, and the I ² CI / O of the decoration control device shown in FIG. 10 from the downstream decoration control device 610 connected to the downstream connector 612. A Zener diode ZD1043 is connected to the internal connection line SDA1011 in order to remove noise of a signal input to the expander 615 via the connection line SDA.

Specifically, the internal connection line SDA1011 branches at a branch 1005, the branched internal connection line SDA1011 is connected to the cathode side of the Zener diode ZD1043, and the anode side of the Zener diode ZD1043 is grounded.

For this reason, a voltage (for example, a pulse noise signal) of a predetermined level or more applied to the internal connection line SDA1011 is released by the Zener diode ZD1043.

Further, in order to remove noise of a signal input via the connection line SCL from the I ² CI / O expander 615 of the decoration control device 610 shown in FIG. 10 to the downstream decoration control device 610 connected to the downstream connector 612. In addition, a Zener diode ZD1 is connected to the internal connection line SCL1012.
044 is connected.

Specifically, the internal connection line SCL1012 branches at a branch 1006, the branched internal connection line SCL1012 is connected to the cathode side of the Zener diode ZD1044, and the anode side of the Zener diode ZD1044 is grounded.

For this reason, a voltage (for example, a pulse noise signal) applied to the internal connection line SCL 1012 is more than a predetermined voltage and is released by the Zener diode ZD1044.

Connection line V for supplying power supply voltage to the I ² CI / O expander 615 of the decoration control device 610
Internal connection line Vcc1071 extending from the Vcc terminal of upstream connector 611 connected to cc
And the internal connection line GND107 extending from the GND terminal of the upstream connector 611 and grounded
2 is connected via a smoothing capacitor C1061 and a bypass capacitor 1062.

The smoothing capacitor C1061 is the same capacitor as the smoothing capacitor C961 shown in FIG. 9, and the bypass capacitor CP1062 is the same capacitor as the bypass capacitor 962 shown in FIG.

Further, an internal connection line Vcc 1073 extending from the Vcc terminal of the downstream connector 612, GN
The internal connection line GND 1074 extending from the D terminal is connected via a smoothing capacitor C 1061 and a bypass capacitor 1062.

FIG. 11 is an explanatory diagram of the slave address 1100 included in the data output from the presentation control device 550 to the decoration control device 610 according to the first embodiment of this invention.

The slave address 1100 includes a fixed address part 1101 consisting of upper 3 bits and a variable address part 1102 consisting of lower 5 bits.

The fixed address portion 1101 is an address that is preset with “110” and cannot be changed by the I ² CI / O expander 615.

Variable address portion 1102 is a configurable address I ² CI / O expander 615, corresponding to a pattern that is set to A0~A3 terminal of I ² CI / O expander 615 to be controlled 4 A bit I ² CI / O expander address 1103 and 1-bit R / W identification data 1104 indicating whether the data is a read request or a write request are included.

Since the effect control data output from the effect control device 550 to the decoration control device 610 is a write request, “0” is normally registered in the R / W identification data 1104.

FIG. 12 shows the I ² CI / O expander address table 12 according to the first embodiment of this invention.
FIG.

The I ² CI / O expander address table 1200 is a table managed by the master IC 570. The I ² CI / O expander address table 1200 shows the correspondence between the slave address 1201 and the I ² CI / O expander address 1202.

The slave address 1201 stores the slave address of the decoration control device 610 specified by the effect control device 550 as a transmission / reception target. As described above with reference to FIG. 13, the slave address includes a fixed address portion consisting of the upper 3 bits and a 4-bit I ² CI /
It is configured by combining an O expander address and 1-bit R / W identification data.

In the I ² CI / O expander address 1202, as described above with reference to FIGS. 8A and 8B,
A 4-bit I ² CI / O expander address corresponding to each slave address is registered.

However, among the I ² CI / O expander addresses, the address “1000” and the address “1011” cannot be used as unique addresses for identifying the I ² CI / O expanders 615 from each other.

“1000” is used as a default value at the time of power-on of an address (all call address) specified when outputting commands to all the decoration control devices 610. "
“1011” is a common address used when all the decoration control devices 610 connected to the master IC 570 are unconditionally reset by software.

As described above, since there are 14 unique addresses that can be set in the I ² CI / O expander 615 of the decoration control device 610, the effect control device 550 controls the 14 I ² CI / O expanders 615. it can. In addition, one decoration control device 610 includes PORT0 to PORT1.
Since 5 are provided, 16 (in other words, 16 types) LEDs can be controlled. Therefore, the production control device 550 can control 224 (in other words, 224 types) LEDs.

FIG. 13 is a diagram for explaining a work register assigned to the output setting register 635 (see FIG. 7) included in the I ² CI / O expander 615 according to the first embodiment of this invention.

A work register (device register) and a control register (control register) are assigned to the output setting register 635 of the I ² CI / O expander 615.
Work register, and information for setting the predefined relative I ² CI / O Expander 615, the output of the effect device connected to the I ² CI / O expander 615 (e.g., LED) Information for specifying an aspect is stored. The control register also stores information defining the procedure for writing data to the work register.

As shown in FIG. 13, the work register has a configuration in which a plurality of pieces of information are distributed and stored in different storage areas, and different register numbers are assigned to the respective storage areas.

A register name “MODE1” is assigned to the storage area with the register number “00h”, and a register name “MODE2” is assigned to the storage area with the register number “01h”. Yes. When values are written in the storage areas of the register numbers “00h” and “01h”, the I ² CI / O expander 615 is initialized based on the written values.

In the storage areas where the register numbers are “02h” to “11h”, “PWM0” to “PWM
The register name “15” is assigned. When a value is written in any of the storage areas of register numbers “02h” to “11h”, the value is written out of the 16 LEDs constituting the light emitting device connected to the I ² CI / O expander 615. LE corresponding to the registered register number
The brightness of D is adjusted based on the written value. For example, when a value is written in the storage area of the register number “02h”, the luminance of the LED 0 connected to the port 0 shown in FIG. 8A is adjusted.

When the accessory driving SOL 560 is connected to the I ² CI / O expander 615, the accessory driving SOL 560 is energized in the storage area of the register number corresponding to the port to which the accessory driving SOL 560 is connected. A value indicating whether to operate or not to energize is written.

When the accessory driving MOT 561 is connected to the I ² CI / O expander 615, the target rotation of the accessory driving MOT 561 is stored in the storage area of the register number corresponding to the port to which the accessory driving MOT 561 is connected. A value indicating the position is written.

A register name “GRPPWM” is assigned to the storage area with the register number “12h”, and a register name “GRPFREQ” is assigned to the storage area with the register number “13h”. When a value is written in the storage areas of the register numbers “12h” and “13h”, a blinking pattern of all LEDs (16 LEDs) is set based on the written value.

Specifically, when a value is written in the storage area of the register number “12h”, the duty cycle that is the on / off ratio of the entire LED is set, and the register number “13h” is set.
When a value is written in the storage area, the blinking cycle of the entire LED is set.

A register name “LEDOUT0” is given to the storage area where the register number is “14h”. When a value is written in the storage area of the register number “14h”, the output states of the LEDs 0 to LED3 are set based on the written value.

A register name “LEDOUT1” is given to the storage area where the register number is “15h”. When a value is written in the storage area of the register number “15h”, the output states of the LEDs 4 to 7 are set based on the written value.

A register name “LEDOUT2” is assigned to the storage area where the register number is “16h”. When a value is written in the storage area of the register number “16h”, the output states of the LEDs 8 to 11 are set based on the written value.

A register name “LEDOUT3” is given to the storage area where the register number is “17h”. When a value is written in the storage area of the register number “17h”, the output states of the LEDs 12 to 15 are set based on the written value.

In the storage areas where the register numbers are “18h” to “1Ah”, “SUBADR1” to “
The register name “SUBADR3” is assigned. Register numbers “18h” to “1A
When a value is written in the storage area of “h”, the first sub-address to
A third subaddress is set.

A register name “ALLCALLADR” is given to the storage area whose register number is “1Bh”. When a value is written in the storage area of the register number “1Bh”, an all-call address is set based on the written value.

FIG. 14 shows that the master IC 570 according to the first embodiment of the present invention has a connection line SDA and a connection line SC.
It is explanatory drawing of the start condition and stop condition of the data output via L.

The connection line SCL has a signal level HIGH when data is not transmitted, and the master IC
When 570 outputs data to the decoration control device 610, the signal level of the connection line SCL is set to L.
The decoration control device 610 operates as a strobe signal for taking in the data of the connection line SDA by changing from OW to HIGH.

The connection line SDA has a signal level HIGH when data is not transmitted, and the connection line SC
Data is output from the connection line SDA in accordance with the L clock signal.

The master IC 570 maintains the signal level of the connection line SCL at HIGH while maintaining the connection line SCL.
By changing the DA signal level from HIGH to LOW, a signal serving as a start condition indicating that data output starts is output.

The I ² CI / O expander 615 of the decoration control device 610 includes a connection line SDA and a connection line S.
When a signal serving as a start condition is input from CL, it is understood that data output starts.

The master IC 570 maintains the signal level of the connection line SCL at HIGH while maintaining the connection line SCL.
By changing the DA signal level from LOW to HIGH, a signal indicating a stop condition indicating the end of data output is output.

The I ² CI / O expander 615 of the decoration control device 610 grasps that the output of data ends when the stop condition is input.

FIG. 15 is a timing chart at which the decoration control device 610 to which the data output from the master IC 570 according to the first embodiment of the present invention is input outputs a response signal.

The decoration control device 610 counts the number of changes in the signal level of the connection line SCL after the start condition is satisfied, and takes in data input from the connection line SDA in accordance with the clock signal of the connection line SCL.

Then, the decoration control device 610 outputs a response signal to the master IC 570 via the connection line SDA immediately after the start condition is satisfied and immediately before the signal line change number of the connection line SCL reaches nine. In other words, the decoration control device 610 receives a response signal via the connection line SDA when the signal level of the connection line SCL changes from HIGH to LOW after taking the 8th bit data from the connection line SDA. Output.

As shown in the figure, a response signal (ACK response signal) indicating that the data has been successfully received is indicated by a LOW level, and a response signal (NA) indicating that the data reception has failed.
The CK response signal (corresponding to no ACK output in the figure) is indicated by a HIGH level.

Further, when the signal level of the connection line SCL changes eight times after the start condition is satisfied, the master IC 570 waits for a response signal from the decoration control device 610 by releasing the connection line SDA. Then, the master IC 570 changes the signal level of the connection line SCL while releasing the connection line SDA, and takes in the response signal from the decoration control device 610.

FIG. 16 is a timing chart of signal levels of the connection line SDA and the connection line SCL when the master IC 570 according to the first embodiment of the present invention outputs effect control data.

First, when starting output of data, the master IC 570 changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, thereby indicating a start condition signal. And the decoration control device 610 is notified that data will be output.

Next, the master IC 570 has a decoration control device 610 that is a control target having a total of 7 bits.
Outputs the slave address. Next, the master IC 570 outputs data indicating whether the write request is a read request to the eighth bit.

The master IC 570 receives a response signal from the decoration control device 610 when the signal level of the connection line SCL becomes HIGH for the ninth time. Therefore, if the response signal is an ACK response signal, the signal level of the connection line SDA is LOW. If the response signal is NACK, the signal level of the connection line SDA changes to HIGH.

Next, after outputting the address data, the master IC 570 outputs the data in the number of bits that is a multiple of 8. After outputting the eighth bit of data, master IC 570 outputs the ninth bit of data after waiting for an ACK response signal to be input. After that, when data of a bit corresponding to a multiple of 8 is output, after confirming that an ACK response signal is input,
Output a multiple of 8 + 1) -th bit and repeat until all data is output.

If the master IC 570 outputs a bit that is a multiple of 8 after the data has been output and the ACK response signal is not received after a predetermined time, the master IC 570 assumes that the data transmission has failed and starts again. Send the condition. Next, the address data is output again via the connection line SDA, and the data is output again from the first bit while confirming the ACK response signal.

The master IC 570 outputs the signal indicating the stop condition after outputting the data of the last bit of the data and waiting for the ACK response signal to be input.

In FIG. 16, there is a total of 24 bits (slave address 8 bits, data 16 bits) from when the signal indicating the start condition is output until the signal indicating the stop condition is output.
However, it may be 24 bits or more or 24 bits or less.

FIG. 17 shows the master IC 57 when the master IC 570 according to the first embodiment of the present invention sets the presentation control data in the decoration control device 610 by specifying the slave individual address.
FIG. 6 is a diagram illustrating a format of data exchanged between 0 and an I ² CI / O expander 615.

The 8-bit data 1801 that is output first includes an address “A0 to A6” of the decoration control device 610 that is the target of data transmission, and a 1-bit R that indicates whether the data is a read request or a write request. / W identification data. This address "A0
Among “A6”, “A4 to A6” are fixed address portions having a value “110”, and “A0 to A6”.
“3” corresponds to the address set in the terminals A0 to A3 of the I ² CI / O expander 615 (see FIG. 8). The data 1801 is “ADRESS” in FIG.
And “R / W”.

Next, the output 8-bit data 1802 includes setting data for the control register assigned to the output setting register 635 (see FIG. 7) of the I ² CI / O expander 615. This data 1802 is “DA” transmitted first in FIG.
Corresponds to “TA”.

Here, the control register will be described. The control register is composed of 8 bits, and the upper 3 bits “AI0 to AI2” are automatic write parameters for designating the writing or reading method to the work register of the output setting register 635, and the lower 5 bits “D0”.
˜D4 ”is a register address that specifies an access start position (a start position at which writing is started or a start position at which reading is started) in the work register.

The automatic write parameter is accessed by the master IC 570 including only the area at the access start position specified by the register address (auto-increment is prohibited) or including the area adjacent to the area at the access start position specified. Is specifically designated as “000”, “100”, “101”.
"," 110 ", or" 111 "can be set.

When a value of “000” is set in the automatic write parameter, auto-increment is prohibited, and only the area at the access start position specified by the register address is accessed, and the area other than the start position is not accessed. For example, if the register address is “10100”, only the storage area with the register number “14h” is accessed, and the other storage areas are not accessed.

When the value of “100” is set in the auto-write parameter, auto-increment is permitted, and after accessing the area at the access start position specified by the register address, the area is accessed in order while moving the area in the direction of increasing the register number. repeat. Then, after accessing the storage area where the register number is “1Bh” at the end, the storage area where the register number is “00h” is accessed and accessed again sequentially while moving the area in the direction in which the register number increases. repeat. For example, if the register address is “10100”, the register number becomes “15h” → “16” after accessing the storage area where the register number becomes “14h”.
"h"->->"1Bh"->"00h"->"01h"->... (i.e., all areas) are repeatedly accessed.

When the value “101” is set in the automatic writing parameter, “100” is set in the automatic writing parameter.
As in the case where the value of is set, after accessing the area at the access start position specified by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area with the register number “11h” is accessed, the storage area with the register number “02h” is accessed.
The recording area (area related to LED brightness adjustment) in the section “11h” is repeatedly accessed. For example, if the register address is “10100”, the register number is “14h”.
After accessing the storage area, the register number is “15h” → “16h” →
1Bh ”→“ 00h ”→“ 01h ”→.. After accessing the storage area where the register number is “11h”, the register number is “02h”.
→ “03h” →... “11h” → “02h” → “03h” →...

When the value “110” is set in the automatic writing parameter, “100” is set in the automatic writing parameter.
As in the case where the value of is set, after accessing the area at the access start position specified by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area with the register number “13h” is accessed, the storage area with the register number “12h” is accessed.
The recording area (area relating to the LED blinking cycle) in the section “13h” is repeatedly accessed. For example, if the register address is “10100”, the register number is “14h”.
After accessing the storage area, the register number is “15h” → “16h” →
1Bh ”→“ 00h ”→“ 01h ”→.. After accessing the storage area where the register number is “13h”, the register number is “12h”.
→ "13h" → "12h" → "13h" → ... repeatedly access the area.

When the value “111” is set in the automatic writing parameter, “100” is set in the automatic writing parameter.
As in the case where the value of is set, after accessing the area at the access start position specified by the register address, the access is repeated in order while moving the area in the direction of increasing the register number. However, once the storage area with the register number “13h” is accessed, the storage area with the register number “02h” is accessed.
The recording area (area relating to LED brightness and blinking cycle) in the section “13h” is repeatedly accessed. For example, if the register address is “10100”, the register number is “
After accessing the storage area of “14h”, the register number is “15h” → “16h” →
・ →→ Access the areas in the order of “1Bh” → “00h” → “01h” → Then, after accessing the storage area where the register number is “13h”, the register number is “
“02h” → “03h” →... “13h” → “02h” → “03h” →...

Returning to FIG. 17, the setting data 1803 to the work register is output following the setting data 1802 to the control register. This setting data 1803 is 2 in FIG.
This corresponds to “DATA” transmitted after the first.

When the automatic writing parameter is “000”, the setting data 1803 is 8-bit data necessary for updating one storage area designated by the register address. When the automatic write parameter is set to a value other than “000”, the setting data 1803 is a multiple of 8 necessary for repeatedly updating a plurality of areas starting from the storage area specified by the register address. Bit data.

FIG. 18 shows the master IC 57 when the master IC 570 of the first embodiment of the present invention specifies the slave individual address and sets the effect control data in the decoration control device 610.
A specific numerical value is applied to effect control data exchanged between 0 and the I ² CI / O expander 615. This figure illustrates the presentation control data that prohibits auto-increment and updates only one storage area of the work register, and is connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615. The case where the light emission state of LED is updated is assumed.

First, 8-bit data 1901 that is output first includes the destination decoration control device 61.
“1101100” indicating the slave address of the 0 I ² CI / O expander 615 is assigned.

The 8-bit data 1902 to be output next is set in the control register of the output setting register 635 of the I ² CI / O expander 615 assigned to set the automatic writing parameter and LED output data. Value to be included.

Here, since the light emission state of the LED connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615 is set, LEDOUT0 (address = 10100) is designated as the register address.

Note that “000” is designated in the auto-write parameter to prohibit auto-increment.

Next, the output 8-bit data 1903 includes data for setting the light emission mode of the decoration device 620 controlled by the destination decoration control device 610. Specifically, LE
Data to be set in the DOUT0 register is assigned. As a result, I ² CI /
The light emission state (lighting, extinguishing, blinking, etc.) of the LED connected to the PORT0 terminal to the PORT3 terminal of the O expander 615 is designated, and the LED emits light in the designated state.

In this way, the light emission state of the LED PORT0 terminal ~PORT3 terminal I ² CI / O expander 615 is controlled, the other PORT terminal I ² CI / O expander 615 (PORT4~PORT15) also Control can be performed by specifying the value of data 1902 to be written to the control register and setting output data 1903. To the PORT terminal
Even if a motor or solenoid is connected, the same control is performed.

FIG. 19 is a diagram illustrating another form of effect control data according to the first embodiment of this invention.
In this figure, it is assumed that auto-increment is permitted and all storage areas of the work register are updated, and the transmission order of each data included in the presentation control data is defined.

First, the master IC 570 transmits 8-bit data (data having the same format as the data 1901 in FIG. 18) that can specify the individual address of the decoration control device 610 to be controlled.

Next, the master IC 570 transmits data (data having the same format as the data 1902 in FIG. 18) set in the control register of the output setting register 635 of the I ² CI / O expander 615 to be controlled. In this figure, since the auto-increment is permitted and all the storage areas of the work register are updated, the automatic write parameter is “100”.
Is specified, and “00h” that is the head area of the work register is specified as the register address that specifies the write destination or the read start position.

Therefore, the decoration control device 6 to be controlled after receiving the control register set value
In the 10 I ² CI / O expander 615, the storage area (MODE1 register) whose register number is “00h” is updated first.

Next, after transmitting the control register set value, the master IC 570 transmits a value (total of 8 bits) to be written to the MODE1 register. When the I ² CI / O expander 615 receives the write value, it updates the value of the MODE 1 register, increments the register number, and prepares to update the next “01h” storage area (MODE 2 register). .

Next, the master IC 570 transmits values to be written to the MODE2 register (8 bits in total), and thereafter transmits the set values in order to the remaining storage area registers whose register numbers are “02h” to “1Bh”. . Each time the I ² CI / O expander 615 receives the write value, the I ² CI / O expander 615 updates the value of the corresponding register, increments the register number, and repeats the preparation for updating the next storage area. “00” assigned to
The values of all the registers “h” to “1Bh” are updated.

When the I ² CI / O expander 615 updates the storage area of “1Bh”, which is the last of the work registers, the register number is changed to “00h” and waits for the update of the MODE1 register.

FIG. 20 shows the case where the master IC 570 according to the first embodiment of the present invention uses the I ² CI / O expander 6.
5 is a diagram illustrating a data format of initialization instruction data transmitted from the master IC 570 to the I ² CI / O expander 615 when initializing 15.

When the CPU 551 of the effect control device 550 instructs the master IC 570 to initialize the decoration control device 610, the master IC 570 transmits initialization instruction data to all the decoration control devices 610 connected thereto. .

The 8-bit data 2001 output first includes a fixed address “11” shown in FIG.
0 ”and a reset address“ 1011 ”(see FIG. 12), which is a common address. This data 2001 corresponds to “ADDRESS” in FIG. 16, and “0” indicating writing is set in the bit of “R / W”.

In the 8-bit data 2002 to be output next, the first predetermined value “10100101” is output, and in the 8-bit data 2003 to be output next, the second predetermined value “01011010”.
Is output. This data 2002 is “D” transmitted first in FIG.
Corresponding to “ATA”, the data 2003 is “DATA” transmitted second in FIG.
Corresponding to

When all the I ² CI / O expanders 615 connected to the master IC 570 receive initialization instruction data including a reset address, a first predetermined value, and a second predetermined value,
Initialize itself.

After outputting the reset address, the first predetermined value and the second predetermined value are output.
Although the master IC 570 has not transmitted the reset address “1011”, the I ² CI / O expander 615 erroneously causes the reset address “101” due to the influence of noise or the like.
This is to prevent the initialization at the wrong timing by fetching “1”.

In addition, the reset address is different from the individual address, and all (in other words, a plurality of) I addresses.
² An address common to the CI / O expander 615. Therefore, only transmit once initialization instruction data including the reset address, it means that initialize Select I ² CI / O expander 615 all (plural), I ² CI / O Aix Compared with the method of individually selecting the panda 615 and instructing initialization, it is possible to instruct initialization at high speed.

In FIG. 20, the first predetermined value and the second predetermined value are different from each other, but may be the same value. Further, either the first predetermined value or the second predetermined value may be transmitted once.

  FIG. 21 is a diagram illustrating the abnormality determination table 2100 according to the first embodiment of this invention.

The abnormality determination table 2100 is stored in the RAM 553 of the effect control device 550. The abnormality determination table 2100 includes the master IC 570 and the master IC 57 of the effect control device 550.
This is for monitoring the connection state with the I ² CI / O expander 615 connected to 0, and corresponding to the confirmation result of the connection state, an error described later corresponding to the corresponding I ² CI / O expander 615. A flag 2105 is set.

The abnormality determination table 2100 includes an I / O expander address 2101, a slave address 2102, an error counter 2103, a comparison value 2104, and an error flag 2105.

The I / O expander address 2101 is an I ² CI / O connected to the master IC 570.
This corresponds to the addresses (see FIG. 8) set in the terminals A0 to A3 of the expander 615.

In the slave address 2102, the slave address registered in the I ² CI / O expander address table 1200 shown in FIG. 12 is registered.

When the error counter 2103 monitors whether or not the ACK from the I ² CI / O expander 615 has been received in response to the transmission of the effect control data from the master IC 570 to the I ² CI / O expander 615, It is incremented when it fails to receive this ACK twice in succession.

A predetermined value is registered in the comparison value 2104. In the error flag 2105, an error flag indicating whether or not an abnormality has occurred in the connection state of the entry with the I ² CI / O expander 615 is registered.

Specifically, when the incremented value of the error counter 2103 reaches a predetermined value registered in the comparison value 2104, the error flag 2105 is set to ON, and the I ² CI / O expander 615 of the entry. It is registered that an error has occurred.

The I ² CI / O of “0110” registered in the I / O expander address 2101
As shown in FIG. 8B, the expander 615 includes the accessory driving SOL560 and the accessory driving MOT5.
A movable device 61 is controlled. Therefore, the decoration control device 610 including the I ² CI / O expander 615 is referred to as a movable control device (movable group unit control means).

On the other hand, an I ² CI other than “0110” registered in the I / O expander address 2101
The / O expander 615 controls a light emitting device such as an LED as shown in FIG. 8A.
For this reason, the decoration control device 610 including the I ² CI / O expander 615 is referred to as a light emission control device (light emission group unit control means) in order to distinguish it from the aforementioned movable control device.

In FIG. 21, the value registered in the movable control device (I / O expander address 2101 is “
No entry of “0110”) exists, and only the entry of the light emission control device is registered.

When an abnormality occurs in the movable control device, the accessory driving MOT 561 rotates too much,
In order to prevent the movable accessory 60 from moving beyond the operable range and damaging the movable accessory 60 and members in the vicinity of the movable accessory, an abnormality is determined in a shorter time than the light emission control device. There is a need. Therefore, since the connection monitoring timing of the movable control device and the connection monitoring timing of the light emission control device are different, in other words, the configuration of the connection monitoring of the movable control device is different from the configuration of the connection monitoring of the light emission control device. The entry of the movable control device is excluded from 2100.

Specifically, in this embodiment, as will be described later, the data output process of the light emission control device (FIG. 2).
2) is executed in synchronization with the VDP interrupt (approximately 33.3 ms cycle), and the data output process of the movable control device is performed in synchronization with the timer interrupt (2 ms cycle). Yes.

As described above, in response to the second transmission of the effect control data from the master IC 570 to the I ² CI / O expander 615 provided in the light emission control device, an ACK from the I ² CI / O expander 615 is received. If not received, the error counter 2103 is incremented.

Therefore, when an abnormality has occurred in the light emission control device, the execution period of the data output process is 33 ms and the comparison value 2104 is “300”, so 33.3 ms × 300≈10 s.
To detect that an abnormality has occurred in the light emission control device.

When an abnormality has occurred in the movable control device, the data output processing execution cycle is 2 m.
As will be described later, since it is detected that an abnormality has occurred without waiting for the next execution cycle, it can be detected that an abnormality has occurred in the movable control device in a very short time (about 2 ms). .

For this reason, the error determination of the movable control device is performed more frequently than the error determination of the light emission control device, and it is possible to detect that an abnormality has occurred in the movable control device earlier than the abnormality has occurred in the light emission control device. Therefore, it is possible to prevent the movable accessory 60 from moving beyond the operable range and damaging the movable accessory 60 and members in the vicinity of the movable accessory.

On the other hand, a light emitting device such as an LED is less likely to be damaged due to a malfunction, and therefore no problem occurs even if it takes time to determine an abnormality related to the light emission control device.

Therefore, the determination cycle is limited to the decoration control device 610 that needs to perform the abnormality determination in a short time, and the abnormality determination of the other decoration control devices 610 is performed with a sufficient period, so that the processing load is balanced. It is possible to execute the abnormality determination process in consideration.

FIG. 22 is a flowchart of processing by the effect control device 550 according to the first embodiment of the present invention.

The processing of the effect control device 550 shown in FIG. 22 is executed by the CPU 551 of the effect control device 550.

When the production control device 550 is turned on, first, the production control device 550 is step 22.
After executing the processing of 01 to 2210, the process waits until a synchronization signal (for example, a synchronization signal having a 33 ms-second cycle) synchronized with the image update cycle is input from the VDP 556 to the CPU 551. Thereafter, each time the synchronization signal synchronized with the image update cycle is input from the VDP 556 to the CPU 551, the processing of steps 2204 to 2210 is repeatedly executed.

First, the effect control device 550 initializes the RAM 553 of the effect control device 550 (22).
01). At this time, the CPU 551 is based on the power-on time of the production control device 550.
The first control data to be output to the VDP 556 and the sound LSI 557 is also generated.

Next, the effect control device 550 executes an I ² C initial reset process for initializing the master IC 570 and the decoration control device 610 connected to the master IC 570 (2202). I ²
Details of the C initial reset process will be described with reference to FIG. When this I ² C initial reset process is executed, initialization operations of the accessory driving MOT 561 and the accessory driving SOL 560 are also started.

Then, the effect control device 550 synchronizes with the image update cycle from the VDP 556 (the synchronization signal (
(VDP interrupt) and timer interrupt acceptance are permitted (2203).

Then, the effect control device 550 displays the image on the display device 53 in order to display the VDP 556.
In order to output data as a command to display an image on the screen (2204), and to output sound from the speaker 30 according to the gaming state, sound control data is output to the sound LSI 557, and the sound LSI 55 is output.
7 is caused to output a sound from the speaker 30 based on the sound control data (2205).

Next, the effect control device 550 executes light emission control slave output processing for outputting effect control data from the master IC 570 to the light emission control device (2206). Details of the light emission control slave output processing will be described with reference to FIG.

Then, the effect control device 550 edits the next data output to the VDP 556 (22
07), the sound control data output next to the sound LSI 557 is edited (2208), and the effect control data output next to the light emission control device of each group is edited (2209).

Next, the effect control device 550 refers to the abnormality determination table 2100 and regards that the reset condition is satisfied when the error flags 2105 of all the light emission control devices are ON, and the master IC 570 and the accessory driving MOT 561 Then, the I ² C ad hoc reset process for instructing the initialization of all the I ² CI / O expanders 615 and the accessory driving SOL 560 connected to the master IC 570 is executed (2210), and then the synchronization signal is sent from the VDP 556 to the CPU 55
Wait until 1 is entered. Details of the I ² C occasional reset process will be described with reference to FIG.

In the process according to FIG. 22, in synchronization with the cycle of updating the image on the display device 53, the effect control data is transmitted from the master IC 570 of the effect control device 550 to the I ² CI / O expander 615 of the decoration control device 610. ^{2 Since the} CI / O expander 615 controls the decoration device 620 based on the received effect control data, the effect on the display device 53 and the effect on the decoration device 620 are harmonized, and the player does not feel uncomfortable. Can be increased.

Also, whenever the decoration control device 610 receives the effect control data transmitted from the master IC 570 in synchronization with the cycle of updating the image on the display device 53, the I ² CI / O expander 615 updates the work register. The value is updated. Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it can be restored to a normal value.

Further, since the error determination process executed in the process of step 2211 is executed in synchronization with the cycle of updating the image of the display device 53, the error determination execution frequency can be made appropriate.
If the execution frequency of the error determination process is too high, the processing load of the CPU 551 of the effect control device 550 increases. Conversely, if the execution frequency of the error determination process is too low, it is possible to appropriately detect that an abnormality has occurred. Therefore, it is possible to prevent processing problems by performing error determination at an appropriate frequency.

FIG. 23 is a flowchart of the I ² C initial reset process according to the first embodiment of this invention.

The I ² C initial reset process is performed immediately after the power to the production control device 550 is turned on.
70, a process for instructing initialization of all the I ² CI / O expanders 615 connected to the master IC 570, and is executed in the process of step 2202 shown in FIG. During the process, the start of the initialization operation of the accessory driving MOT 561 and the accessory driving SOL 560 is instructed. First, the CPU 551 of the effect control device 550 displays a reset request flag indicating that initialization is in progress. Setting is performed (2301), a reset pulse is input to the master IC 570 via the input / output I / F 558 and the NOR gate circuit 590, and the master IC 570 is initialized (hard reset) in hardware (2302).

The hard reset means that a master IC 570 is connected to a reset circuit (not shown) of the master IC 570.
This means that the reset circuit of the master IC 570 resets the master IC 570 itself when the voltage applied to the RESET terminal is held at a low level for a predetermined time. The RESET terminal functions as an initialization signal input instruction terminal in the present embodiment.

In the present embodiment, as described above, the reset signal applied to the RESET terminal is as follows.
It is also connected to other circuits provided in the effect control device 550. The other circuits are, for example, the VDP 556 and the sound LSI 557, and are initialized by the CPU 551 when the presentation control device 550 is powered on and activated. Therefore, when the power is turned on, these circuits can be initialized together with the master IC 570 by a hard reset, so that high-speed processing can be expected.

Next, the effect control device 550 includes all the decoration control devices 6 connected to the master IC 570.
In order to initialize the 10 I ² CI / O expander 615, slave reset processing for outputting initialization instruction data from the master IC 570 is executed (2303). The slave reset process will be described in detail with reference to FIG.

Next, since the initialization of the master IC 570 and the I ² CI / O expander 615 has been completed in the process of step 2302 and the process of step 2303, the effect control device 550 cancels the reset request flag (2304). And the production control device 550 is the accessory driving MO.
A motor initialization flag indicating that T561 is being initialized is set (2305). The initialization of the accessory driving MOT 561 is a process of returning the rotation axis of the accessory driving MOT 561 to the initial position, and is performed by a timer interrupt process shown in FIG.

Next, the effect control device 550, when initializing the accessory driving MOT 561, the accessory driving MO
The motor output data output to T561 is set in the RAM 553 (2306). Then, the effect control device 550 initializes the accessory driving SOL 560 to perform the accessory driving SOL5.
The off data for changing the energized state of 60 to the de-energized state is output to the accessory drive SOL 560 (230
7) The process proceeds to step 2203 shown in FIG. The initialization of the accessory driving SOL 560 is to change the energized state of the accessory driving SOL 560 to a non-energized state.

The CPU 551 inputs a reset pulse to the master IC 570 via the input / output I / F 558 and the NOR gate circuit 590 to reset the master IC 570 in hardware. However, the CPU 551 resets the reset register 573 via the bus 563. The master IC 570 may be reset by software by writing information into the.

  FIG. 24 is a flowchart of slave reset processing according to the first embodiment of this invention.

Slave reset process is a process of transmitting an initialization instruction data for initializing the I ² CI / O expander 615 to I ² CI / O expander 615, the process of step 2303 shown in FIG. 23, and FIG. This is executed in the process of step 2706 shown in FIG.

The initialization instruction data is transmitted from the master IC 570 in the byte mode. In byte mode, the master IC570, every time one byte transmit data to I ² CI / O expander 615 receives the ACK or NACK from the I ² CI / O expander 615, receiving either an ACK or NACK Even in this case, an interrupt signal is output to the CPU 551. In other words, if transmission of 1-byte data from the master IC 570 to the I ² CI / O expander 615 is completed, the master IC 570 always sends the CPU 55 to the CPU 55 regardless of reception of ACK / NACK.
An interrupt signal is output to 1.

First, the master IC 570 changes the signal levels of the connection line SDA and the connection line SCL to a signal level indicating a start condition (2401).

Next, the CPU 551 sets 1-byte data indicating the reset address (see FIG. 20) in the output BUF 572 (2402).

Then, from the time when the CPU 551 instructs the master IC 570 to start data transmission,
In order to monitor the time until the master IC 570 transmits an interrupt signal to the CPU 551,
Start of the monitoring timer for the byte mode is started (2403). Hereinafter, this monitoring time is referred to as byte mode monitoring time.

If the CPU 551 does not accept an interrupt signal from the master IC 570 even after a predetermined time has elapsed since the start of monitoring of the byte mode time, a time-out occurs.
In order to interrupt the data transmission, the master IC 570 outputs a stop condition (2415).
Thereafter, the process returns to step 2401, and the master IC 570 is made to output the start condition again, and then the initialization instruction data is transmitted from the first data.

Next, the master IC 570 outputs the reset address set in the output buffer 572 in the process of step 2402 to the I ² CI / O expander 615 (2404). When outputting the reset address, the master IC 570 temporarily turns off the driver 576A to release the connection line SDA (change it to high level). If the connection line SDA is not released (even if the driver 576A is turned off, the connection line SDA remains at a low level instead of a high level), the reset address output is It waits until the line SDA is released (the connection line SDA becomes high level).

Next, the master IC 570 determines whether or not an ACK response signal has been input to the master IC 570 within a predetermined time (a monitoring time shorter than the above-described byte mode monitoring time) from the completion of data output for one byte. Is confirmed (2405).

Then, the master IC 570 determines whether or not an ACK response signal is input within a predetermined time after the data is output based on the confirmation result of the processing in step 2405 (
2406).

If it is determined in step 2406 that an ACK response signal has not been input within a predetermined time after data is output, master IC 570 sets information indicating that the response signal is NACK in status REG579. Then, generate an interrupt signal. As a result, the NACK response signal is received from the I ² CI / O expander 615.
U551 is notified. At this time, the CPU 551 ends the time monitoring in the byte mode (
2407).

Next, the CPU outputs a stop condition to the master IC 570 in order to interrupt the data transmission (2415), and then returns to the processing of step 2401 and again master IC 570.
After outputting the start condition, the initialization instruction data is output again.

If it is determined in step 2406 that an ACK response signal is input within a predetermined time after the data is output, the master IC 570 sets information indicating that the response signal is ACK in the status REG579. Then, an interrupt signal is generated. As a result, I
^{2 The} CPU 551 is notified that an ACK response signal has been received from the CI / O expander 615. At this time, the CPU 551 ends the time monitoring in the byte mode (2408).
.

The CPU 551 outputs all three types of data constituting the initialization instruction data (data 2001 including the reset address, data 2002 of the first predetermined value, and data 2003 of the second predetermined value shown in FIG. 20). It is determined whether or not (2409). Since the output order of these data is determined in advance, in the processing of step 2409, it may be determined whether or not it is immediately after the data 2003 of the second predetermined value is output.

If it is determined in step 2409 that all the data constituting the initialization instruction data has been output, that is, if data indicating the second predetermined value shown in FIG. 20 has been output, the master IC 570 connects The signal levels of the line SDA and the connection line SCL are changed to signal levels indicating a stop condition (2410), and the slave reset process is terminated.

If it is determined in step 2409 that all the data constituting the initialization instruction data has not been output, the CPU 551 uses the 1-byte data to be transmitted next as the output BU.
F572 is set (2411). In the processing of step 2411 executed immediately after outputting the reset address, the output BUF 572 contains the first predetermined value data 20 shown in FIG.
In the process of step 2411 executed immediately after the data of the first predetermined value is set and 02, the data 2002 of the second predetermined value shown in FIG. 20 is set in the output BUF 572.

Then, from the time when the CPU 551 instructs the master IC 570 to start data transmission,
In order to monitor the time until the master IC 570 transmits an interrupt signal to the CPU 551,
Start of the monitoring timer for the byte mode is started (2412).

Next, the master IC 570 monitors the voltage level of the connection line SDA, confirms that the connection line SDA is released (2413), and then outputs 1-byte data set in the output BUF 572 ( 2414), the process proceeds to step 2405. In the processing of step 2413, the connection line SDA is occupied by the response signal until the output of the response signal from the group unit control means is completed, so that the master IC 570 outputs the response signal from the group unit control means. This is a process of waiting until the connection line SDA is released.

As described above, every time 1-byte data is output (that is, during the transmission of 3-byte initialization data), the initialization instruction data indicates whether or not there is a response signal for the output 1-byte data. Is transmitted in a byte mode for monitoring whether or not an output signal is output.

In the processing of step 2403 and the processing of step 2412, monitoring of the time from when 1-byte data is transmitted until the interrupt signal is output from the master IC 570 is
Although it is performed by the PU 551, the time from when the master IC 570 itself transmits 1-byte data to when the master IC 570 outputs an interrupt signal may be monitored.

FIG. 25 is a flowchart of light emission control slave output processing according to the first embodiment of this invention.

The light emission control slave output process is performed by the I ² CI / O expander 615 connected to the light emitting device.
This is a process of transmitting the issuance control data to the (light emission control device), and step 220 shown in FIG.
6 is executed.

The effect control device 550 selects one light emission control device from a plurality of light emission control devices (25
01), a slave continuous process for outputting data from the master IC 570 to the light emission control device selected in the process of step 2501 is executed (2502). Details of the slave continuous processing will be described with reference to FIG.

Then, the effect control device 550 determines whether data is output to all the light emission control devices (2503).

If it is determined in step 2503 that data has not been output to all the light emission control devices, the next light emission decoration control device is selected (2504), and the light emission control device selected in step 2504 is mastered. Slave continuous processing for outputting data from the IC 570 is executed (2502).

On the other hand, if it is determined in step 2503 that data has been output to all the light emission control devices, the CPU 551 causes the master IC 570 to output a stop condition to end the light emission control slave output processing (2505), and FIG. The process proceeds to step 2207 shown in FIG.

  FIG. 26 is a flowchart of slave continuous processing according to the first embodiment of this invention.

The slave continuous processing is processing for transmitting the light emission control data, which is the effect control data, to the I ² CI / O expander 615 connected to the light emitting device. Step 2502 shown in FIG.
This process is executed.

The light emission control data is transmitted from the master IC 570 in the buffer mode. In the buffer mode, the master IC 570 receives a plurality of bytes of data stored in the output BUF 572,
I ² CI / O Aix to expander 615 transmits each byte, each of the transmission and receives an ACK or NACK from the I ² CI / O expander 615. When a NACK is received, an interrupt signal is output to the CPU 551 at that time.

However, when ACK is received, an interrupt signal is output to the CPU 551 only when transmission of all data stored in the output BUF 572 is completed. Master IC 570
When an ACK is received from the I ² CI / O expander 615 with unsent data remaining in the output BUF 572, the output B is not output to the CPU 551.
The next data to be transmitted is extracted from the UF 572 and output to the I ² CI / O expander 615.

In other words, in the buffer mode, the master IC 570 does not transmit the data stored in the output BUF 572 to the I ² CI / O expander 615 until I ² CI.
As long as ACK is continuously received from the / O expander 615, the processing is continued without passing the processing to the CPU 551.

First, the CPU 551 sets 0 to an ACK counter that counts failure in receiving an ACK response signal (2601).

Next, the CPU 551 generates data to be output to the selected decoration control device 610 (2602).

Then, the CPU 551 outputs the data generated by the processing of step 2602 to the output BUF.
The buffer setting process set to 572 is executed (2603). The data to be set is shown in FIG.
9 is the format of the production control data shown in FIG. 9, and according to the transmission order shown in FIG.
The data is transmitted to the I ² CI / O expander 615 while being divided for each byte.

Then, the master IC 570 changes the signal levels of the connection line SDA and the connection line SCL to a signal level indicating a start condition (2604).

Specifically, the master IC 570 outputs a signal indicating a start condition by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH.

Note that, after outputting a signal indicating the start condition, the master IC 570 changes the level of the connection line SCL to LOW in order to send data to the decoration control device 610 to be controlled.

Next, the CPU 551 starts activation of the monitoring timer for the buffer mode in order to monitor the time from when the master IC 570 is instructed to start data transmission until the master IC 570 transmits the interrupt signal to the CPU 551. (2605). Hereinafter, this monitoring time is referred to as buffer mode monitoring time.

Then, the master IC 570 obtains data for 8 bits corresponding to the slave address of the decoration control device 610 to be controlled from the head of the data set in the output BUF 572, and uses the value of this address as the connection line SCL. The connection line SD while changing the signal level of
Output via A (2606).

Since the address data output in the process of Step 2606 is an 8-bit data string, the address data is output in one output process (output while the connection line SCL changes to HIGH for 8 times).

When the master IC 570 outputs the slave address, the driver 5 temporarily
The operation of turning off 76A to release the connection line SDA (change it to high level) is performed. If the connection line SDA is not released, the slave address output waits until the connection line SDA is released.

The address data output in step 2606 is the I ² CI / O expander 61.
5, the I ² CI / O expander 615 determines whether or not the input address data matches the address set in itself.

The I ² CI / O expander 615 in which an address that matches the input address data is set immediately after the connection line SCL is changed from LOW to HIGH for the eighth time, A response signal is output from the connection line SDA to the master IC 570 when the connected connection line SCL changes to the LOW level.

Next, the master IC 570 confirms whether or not an ACK response signal is input to the master IC 570 within a predetermined time after the address data is output in the process of step 2605 (
2607).

Next, the master IC 570 determines whether or not an ACK response signal is input within a predetermined time after the address data is output in the process of step 2602 based on the confirmation result of the process of step 2606 (2608). ).

If it is determined in step 2608 that an ACK response signal is not input within a predetermined time after the address data is output in step 2605, the master I
C570 sets information indicating that the response signal is NACK in the status REG579, and then generates an interrupt signal. This causes the I ² CI / O expander 615 to
The CPU 551 is notified that the CK response signal has been received. At this time, the CPU 551
Ends the time monitoring in the byte mode (2609).

When the CPU 551 receives an interrupt signal in step 2609, it instructs the master IC 570 to issue a stop condition. The master IC 570 instructed to issue the stop condition controls the signal levels of the connection line SDA and the connection line SCL, and issues a stop condition (2610). Thereafter, it is determined whether or not the ACK counter is 0 (2611).
).

If it is determined in step 2611 that the ACK counter is 0, the ACK counter is updated by 1 to count that the reception of the ACK response signal has failed (2612).
In order to transmit the same data to the decoration control device 610 again, the processing returns to step 2602.

On the other hand, if it is determined in step 2611 that the ACK counter is not 0, CP
U551 is the I ² CI / O expander 615 of the decoration control device 610 in which the I / O expander address 2101 is selected from the entries registered in the abnormality determination table 2100.
The entry matching the address of the selected entry is selected, and the error counter 2103 of the selected entry is selected.
Is incremented (2613).

Then, the CPU 551 determines whether or not the value of the error counter 2103 incremented in step 2613 has reached the comparison value 2104 (2614).

If it is determined in step 2614 that the value of the error counter 2103 incremented in step 2613 has reached the comparison value 2104, the CPU 551
Of the entries registered in the abnormality determination table 2100, the selected decoration control device 610 is selected.
Is set to ON (2615), and the slave continuous output process is terminated.

On the other hand, if the error counter 2103 incremented in the process of step 2613 has not reached the comparison value 2104, if it is determined in the process of step 2614, the slave continuous output process is terminated.

On the other hand, if it is determined in step 2608 that an ACK response signal has been input within a predetermined time, the master IC 570 determines whether all data stored in the output BUF 572 has been output. (2616).

If it is determined in step 2616 that all data stored in the output BUF 572 has been output, the master IC 570 sets information indicating that the response signal is ACK in the status REG 579. Generate an interrupt signal. As a result, I ²
The completion of the transmission of all the byte data to the CI / O expander 615 indicates that the CPU 551
Will be notified. At this time, the CPU 551 ends the time monitoring in the buffer mode (26
19).

Then, the CPU 551 performs the abnormality determination table 21 after executing the processing of step 2619.
Of the entries registered in 00, the entry that matches the address of the I ² CI / O expander 615 of the decoration control device 610 for which the I / O expander address 2101 is selected is selected, and the error counter of the selected entry is selected. 2103 is initialized to zero (2620), the error flag 2105 of the entry is set to OFF (2621), the process proceeds to step 2615, and the master IC 570 outputs a signal indicating a stop condition.

On the other hand, if it is determined in step 2616 that all data stored in the output BUF 572 has not been output, the master IC 570 monitors the voltage level of the connection line SDA, and the connection line SDA After confirming that it is open (2617), 1-byte data to be transmitted next is transmitted among the data stored in the output BUF 572 (26).
18) The process proceeds to step 2607.

As described above, the emission control data is monitored by the master IC 570 every time 1-byte data is output (that is, while the emission control data is being transmitted).
As long as the CK response signal is input, all data stored in the output BUF 572 is transmitted in the buffer mode in which the processing is not delivered from the master IC 570 to the CPU 551 until the transmission is completed.

Here, the initialization instruction data including the common address is transmitted in the byte mode. As shown in FIG. 24, every time transmission of 1-byte data is started, the master IC 57
The time (byte mode monitoring time) from 0 until the interrupt signal is returned to the CPU 551 is monitored.

On the other hand, the light emission control data including the slave address serving as the individual address is transmitted in the buffer mode. As shown in FIG. 26, the last byte is stored from the start of data transmission of the first byte stored in the output BUF572. The time until the end of data transmission (buffer mode monitoring time) is monitored.

In the present embodiment, when data is transmitted from the effect control device 550 to the decoration control device 610, either the byte mode or the buffer mode described above is selected. Here, characteristics of the byte mode and the buffer mode will be described.

In the byte mode, no matter what response signal is input from the decoration control device 610 (either ACK or NACK) to 1-byte data transmitted from the master IC 570, an interrupt signal is immediately transmitted from the master IC 570 to the CPU 551. The At this time, in the byte mode monitoring time, a time value is set in accordance with the time required for transmitting 1-byte data and receiving a response signal.

When an ACK response signal is transmitted from the decoration control device 610 to the master IC 570, the CPU 551 determines that 1-byte data transmission has been successful and performs the following processing. On the other hand,
The CPU 551 determines that an error has occurred in data transmission when a NACK response signal is transmitted from the decoration control device 610 to the master IC 570, or when the byte mode monitoring time has timed out, and necessary processing is performed. I do.

On the other hand, in the buffer mode, an interrupt signal is immediately sent from the master IC 570 to the CPU 551 only when a NACK response signal is input from the decoration control device 610 to 1-byte data transmitted from the master IC 570. Communicated. However, when an ACK response signal is input from the decoration control device 610, an interrupt signal is transmitted from the master IC 570 to the C if the data stored in the output BUF 572 is not all transmitted.
Without being transmitted to the PU 551, the master IC 570 performs a process of successively transmitting data stored in the output BUF 572.

Therefore, in the data transmission in the buffer mode, the number of times that the interrupt signal is transmitted from the master IC 570 to the CPU 551 is smaller than in the data transmission in the byte mode. The overall transmission time when transmitting a plurality of bytes of data can be shortened.

On the other hand, in the buffer mode, as long as the ACK response signal is continuously input from the decoration control device 610, until the transmission of all the data to be transmitted is completed from the master IC 570
Processing is not handed over to PU551. Therefore, whenever a state in which data cannot be transmitted using the connection line SDA occurs for some reason during data transmission, the master IC 570 is generated each time.
As a result, data transmission is interrupted and the time from when the master IC 570 is transferred to the CPU 551 may become very long.

In order to monitor the time until the process is transferred from the master IC 570 to the CPU 551, the above-mentioned buffer mode monitoring time has a time value that matches the time required for data transmission of all bytes to be transmitted and reception of the response signal. Is set. Inevitably, the buffer mode monitoring time is set longer than the byte mode monitoring time described above.

When an ACK response signal is transmitted from the decoration control device 610 to the master IC 570, the CPU 551 determines that data transmission of all the bytes to be transmitted has been successful, and performs the following processing. On the other hand, when a response signal of NACK is transmitted from the decoration control device 610 to the master IC 570 or when the buffer mode monitoring time has timed out, the CPU 551
Determine that an error has occurred in data transmission and perform the necessary processing.

From the above, if it is assumed that no abnormality will occur with respect to data transmission, data of a plurality of bytes (necessarily becomes data having a bit number longer than 8 bits which is a transmission unit).
When data is transmitted, it is certain that data transmission using the buffer mode can perform higher-speed processing than data transmission using the byte mode. However, considering the possibility of anomalies during data transmission, the byte mode has the advantage that processing can be performed while confirming the completion of data transmission for each byte, so which mode is superior Cannot be compared.

In the present embodiment, initialization instruction data is transmitted in the byte mode, and the light emission control data is transmitted in the buffer mode. The effects achieved by such a configuration will be described.

First, for initialization instruction data including a common address, an ACK response signal is output from all the decoration control devices 610 to which the common address is assigned in advance. On the other hand, for the light emission control data including the individual address, an ACK response signal is output from one decoration control device 610 to which the individual address is assigned in advance.

Therefore, when the initialization instruction data is transmitted, response signals are output from the plurality of decoration control devices 610. Therefore, the connection line SDA after transmitting the 1-byte data of the initialization instruction data.
The waiting time until the release is released depends on the time until all of the decoration control devices 610 release the connection line SDA. On the other hand, the waiting time until the connection line SDA is released after the 1-byte data of the light emission control data is transmitted is the time until only one decoration control device 610 to be transmitted opens the connection line SDA. Depends on time. Therefore, the former has a longer waiting time until the connection line SDA is released.

The initialization instruction data includes common address data 2001 and first predetermined value data 20.
02 and the second predetermined value data 2003 are transmitted in three times. further,
When these three types of initialization instruction data are not accurately transmitted to the decoration control device 610, a process of repeatedly transmitting the initialization instruction data is performed many times in order to reliably initialize the decoration control device 610. .

Here, the case where the initialization instruction data is transmitted using the buffer mode is compared with the case where the initialization instruction data is transmitted using the byte mode. In each mode, what happens when an abnormal state occurs in which the connection line SDA is not released for some reason after the transmission of the first common address data 2001 or after the transmission of the next first predetermined value data 2002? Explain how.

When the initialization instruction data is transmitted in the buffer mode, the buffer mode monitoring time includes A by transmission of the second predetermined value data 2003 from the start of transmission of the common address data 2001.
The time required for transmitting data of at least 3 bytes until the reception of CK must be set. For this reason, when the initialization instruction data is transmitted in the buffer mode, if an abnormality occurs in which the connection line SDA is not released, the CPU 551 waits for the buffer mode monitoring time to expire.

On the other hand, when the initialization instruction data is transmitted in the byte mode, the byte mode monitoring time includes
The time required to transmit at least one byte of data must be set. For this reason, when the initialization instruction data is transmitted in the byte mode, if an abnormality occurs in which the connection line SDA is not released, the CPU 551 waits for the time-up of the byte mode monitoring time.

For this reason, when the initialization instruction data is transmitted in the buffer mode, if an abnormality occurs in which the connection line SDA is not released, the CPU 551 waits for a long time-up time to elapse before canceling the abnormality. As a result, inefficient data transmission is performed.

On the other hand, when the initialization instruction data is transmitted in the byte mode, the connection line SDA
Even if an abnormality that cannot be released occurs, the CPU 551 cancels the abnormality after waiting for a short time-up time, so that useless time can be suppressed and efficient data transmission can be performed.

For this reason, in this embodiment, since the initialization instruction data is transmitted in the byte mode, an abnormality that the connection line SDA is not released can be detected quickly, and as a result, the data transmission time can be shortened.

In particular, as described above, the initialization instruction data is transmitted to the plurality of decoration control devices 610, and since it is monitored that all response signals are output from these decoration control devices 610, the connection line SDA is released. Since it is necessary to set the monitoring time itself longer, it is preferable to perform time monitoring using the byte mode.

On the other hand, in the present embodiment, the light emission control data is transmitted in the buffer mode. As described above, in the data transmission in the buffer mode, compared to the byte mode,
Since the number of times the interrupt signal is transmitted from the master IC 570 to the CPU 551 is reduced, the number of times the processing is transferred from the master IC 570 to the CPU 551 is reduced, and the overall transmission time when transmitting a plurality of bytes of data can be shortened. Because it can.

Note that the emission control data is transmitted in the buffer mode, and for some reason, the connection line SD
When an abnormal state in which A is not released occurs, the abnormality is canceled after the buffer mode monitoring time is up, and the light emission control data is retransmitted to the decoration control device 610 only once. If a transmission abnormality of the light emission control data occurs twice consecutively, the transmission of the light emission control data is stopped.

Therefore, when transmitting the light emission control data, the number of times the interrupt signal is output is reduced by reducing the number of times the interrupt signal is output, rather than reducing the useless time until the abnormality in which the connection line SDA is not released is detected.
Since the data transmission time can be shortened by reducing the processing load applied to the PU 551, the light emission control data is transmitted in the buffer mode in which the number of times the interrupt signal is output is smaller than that in the byte mode.

Also, as shown in FIG. 24, in the initialization instruction data, when the connection line SDA is not released and a timeout occurs, or a response signal for 1-byte data is sent to the master IC 5.
If it is not input to 70, retransmission is performed from the first data (data 2001 including the common address) of the initialization instruction data, and the initialization instruction data is the I ² CI / O expander 6
Since the retransmitted until received is repeatedly performed by 15, since the initialization command data is correctly received I ² CI / O expander 615 can be accurately initialize the I ² CI / O expander 615 . As shown in FIG. 26, in the light emission control data, if the connection line SDA is not released and a timeout occurs, or if a response signal for 1-byte data is not input to the master IC 570, the light emission is performed. Since re-transmission is performed only once from the first data of the control data, high-speed data transmission is possible.

Since the initialization of the I ² CI / O expander 615 is a process that is performed in order to eliminate the abnormality that occurred when the abnormality occurred, the initialization instruction data is I ² so that the initialization can be performed reliably.
The retransmission is repeatedly performed until the CI / O expander 615 receives the data reliably. On the other hand, even if the emission control data is not received by the I ² CI / O expander 615, the output mode of the light emitting device only stops in the previous output mode. Re-transmission is performed only once.

FIG. 27 is a flowchart of the I ² C occasional reset process according to the first embodiment of this invention.

The I ² C occasional reset process includes master IC 570, accessory driving MOT 561, master IC 5
70, all I ² CI / O expanders 615 connected to 70, and the accessory drive SOL 560
This is a process for instructing initialization, and is the process of step 2210 shown in FIG.

First, the effect control device 550 determines whether or not the reset request flag is ON (2
701).

If it is determined in step 2701 that the reset request flag is not on, the effect control device 550 refers to the abnormality determination table 2100 to determine whether or not a condition for instructing reset is satisfied. Whether or not an ACK response signal has been continuously received a predetermined number of times from all of the I ² CI / O expanders 615 to which the decoration device is connected among the I ² CI / O expanders 615 connected to the master IC 570 Is confirmed (2702).

Specifically, the effect control device 550 determines whether or not “ON” is registered in the error flag 2105 of all entries registered in the abnormality determination table 2100.

Next, the effect control device 550 determines whether or not a reset condition is satisfied based on the confirmation result of the processing in step 2702 (2703).

Specifically, when all the error flags 2105 are ON at the time of the processing in step 2702 (when there is no light emission control device in which the error flag 2105 is OFF), the processing in step 2703 is performed. It is considered that the reset condition is satisfied. In other cases, it is considered that the reset condition is not satisfied in step 2703.

If it is determined in step 2703 that the reset condition is satisfied, the effect control device 550 sets a reset request flag indicating that initialization is in progress (2704).

Then, the production control device 550 soft resets the master IC 570 (2705).
. Specifically, the CPU 551 writes a predetermined value to the reset REG 573 provided in the master IC 570 via the data bus. When a predetermined value is written in the reset REG 573 provided in the master IC 570, the controller of the master IC 570 causes the input BUF 571,
The values of the output BUF 572, the reset REG 573, and the transmission mode REG 574 are set to initial values, and the master IC 570 is initialized. The CPU 551 is connected to the master I via the data bus.
By writing a predetermined value into the reset REG 573 provided in the C570, the master IC
Initializing 570 is called soft reset.

In this embodiment, when the master IC 570 is hard reset, as described above, other circuits (circuits initialized when the power such as the VDP 556 and the sound LSI 557 are turned on) provided in the effect control device 550 are also initialized. When it is determined that an abnormality has occurred in the master IC 570, by performing such a soft reset, only the master IC in which the abnormality has occurred is reset, and even a circuit that is not directly related to the master IC 570 is reset. Prevents resetting.

Next, the effect control device 550 includes all the decoration control devices 6 connected to the master IC 570.
In order to initialize the 10 I ² CI / O expander 615, the slave reset process shown in FIG. 24 for outputting a reset signal from the master IC 570 is executed (2706).

As described above, when the master IC 570 is initialized, the initialization instruction data is transmitted to all the I ² CI / O expanders 615 connected to the master IC 570, so that the gaming machine 1 is surely initialized. can do.

Then, the effect control device 550 sets a motor initialization flag indicating that the accessory driving MOT 561 is being initialized (2707), and is output to the accessory driving MOT 561 when initializing the accessory driving MOT 561. Motor output data is set in the RAM 553 (2708).
. Then, in order to initialize the accessory driving SOL 560, the effect control device 550 sets off data in the RAM 553 to turn off the energization state of the accessory driving SOL 560 (270).
9) The reset request flag is canceled (2710), and the I ² C optional reset process is terminated.

If it is determined in step 2701 that the reset request flag is set, the initialization must be executed immediately, so that it is not determined whether the reset condition is satisfied. The process proceeds to 2705.

If it is determined in step 2704 that the reset condition is not satisfied,
Since initialization is not necessary, the process proceeds to step 2710, the reset request flag is canceled, and the I ² C optional reset process is terminated.

As described above, when it is determined that the reset condition is satisfied, in the process of step 2706, for all the I ² CI / O expanders 615 connected to the master IC 570,
Since initialization is simultaneously instructed, in other words, all I ² CI / O expanders 615
Since the I ² CI / O expander 615 is individually selected and the initialization is instructed, the initialization can be performed at a higher speed and the I ² CI can be initialized.
The / O expander 615 can be returned to a normal state at high speed.

Note that the RESET terminal (see FIG. 7) input to all the I ² CI / O expanders 615 is electrically connected to the CPU 551, and all the I ² CI / O are simultaneously transmitted from the CPU 551.
Even if the reset signal is transmitted to the RESET terminal of the expander 615, all I
It is possible to select and initialize ² CI / O expanders 615 simultaneously.

If the reset condition is deemed to be satisfied in the process of step 2702, the master IC 5
70, the master IC 570 is also initialized by the processing in step 2705.

The master IC 570 receives the connection line SDA and the connection line SC in response to a command from the CPU 551.
Since it functions as a signal level control means for controlling the L signal level, if an abnormality relating to data transmission occurs in all the light emission control devices, an abnormality may have occurred in the master IC 570 itself. Conceivable.

Therefore, when an abnormality relating to data transmission occurs in all the decoration control devices 610, the master IC 570 is initialized by the CPU 551 (arithmetic processing means) just in case. Accordingly, even if an abnormality occurs in the master IC 570, the master IC 570 can be reliably controlled.

Also, as shown in FIG. 22, in synchronization with the cycle of updating the image on the display device 53, the emission control data is transmitted from the master IC 570 of the effect control device 550 to the I ² CI / O expander 615, and the I ² CI Since the / O expander 615 controls the light-emitting device based on the received light-emission control, the effect on the display device 53 and the effect on the light-emitting device are harmonized and does not give the player a sense of incongruity. .

Further, whenever the decoration control device 610 receives the light emission control data transmitted from the master IC 570 in synchronization with the cycle of updating the image on the display device 53, the I ² CI / O expander 615 updates the work register. The value is updated. Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it can be restored to a normal value.

In addition, since the error determination process is executed in synchronization with the cycle of updating the image on the display device 53, the error determination execution frequency can be made appropriate. That is, if the error determination process is executed too frequently, the effect control apparatus If the processing load of the CPU 551 of the 550 increases and, on the contrary, the frequency of execution of the error determination process is too low, it becomes impossible to properly detect that an abnormality has occurred. It is possible to prevent processing problems by performing the above.

FIG. 28 is a flowchart of timer interrupt processing executed when a timer interrupt occurs according to the first embodiment of this invention.

The timer interrupt is executed in a form of interrupting the process shown in FIG. 22 when the CPU 551 accepts a timer interrupt generated at a cycle of 2 ms under the condition that the timer interrupt is permitted.

The timer interruption process is a process for outputting control data to the I ² CI / O expander 615 (movable control device) connected to the accessory driving MOT 561 and the accessory driving SOL 560 (movable object) to control the movable object. is there.

First, the effect control device 550 determines whether a reset request flag is set (2801).

If it is determined in step 2801 that the reset request flag has been set, the process waits for the reset processing of the decoration control device 600 including the movable control device to start. Finish the process.

On the other hand, if it is determined in step 2801 that the reset request flag is not set, the movable control device to be controlled is selected (2802), and the movable control device selected in step 2802 is selected. Then, a slave single output process for transmitting the movable control data which is the effect control data is executed (2803). The slave single output process will be described in detail with reference to FIG.

Next, the effect control device 550 determines whether or not the slave single-shot output process executed in the process of step 2803 has ended normally (2804). In the slave single output process, the first data output to the movable control device selected in the process of step 2802 has failed, and 2
If the second data output fails, the process ends abnormally.

If it is determined in step 2804 that the slave single-shot output process has not ended normally, that is, if it is determined that the slave single-shot output process has ended abnormally, the effect control device 550 causes the accessory drive MOT 561 to A motor initialization flag indicating that initialization is in progress is set (2805), and a reset request flag is set to start the reset processing of the decoration control device 600 (2806).

Then, the effect control device 550 sets the motor output data output to the movable control device in the RAM 553 when initializing the accessory driving MOT 561 (2807), and the accessory driving SOL.
Off data for turning off the energization state of the accessory driving SOL 560, which is output to the movable control device when initializing 560, is set in the RAM 553 (2808), and the timer interrupt process is terminated.

On the other hand, if it is determined in step 2804 that the slave single-shot output processing has ended normally, the motor initialization flag is set to determine whether or not to initialize the accessory driving MOT 561. It is determined whether or not (2809).

If it is determined in step 2809 that the motor initialization flag is set, it is determined whether or not the motor position detection sensor 510 has detected that the rotation axis of the accessory driving MOT 561 has returned to the initial position. Determine (2810).

If it is determined in step 2810 that the motor position detection sensor 510 has not detected that the rotation axis of the accessory driving MOT 561 has returned to the initial position, the processing proceeds to step 2807 to initialize the accessory driving MOT 561. The motor output data that is output to the movable control device in the case of conversion is set in the RAM 553.

On the other hand, in the process of step 2810, the motor position detection sensor 510 performs the accessory driving MOT 56.
When it is determined that the rotation axis of 1 has returned to the initial position, the accessory driving MOT 561 is detected.
In order to output stop data for stopping the rotation of the motor to the movable control device, it is set in the RAM 553 (2811). Since the initialization of the accessory driving MOT 561 is completed, the motor initialization flag is canceled (2812), Finish the process.

If it is determined in step 2809 that the motor initialization flag has not been set, the effect control device 550 determines whether an operation abnormality has been detected in the accessory driving MOT 561 (2813).

If it is determined in step 2813 that an abnormality has been detected in the accessory driving MOT 561, the process proceeds to step 2805 to initialize the accessory driving MOT 561.

On the other hand, if it is determined in step 2813 that no abnormal operation is detected in the accessory driving MOT 561, the effect control device 550 performs control for rotating the rotation axis of the accessory driving MOT 561 to the target value. In order to output data to the movable control device, it is set in the RAM 553 (2814), and solenoid output data indicating whether the accessory driving SOL 560 is to be energized or de-energized is output to the movable control device. Set to RAM553 (281
5) The timer interrupt process is terminated.

  FIG. 29 is a flowchart of slave single output processing according to the first embodiment of this invention.

The slave single output process is a process for transmitting the movable control data to the movable control device.
This is executed in the process of step 2803 shown in FIG.

The movable control data is transmitted from the master IC 570 in the byte mode. In byte mode, the master IC570, every time one byte transmit data to I ² CI / O expander 615 receives the ACK or NACK from the I ² CI / O expander 615, ACK and N
When any ACK is received, an interrupt signal is output to the CPU 551. That is, if transmission of 1-byte data from the master IC 570 to the I ² CI / O expander 615 is completed, the master IC 570 always receives the CPU 551 regardless of reception of ACK / NACK.
An interrupt signal is output.

First, the CPU 551 sets 0 to an ACK counter that counts failure in receiving an ACK response signal (2901).

Then, the master IC 570 changes the signal levels of the connection line SDA and the connection line SCL to a signal level indicating a start condition (2902).

Specifically, the master IC 570 outputs a signal indicating a start condition by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH.

Note that, after outputting a signal indicating the start condition, the master IC 570 changes the level of the connection line SCL to LOW in order to send data to the decoration control device 610 to be controlled.

Next, the CPU 551 sets the address data of the movable control device selected as the transmission target in the output BUF 572 (2903).

Then, from the time when the CPU 551 instructs the master IC 570 to start data transmission,
In order to monitor the time until the master IC 570 transmits an interrupt signal to the CPU 551,
Start of the monitoring timer for the byte mode is started (2904).

If the interrupt signal is not received even after a predetermined time has elapsed since the start of the monitoring of the byte mode time, the CPU 551 causes the master IC 570 to output a stop condition in order to interrupt the data transmission (2912). Thereafter, the value of the ACK counter is incremented by one, and the process returns to step 2902 to output the start condition again to the master IC 570, and then transmit the movable control data from the first data (address of the movable control device). . However, if the value of the ACK counter is a predetermined value (eg, “1”) at the time of step 2913,
The process ends.

Then, the CPU 551 outputs a command for transmitting the address data set in the output BUF 572 in the process of step 2902 to the master IC 57, and when the master IC 570 receives the command, the CPU 551 sets the output BUF 572 in the process of step 2902. The address data thus obtained is connected to the I ² CI via the connection line SDA while changing the signal level of the connection line SCL.
The data is transmitted to the / O expander 615 (2905). When the master IC 570 outputs the address data, the master IC 570 temporarily turns off the driver 576A to release the connection line SDA (change it to high level). If the connection line SDA is not released (even if the driver 576A is turned off, the connection line SDA remains at a low level instead of a high level), the output of this address data is It waits until the line SDA is released (the connection line SDA becomes high level).

Since the address data output in step 2905 is an 8-bit data string, the address data is output in one output process (output while the connection line SCL changes to HIGH eight times).

The address data output in step 2905 is the I ² CI / O expander 61.
5, the I ² CI / O expander 615 determines whether or not the input address data matches the address set in itself.

The I ² CI / O expander 615 in which an address that matches the input address data is set immediately after the connection line SCL is changed from LOW to HIGH for the eighth time, A response signal is output from the connection line SDA to the master IC 570 when the connected connection line SCL changes to the LOW level.

Next, the master IC 570 determines whether or not an ACK response signal has been input to the master IC 570 within a predetermined time (a monitoring time shorter than the above-described byte mode monitoring time) from the completion of data output for one byte. Is confirmed (2906).

Next, the master IC 570 determines whether or not an ACK response signal is input within a predetermined time after the address data is output in the process of step 2905 based on the confirmation result of the process of step 2906 (2907). ).

If it is determined in step 2907 that an ACK response signal has not been input within a predetermined time after the address data is output in step 2905, the master I
C570 sets information indicating that the response signal is NACK in the status REG579, and then generates an interrupt signal. This causes the I ² CI / O expander 615 to
The CPU 551 is notified that the CK response signal has been received. At this time, the CPU 551
Terminates the byte mode time monitoring (2911).

Next, in order to interrupt data transmission, the CPU 551 causes the master IC 570 to output a stop condition (2912), and determines whether or not the ACK counter is a predetermined value (291).
3).

If it is determined in step 2912 that the ACK counter is a predetermined value, the slave single output process is abnormally terminated.

On the other hand, if it is determined in step 2913 that the ACK counter is not a predetermined value,
The ACK counter is incremented, and the processing returns to step 2902 and the master IC 5 again.
After the start condition is output to 70, the same movable control data is output again (re-output from the address of the movable control device).

On the other hand, if it is determined in step 2907 that an ACK response signal has been input within a predetermined time after completion of outputting 1 byte of data in the processing of step 2905, the master IC 570 returns a response to status REG579. An interrupt signal is generated after setting information indicating that the signal is ACK. This causes the I ² CI / O expander 615 to
The CPU 551 is notified that the CK response signal has been received. At this time, the CPU 551
Terminates the byte mode time monitoring (2908).

Next, the CPU 551 determines whether or not all data to be output to the movable control device has been output (2909).

If it is determined in step 2909 that all data to be output to the movable control device has been output, the signal levels of the connection line SDA and the connection line SCL are changed to signal levels indicating a stop condition (2910). Complete the slave single output process normally.

On the other hand, if it is determined in step 2909 that the data to be output to the movable control device has not yet been output, the CPU 551 supplies the next 1-byte data to be output to the movable control device to the output BUF 572. Set (2915).

Next, in order to monitor the time from when the master IC 570 instructs the master IC 570 to start data transmission until the master IC 570 transmits the interrupt signal to the CPU 551, the CPU 551 starts to start the monitoring timer for the byte mode. (2916).

Monitoring of the time (byte mode time) from when 1-byte data is transmitted until an interrupt is issued to notify whether or not a response signal that is an ACK for the 1-byte data is input from the master IC 570 Is started (2916).

As described above, the CPU 551 sets a stop condition to the master IC 570 in order to interrupt data transmission when an interrupt signal is not received after a predetermined time has elapsed since the start of monitoring of the byte mode time. After that, the value of the ACK counter is incremented by one, and the process returns to the step 2902 to output the start condition to the master IC 570 again, and then the movable control data is set to the initial data (of the movable control device). Address).
However, if the value of the ACK counter is a predetermined value at the time of step 2913,
The process ends.

Next, the master IC 570 monitors the voltage level of the connection line SDA, confirms that the connection line SDA is released (2917), and then outputs 1-byte data set in the output BUF572 ( 2918), the process proceeds to Step 2906. In the process of step 2917, since the connection line SDA is occupied by the response signal until the output of the response signal from the group unit control means is completed, the master IC 570 outputs the response signal from the group unit control means. This is a process of waiting until the connection line SDA is released.

Thereafter, the movable control data is sequentially transmitted, and when the transmission of all the movable control data is completed, the process ends normally through the process of step 2910 as described above.

The order of the movable motion control data to be transmitted is in the format shown in FIG. 19 like the light emission control data. However, since the movable motion control data is transmitted in the byte mode, all data in the format shown in FIG. Instead of setting the output BUF 572 at a time, the data is transmitted while setting the output BUF 572 by dividing it by one byte from the beginning. Therefore, all data in the format shown in FIG. 19 (including motor and solenoid control data) is temporarily stored in the RAM 553.

Thereby, the accessory driving MOT 561 and the accessory driving SOL 560 controlled by the movable control device.
Outputs the movable control data in synchronization with the VDP interrupt (a period of about 33.3 ms). Since the movable member cannot be controlled in accordance with the production, a timer interrupt with a shorter period than the VDP interrupt (2
The movable control data is output in synchronization with the ms cycle. Thereby, it is possible to produce an effect by the movable member in accordance with the gaming state.

The movable control data is transmitted in the byte mode as shown in FIG. this is,
When an abnormality that does not release the connection line SDA occurs, the movable control device cannot be controlled,
The accessory drive MOT 561 may move the movable member beyond the preset movable range of the movable member. Therefore, the connection line SDA is released by performing a short time-up monitoring by the byte mode monitoring time. This is to immediately detect an abnormality that is not performed.

In the processing according to FIGS. 26 and 29, the master IC 570 determines the success or failure of the data transfer by fetching the response signal from the decoration control device 610 after outputting the 8-bit data, and the data transfer has failed. In this case (that is, when a NACK response signal is input to the master IC 570), the output data is output again only once, so that the data can be output to the decoration control device 610 as reliably as possible. Can be prevented from malfunctioning.

Note that when the master IC 570 transmits the start condition, the connection line SDA needs to be HIGH. However, due to the influence of noise or the like, the connection line SDA remains LOW and does not change. There is.

In the present embodiment, only the slave address that the master IC 570 transmits to the I ² CI / O expander 615 of the decoration control device 610 has R / W identification data “0” (means writing). (See FIG. 11), but due to the influence of noise and the like, R
The / W identification data may be transmitted to the I ² CI / O expander 615 in a state where the identification data is “1” (meaning reading).

In this case, the I ² CI / O expander 615 enters the read mode, and the master IC 57
In response to the signal level of the connection line SCL being changed by 0, processing for transmitting data bit by bit from the I ² CI / O expander 615 to the master IC 570 via the connection line SDA is performed.

At this time, every time the I ² CI / O expander 615 transmits 8-bit data,
A process of receiving an acknowledge signal from the master IC 570 via the connection line SDA is performed, and when the acknowledge signal is received, further 8-bit data transmission is performed. Thereafter, the 8-bit data transmission and the acknowledge signal confirmation are repeated. The connection line SDA is I ² CI
/ O expander 615 is in a dedicated state.

On the other hand, the I ² CI / O expander 615 performs the master IC after the 8-bit data transmission.
When an acknowledge signal cannot be received from the 570 via the connection line SDA, the connection line SDA
Is released to cancel data transmission. Note that the I ² CI / O expander 615 is the master I
When receiving an acknowledge signal from the C570 via the connection line SDA, if the connection line SDA is at the LOW level, it is interpreted that the acknowledge signal has been received. If the connection line SDA is at the HIGH level, the acknowledge signal must be received. Interpret.

Therefore, when the data from the master IC 570 changes due to the influence of noise or the like, and the I ² CI / O expander 615 that receives the changed data and enters the read mode is generated, the connection line SDA is changed. It will not be released forever.

In such a case, the signal level of the connection line SDA remains LOW, and the master IC 570 and the I ² CI / O of the decoration control device 610 that was originally intended to transmit.
Communication with the expander 615 via the connection line SDA cannot be performed.

Therefore, the master IC 570 outputs the connection line SDA before outputting a signal indicating the start condition.
In order to determine whether or not data is ready to be output, it is determined whether or not the signal level of the connection line SDA is HIGH.

When it is determined that the signal level of the connection line SDA is not HIGH, data cannot be output from the connection line SDA. Therefore, the driver 576A does not apply an operable voltage to the transistor 578A without turning on the transistor 578A (connection line With the SDA released, the signal level of the connection SCL is changed at least nine times.

By performing such processing, the I ² CI / O expander 61 that has entered the read mode is used.
5 outputs data to the connection line SDA in accordance with the change in the signal level of the connection SCL, but in the middle of the change of the signal level of the connection SCL at least nine times, the master IC 570
The timing for confirming the acknowledge signal from is generated. At this time, since the connection line SDA is released, it becomes HIGH level, and the I ² CI / O expander 615 that has entered the read mode determines that it has not received an acknowledge signal, so it stops data transmission and disconnects the connection line SDA. Will be released.

This process is performed not only before the signal indicating the start condition is output, but also in the master IC 57.
0 may be performed before the actual data is output to the decoration control device 610.

In this way, the connection line SDA is forcibly released from the I ² CI / O expander 615 of the decoration control device 610 in the read mode, so that the signal level of the connection line SDA is H
It will be maintained at IGH.

FIG. 30 is a diagram illustrating a connection form of the decoration control device 610 provided in the entire gaming machine according to the first embodiment of the present invention, and is a diagram illustrating the decoration control device 610 provided in the front frame 3 in particular.

The decoration control device 610 is mainly attached to the game board 10 and the front frame 3. The LED controlled by the decoration control device 610 attached to the front frame 3 irradiates the decoration member 9, the illumination unit 11, and the abnormality notification LED 29.

The gaming machine has a plurality of specifications, and there are a normal version gaming machine 1 and a low price gaming machine 1. The normal version gaming machine 1 includes a front frame 3 (normal version front frame) including a decorative member 9 of standard specifications. The low-priced gaming machine 1 includes a front frame 3 (low-priced front frame) including a decorative member 9 ′ configured at a lower cost than a standard decorative member 9.

The number of the decoration control devices 610 attached to irradiate the decorative member 9 is different between the normal plate front frame 3 and the inexpensive plate front frame 3. Specifically, the decoration member 9 of the normal plate front frame 3 is irradiated by four decoration control devices 610, and the decoration member 9 ′ of the inexpensive plate front frame 3 is irradiated by two decoration control devices 610. The decoration member 9 is illuminated by a maximum of 60 LEDs, whereas the decoration member 9 ′ is illuminated by a maximum of 30 LEDs, so that the decoration member 9 is brighter than the decoration member 9 ′. For this reason, the control of the decoration control device 610 when the normal plate front frame 3 is attached is different from the control of the decoration control device 610 when the inexpensive plate front frame 3 is attached.

I ² CI / O expander 61 of the decoration control device 610 attached to the normal front frame 3
If the address of 5 is the same as the unique address of the I ² CI / O expander 615 of the decoration control device 610 attached to the low-priced front frame 3, normal control is performed when the normal plate front frame 3 is attached. An effect control device 550 for the plate and an effect control device 550 for the cheap version that performs control when the cheap plate front frame 3 is attached are prepared, and the effect control device corresponding to the front frame 3 to be attached 550 must be replaced. Therefore, when the manufacturer ships the gaming machine 1, the effect control device 550 for the normal version and the effect control device 55 for the low-cost version.
0 must be prepared, which increases the manufacturing cost.

For this reason, in this embodiment, different addresses are assigned to the individual addresses of the I ² CI / O expander 615 of the decoration control device 610 whose control is different between the normal version front frame 3 and the inexpensive version front frame 3. The production control device 550 can perform control for the normal version and control for the inexpensive version. As a result, the production control device 550 for the normal version and the production control device 550 for the low-priced version.
It is no longer necessary to prepare the device and manufacturing costs can be reduced.

Specifically, the I ² CI / O expander 6 of the four decoration control devices 610 (first specification-dependent group unit control means) connected to the LEDs that irradiate the decoration member 9 of the normal plate front frame 3.
The 15 unique addresses include “1001”, “1010”, “1100”, and “1101”.
Is assigned.

On the other hand, the I ² CI / O expander 615 (second specification-dependent group unit control means) of the two decoration control devices 610 connected to the LEDs that irradiate the decoration member 9 ′ of the inexpensive front frame 3.
Is different from the unique address of the I ² CI / O expander 615 of the four decoration control devices 610 connected to the LEDs that irradiate the decoration member 9 of the normal plate front frame 3.
And “1111” are assigned.

Then, regardless of whether it is used for the normal version front frame 3 or the cheap version front frame 3, the effect control device 550 assigns it to the I ² CI / O expander 615 of the decoration members 9, 9 ′. Unique addresses “1001”, “1010”, “1100”, “1101”, “
Production control data including all of “1110” and “1111” is transmitted to the decoration control device 610.

Therefore, the decoration control device 610 of the normal plate front frame 3 and the decoration control device 610 for the low cost version can be controlled by one production control device 550 that can perform the control for the normal version and the control for the low cost version. Manufacturing cost can be reduced.

In addition, the I ² CI / O expander 615 of the decoration control device 610 connected to the illumination unit 11 that performs the same control in the normal version front frame 3 and the inexpensive version front frame 3 and the LED that emits the abnormality notification LED 29 includes: It is not necessary to use different addresses for the normal version front frame 3 and the low cost version front frame 3, and the same address is assigned.

In the low-priced front frame 3, the unique addresses are “1001”, “1010”, “1100
”And“ 1101 ”, the I ² CI / O expander 615 is not used, and the normal version front frame 3
Then, the I ² CI / O expander 61 whose unique addresses are “1110” and “1111”.
5 is not used. Therefore, the abnormality determination table 21 is used for the front frame 3 of any specification.
00 (FIG. 21), there is an unconnected I ² CI / O expander 615. As described above, one of the I ² CI / O expanders 615 registered in the abnormality determination table 2100 If data transmission / reception is performed with the master IC 570, it is processed as a normal state, so there is no problem.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS.

The second embodiment of the present invention is an embodiment in the case where the effect control device 550 includes a plurality of master ICs 570.

FIG. 31 is an explanatory diagram of the connection between the effect control device 550 and the decoration control device 610 according to the second embodiment of the present invention.

In the second embodiment, the effect control device 550 includes a plurality of master ICs 570.

  In FIG. 31, the production control device 550 includes three master ICs 570A to 570C.

The master IC 570A is connected to the relay board 600A, and the relay board 600A is connected in series with the decoration control devices 610A to 610C and the decoration control devices 610D to 610F.
Connected in series.

The master IC 570B is connected to the relay board 600B, and the relay board 600B is connected in series with the decoration control devices 610G to 610I and the decoration control devices 610J to 610L.
Connected in series.

The master IC 570C is connected to the relay board 600C. The relay board 600C is connected in series to the decoration control devices 610M to 610O, and is connected in series to the decoration control device 610P connected to the accessory driving SOL560 and the accessory driving MOT561. Connected.

Here, the decoration control device 610 group connected to one master IC 570 is referred to as a system. Specifically, in the case of the master IC 570A, the system is the relay board 600A and the decoration control devices 610A to 610F.

Since the master IC 570 can output data to the connected decoration control device 610, the master IC 570 can control the connected decoration control device 610.

With such a configuration, the number of I ² CI / O expanders 615 that can be controlled by one master IC 570 is eliminated (up to 14 as shown in FIG. 12), and a variety of presentation control is possible. Can be expected to do.

Also in this embodiment, the I ² CI / O registered in the abnormality determination table 2100 (see FIG. 32).
One I ² CI / O expander 615 of the expander 615 and the master IC 570
If data is sent to and received from, the process is performed in a normal state.
In addition, the first embodiment is different from the first embodiment in that initialization processing of the I ² CI / O expander 615 and the master IC 570 is performed independently for each system.

In the present embodiment, as shown in FIG. 32, an abnormality determination table 2100 is prepared for each system. In other words, the abnormality determination table 2100 corresponding to each master IC 570 is stored in the RAM 553 of the effect control device 550.

The abnormality determination table 2100 will be specifically described. FIG. 32 is an explanatory diagram of the abnormality determination table 2100 according to the second embodiment of this invention.

A first abnormality determination table 2100A for determining an abnormality in data transmission / reception performed between the master IC 570A and the decoration control devices 610A to 610F for each decoration control device, and a master IC 57
A second abnormality determination table 2100B for determining an abnormality in data transmission / reception performed between 0B and the decoration control devices 610G to 610L for each decoration control device, and data performed between the master IC 570C and the decoration control devices 610M to 610O. There are three types of tables, a third abnormality determination table 2100C for determining transmission / reception abnormality for each decoration control device.

An abnormality in data transmission / reception between the master IC 570 and the movable control device (decoration control device 610P) is not registered in the third abnormality determination table 2100C. The abnormality in data transmission between the master IC 570 and the movable control device is determined based on whether the process in FIG. 29 is completed normally or abnormally. If it is determined that the process ends abnormally, in the process in FIG. This is because the accessory driving SOL 560 is initialized.

If any abnormality determination table determines that a data transmission / reception abnormality has occurred with respect to all the I ² CI / O expanders 615, all the decoration control devices 610 belonging to the abnormality determination table are initialized. At the same time, the corresponding master IC 570 is also initialized. However, the decoration control device 610 and the master IC 570 belonging to other abnormality determination tables are not initialized.

For example, in the first abnormality determination table described above, all the I ² CI / O expanders 61
5, when it is determined that a data transmission / reception abnormality has occurred, only the master IC 570A and the decoration control devices 610A to 610F are initialized, and the other master ICs 570B, 570C are initialized.
The decoration control devices 610G to 610P are not initialized.

For this reason, even if the master IC 570 in which the data transmission abnormality has occurred and the decoration control device 610 connected to the master IC 570 in which the data transmission abnormality has occurred are being initialized, the master IC 570 and the decoration control device 610 in which no abnormality has occurred. Since the decoration control data can be transmitted / received between the two, the effect by the decoration device 620 can be prevented from being suddenly stopped during the game.

As a method for initializing the master ICs 570A to 570C, there are a soft reset and a hard reset.

In the soft reset, the CPU 551 initializes one of the master ICs 570A to 570C.

Specifically, each of the master ICs 570A to 570C has a reset REG 573 (FIG. 4).
See). When the CPU 551 writes a specific value (initialization instruction data) to the reset register via the bus 563, only the master IC 570 including the reset REG 573 written with the specific value is initialized.

In the hard reset, N connected to the input / output I / F 558 and the power-on detection circuit 559
When the RESET terminal of each of the master ICs 570A to 570C is connected to the OR gate circuit 590, and the voltage applied to the NOR gate circuit 590 is held low for a predetermined time, the RES
The voltage applied to the ET terminal is also held low for a predetermined time, and all the master ICs 570A-57
0C is initialized.

The NOR gate circuit 590 is connected to the RESET terminal of all the master ICs 570. When the voltage applied to the NOR gate circuit 590 is held low for a predetermined time, the voltage applied to the RESET terminals of all the master ICs 570. Also goes low for a predetermined time and is taken as an initialization signal by all the master ICs 570.

Note that a line connecting the NOR gate circuit 590 and the RESET terminal of the master IC 570 is a separate line from the bus 563.

In the present embodiment, all the master ICs 570 are reset by hardware reset when the power is turned on.
A to 570C are initialized, and the corresponding decoration control device 610 is initialized. If any abnormality determination table determines that a data transmission / reception abnormality has occurred with respect to all the I ² CI / O expanders 615, only the master IC belonging to the abnormality determination table is initialized by a soft reset. At the same time, the corresponding decoration control device 610 is initialized, but the other master IC and decoration control device 610 are not reset.

As described above, when the production control device 550 includes a plurality of master ICs 570, only the master IC in which an abnormality has occurred is reset, so that the decoration of the entire gaming machine 1 does not pause and the player feels uncomfortable. Can be suppressed. All master ICs 570
If you want to reset at a high speed at the same time, you can reset by hard reset,
Various forms of reset processing can be implemented.

In the second embodiment, the same processing as that of the first embodiment is executed, but only the processing different from that of the first embodiment will be described in detail with reference to FIGS. 33 and 34.

FIG. 33 is a flowchart of the I ² C initial reset process according to the second embodiment of this invention.
In FIG. 33, the same process as the I ² C initial reset process shown in FIG.

I ² C initial reset process is a process executed when the power is turned, in I ² C initial reset process of the second embodiment transmits an initialization instruction data to the decoration control device 610 which is connected to each master IC570.

Specifically, after all the master ICs 570 are hard reset in the process of step 2302, the CPU 551 selects the first master IC 570A (3301) and is connected to the master IC 570A selected in the process of step 3301. Decoration control devices 610A-6
Slave reset processing for transmitting initialization instruction data to 10F is executed (2303), and the decoration control devices 610A to 610F connected to the master IC 570A are initialized.

Then, the CPU 551 selects the second master IC 570B (3302), and the decoration control devices 610G to 610G connected to the master IC 570B selected in the process of step 3302 are displayed.
Slave reset processing for transmitting initialization instruction data to 610L is executed (2303), and the decoration control devices 610G to 610L connected to the master IC 570B are initialized.

Then, the CPU 551 selects the third master IC 570C (3303), and the decoration control device 610M to be connected to the master IC 570C selected in the process of step 3303.
Slave reset processing for transmitting initialization instruction data to 610P is executed (2303), and the decoration control devices 610M to 610P connected to the master IC 570C are initialized.

FIG. 34 is a flowchart of the I ² C optional reset process according to the second embodiment of this invention.
In FIG. 34, the same processes as the I ² C occasional reset process shown in FIG.

If it is determined in step 2701 that the reset request flag is set, or if it is determined in step 2703 that the reset condition is satisfied, the CPU 5
51 selects the master IC 570 for which the reset condition is satisfied (3401).
In the process 01, a predetermined value is written in the reset REG 573 provided in the master IC 570, and the master IC 570 is soft reset (3402).

Then, the CPU 551 executes slave reset processing for transmitting initialization instruction data to all the decoration control devices 610 connected to the master IC 570 selected in step 3401 (2706).

Next, the CPU 551 determines whether or not the master IC 570 in which the reset condition is satisfied is the master IC 570 (master IC 570C in FIG. 31) connected to the movable control device (
3403).

If it is determined in step 3403 that the master IC 570 for which the reset condition is satisfied is the master IC 570 connected to the movable control device, the accessory driving MOT 561 and the accessory driving SOL 560 controlled by the movable control device are set to the initial positions. Since the initialization process to return is executed,
Proceed to step 2707.

On the other hand, if it is determined in step 3403 that the master IC 570 for which the reset condition is satisfied is not the master IC 570 connected to the movable control device, the process proceeds to step 2710.

Thus, in this embodiment, since only the master IC 570 in which an abnormality is detected is soft reset, it is not necessary to initialize the master IC 570 in which no abnormality is detected, so that the decoration device whose output is temporarily stopped during the game The number of players can be minimized, and the uncomfortable feeling given to the player can be reduced.

Further, when the master IC 570 is initialized by a hard reset or a software reset, all the decoration control devices 610 connected to the master IC 570 to be initialized are also initialized, so that the abnormality can be reliably eliminated.

FIG. 35 is a timing chart before and after initialization of the master IC 570 upon power-on according to the second embodiment of the present invention.

When the gaming machine 1 is powered on, the CPU 551 executes the process of FIG. 22 and executes the I ² C initial reset process shown in FIG. In the process of Step 2302 shown in FIG. 33, all the master ICs 570 provided in the effect control device 550 have the RSE.
All the master ICs 570 provided in the effect control device 550 are held low for a predetermined time applied to the T terminal, and are hard reset.

In step 3301, the first master IC 570A is selected, and initialization instruction data is transmitted to all the I ² CI / O expanders 615 connected to the first master IC 570A.

Next, the second master IC 570B is selected in the process of step 3302, and the second master I
The initialization instruction data is transmitted to all the I ² CI / O expanders 615 connected to C570B.

Next, the third master IC 570C is selected in the process of step 3303, and the third master I
Initialization instruction data is transmitted to all the I ² CI / O expanders 615 connected to C570C.

When the movable control device (decoration control device 610P) receives the initialization instruction data from the third master IC 570, the motor initialization operation for returning the rotation axis of the accessory driving MOT 561 to the initial position is performed, which is shown in FIG. When the motor initialization flag is set in the process of step 2305 and the output data of the motor at the time of initialization is output in the process of step 2306, the motor initialization operation for returning the rotating shaft of the accessory driving MOT 561 to the initial position is performed. Executed.

When the I ² C initial reset process shown in FIG. 33 is completed, step 2 shown in FIG.
In the process 203, timer interruption is permitted. Thereafter, the VDP interrupt shown in FIG.
Each time 1 is input, the processing of steps 2204 to 2210 shown in FIG. 22 is repeatedly executed. When a timer interrupt is input to the CPU 551 in a cycle of 2 ms, the timer interrupt processing shown in FIG. 28 is executed.

Even during the motor initialization operation, the process of step 2206 shown in FIG.
Master ICs 570A and 570B, to which only the light emission control device is connected, transmit light emission control data to the light emission control device. Thereby, in the light emission control device connected to the master ICs 570A and 570B, normal decoration effect control is performed.

On the other hand, in the timer interruption process shown in FIG. 28 executed at a cycle of 2 ms, if the motor initialization operation is being performed, it is confirmed that the rotation axis of the accessory driving MOT 561 has been returned to the initial position in the process of step 2810. The motor initialization operation is executed until detection. During the motor initialization operation, the light emission control device connected to the master IC 570C stands by without performing a normal decoration effect. During this standby period, the light emission control data is not transmitted from the master IC 570C to the light emission control device, and the light emission device connected to the light emission control device connected to the master IC 570C does not start light emission.

When it is detected in step 2810 that the rotation shaft of the accessory driving MOT 561 has been returned to the initial position and the motor initialization operation is completed, the normal motor output data is obtained in step 2814 shown in FIG. Is transmitted, the decoration effect operation by the accessory driving MOT 561 becomes possible. At this time, normal decoration effect control is also started in the light emission control device connected to the master IC 570C.

As described above, even if the accessory driving MOT 561 is in the initialization operation by turning on the power, the master IC 5 connected to the movable control device that controls the accessory driving MOT 561 in the initialization operation.
Master ICs 570 other than 70 transmit decoration control data for performing normal presentation control to the decoration control device 610. Therefore, the light emitting device starts decoration display immediately after the power is turned on, so that the light emitting device is turned on after the power is turned on. The time required for checking the light emitting device immediately after power-on can be shortened.

On the other hand, in the master IC 570 connected to the movable control device that controls the accessory driving MOT 561 during the initialization operation, the master IC 570 again during the initialization operation.
Since there is a possibility that 570 may be initialized, the light emission of the light emitting device that performs light emission control again is made to stand by via the master IC 570 so that abnormal lighting is not performed.

FIG. 36 is a timing chart before and after initialization of the master IC 570 in which an abnormality has occurred according to the second embodiment of the present invention.

FIG. 36 illustrates a case where a reset condition is established in the third master IC 570C connected to the movable control device, that is, a case where an abnormality is detected in the third master IC 570C.

When an abnormality is detected in the third master IC 570, the third master IC 570 is selected in the process of step 3401 shown in FIG. 34, and the third master IC 570 is soft reset in the process of step 3402.

In step 2706 shown in FIG. 34, initialization instruction data is transmitted to all the decoration devices 620 connected to the third master IC 570. And master I of movable control
Since an abnormality is detected in C570C, a motor initialization flag is set in step 2707, and motor output data at the time of initialization is output in step 2708.

Even during the motor initialization operation, the processing of step 2206 shown in FIG. 22 is executed, and master ICs 570A and 570B to which only the light emission control device is connected transmit the light emission control data to the light emission control device. . Thereby, in the light emission control device connected to the master ICs 570A and 570B, normal decoration effect control is continuously performed.

On the other hand, in the timer interruption process shown in FIG. 28 executed at a cycle of 2 ms, if the motor initialization operation is being performed, it is confirmed that the rotation axis of the accessory driving MOT 561 has been returned to the initial position in the process of step 2810. The motor initialization operation is executed until detection.

During the motor initialization operation, in the light emission control device connected to the master IC 570C,
Waiting without performing normal decoration effects. During this standby period, the light emission control data is not transmitted from the master IC 570C to the light emission control device, and the light emission device connected to the light emission control device connected to the master IC 570C does not start light emission.

When it is detected in step 2810 that the rotation shaft of the accessory driving MOT 561 has been returned to the initial position and the motor initialization operation is completed, the normal motor output data is obtained in step 2814 shown in FIG. Is transmitted, the decoration effect operation by the accessory driving MOT 561 becomes possible. At this time, normal decoration effect control is also started in the light emission control device connected to the master IC 570C.

As described above, a master other than the master IC 570 connected to the movable control device that controls the accessory driving MOT 561 during the initialization operation even if the accessory driving MOT 561 is in the initialization operation due to the occurrence of an abnormality. Since the IC 570 continuously transmits decoration control data for performing normal presentation control to the decoration control device 610, the board surface of the gaming machine 1 becomes dark even if the accessory driving MOT 561 is frequently initialized. Can be prevented.

It should be noted that the embodiments disclosed in the present specification are naturally intended to be applicable not only to pachinko machines but also to other gaming machines such as pachislot machines.

Also, as an embodiment, a pachinko machine that generates a special game state corresponding to the result of the variable display game is disclosed, but not limited to the variable display game, the special game corresponding to the result of other auxiliary games Of course, it may be a gaming machine that generates a state.

For example, when a predetermined condition is satisfied, an entrance of a specific winning device is opened (the movable member of the specified winning device is actuated to open the entrance), and a game ball taken into the winning device is provided inside the winning device. A game in which lottery is selected for which winning area (there is a specific winning area or a general winning area) may be used as an auxiliary game. In this case, a special game state occurs when the game ball taken into the winning device wins a specific winning area.

In addition, as an embodiment, a pachinko machine that generates a special game state corresponding to the result of the special figure variation display game is disclosed, but in response to the result of the general figure variation display game (or It is naturally intended that the present invention can be applied even to a pachinko machine that generates a special gaming state (due to the result of the display game). For example, even a pachinko machine that generates a special game state when the entrance of a specific winning device is opened according to the result of the normal game display game and a game ball taken into the winning device wins a specific winning area. The present invention is applicable.

Further, as an embodiment, a configuration in which the game control device and the effect control device are separated is disclosed, but the game control device and the effect control device constitute a single control device. Of course, it is intended that the game control device itself may be configured as a group overall control means.

The embodiment disclosed this time is illustrative in all points and is not restrictive. The scope of the present invention is shown not by the above description of the invention but by the scope of claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims.

As described above, the present invention can be applied to a gaming machine in which an effect control device controls a decoration control device.

1 gaming machine 2 body frame (outer frame)
3 Front frame 4 Hinge 10 Game board 11 Illumination unit 17 Production button 18 Glass frame 34 Regular start gate 36 Regular variation prize device 42 Special variation prize device 44 General prize opening 45 First start prize opening 51 Center case 52 Window 53 Display Device 55 Vibration sensor 60 Movable accessory 500 Game control device 550 Production control device 560 Actor drive SOL
561 Actor Drive MOT
570 Master IC
573 Reset REG
574 Transmission mode REG
580 Dispensing control device 600 Relay board (decoration control device)
610 decoration device 620 decoration device 2100 abnormality determination table

In the game machine described in Patent Document 1, it is impossible to sufficiently reduce wiring.

The present invention aims to provide a game machine capable of reducing the number of connection lines for connecting the group supervisory controlling means and each group control unit.

The present invention Rutotomoni provided to divide the effect producing device for several to several groups, the group-unit control unit for controlling the effect device belonging to the divided groups in each group, each of said group unit control means A group overall control means for overall control, a timing signal line for transmitting a timing signal, a data signal line for transmitting a data signal, between the group overall control means and each group unit control means, Data transmission between the group overall control means and each group unit control means, and the group overall control means initializes itself when power supply to the group overall control means is started. The timing signal line and the data signal line have a pull-up resistor to which a predetermined power supply voltage is applied. The group overall control means and the pull-up resistor are arranged in the same control device, and the effects related to the game are controlled based on a command from the game control means for overall control of the game. The possible production control means is configured as a group overall control means for comprehensively controlling the group unit control means .

According to the present invention, it is possible to reduce the number of connection lines connecting the group overall control unit and the group unit control unit.

Claims (6)

In a gaming machine comprising game control means for overall control of a game and effect control means for controlling a plurality of effect devices for effecting a game in response to a command from the game control means,
Dividing the plurality of effect devices into a plurality of groups, and providing group unit control means for each group to control the effect devices belonging to the divided group,
The production control means is configured as a group overall control means for overall control of the plurality of group unit control means,
The group control unit includes a timing signal line for transmitting a timing signal from the group control unit to the group unit control unit, and a data line for communicating data between the group control unit and the group unit control unit. And the group unit control means are connected to enable data communication between the group overall control means and each group unit control means,
The group overall control means is:
Arithmetic processing means for performing arithmetic processing related to the control of the rendering device;
Signal level control means for controlling each signal level of the data line and the timing signal line based on a command from the arithmetic processing means;
A data bus that exchanges data with each other between the arithmetic processing means and the signal level control means,
The signal level control means includes
The group unit control means by repeatedly changing the signal level of the timing signal line while setting the signal level of the data line to a signal level corresponding to transmission data based on a transmission command from the arithmetic processing means. Transmitting means for sequentially transmitting data to
A reply signal fetching means for fetching a reply signal from the group unit control means after data transmission by the sending means;
Determining means for determining success or failure of data transmission according to the response signal captured by the response signal capturing means;
Initialization means for initializing the signal level control means;
An initialization instruction data storage area in which initialization instruction data for instructing initialization of the signal level control means is written to the initialization means via the data bus;
An initialization signal input instruction terminal that is provided separately from the data bus and receives an initialization signal that instructs the initialization means to initialize the signal level control means;
The group unit control means includes a response signal output means for outputting the response signal to the group overall control means via the data line on which the transmission means has transmitted data,
The initialization signal input instruction terminal passes through a predetermined output port from the arithmetic processing means,
The initialization signal is input without going through the data bus,
The initialization means includes
First initialization means for initializing the signal level control means by inputting the initialization signal to the initialization signal input terminal;
By writing the initialization instruction data in the initialization instruction data storage area,
And a second initialization means for initializing the signal level control means. The group overall control means includes a plurality of the signal level control means,
The arithmetic processing means and the plurality of signal level control means are connected by the data bus,
The initialization signal output from the arithmetic processing means is input to the initialization signal input terminal provided in the plurality of signal level control means,
When initializing all of the plurality of signal level control means, using the first initialization means provided in the signal level control means, all of the signal level control means are initialized,
When only a part of the plurality of signal level control means is initialized, the initialization instruction data is stored in the initialization instruction data storage area provided in the part of the signal level control means. 2. The gaming machine according to claim 1, wherein the part of the signal level control means is initialized by writing. The group overall control unit includes an abnormality detection unit that detects a signal level control unit in which an abnormality has occurred from the plurality of signal level control units based on a determination result of the determination unit,
3. The gaming machine according to claim 2, wherein the signal level control means detected by the abnormality detection means is initialized using the second initialization means provided in the signal level control means. 3. The group overall control unit, when the signal level control unit is initialized, instructs all group unit control units controlled by the signal level control unit to perform initialization. Or the game machine of Claim 3. The group of effect devices includes a group of light emitting devices that decorate the gaming machine by emitting light, and a group of movable devices that decorate the gaming machine by moving a movable member provided in the gaming machine,
The group unit control means includes a light emission group unit control means for controlling a group of the light emitting devices, and a movable group unit control means for controlling a group of the movable devices,
The group overall control means initializes all of the signal level control means provided in the group overall control means via a first initialization means provided in each signal level control means when a predetermined condition is satisfied, and Instruct initialization to the group unit control means connected to each signal level control means,
When the light emission group unit control means is instructed to initialize from the group overall control means, the light emission group unit control means controls the output state of the light emitting device controlled by the light emission group unit control means to not output,
When the movable group unit control means is instructed to initialize by the group overall control means, the movable group unit control means executes an initial position operation on the movable device to return the movable member controlled by the movable group unit control means to the initial position. Let
Even while the movable member is returned to the initial position, the signal level control means different from the signal level control means connected to the movable group unit control means transmits the light emission control data to the group unit control means. The gaming machine according to claim 2, wherein transmission is started. The group of effect devices includes a group of light emitting devices that decorate the gaming machine by emitting light, and a group of movable devices that decorate the gaming machine by moving a movable member provided in the gaming machine,
The group unit control means includes a light emission group unit control means for controlling a group of the light emitting devices, and a movable group unit control means for controlling a group of the movable devices,
The abnormality detection unit detects an abnormality of the signal level control unit connected to the movable group unit control unit when the determination unit determines that data transmission to the movable group unit control unit has failed,
The group overall control unit initializes a signal level control unit in which an abnormality is detected by the abnormality detection unit via a second initialization unit provided in the signal level control unit, and is connected to the signal level control unit. Instruct the group unit control means to initialize,
When the light emission group unit control means is instructed to initialize from the group overall control means, the light emission group unit control means controls the output state of the light emitting device controlled by the light emission group unit control means to not output,
When the movable group unit control means is instructed to initialize by the group overall control means, the movable group unit control means executes an initial position operation on the movable device to return the movable member controlled by the movable group unit control means to the initial position. Let
Even while the movable member is returned to the initial position, the signal level control means different from the signal level control means connected to the movable group unit control means transmits the light emission control data to the group unit control means. 4. The gaming machine according to claim 3, wherein transmission is continued.

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