JP2015106654A - Joining method, method for manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce connection failures by suppressing warpage of substrates in joining the substrates to each other with a connection terminal.SOLUTION: A metal layer for joining is formed on one of a first conductor on a first substrate and a second conductor on a second substrate; metal particles having a sintering temperature lower than a melting point of the metal layer is disposed between the first conductor and the second conductor, and the first conductor is laid over the second conductor; the metal particles are heated at a first temperature lower than a melting point of the metal layer to be sintered and thereby the first conductor and the second conductor are fixed temporarily; and, after having been fixed temporarily, the first conductor and the second conductor are heated at a second temperature equal to or higher than a melting point of the metal layer to be joined.

Description

  The present invention relates to a bonding method, a semiconductor device manufacturing method, and a semiconductor device.

  Electronic devices are required to be small in size and low in power consumption, but are also required to have high speed and large capacity. In order to improve the calculation processing speed and reduce the power consumption, a many-core processor configuration that increases the number of cores to be processed in parallel rather than increasing the clock speed is effective. With a connection structure on a two-dimensional plane (including 2.5-dimensional mounting), increasing the number of cores in one chip increases the chip size and lengthens the wiring length in the chip, making it difficult to achieve both improved characteristics . Therefore, three-dimensional mounting (3D-LSI) has been developed in which LSI (Large Scale Integrated circuit) chips that have been conventionally connected in a plane are connected by through silicon vias (TSV: Through Si Via) and stacked vertically with the substrate. Has been.

  LSI chips that are three-dimensionally stacked are connected by through electrodes called TSV as described above, and a diameter of 10 μm or less has been studied as the size of the through electrodes. In order to form such a small-diameter TSV, the aspect ratio is limited, and the chip tends to be thinner. On the other hand, the size of LSI chips used in HPC (High Performance Computer) such as servers and supercomputers tends to increase year by year.

  As shown in FIG. 1A, when mounting the semiconductor chip 120 on the substrate 110, generally, a flux (not shown) is applied to the electrode 112 on the substrate 110, and the semiconductor chip 120 is temporarily mounted by a flip chip bonder. Then, it connects by heating in a reflow furnace. The semiconductor chip 120 has a connection terminal 126 in which solder 125 is formed at the tip of a copper (Cu) pillar 122, and the solder 125 is melted and solidified to connect the connection terminal 126 to the electrode 112 on the substrate 110. In the case of continuing the stacking, flux is applied to the electrode (not shown) on the back surface of the mounted semiconductor chip 120, and the semiconductor chips are sequentially mounted.

  When flip chip connection is performed using the connection terminal 126 having the solder 125 formed at the tip, the warp generated when the semiconductor chip 120 is heated is absorbed by the molten solder 125 and connected. In other words, the solder 125 becomes a margin for absorbing the warp of the semiconductor chip 120. Increasing the amount of solder 125 increases the margin of chip warpage, but short-circuiting between adjacent terminals due to molten solder 125 becomes a problem, and the amount of solder 125 formed on connection terminal 126 is limited. Further, since the solder 125 to be formed is also miniaturized by miniaturization of the joint portion, the thickness of the solder 125 that can be formed on the connection terminal 126 tends to decrease.

  With the miniaturization of the connection terminal 126, the allowable amount of warpage decreases, and there is a concern that poor connection frequently occurs between the connection terminal 126 of the semiconductor chip 120 and the electrode 112 of the substrate 110 as shown in FIG. There is. This problem is considered to become more apparent as the chip size increases.

  Recently, metal nanoparticles and metal nano pastes have been developed for bonding electronic components. After forming a low melting point metal layer on the surface of the circuit board electrode and the surface of the chip electrode, a metal powder is placed on the low melting point metal layer, and heated and pressed at a temperature at which the low melting point metal layer melts to form a low melting point metal. There has been proposed a method in which a layer is solid-liquid diffused and bonded to a chip electrode, a circuit board electrode, and a metal powder (see, for example, Patent Document 1).

JP 2007-19360 A

  Provided are a bonding method capable of suppressing warpage of a substrate and reducing connection failure when bonding the substrates to each other with a connection terminal, and manufacturing a semiconductor device using the bonding method.

In one aspect, a joining method is provided. In this joining method,
Forming a bonding metal layer on one of the first conductor on the first substrate and the second conductor on the second substrate;
Disposing metal particles having a sintering temperature lower than the melting point of the metal layer between the first conductor and the second conductor, and superimposing the first conductor and the second conductor,
Heating at a first temperature lower than the melting point of the metal layer to sinter the metal particles to temporarily fix the first conductor and the second conductor;
After the temporary fixing, the first conductor and the second conductor are joined by heating at a second temperature equal to or higher than the melting point of the metal layer.

  When the substrates are joined to each other with the connection terminals, the warpage of the substrates can be suppressed and connection defects can be reduced. As a result, the connection reliability of the product is improved.

It is a figure which shows the problem which arises in the conventional chip mounting. It is a figure which shows the joining method of embodiment. It is a manufacturing process figure of the semiconductor device of an embodiment. It is a figure which shows the structure of the junction part of the semiconductor device produced by the method of embodiment. It is a figure which shows the effect of embodiment. It is a figure which shows the structural example of the semiconductor device mounted three-dimensionally.

  FIG. 2 is a diagram illustrating the bonding method according to the embodiment. In the example of FIG. 2, the conductor 62 formed on the substrate 60 and the conductor 72 formed on the substrate 70 are bonded using the bonding metal layer 25 and the metal particles 30.

  As shown in FIG. 2A, for example, the metal layer 25 is formed on one side of the conductor 62 and the conductor 72, the metal particle 30 is disposed on the other side, and the conductor 62 and the conductor 72 are aligned. To do. The metal layer 25 is, for example, a solder bump for bonding, and includes Sn—Cu, Sn—Ag, Sn—Ag—Cu, Sn—Cu—Co, Sn—Cu—Ni—Ge, Sn—Ag—Cu—Ni—. It contains a binary alloy, ternary alloy, quaternary alloy, or higher elements such as Ge as a main component. The metal layer 25 is formed of any material capable of forming an alloy with the metal particles 30.

  The metal particles 30 may be powder particles or may be a paste in which metal particles are dispersed in a solvent. When the diameter of the metal particle 30 is less than 1 μm, it is called “metal nanoparticle”. In the embodiment, the size of the metal particles 30 is not limited as long as the condition that the sintering temperature of the metal particles 30 is lower than the melting point of the metal layer 25 is satisfied.

  As the metal particles 30, silver (Ag), gold (Au), copper (Cu), nickel (Ni) alone, or a mixture containing one or more of these can be used. When the size of the metal particle 30 becomes nano-order, the metal particle 30 can be sintered at a temperature lower than the original melting point of the metal. Therefore, it may be desirable to use nanoparticles having a diameter of less than 1 μm in relation to the material of the metal layer 25 for bonding.

  As an example, a tin-silver (Sn—Ag) alloy 25 is used for the metal layer 25, and silver (Ag) nanoparticles 30 or silver (Ag) nanopaste 30 is used as the metal particles 30.

  Next, as shown in FIG. 2B, heating is performed at a first temperature lower than the melting point of the metal layer 25 to form a sintered body 31 of the metal particles 30, and the conductor 72 and the conductor 62 are temporarily fixed. To do. Sintering is a phenomenon in which the metal particles 30 adhere to each other on the surface by heating at a temperature lower than the melting point of the metal particles 30 themselves, and shrink as a whole and the gaps between the particles become smaller and become denser. is there. In the case of using nanoparticles as the metal particles 30, it is known that the melting point is lower than that of the bulk material and can be sintered at a relatively low temperature. This is explained by the fact that the total surface area per unit weight increases as the particle size decreases, the contribution of surface energy increases, and the thermal energy required for dissolution decreases. The sintering temperature is considered to correlate with the particle size of the metal nanoparticles, and metal nanoparticles having an appropriate size can be used according to the melting point of the metal layer 25 for bonding.

  When the bonding metal layer 25 is formed of Sn-3.5Ag or Sn-3.0Ag, the melting point at the solidus is 221 ° C. In this case, the Ag nanoparticles (or Ag nanopaste) 30 can be sintered at 120 ° C. to 200 ° C. depending on the size. When Ag nanopaste is used, the solvent volatilizes during the sintering process, the protective agent (dispersant) covering the surface of the Ag particles is decomposed, and surface bonding of the particles proceeds.

  The temperature is lowered after sintering to stabilize the sintered body 31. At this stage, the joining metal layer 25 is not melted, and the conductor 72 and the metal layer 25 are temporarily fixed on the conductor 62 via the sintered body 31.

  Next, as shown in FIG. 2C, reflow heating is performed at a second temperature equal to or higher than the melting point of the metal layer 25 to finally join the conductor 72 to the conductor 62. By the reflow heating, the metal layer 25 is melted to form an alloy with the sintered body 31, and the strong bonding is realized by the cooling after the reflow. In addition, the molten metal layer 25 enters the gap between the sintered bodies 31 and forms an alloy with the conductor 62. In this way, the joined portion 33 including the sintered body 31 and the alloy layer 27 is formed between the conductor 72 and the conductor 62 after joining.

  In the heating process at the reflow temperature, a warp has conventionally occurred due to a difference in thermal expansion coefficient between the substrate 60 and the substrate 70. When the pattern of the conductor 72 was fine, the warp of the substrate 70 could not be absorbed even by reflow of the metal layer 25. On the other hand, according to the method of FIG. 2, since the conductor 72 and the conductor 62 are temporarily fixed by the sintered body 31, warping of the substrate 70 can be suppressed during reflow. This is because temporary fixing by firing does not have final bonding strength, but has a fixing force that can suppress warping due to stress. This improves connection reliability.

  FIG. 3 is a manufacturing process diagram of a semiconductor device using the bonding method of FIG. In FIG. 3A, the connection terminal 26 of the semiconductor chip 20 is aligned with the electrode 12 on the circuit board 10. The semiconductor chip 20 has connection terminals 26 having copper (Cu) pillars 22 on the main surface of a silicon (Si) wafer having a 13 mm square and a thickness of 50 μm, for example. The Cu pillar 22 is formed on a predetermined electrode (not shown) of the semiconductor chip 20 by, for example, photolithography and electrolytic plating. The size of the Cu pillar 22 is, for example, a diameter of 30 μm, a pitch of 50 μm, and a height of 15 μm. A metal layer 25 having a thickness of 10 μm is formed of Sn—3.5Ag solder material at the tip of the Cu pillar 22. Thereby, the connection terminal 26 of the semiconductor chip 20 is formed.

  The circuit board 10 is a 20 mm square chip, for example, and may be another LSI chip 10. A copper (Cu) electrode 12 is formed on the circuit board 10 at a position facing the connection terminal 26 of the semiconductor chip 20. The diameter of the Cu electrode 12 is 30 μm, and the height from the substrate surface is 5 μm. After the Ag nano paste 30 is supplied onto the Cu electrode 12, the upper semiconductor chip 20 is aligned with the circuit board 10 by a flip chip bonder and temporarily mounted. The Ag nano paste 30 contains Ag nanoparticles having a particle diameter of several nm to several hundreds of nm as a main component, and can be applied by, for example, an inkjet method or screen printing.

  Next, in FIG. 3B, first heating is performed at 150 ° C. for 60 minutes to sinter the Ag nanopaste 30 and perform temporary fixing. When the semiconductor chip 20 is temporarily mounted on the circuit board 10 by the flip chip bonder, the semiconductor chip 20 may be mounted while heating at a heating temperature lower than the melting point of the metal layer (solder) 25. In this case, positioning, temporary mounting, and temporary fixing can be performed integrally. In the stage of FIG. 3B, the Ag nano paste 30 is sintered to form the sintered body 31, but the metal layer 25 of the connection terminal 26 of the semiconductor chip 20 is not changed, and the connection terminal 26 is the sintered body. It is temporarily fixed to the electrode 12 via 31.

  Next, in FIG. 3C, second heating is performed in a conveyor type nitrogen reflow furnace to perform a reflow process. When the Sn-3.5Ag solder 25 is used for the metal layer 25, heating is performed at a temperature of 221 ° C. or higher and a peak temperature of 250 ° C. for 60 seconds. Due to the second heating profile, the metal layer 25 is melted and solidified, and a joint 33 is formed between the Cu pillar 22 of the semiconductor chip 20 and the electrode 12 of the circuit board 10. The joint portion 33 includes the solder layer 27 and the sintered body 31 after reflow. As a result, the semiconductor chip 20 is firmly bonded to the circuit board 10 to complete the semiconductor device 1A.

  FIG. 4 is a diagram illustrating the configuration of the joint portion 33 in the case where reflow joining is performed after temporary fixing in comparison with the case where the joint portion is formed by a single heat treatment.

  4A, an Ag nano paste is disposed on the electrode 12 of the circuit board 10, and the metal layer (solder) 25 at the tip of the Cu pillar 22 and the Ag nano paste are melted and bonded by one reflow heating. As shown in the enlarged view of the interface region A between the joint 133 and the Cu electrode 12, the Ag particles 28 are uniformly dispersed in the reflowed solder (Sn-3.5Ag) to form an Ag3Sn alloy layer 29. A Cu—Sn alloy layer 21 is formed at the interface between the Cu electrode 12 and the alloy layer 29.

  On the other hand, in FIG. 4B, in accordance with the method of the embodiment, the heating at the first temperature and the reflow at the second temperature are performed twice. As shown in the enlarged view of the interface region B, an intermediate layer 35 including a sintered body 31 of Ag nanoparticles and an Ag-rich alloy layer 32 exists at the interface between the solder layer 27 and the Cu electrode 12 after reflow. The sintered body 31 of Ag nanoparticles maintains the sintered shape even after the reflow process and is welded to the interface with the Cu electrode 12. The diffusion of the Ag particles 28 into the solder layer 27 after reflow is very small, and the SnAg alloy layer 32 having a high Ag concentration is formed in the vicinity of the sintered body 31. The sintered body 31 has a high density due to adhesion between particles, but there are gaps (voids) inside. Sn that has passed through the gaps between the sintered bodies 31 reacts with the copper of the Cu electrode 12 to form the Cu—Sn alloy layer 21.

  As described above, the bonding portion 33 of the semiconductor device 1A manufactured by the method of the embodiment includes the metal particle sintered body 31 and the Ag rich between the Cu electrode 12 on the circuit board 10 and the solder layer 27 after reflow. The semiconductor device has a configuration different from that of the junction portion 133 of the semiconductor device manufactured by one reflow in that the intermediate layer 35 including the alloy layer 32 is included.

  When the reflow-melted metal layer (solder) 25 and the sintered body 31 of the metal particles 30 are alloyed, the joint portion 33 becomes strong and has resistance to breakage due to stress.

  FIG. 5 is a diagram illustrating the effects of the method and configuration of the embodiment. When the solder material for forming the metal layer 25 at the tip of the connection terminal 26 of the semiconductor chip 20 and the material of the metal particles 30 are changed and reflowing is performed after temporary fixing by sintering, 1 is performed without performing temporary fixing. Compare the results of the continuity test when reflow heating is performed.

  In the continuity test, ten different samples 1 to 6 were produced, and the ratio of the samples that could not obtain continuity was shown as a continuity check result. All the sample dimensions are the same as the size of the semiconductor chip 20, the size and pitch of the Cu pillar 22, the size of the circuit board 10, and the size of the Cu electrode 12 described in connection with FIG. 3.

  In Sample 1, a metal layer 25 is formed of Sn-3.5Ag at the tip of the Cu pillar 22, and an Ag paste is used as a temporary fixing metal paste. The first heating was performed at 150 ° C. to sinter the Ag paste, and then the second heating (reflow heating) was performed at the peak temperature of 260 ° C. to join. As for the continuity check result of sample 1, continuity can be obtained in all of the ten samples, and the occurrence of defects is zero.

  In the sample 2, the solder material of the metal layer 25 is the same as that in the sample 1, but the metal paste for temporary fixing is not applied and only reflow heating is performed without temporary fixing. In the continuity check result of sample 2, 6 out of 10 defects have occurred. This is presumably because the warpage of the chip 10 cannot be absorbed only by reflow of the solder material, and contact failure occurred.

  In Sample 3, a metal layer 25 is formed of Sn-3Ag-0.5Cu at the tip of the Cu pillar 22, and Au paste is used as a temporary fixing metal paste. The first heating was performed at 200 ° C. to sinter the Au paste, and then the second heating (reflow heating) was performed at the peak temperature of 260 ° C. to join. The continuity check result of sample 3 can be continuity in all ten samples, and the occurrence of defects is zero.

  In the sample 4, the solder material of the metal layer 25 is the same as that in the sample 3, but only the reflow heating is performed without applying the temporary fixing metal paste and without sintering for the temporary fixing. As for the continuity check result of sample 4, 5 out of 10 defects have occurred.

  In Sample 5, a metal layer 25 is formed of Sn-0.75Cu at the tip of the Cu pillar 22, and Cu paste is used as a temporary fixing metal paste. The first heating was performed at 200 ° C. to sinter the Cu paste, and then the second heating (reflow heating) was performed at the peak temperature of 265 ° C. for bonding. As for the continuity check result of sample 5, continuity can be obtained in all 10 samples, and the occurrence of defects is zero.

  In the sample 6, the solder material of the metal layer 25 is the same as that of the sample 5, but only the reflow heating is performed without applying the temporary fixing metal paste and without sintering for temporary fixing. In the continuity check result of sample 6, 6 out of 10 defects have occurred.

  As can be seen from the test results, when the substrates are joined with the conductors formed on the surfaces, the metal particles are sintered and the substrates are temporarily fixed, and then reflow heating is performed to suppress the warpage of the substrates. Thus, the bonding between the conductors can be ensured.

  FIG. 5 shows the test results of a specific solder material and metal paste, but even when a ternary alloy, a quaternary alloy, or an alloy mainly composed of more elements is used for the metal layer 25, the metal layer 25 The same effect can be obtained by reflowing after temporarily fixing using metal particles or metal paste sintered at a temperature lower than the melting point of the layer 25.

  FIG. 6 is a diagram in which the method shown in FIGS. 2 and 3 is applied to a three-dimensionally mounted semiconductor device 1B. In the semiconductor device 1 </ b> B, a plurality of chips 60 and 40 a to 40 d are stacked on the circuit board 51. In this example, the logic chip 60 is disposed on the circuit board 51, and the memory chips 40 a to 40 d are stacked on the logic chip 60. The logic chip 60 and the memory chips 40 a to 40 b are connected to each other by a vertical wiring by a through silicon via (TSV) 47. The logic chip 60 and the memory chips 40a to 40d are collectively referred to as “chip 40”.

  Three-dimensional mounting enables parallel processing without changing the functions of individual semiconductor chips, and can increase the processing speed. In addition, since the wiring distance between chips can be shortened, power consumption can be reduced. By stacking without increasing the chip occupation area, the performance per mounting area can be improved.

  In order to perform three-dimensional mounting, an electrode 41 connected to the TSV 47 is formed on the back surface (the upper surface in the stacking direction) of the chip 40i, and metal particles (or metal paste) 30 are disposed on the electrode 41. Connection terminals 46 are formed on the element surface (the lower surface in the stacking direction) of the chip 40i + 1 disposed on the chip 40i. The connection terminal 46 has a metal layer 45 for bonding at the tip of the pillar electrode 42. By sintering the metal particles 30 at a temperature lower than the melting point of the metal layer 45, the connection terminals 46 are temporarily fixed to the electrodes 41 of the lower chip 40i. In the case of continuing the lamination, the metal particles 30 are arranged on the electrode (not shown) on the back surface of the upper chip 40i + 1 and temporarily fixed by the same method.

  After all the chips 40 to be stacked are temporarily fixed, they are joined by one reflow. When stacking chips with a flip chip bonder while heating to the sintering temperature, the upper chip 40i + 1 can be placed on the lower chip 40i and simultaneously fixed temporarily. This method is advantageous for three-dimensional mounting in which high alignment accuracy is required for the vertical wiring. In addition, since the reflow bonding can be performed in a lump in a state where the entire stack is temporarily fixed, the manufacturing process is not complicated.

  The method and configuration of the embodiment are not limited to three-dimensional mounting but can be applied to 2.5-dimensional mounting in which different types of chips mixedly mounted on a circuit board are connected by planar wiring. In the conventional bonding method, local warpage has occurred in each chip disposed on the circuit board. However, according to the method and configuration of the embodiment, the warpage of each chip is suppressed to ensure bonding. Can do. In this case as well, each chip 40i is arranged at a predetermined position on the circuit board, temporarily fixed by sintering, and then reflowed in a lump to realize the simplicity of the process and the certainty of joining. Can do. Prior to the reflow, the metal particles or the metal paste are sintered and temporarily fixed, whereby the warpage of the chip that occurs until the solder is melted in the reflow process is suppressed, and the connection failure is reduced. In particular, when a thin laminated chip or a large-area chip whose terminals are miniaturized is mounted, warping during reflow heating can be suppressed and connection failures can be reduced.

The following notes are presented for the above explanation.
(Appendix 1)
Forming a bonding metal layer on one of the first conductor on the first substrate and the second conductor on the second substrate;
Disposing metal particles having a sintering temperature lower than the melting point of the metal layer between the first conductor and the second conductor, and superimposing the first conductor and the second conductor,
Heating at a first temperature lower than the melting point of the metal layer to sinter the metal particles to temporarily fix the first conductor and the second conductor;
After the temporary fixing, the first conductor and the second conductor are joined by heating at a second temperature equal to or higher than the melting point of the metal layer.
The joining method characterized by the above-mentioned.
(Appendix 2)
The joining method according to appendix 1, wherein the temporary fixing is performed after the heating at the first temperature.
(Appendix 3)
The joining method according to appendix 1, wherein the particle size of the metal particles is less than 1 μm.
(Appendix 4)
The joining method according to appendix 1, wherein the metal particles are a simple substance of Cu, Ni, Ag, or Au, or a combination of two or more thereof.
(Appendix 5)
Form a metal layer for bonding at the tip of the connection terminal of the semiconductor element,
Between the connection terminal and the electrode on the circuit board, metal particles having a sintering temperature lower than the melting point of the metal layer are arranged, and the semiconductor element and the circuit board are overlapped,
Heating at a first temperature lower than the melting point of the metal layer to sinter the metal particles and temporarily fixing the connection terminal to the electrode;
After the temporary fixing, the connection terminal and the electrode are joined by heating at a second temperature equal to or higher than the melting point of the metal layer.
(Appendix 6)
6. The method of manufacturing a semiconductor device according to appendix 5, wherein the temporary fixing is performed after the heating at the first temperature.
(Appendix 7)
6. The manufacturing of a semiconductor device according to appendix 5, wherein the superposition and the temporary fixing are performed simultaneously by placing the semiconductor element on the circuit board while heating the circuit board at the first temperature. Method.
(Appendix 8)
Laminating a plurality of the semiconductor elements on the circuit board with the metal particles interposed therebetween,
Sintering the metal particles at the first temperature, temporarily fixing the plurality of semiconductor elements in a stacked state,
6. The method of manufacturing a semiconductor device according to appendix 5, wherein the semiconductor device is bonded by performing heating at the second temperature after being temporarily fixed in the stacked state.
(Appendix 9)
9. The method of manufacturing a semiconductor device according to appendix 8, wherein the temporary fixing in the stacked state temporarily fixes an upper semiconductor element to a lower semiconductor element every time one layer is stacked.
(Appendix 10)
A substrate having a first electrode;
A semiconductor element having a second electrode and mounted on the substrate;
A joint located between the first electrode and the second electrode;
Have
The junction unit includes an intermediate layer including a sintered body of metal particles in an interface region with the first electrode.
(Appendix 11)
11. The semiconductor device according to appendix 10, wherein the intermediate layer has an alloy layer in the vicinity of the sintered body that has a higher concentration of elements constituting the metal particles than other regions of the joint.
(Appendix 12)
The semiconductor device according to appendix 11, wherein the substrate is another semiconductor element disposed below the semiconductor element.
(Appendix 13)
The semiconductor device according to appendix 11, wherein the substrate is an insulating circuit substrate.

1A, 1B Semiconductor devices 10, 51 Circuit board 12 Substrate side electrode (Cu electrode)
20, 40 Semiconductor chip (semiconductor element)
22 Element side electrode (Cu pillar)
25 Joining metal layer 26 Connection terminal 30 Metal particle 31 Sintered metal particle 32 Alloy layer 33

Claims (7)

Forming a bonding metal layer on one of the first conductor on the first substrate and the second conductor on the second substrate;
Disposing metal particles having a sintering temperature lower than the melting point of the metal layer between the first conductor and the second conductor, and superimposing the first conductor and the second conductor,
Heating at a first temperature lower than the melting point of the metal layer to sinter the metal particles to temporarily fix the first conductor and the second conductor;
After the temporary fixing, the first conductor and the second conductor are joined by heating at a second temperature equal to or higher than the melting point of the metal layer.
The joining method characterized by the above-mentioned.   The joining method according to claim 1, wherein the temporary fixing is performed after the heating at the first temperature. Form a metal layer for bonding at the tip of the connection terminal of the semiconductor element,
Between the connection terminal and the electrode on the circuit board, metal particles having a sintering temperature lower than the melting point of the metal layer are arranged, and the semiconductor element and the circuit board are overlapped,
Heating at a first temperature lower than the melting point of the metal layer to sinter the metal particles and temporarily fixing the connection terminal to the electrode;
After the temporary fixing, the connection terminal and the electrode are joined by heating at a second temperature equal to or higher than the melting point of the metal layer.   The method of manufacturing a semiconductor device according to claim 3, wherein the temporary fixing is performed after the heating at the first temperature.   4. The semiconductor device according to claim 3, wherein the superposition and the temporary fixing are simultaneously performed by arranging the semiconductor element on the circuit board while heating the circuit board at the first temperature. Production method. Laminating a plurality of the semiconductor elements on the circuit board with the metal particles interposed therebetween,
Sintering the metal particles at the first temperature, temporarily fixing the plurality of semiconductor elements in a stacked state,
The method for manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is bonded by performing heating at the second temperature after being temporarily fixed in the stacked state. A substrate having a first electrode;
A semiconductor element having a second electrode and mounted on the substrate;
A joint located between the first electrode and the second electrode;
Have
The junction unit includes an intermediate layer including a sintered body of metal particles in an interface region with the first electrode.

Images