JP2006202944A - Joining method and joining structure - Google Patents

Joining method and joining structure Download PDF

Info

Publication number
JP2006202944A
JP2006202944A JP2005012397A JP2005012397A JP2006202944A JP 2006202944 A JP2006202944 A JP 2006202944A JP 2005012397 A JP2005012397 A JP 2005012397A JP 2005012397 A JP2005012397 A JP 2005012397A JP 2006202944 A JP2006202944 A JP 2006202944A
Authority
JP
Japan
Prior art keywords
metal
metal layer
joining
porous
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005012397A
Other languages
Japanese (ja)
Other versions
JP4635230B2 (en
Inventor
Masanori Yamagiwa
正憲 山際
Yoshinori Murakami
善則 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP2005012397A priority Critical patent/JP4635230B2/en
Publication of JP2006202944A publication Critical patent/JP2006202944A/en
Application granted granted Critical
Publication of JP4635230B2 publication Critical patent/JP4635230B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Abstract

<P>PROBLEM TO BE SOLVED: To provide a joining method and a joining structure advantageous for joining of large areas. <P>SOLUTION: A Cu porous plate 3 that has a vacancy therein and that is a porous metal layer comprising a third metal is interposed between a first metal layer 11 comprising a first substance first metal and a Cu substrate 21a that is a second metal layer comprising a second substance second metal. Further, Ag nanopaste 4 is disposed between the first metal layer 11 and the Cu porous plate 3, and between the Cu substrate 21a and the Cu porous plate 3, for joining thereof by heating. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、第一の物体と第二の物体とを接合する接合方法及び接合構造に関する。   The present invention relates to a joining method and a joining structure for joining a first object and a second object.

従来のはんだに代えて、金属ナノ粒子を用いて2つの部材を接合する電極配設基体とその接合方法に関する技術が下記特許文献1に記載されている。この技術では、平均直径100nm以下の金属超微粒子の周囲を有機化合物で被覆することによって生成された金属ナノ粒子を、2つの部材の接合部に介在させ、加熱・焼成して接合させる。
また、下記非特許文献1においては、有機溶媒でコーティングしたAgナノ粒子からなるAgナノペーストを用いてCuの試験片どうしを面で接合し、その接合強度の測定と接合部の断面組織の観察を行っている。接合条件である温度と時間と加圧力を変化させて、接合部の強度を検討している。
Japanese Patent Application Laid-Open Publication No. 2003-228667 describes a technique related to an electrode-arranged base for joining two members using metal nanoparticles instead of conventional solder and a joining method thereof. In this technique, metal nanoparticles generated by coating the periphery of metal ultrafine particles having an average diameter of 100 nm or less with an organic compound are interposed in a joint between two members, and heated and fired to bond them.
In Non-Patent Document 1 below, Cu test pieces are joined on the surface using Ag nano paste made of Ag nanoparticles coated with an organic solvent, and the joint strength is measured and the cross-sectional structure of the joint is observed. It is carried out. The strength of the joint is examined by changing the joining conditions of temperature, time and applied pressure.

特開2004−128357号公報JP 2004-128357 A Mate 2004にて発表された論文集P.213「銀ナノ粒子を用いた接合プロセス」大阪大学大学院工学研究科Proceedings of Mate 2004, P.213 “Joint process using silver nanoparticles”, Graduate School of Engineering, Osaka University

しかしながら、上記の方法を用いて2つの部材を大面積で接合する場合、金属ナノ粒子を被覆する有機保護膜やペースト化するための有機溶媒を揮発させることが接合面の中央付近では難しく、その結果、炭化物が接合層に残存し、接合部の強度劣化や電気的熱的特性の劣化を招いていた。すなわち、上記の方法は、従来のはんだやろう付けに比べ、大面積の接合には不向きであった。
本発明の目的は、大面積の接合に有利な接合方法及び接合構造を提供することにある。
However, when joining two members in a large area using the above method, it is difficult to volatilize the organic protective film covering the metal nanoparticles and the organic solvent for pasting in the vicinity of the center of the joint surface, As a result, the carbide remained in the bonding layer, resulting in deterioration of the strength of the bonded portion and deterioration of the electrothermal characteristics. That is, the above method is not suitable for joining large areas as compared with conventional soldering and brazing.
An object of the present invention is to provide a bonding method and a bonding structure that are advantageous for large-area bonding.

上記課題を解決するために、本発明は、第一の物体に設けられた第一の金属層と、第二の物体に設けられた第二の金属層との間に、多孔質金属層を介在させ、金属を含む有機系接合材を、前記第一の金属層及び第二の金属層と前記多孔質金属層との間に設置し、加熱して接合するという構成になっている。   In order to solve the above problems, the present invention provides a porous metal layer between a first metal layer provided on a first object and a second metal layer provided on a second object. An organic bonding material containing a metal is interposed between the first metal layer and the second metal layer and the porous metal layer, and is heated and bonded.

本発明によれば、大面積の接合に有利な接合方法及び接合構造を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the joining method and joining structure advantageous to joining of a large area can be provided.

以下、図面を用いて本発明の実施の形態について詳細に説明する。なお、以下で説明する図面で、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
《第一の実施の形態》
図1(a)〜(d)は、本発明の接合方法及び接合構造の第一の実施の形態を示す図であり、(a)は第一の物体と第二の物体とが接合された接合構造の全体断面図、(b)は(a)の接合部(A部)の拡大断面図、(c)は多孔質金属層の内部の形状を示す平面図、(d)は別の多孔質金属層の内部の形状を示す平面図である。
図1(a)、(b)において、1は第一の物体である例えば半導体素子、11は第一の金属(ここではAg:銀)からなる第一の金属層、21aは第二の金属(ここではCu:銅)からなる第二の物体である金属基板であるCu基板、3は第三の金属(ここではCu)からなる多孔質金属層であるCuポーラス板、4は平均直径が100nm以下の第四の金属(ここではAg)からなる超微粒子を有機系の溶媒中に分散させてなる金属ナノペーストであるAgナノペースト、(c)、(d)において、31a、31bはそれぞれCuポーラス板3の空孔である。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
First embodiment
FIGS. 1A to 1D are diagrams showing a first embodiment of a joining method and a joining structure according to the present invention. FIG. 1A shows a first object and a second object joined together. (B) is an enlarged cross-sectional view of the joint portion (A) of (a), (c) is a plan view showing the internal shape of the porous metal layer, and (d) is another porous view. It is a top view which shows the shape inside a porous metal layer.
1A and 1B, 1 is a first object, for example, a semiconductor element, 11 is a first metal layer made of a first metal (here, Ag: silver), and 21a is a second metal. A Cu substrate which is a metal substrate which is a second object made of (here Cu: copper), 3 is a Cu porous plate which is a porous metal layer made of a third metal (here Cu), 4 is an average diameter In Ag nanopaste, which is a metal nanopaste in which ultrafine particles made of a fourth metal (here Ag) of 100 nm or less are dispersed in an organic solvent, (c) and (d), 31a and 31b are respectively This is a hole in the Cu porous plate 3.

〈部材の準備〉
まず、半導体素子1、Cu基板21a、Cuポーラス板3、Agナノペースト4、を準備する。
〈半導体素子〉
半導体素子1はシリコン(Si)からなり、該半導体素子1の裏面には、オーミック接続を取るためのチタン(Ti)層(図示省略)が形成され、その上に異種金属の拡散を防止するためのニッケル(Ni)層(図示省略)が形成され、最後に、第一の金属層11であるAg層が形成されている。
〈Agナノペースト〉
Agナノペーストとは、粒径が例えば約10nm前後の銀からなるAgナノ粒子(第三の金属からなる超微粒子)からなり、その粒子の周囲を、有機保護膜によってコーティングした状態で溶媒に分散されたペースト状のものである。これに熱を加えて、ある温度になると溶媒や有機保護膜が分解され、揮発し、超微粒子である銀の表面が現れ、互いに焼結する原理を利用して接合材として機能させるものである。
〈金属ナノ粒子の接合原理〉
その基本的な原理は、材料によって違いはあるが、ナノレベルの粒子になるとその表面のエネルギーによってバルクの融点より低温で凝集し、焼結することが一般的に知られており、関連の文献に詳細が記載されている。従って、Agナノペーストは、通常、銀の超微粒子が互いに結合することはなく、溶媒中で安定であり、熱処理によって有機物が揮発することによって銀が焼結することを利用した接着剤である。
〈多孔質金属層〉
多孔質金属層(多孔質金属板)として、例えば銅などの金属からなるCuポーラス板3を用いる。内部の形状は図1(c)、(d)に例示するような例えば角型、丸型、棒状などの空孔31a、31bが部分的に繋がった形状や、繊維状の金属が部分的につながった形状であっても構わない。また、空孔率も数%程度から数十%まで等いずれであっても構わない。ただし、Agナノペースト4の有機物が接合面の外部へ揮発すべく面に平行な方向に空孔が繋がっている形状である必要がある。
〈金属基板〉
金属基板はCuからなるCu基板21aを用いる。
<Preparation of parts>
First, the semiconductor element 1, Cu substrate 21a, Cu porous plate 3, and Ag nano paste 4 are prepared.
<Semiconductor element>
The semiconductor element 1 is made of silicon (Si), and a titanium (Ti) layer (not shown) for establishing ohmic connection is formed on the back surface of the semiconductor element 1 to prevent diffusion of dissimilar metals thereon. A nickel (Ni) layer (not shown) is formed, and finally, an Ag layer which is the first metal layer 11 is formed.
<Ag nano paste>
Ag nanopaste consists of Ag nanoparticles (ultrafine particles made of a third metal) made of silver having a particle size of about 10 nm, for example, and the periphery of the particles is dispersed in a solvent while being coated with an organic protective film. Pasted. When heat is applied to this, the solvent and the organic protective film are decomposed and volatilized at a certain temperature, and the surface of silver, which is an ultrafine particle, appears and functions as a bonding material by utilizing the principle of sintering each other. .
<Principle of joining metal nanoparticles>
Although its basic principle varies depending on the material, it is generally known that when it becomes nano-level particles, it aggregates and sinters at a temperature lower than the melting point of the bulk due to the energy of its surface. Details. Therefore, the Ag nanopaste is an adhesive utilizing the fact that silver ultrafine particles are not usually bonded to each other, are stable in a solvent, and silver is sintered by volatilization of organic substances by heat treatment.
<Porous metal layer>
As the porous metal layer (porous metal plate), for example, a Cu porous plate 3 made of a metal such as copper is used. The internal shape is, for example, a shape in which holes 31a and 31b such as square, round, and rod are partially connected as illustrated in FIGS. 1C and 1D, and a fibrous metal is partially It may be a connected shape. Also, the porosity may be anywhere from about several percent to several tens percent. However, it is necessary that the organic substance of the Ag nanopaste 4 has a shape in which pores are connected in a direction parallel to the surface so that the organic substance can volatilize outside the bonding surface.
<Metal substrate>
As the metal substrate, a Cu substrate 21a made of Cu is used.

〈接合方法〉
次に、それぞれの部材を用いて接合を行う。
まず、Cu基板21a上の半導体素子1が実装される側の所定の面上にAgナノペースト4を、スクリーン印刷法を用いて厚みを一定にして塗布する。
次に、そのAgナノペースト4を塗布した面上に、Cuポーラス板3の一方の面を設置する。
その後、Cuポーラス板3の他方の面上に、再度、Agナノペースト4を、スクリーン印刷法を用いて厚みを一定にして塗布する。
その後、裏面にAg層(第一の金属層11)を形成した半導体素子1を、裏面がAgナノペースト4と接着するように設置し、加熱する。例えば300℃程度の加熱が適当である。こうすることで、Agナノペースト4を構成する有機物に含まれる炭素によって、半導体素子1の裏面の第一の金属層11であるAg層の最表面、第四の金属であるAgナノペースト4のAgナノ粒子の最表面及び第三の金属からなるCuポーラス板3の最表面、並びに第二の金属からなるCu基板21aの最表面は、酸化還元され、有機物の揮発によってAgナノ粒子が凝集し、互いに結合が始まる。また、有機物は、Cuポーラス板3の内部を経由して接合面に平行な方向に接合面の外側へ揮発され易いため、加圧することなく確実なAgナノ粒子の凝集、焼結が可能となる。その結果、第一の物体である半導体素子1と、第二の物体であるCu基板21aとが、Cuポーラス板3を挟んで、Agの接合層によって接合された構造が完成する。
<Join method>
Next, it joins using each member.
First, Ag nano paste 4 is applied to a predetermined surface on the Cu substrate 21a on the side where the semiconductor element 1 is mounted with a constant thickness using a screen printing method.
Next, one surface of the Cu porous plate 3 is placed on the surface to which the Ag nanopaste 4 is applied.
Thereafter, the Ag nano paste 4 is again applied on the other surface of the Cu porous plate 3 with a constant thickness using a screen printing method.
Thereafter, the semiconductor element 1 having the Ag layer (first metal layer 11) formed on the back surface is placed and heated so that the back surface adheres to the Ag nano paste 4. For example, heating at about 300 ° C. is appropriate. By doing so, the outermost surface of the Ag layer, which is the first metal layer 11 on the back surface of the semiconductor element 1, and the Ag nano paste 4, which is the fourth metal, are contained in the organic matter constituting the Ag nano paste 4. The outermost surface of the Ag nanoparticles, the outermost surface of the Cu porous plate 3 made of the third metal, and the outermost surface of the Cu substrate 21a made of the second metal are oxidized and reduced, and Ag nanoparticles are aggregated by the volatilization of organic substances. , The bond starts with each other. In addition, since the organic substance is easily volatilized to the outside of the joint surface in the direction parallel to the joint surface through the inside of the Cu porous plate 3, it is possible to reliably aggregate and sinter Ag nanoparticles without applying pressure. . As a result, a structure in which the semiconductor element 1 as the first object and the Cu substrate 21a as the second object are joined by the Ag joining layer with the Cu porous plate 3 interposed therebetween is completed.

以上説明したように本実施の形態の接合方法は、第一の物体の第一の金属からなる第一の金属層11と、第二の物体の第二の金属からなる第二の金属層である例えばCu基板21aとの間に、内部に空孔を有し、第三の金属からなる多孔質金属層である例えばCuポーラス板3を介在させ、金属を含む有機系接合材を、第一の金属層11とCuポーラス板3との間、及びCu基板21aとCuポーラス板3との間に設置し、加熱して接合するという構成になっている。
まず、金属ナノペーストを用いた場合の基本的な効果は、上記従来例でも記述のあるとおり、有機系の溶媒に分散させた金属ナノペーストは、有機系の溶媒や保護膜をある温度で揮発させると、第四の金属からなるナノ粒子を含むそれぞれの金属は互いに直接接触してナノ粒子特有の低温での焼結が開始される。これにより、超微粒子を構成する第四の金属からなる接合層を形成するとともに、半導体素子1の表面の第一の金属層11と第二の金属層からなるCu基板21aとを接合することができる。従って、比較的低温で接合できる上に、それ以上の温度、例えば超微粒子を構成する第四の金属のバルク状態での融点まで使用することができる。このことは、同一部品に対してこの接合材料は何度でも使用できることを意味しており、高温はんだと共晶はんだを2ステップで用いている従来の工程に対しても、同一の金属ナノペーストのみを使用することで代替可能である。
上記のように第一の物体と第二の物体との間に内部に空孔を有する多孔質金属層を介在させて、金属を含む有機系接合材を第一の物体と多孔質金属層との間及び第二の物体と多孔質金属層との間に設置し、これらを加熱して接合することにより、多孔質金属層内を有機物の揮発経路として用いることで接合面の中央付近でも十分に有機物の揮発が可能となり、接合時に加圧することなく、高強度でかつ電気的、熱的にも最も良好な接合を達成することができる。また、この構造により、第一の物体と第二の物体が熱膨張係数の異なる異種材料の場合、その接合部に発生する熱応力による接合部のクラックを多孔質金属層内で止めることができる。
As described above, the bonding method of the present embodiment includes the first metal layer 11 made of the first metal of the first object and the second metal layer made of the second metal of the second object. For example, a Cu porous plate 3, which is a porous metal layer made of a third metal, is interposed between the Cu substrate 21 a and an organic bonding material containing a metal, It installs between the metal layer 11 and the Cu porous plate 3, and between the Cu substrate 21a and the Cu porous plate 3, and is heated and joined.
First, the basic effect of using metal nanopaste is that, as described in the previous example, metal nanopaste dispersed in an organic solvent volatilizes an organic solvent or protective film at a certain temperature. Then, the respective metals including the nanoparticles made of the fourth metal come into direct contact with each other, and sintering at a low temperature peculiar to the nanoparticles is started. Thus, a bonding layer made of the fourth metal constituting the ultrafine particles can be formed, and the first metal layer 11 on the surface of the semiconductor element 1 and the Cu substrate 21a made of the second metal layer can be bonded. it can. Accordingly, the bonding can be performed at a relatively low temperature, and a temperature higher than that, for example, the melting point in the bulk state of the fourth metal constituting the ultrafine particles can be used. This means that this bonding material can be used any number of times for the same component, and the same metal nanopaste is used for the conventional process using high-temperature solder and eutectic solder in two steps. It is possible to substitute by using only.
As described above, the porous metal layer having pores is interposed between the first object and the second object, and the organic bonding material containing metal is formed between the first object and the porous metal layer. And between the second object and the porous metal layer, and by heating and bonding them, the inside of the porous metal layer can be used as a volatilization path for organic matter, even near the center of the joint surface In addition, the organic substance can be volatilized, and the best bonding can be achieved with high strength and electrical and thermal properties without applying pressure during bonding. Also, with this structure, when the first object and the second object are dissimilar materials having different thermal expansion coefficients, cracks in the joint due to thermal stress generated in the joint can be stopped in the porous metal layer. .

また、Cuポーラス板3は、接合面に平行な方向に空孔が繋がっている。このような構造により、上記有機物の揮発を接合面に平行な方向により一層確実に達成することができる。
また、前記有機系接合材は、平均直径が100nm以下の第四の金属からなる超微粒子を有機系溶媒中に分散させてなる金属ナノペースト、例えばAgナノペーストである。このような金属ナノペーストを用いて加熱接合する接合方法なので、より低温で接合することができ、その結果、接合時に生じる残留応力も緩和でき、信頼性の高い接合を達成できる。
また、第一の金属層11の表面に、前記有機系接合材を用いて、予めCuポーラス板3の第一の面を加熱接合し、その後、Cuポーラス板3の前記第一の面と対向する第二の面に、第二の金属層であるCu基板21aを前記有機系接合材を用いて加熱接合する方法を取ってもよい。金属ナノペーストは有機物を揮発させる温度で一度接合が完了すると、その後、同じ温度をかけても接合部が溶解しないので、この接合方法が可能となる。このような構成によりCuポーラス板3の両面を同時に接合する必要がなく、上記効果をより簡易的にかつより正確に達成できる。
The Cu porous plate 3 has pores connected in a direction parallel to the joint surface. With such a structure, the volatilization of the organic substance can be more reliably achieved in a direction parallel to the bonding surface.
The organic bonding material is a metal nanopaste, for example, an Ag nanopaste, in which ultrafine particles made of a fourth metal having an average diameter of 100 nm or less are dispersed in an organic solvent. Since it is a joining method in which such metal nanopaste is used for heat joining, joining can be performed at a lower temperature. As a result, residual stress generated during joining can be alleviated, and highly reliable joining can be achieved.
In addition, the first surface of the Cu porous plate 3 is preliminarily heated and bonded to the surface of the first metal layer 11 using the organic bonding material, and then opposed to the first surface of the Cu porous plate 3. Alternatively, the Cu substrate 21a, which is the second metal layer, may be heated and bonded to the second surface using the organic bonding material. Once the metal nanopaste has been bonded once at the temperature at which the organic substance is volatilized, the bonded portion does not dissolve even when the same temperature is applied thereafter, so this bonding method becomes possible. With such a configuration, it is not necessary to join both surfaces of the Cu porous plate 3 at the same time, and the above effect can be achieved more simply and more accurately.

また、前記接合後、第一の物体と第二の物体とを接合面に対して垂直な方向に加圧し、前記多孔質金属層を圧縮して空孔を無くすようにしてもよい。このようにCuポーラス板3を圧縮し、空孔を無くすことができ、上記効果に加え、より電気的、熱的に良好な接合が達成できる。
また、本実施の形態の接合構造は、前記第一の物体は、二つの主面のうちの少なくとも一方の主面に、前記第一の金属層を有する面接合タイプの半導体素子1であり、前記第二の物体は、前記第二の金属層からなる金属基板である。これにより半導体装置の製造構造として、上記効果が得られる。
さらに、前記第一の金属、前記第二の金属、前記第三の金属、前記第四の金属は、金、銀、白金、銅、ニッケル、クロム、鉄、鉛、コバルトのうちのいずれかの金属、またはこれらの金属のうちの少なくとも一種を含む合金、またはこれら金属もしくは合金の混合物からなる。これにより有機系接合材に含まれる有機物による金属の酸化還元が可能であり、より正確に上記効果が得られる。
Further, after the joining, the first object and the second object may be pressurized in a direction perpendicular to the joining surface, and the porous metal layer may be compressed to eliminate voids. In this way, the Cu porous plate 3 can be compressed and voids can be eliminated, and in addition to the above effects, more electrical and thermal bonding can be achieved.
In the bonding structure of the present embodiment, the first object is a surface bonding type semiconductor element 1 having the first metal layer on at least one main surface of two main surfaces. The second object is a metal substrate made of the second metal layer. As a result, the above-described effects can be obtained as a semiconductor device manufacturing structure.
Furthermore, said 1st metal, said 2nd metal, said 3rd metal, and said 4th metal are either gold | metal | money, silver, platinum, copper, nickel, chromium, iron, lead, cobalt It consists of a metal, an alloy containing at least one of these metals, or a mixture of these metals or alloys. As a result, the metal can be oxidized / reduced by the organic substance contained in the organic bonding material, and the above-described effect can be obtained more accurately.

《第二の実施の形態》
図2は、本発明の第二の実施の形態の接合構造の全体断面図である。
図1に示した第一の実施の形態との違いは、本実施の形態においては、金属基板が、第五の金属であるAl(アルミニウム)からなるAl基板22であり、その周囲にメッキや蒸着等を利用して第二の金属層としてAg層21bが形成されている点である。
すなわち、本実施の形態の接合構造は、前記第一の物体は、二つの主面のうちの少なくとも一方の主面に、前記第一の金属層を有する面接合タイプの半導体素子1であり、前記第二の物体は、第二の金属層であるAg層21bを少なくとも前記接合する側の表面に有する(ここではAl基板22の全面に有する)、第五の金属からなるAl基板22である。これによって、Alの塑性変形し易い特性を活かした接合部の応力緩和が可能となると同時に、Agナノペースト4を用いた上記接合方法及び接合構造も達成可能となる。また、半導体装置の製造構造として、上記効果が得られる。その他の構成、接合方法、作用、効果は第一の実施の形態と同様である。
<< Second Embodiment >>
FIG. 2 is an overall cross-sectional view of the joint structure according to the second embodiment of the present invention.
The difference from the first embodiment shown in FIG. 1 is that in this embodiment, the metal substrate is an Al substrate 22 made of Al (aluminum), which is the fifth metal, and the periphery thereof is plated or The Ag layer 21b is formed as the second metal layer by utilizing vapor deposition or the like.
That is, the bonding structure of the present embodiment is the surface bonding type semiconductor element 1 in which the first object has the first metal layer on at least one main surface of two main surfaces. The second object is an Al substrate 22 made of a fifth metal having an Ag layer 21b as a second metal layer on at least the surface on the side to be joined (here, on the entire surface of the Al substrate 22). . This makes it possible to relieve stress at the joint utilizing the characteristics of Al that are easily plastically deformed, and at the same time, achieve the above-described joining method and joint structure using the Ag nanopaste 4. In addition, the above-described effects can be obtained as a semiconductor device manufacturing structure. Other configurations, joining methods, operations, and effects are the same as those in the first embodiment.

《第三の実施の形態》
図3は、本発明の第三の実施の形態の接合構造の全体断面図である。
図2に示した第二の実施の形態との違いは、金属基板であるAl基板22に絶縁板23が予め接合されている点である。例えば、絶縁板23は、窒化アルミニウム(AlN)や窒化珪素(SiN)等のセラミックスからなる。すなわち、本実施の形態の接合構造は、前記第一の物体は、二つの主面のうちの少なくとも一方の主面に、前記第一の金属層を有する面接合タイプの半導体素子1であり、前記第二の物体は、Al基板22と絶縁板23とを有する金属付き絶縁基板24である。なお、第二の実施の形態と同様に、Al基板22の少なくとも前記接合する側の表面には、第二の金属層であるAg層21bを有する(ここではAl基板22の全面に有する)。
このような構成によって、半導体装置の製造構造として、上記効果が得られる。その他の構成、接合方法、作用、効果は第一の実施の形態と同様である。さらに、本実施の形態では、半導体素子1が接合される側のAl基板22と、絶縁板23を挟んで反対側のAl基板22とは、絶縁板23によって完全に絶縁されており、半導体装置としての絶縁性も確保することが可能となる。
<< Third embodiment >>
FIG. 3 is an overall cross-sectional view of the joint structure according to the third embodiment of the present invention.
The difference from the second embodiment shown in FIG. 2 is that an insulating plate 23 is bonded in advance to an Al substrate 22 which is a metal substrate. For example, the insulating plate 23 is made of a ceramic such as aluminum nitride (AlN) or silicon nitride (SiN). That is, the bonding structure of the present embodiment is the surface bonding type semiconductor element 1 in which the first object has the first metal layer on at least one main surface of two main surfaces. The second object is an insulating substrate 24 with metal having an Al substrate 22 and an insulating plate 23. Note that, similarly to the second embodiment, at least the surface of the Al substrate 22 on the side to be joined has an Ag layer 21b that is a second metal layer (in this case, the entire surface of the Al substrate 22).
With such a configuration, the above-described effect can be obtained as a semiconductor device manufacturing structure. Other configurations, joining methods, operations, and effects are the same as those in the first embodiment. Furthermore, in the present embodiment, the Al substrate 22 on the side to which the semiconductor element 1 is bonded and the Al substrate 22 on the opposite side across the insulating plate 23 are completely insulated by the insulating plate 23, and the semiconductor device It is also possible to ensure insulation as.

なお、以上説明した実施の形態は、本発明の理解を容易にするために記載されたものであって、本発明を限定するために記載されたものではない。したがって、上記実施の形態に開示された各要素は、本発明の技術的範囲に属する全ての設計変更や均等物をも含む趣旨である。例えば、以上の実施の形態では、金属としてAgやCuやAl等を用いたが、本発明はこれに限定されることなく、クレームに基づく接合方法及び接合構造によって同様な効果が得られる金属であればいずれであっても構わない。また、半導体素子1としては、Siを用いたが、その他のガリウム砒素(GaAs)や炭化シリコン(SiC)などであっても構わない。特に、本発明によって得られる効果である、Agナノペーストを用いた低温接合による残留応力低減と、接合後の使用温度の高耐熱化と、Al基板による応力緩和を有効に活用できる用途として、高耐熱素子として有望なSiCの高温使用に対する実装方法として最適であると言える。   The embodiment described above is described for facilitating the understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in the above embodiment includes all design changes and equivalents belonging to the technical scope of the present invention. For example, in the above embodiment, Ag, Cu, Al, or the like is used as a metal. Any one is acceptable. Further, although Si is used as the semiconductor element 1, other gallium arsenide (GaAs) or silicon carbide (SiC) may be used. In particular, the effects obtained by the present invention include a reduction in residual stress due to low-temperature bonding using Ag nanopaste, an increase in heat resistance at the use temperature after bonding, and stress relief due to an Al substrate can be effectively utilized. It can be said that it is optimal as a mounting method for high-temperature use of SiC that is promising as a heat-resistant element.

(a)は本発明の第一の実施の形態の接合構造の全体断面図、(b)は(a)の接合部(A部)の拡大断面図、(c)は多孔質金属層の内部の形状を示す平面図、(d)は別の多孔質金属層の内部の形状を示す平面図である。(A) is whole sectional drawing of the junction structure of 1st embodiment of this invention, (b) is an expanded sectional view of the junction part (A part) of (a), (c) is the inside of a porous metal layer (D) is a top view which shows the internal shape of another porous metal layer. 本発明の第二の実施の形態の接合構造の全体断面図である。It is whole sectional drawing of the junction structure of 2nd embodiment of this invention. 本発明の第三の実施の形態の接合構造の全体断面図である。It is a whole sectional view of the junction structure of a third embodiment of the present invention.

符号の説明Explanation of symbols

1…半導体素子 3…Cuポーラス板
4…Agナノペースト 11…第一の金属層
21a…Cu基板 21b…Ag層
22…Al基板 23…絶縁板
24…金属付き絶縁基板 31a、31b…空孔
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element 3 ... Cu porous board 4 ... Ag nanopaste 11 ... 1st metal layer 21a ... Cu board | substrate 21b ... Ag layer 22 ... Al board | substrate 23 ... Insulation board 24 ... Insulation board | substrate 31a, 31b with metal | air_hole

Claims (7)

第一の物体の第一の金属からなる第一の金属層と、第二の物体の第二の金属からなる第二の金属層との間に、内部に空孔を有し第三の金属からなる多孔質金属層を介在させ、
金属を含む有機系接合材を、前記第一の金属層と前記多孔質金属層との間、及び第二の金属層と前記多孔質金属層との間に設置し、
加熱して接合することを特徴とする接合方法。
Between the first metal layer made of the first metal of the first object and the second metal layer made of the second metal of the second object, there is a void inside and the third metal Interposing a porous metal layer consisting of
An organic bonding material containing a metal is installed between the first metal layer and the porous metal layer, and between the second metal layer and the porous metal layer,
A joining method characterized by heating and joining.
第一の物体の第一の金属からなる第一の金属層の表面に、予め内部に空孔を有し第三の金属からなる多孔質金属層の第一の面を、金属を含む有機系接合材を用いて加熱して接合し、
その後、前記多孔質金属層の前記第一の面と対向する第二の面に、第二の物体の第二の金属からなる第二の金属層を、前記有機系接合材を用いて加熱して接合することを特徴とする接合方法。
An organic system containing a metal on a surface of a first metal layer made of a first metal of a first object and having a first surface of a porous metal layer made of a third metal having pores therein in advance. Heat and bond using bonding material,
Thereafter, a second metal layer made of the second metal of the second object is heated on the second surface facing the first surface of the porous metal layer using the organic bonding material. Joining method characterized by joining.
前記多孔質金属層は、前記接合する面に空孔が露出しており、かつ、前記接合する面に平行な方向に空孔が連続していることを特徴とする請求項1または2記載の接合方法。   3. The porous metal layer according to claim 1, wherein pores are exposed on the surfaces to be joined, and the pores are continuous in a direction parallel to the surfaces to be joined. Joining method. 前記有機系接合材は、平均直径が100nm以下の第四の金属からなる超微粒子を有機系溶媒中に分散させてなる金属ナノペーストであることを特徴とする請求項1乃至3のいずれか記載の接合方法。   The organic bonding material is a metal nanopaste obtained by dispersing ultrafine particles made of a fourth metal having an average diameter of 100 nm or less in an organic solvent. Joining method. 前記接合後、第一の物体と第二の物体とを接合面に対して垂直な方向に加圧し、前記多孔質金属層を圧縮して空孔を無くすことを特徴とする請求項1乃至4のいずれか記載の接合方法。   5. The first object and the second object are pressurized in a direction perpendicular to the joining surface after the joining, and the porous metal layer is compressed to eliminate voids. Any one of the joining methods. 前記第一の物体は、
二つの主面のうちの少なくとも一方の主面に、前記第一の金属層を有する面接合タイプの半導体素子であり、
前記第二の物体は、
前記第二の金属層からなる金属基板、
第二の金属層を少なくとも前記接合する側の表面に有し、第五の金属からなる金属基板、
または前記金属基板と絶縁板とを有する金属付き絶縁基板であることを特徴とする請求項1乃至5のいずれか記載の接合方法によって接合された接合構造。
The first object is
A surface junction type semiconductor element having the first metal layer on at least one main surface of two main surfaces,
The second object is
A metal substrate comprising the second metal layer;
A metal substrate having a second metal layer on at least the surface to be joined and made of a fifth metal;
The bonding structure bonded by the bonding method according to claim 1, wherein the bonding structure is a metal-attached insulating substrate having the metal substrate and an insulating plate.
前記第一の金属、前記第二の金属、前記第三の金属、前記第四の金属は、
金、銀、白金、銅、ニッケル、クロム、鉄、鉛、コバルトのうちのいずれかの金属、またはこれらの金属のうちの少なくとも一種を含む合金、またはこれら金属もしくは合金の混合物からなることを特徴とする請求項6記載の接合構造。
The first metal, the second metal, the third metal, and the fourth metal are:
It is made of any metal of gold, silver, platinum, copper, nickel, chromium, iron, lead, cobalt, an alloy containing at least one of these metals, or a mixture of these metals or alloys The joint structure according to claim 6.
JP2005012397A 2005-01-20 2005-01-20 Joining method and joining structure Expired - Fee Related JP4635230B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005012397A JP4635230B2 (en) 2005-01-20 2005-01-20 Joining method and joining structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005012397A JP4635230B2 (en) 2005-01-20 2005-01-20 Joining method and joining structure

Publications (2)

Publication Number Publication Date
JP2006202944A true JP2006202944A (en) 2006-08-03
JP4635230B2 JP4635230B2 (en) 2011-02-23

Family

ID=36960670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005012397A Expired - Fee Related JP4635230B2 (en) 2005-01-20 2005-01-20 Joining method and joining structure

Country Status (1)

Country Link
JP (1) JP4635230B2 (en)

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214340A (en) * 2006-02-09 2007-08-23 Hitachi Ltd Metallic ultra-fine particle using bonding material and semiconductor device using the same
JP2008244242A (en) * 2007-03-28 2008-10-09 Hitachi Ltd Semiconductor device and its manufacturing method, and composite metallic body and its manufacturing method
JP2009164208A (en) * 2007-12-28 2009-07-23 Mitsubishi Electric Corp Semiconductor device and manufacturing method of semiconductor device
US7682875B2 (en) 2008-05-28 2010-03-23 Infineon Technologies Ag Method for fabricating a module including a sintered joint
JP2011134785A (en) * 2009-12-22 2011-07-07 Panasonic Electric Works Co Ltd Light emitting device
JP2011134786A (en) * 2009-12-22 2011-07-07 Panasonic Electric Works Co Ltd Light emitting device
WO2011114747A1 (en) 2010-03-18 2011-09-22 古河電気工業株式会社 Electrically conductive paste, and electrically conductive connection member produced using the paste
CN102272921A (en) * 2008-12-23 2011-12-07 罗伯特·博世有限公司 Electrical or electronic composite component and method for producing an electrical or electronic composite component
WO2014057902A1 (en) * 2012-10-09 2014-04-17 三菱マテリアル株式会社 Semiconductor device, ceramic circuit board, and semiconductor device manufacturing method
JP2014067917A (en) * 2012-09-26 2014-04-17 Tanaka Kikinzoku Kogyo Kk Die bond structure of semiconductor element and die bonding method of semiconductor element
JP2014130981A (en) * 2012-12-30 2014-07-10 Tohoku Univ Method for joining substrate, and electronic component package
JP2015057825A (en) * 2008-04-30 2015-03-26 日立化成株式会社 Connection material and semiconductor device
JP2015106654A (en) * 2013-11-29 2015-06-08 富士通株式会社 Joining method, method for manufacturing semiconductor device, and semiconductor device
CN104979312A (en) * 2014-04-14 2015-10-14 中国科学院苏州纳米技术与纳米仿生研究所 Semiconductor structure and preparation method thereof
JP2015185559A (en) * 2014-03-20 2015-10-22 三菱電機株式会社 Method of manufacturing semiconductor module, and semiconductor module
JP2016162919A (en) * 2015-03-03 2016-09-05 国立大学法人大阪大学 Bonding structure and manufacturing method of same
JP2016536461A (en) * 2013-08-29 2016-11-24 アルファ・メタルズ・インコーポレイテッドAlpha Metals, Inc. Composite and multilayer silver films for joining electrical and mechanical parts
JP2020077761A (en) * 2018-11-08 2020-05-21 日本特殊陶業株式会社 Electrostatic chuck
JP6713120B1 (en) * 2019-12-27 2020-06-24 小松 晃雄 Copper Sintered Substrate Nano Silver Impregnated Bonding Sheet, Manufacturing Method and Bonding Method
JP2020155461A (en) * 2019-03-18 2020-09-24 三菱マテリアル株式会社 Bonding sheet and method for bonding electronic component to substrate using bonding sheet
DE102019124954A1 (en) * 2019-09-17 2021-03-18 Danfoss Silicon Power Gmbh Method for connecting a first electronic component to a second electronic component
DE102022127168A1 (en) 2022-01-31 2023-08-03 Mitsubishi Electric Corporation semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11245085A (en) * 1998-02-27 1999-09-14 Fuji Xerox Co Ltd Joint member and semiconductor mounting device using it
JP2004128357A (en) * 2002-10-04 2004-04-22 Ebara Corp Electrode arranged substrate and its electrode connection method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11245085A (en) * 1998-02-27 1999-09-14 Fuji Xerox Co Ltd Joint member and semiconductor mounting device using it
JP2004128357A (en) * 2002-10-04 2004-04-22 Ebara Corp Electrode arranged substrate and its electrode connection method

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4598687B2 (en) * 2006-02-09 2010-12-15 株式会社日立製作所 Bonding material using ultrafine metal particles and semiconductor device using the same
JP2007214340A (en) * 2006-02-09 2007-08-23 Hitachi Ltd Metallic ultra-fine particle using bonding material and semiconductor device using the same
JP2008244242A (en) * 2007-03-28 2008-10-09 Hitachi Ltd Semiconductor device and its manufacturing method, and composite metallic body and its manufacturing method
JP2009164208A (en) * 2007-12-28 2009-07-23 Mitsubishi Electric Corp Semiconductor device and manufacturing method of semiconductor device
JP2015057825A (en) * 2008-04-30 2015-03-26 日立化成株式会社 Connection material and semiconductor device
US7682875B2 (en) 2008-05-28 2010-03-23 Infineon Technologies Ag Method for fabricating a module including a sintered joint
JP2012513683A (en) * 2008-12-23 2012-06-14 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Electrical or electronic composite component and method for manufacturing electrical or electronic composite component
CN102272921A (en) * 2008-12-23 2011-12-07 罗伯特·博世有限公司 Electrical or electronic composite component and method for producing an electrical or electronic composite component
JP2011134786A (en) * 2009-12-22 2011-07-07 Panasonic Electric Works Co Ltd Light emitting device
JP2011134785A (en) * 2009-12-22 2011-07-07 Panasonic Electric Works Co Ltd Light emitting device
WO2011114747A1 (en) 2010-03-18 2011-09-22 古河電気工業株式会社 Electrically conductive paste, and electrically conductive connection member produced using the paste
US10046418B2 (en) 2010-03-18 2018-08-14 Furukawa Electric Co., Ltd. Electrically conductive paste, and electrically conducive connection member produced using the paste
JP2014067917A (en) * 2012-09-26 2014-04-17 Tanaka Kikinzoku Kogyo Kk Die bond structure of semiconductor element and die bonding method of semiconductor element
WO2014057902A1 (en) * 2012-10-09 2014-04-17 三菱マテリアル株式会社 Semiconductor device, ceramic circuit board, and semiconductor device manufacturing method
KR20150063065A (en) * 2012-10-09 2015-06-08 미쓰비시 마테리알 가부시키가이샤 Semiconductor device, ceramic circuit board, and semiconductor device manufacturing method
JP2014078558A (en) * 2012-10-09 2014-05-01 Mitsubishi Materials Corp Semiconductor device, ceramic circuit board, and method for manufacturing semiconductor device
KR102163532B1 (en) * 2012-10-09 2020-10-08 미쓰비시 마테리알 가부시키가이샤 Semiconductor device, ceramic circuit board, and semiconductor device manufacturing method
US9401340B2 (en) 2012-10-09 2016-07-26 Mitsubishi Materials Corporation Semiconductor device and ceramic circuit substrate, and producing method of semiconductor device
JP2014130981A (en) * 2012-12-30 2014-07-10 Tohoku Univ Method for joining substrate, and electronic component package
JP2016536461A (en) * 2013-08-29 2016-11-24 アルファ・メタルズ・インコーポレイテッドAlpha Metals, Inc. Composite and multilayer silver films for joining electrical and mechanical parts
JP2015106654A (en) * 2013-11-29 2015-06-08 富士通株式会社 Joining method, method for manufacturing semiconductor device, and semiconductor device
JP2015185559A (en) * 2014-03-20 2015-10-22 三菱電機株式会社 Method of manufacturing semiconductor module, and semiconductor module
CN104979312A (en) * 2014-04-14 2015-10-14 中国科学院苏州纳米技术与纳米仿生研究所 Semiconductor structure and preparation method thereof
JP2016162919A (en) * 2015-03-03 2016-09-05 国立大学法人大阪大学 Bonding structure and manufacturing method of same
JP2020077761A (en) * 2018-11-08 2020-05-21 日本特殊陶業株式会社 Electrostatic chuck
JP7202852B2 (en) 2018-11-08 2023-01-12 日本特殊陶業株式会社 electrostatic chuck
JP2020155461A (en) * 2019-03-18 2020-09-24 三菱マテリアル株式会社 Bonding sheet and method for bonding electronic component to substrate using bonding sheet
JP7196706B2 (en) 2019-03-18 2022-12-27 三菱マテリアル株式会社 Bonding sheet and method of bonding electronic component to substrate using bonding sheet
DE102019124954A1 (en) * 2019-09-17 2021-03-18 Danfoss Silicon Power Gmbh Method for connecting a first electronic component to a second electronic component
JP6713120B1 (en) * 2019-12-27 2020-06-24 小松 晃雄 Copper Sintered Substrate Nano Silver Impregnated Bonding Sheet, Manufacturing Method and Bonding Method
JP2021107569A (en) * 2019-12-27 2021-07-29 小松 晃雄 Copper sintered substrate nano-silver impregnated joint sheet, method therefor and joining method
DE102022127168A1 (en) 2022-01-31 2023-08-03 Mitsubishi Electric Corporation semiconductor device

Also Published As

Publication number Publication date
JP4635230B2 (en) 2011-02-23

Similar Documents

Publication Publication Date Title
JP4635230B2 (en) Joining method and joining structure
JP6632686B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP2006202586A (en) Bonding method and bonding structure
JP4770533B2 (en) Semiconductor device manufacturing method and semiconductor device
JP2006202938A (en) Semiconductor device and its manufacturing method
TWI624356B (en) Metal joint structure using metal nanoparticle, metal joint method, and metal joint material
JP6432466B2 (en) Bonded body, power module substrate with heat sink, heat sink, method for manufacturing bonded body, method for manufacturing power module substrate with heat sink, and method for manufacturing heat sink
JP6262968B2 (en) Electronic component mounting substrate and manufacturing method thereof
JP4969589B2 (en) Peltier element purification process and Peltier element
JP2016208010A (en) Bonded body, substrate for power module with heat sink, heat sink, method for producing bonded body, method for producing substrate for power module with heat sink, and method for producing heat sink
TW201325330A (en) Wiring substrate and method for manufacturing same and semiconductor device
JP6029222B1 (en) Metal particles, paste, molded body, and laminate
JP5659663B2 (en) Semiconductor device and manufacturing method of semiconductor device
CN104347564A (en) Bonding structure and bonding method using metal nano particles
US9905532B2 (en) Methods and apparatuses for high temperature bonding and bonded substrates having variable porosity distribution formed therefrom
JP5642336B2 (en) Semiconductor device and manufacturing method thereof
JP6384894B2 (en) Metal bonding structure, metal bonding method and metal bonding material using metal nanoparticles
JP2021107569A (en) Copper sintered substrate nano-silver impregnated joint sheet, method therefor and joining method
JP6403930B1 (en) Semiconductor device and manufacturing method thereof
JP2006228804A (en) Ceramic substrate for semiconductor module and its manufacturing method
EP3093882B1 (en) Electronic circuit device
CN108305838B (en) Low-temperature chip mounting method and chip mounting structure without organic matters
JP2009094385A (en) Semiconductor device, and manufacturing method thereof
KR20180073767A (en) Bonding paste for high temperature applications and bonding method using the in situ formation of fine Ag bumps
JPH05319946A (en) Ceramic substrate joined to metallic plate

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071221

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100118

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100126

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100323

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100427

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100628

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100803

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100930

TRDD Decision of grant or rejection written
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20101015

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101019

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20101111

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101101

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131203

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees