JP2015090926A - Film for manufacturing semiconductor device, semiconductor device using the same, and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wafer level semiconductor device which enables thickness reduction and achieves small warpage and excellent heat radiation performance, and to provide a manufacturing method for efficiently manufacturing the semiconductor device at low cost.SOLUTION: A film for manufacturing a semiconductor device, which includes a thermosetting resin composition layer 1 capable of sealing a semiconductor element and a thermosetting resin composition layer 2 capable of forming wiring, is used.

Description

  The present invention relates to a film for manufacturing a semiconductor device, a semiconductor device using the film, and a method for manufacturing the semiconductor device. More specifically, the present invention relates to a manufacturing method that can efficiently manufacture a wafer level semiconductor device that is highly demanded for miniaturization and thinning at low cost.

  As electronic devices become more sophisticated, semiconductor devices are becoming smaller and thinner, and wafer-level semiconductor devices that are almost the same size as semiconductor elements and package-on devices that stack semiconductor devices on top of the semiconductor devices.・ Mounting forms such as packages are also popular. In the future, semiconductor devices are expected to become smaller and thinner.

  By the way, a wafer level semiconductor device can be obtained by forming a rewiring layer on a wafer, providing an external connection terminal such as a solder ball, and then dicing it into individual pieces. When the number of terminals is about several tens to 100 pins, external connection terminals such as solder balls can be provided on the wafer.

  However, when miniaturization of semiconductor elements progresses and the number of terminals increases, it becomes difficult to form a rewiring layer only on the wafer and to provide external connection terminals. When the terminals for external connection are forcibly provided, the pitch between the terminals is reduced and the height of the terminals is reduced, so that it is difficult to ensure connection reliability after mounting the semiconductor device. For this reason, it is required to cope with the miniaturization of semiconductor elements, that is, the increase in the number of external connection terminals. Recently, development of a semiconductor device in which a terminal for external connection can be provided outside a semiconductor element by dividing the wafer into a predetermined size and rearranging the wafer is progressing (for example, Patent Documents 1 to 4). reference).

Japanese Patent No. 3616615 JP 2001-244372 A Japanese Patent Laid-Open No. 2001-127095 US Patent Application Publication No. 2007/205513

  In the semiconductor devices described in Patent Documents 1 to 4, since the wafer is separated into a predetermined size and the separated semiconductor devices are rearranged, a wide rewiring area is secured rather than rewiring on the wafer. Therefore, it is possible to cope with the increase in the number of pins of the semiconductor element.

  1 to 3 are diagrams showing a conventional method of manufacturing a semiconductor device. The semiconductor device shown in FIG. 3N is obtained through processes such as rearrangement of semiconductor elements, sealing, rewiring layer formation, wiring formation, external connection terminal formation, and singulation.

  A temporary fixing film is bonded to one side of the support plate (see FIG. 1A). Next, the semiconductor elements are rearranged at a predetermined interval so that the active surface (surface; the surface on which the circuit is formed) is bonded to the temporary fixing film (see FIG. 1B). Next, the semiconductor element is sealed with a sealing material (see FIG. 1C). After sealing, post-curing is performed at a predetermined temperature and time. Next, the substrate is placed on a hot plate set at a predetermined temperature, and the support plate is removed (see FIG. 1D). Next, the temporary fixing film is peeled off to expose the active surface (surface) of the semiconductor element (see FIG. 1E). Next, a coating type photosensitive resin composition is spin-coated on the active surface of the semiconductor element, and dried on a hot plate (see FIG. 2F). Next, a predetermined portion is exposed and developed, and post-cured in an oven (see FIG. 2G). Next, a seed layer is formed by sputtering (see FIG. 2H). A circuit forming resist is laminated on the seed layer, and a predetermined portion is exposed and developed (see FIG. 2 (i)). Next, a wiring pattern is formed by electroplating (see FIG. 2 (j)). Next, the resist for circuit formation is removed with a peeling solution (see FIG. 3 (k)). Next, the seed layer is removed by etching (see FIG. 3L). Next, the photosensitive resin composition is spin-coated again, dried on a hot plate at about 80 ° C., subjected to exposure / development processing at a predetermined location, and then post-cured in an oven (see FIG. 3 (m)). Next, the solder balls are reflow mounted. Finally, a semiconductor device can be manufactured by dicing into individual pieces (see FIG. 3N).

  Since the semiconductor device obtained in this manner can be reduced in size and thickness, it is suitable for electronic devices such as smartphones and tablet terminals whose functions are becoming higher and more multifunctional. However, the semiconductor device manufactured by such a method has a complicated manufacturing process, and the passive surface (back surface) of the semiconductor element is sealed, so that warpage is likely to occur, and further reduction in thickness is possible. There are problems such as being difficult to heat and unsuitable for heat dissipation.

  The film for manufacturing a semiconductor device of the present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device capable of reducing the thickness of the semiconductor device, low warpage, and high heat dissipation. Moreover, it aims at providing the manufacturing method for manufacturing efficiently and low-cost using the film for semiconductor device manufacture of this invention.

The present invention provides the following film for manufacturing a semiconductor device, a semiconductor device using the film, and a method for manufacturing the semiconductor device.
[1] A film for manufacturing a semiconductor device, comprising a thermosetting resin composition layer 1 capable of sealing a semiconductor element, and a thermosetting resin composition layer 2 capable of forming a wiring.
[2] The film for manufacturing a semiconductor device according to [1], further including a support, wherein the thermosetting resin composition layer 1, the thermosetting resin composition layer 2, and the support are provided in this order. .
[3] Furthermore, the thermosetting resin composition layer 1 and the thermosetting resin composition layer 2 contain an inorganic filler, and the filling amount of the inorganic filler contained in the thermosetting resin composition layer 1 is the solid content of the resin. On the other hand, the film for manufacturing a semiconductor device according to the above [1] or [2], wherein the film is 30 to 95% by mass and the filling amount of the inorganic filler contained in the thermosetting resin composition layer 2 is 30% by mass or less. .
[4] The maximum particle size of the inorganic filler contained in the thermosetting resin composition layer 1 is 20 μm or less, the average particle size is 5 μm or less, and the maximum inorganic filler contained in the thermosetting resin composition layer 2. The film for manufacturing a semiconductor device according to the above [3], wherein the particle diameter is 5 μm or less and the average particle diameter is 1 μm or less.
[5] A semiconductor device using the film for manufacturing a semiconductor device according to any one of [1] to [4].
[6] (A) After forming the temporary fixing layer on the support plate, placing at least one semiconductor element so that the passive surface (back surface) of the semiconductor element and the temporary fixing layer are bonded together;
(B) sealing with the film for manufacturing a semiconductor device according to any one of the above [1] to [4] so as to cover an active surface (surface) of at least one semiconductor element;
(C) peeling the support plate and the temporary fixing layer to expose the passive surface (back surface) of the semiconductor element;
(D) grinding the second insulating layer on the active surface (front surface) of the semiconductor element to form an opening reaching the active surface (front surface) of the semiconductor element;
(E) forming a seed layer on the insulating layer;
(F) forming a resist for circuit formation on the seed layer, and performing an exposure process and a development process to form a resist pattern for rewiring;
(G) forming a wiring pattern by an electroplating method, and removing the resist pattern by a peeling process;
(H) removing the seed layer;
(I) forming a third insulating layer on the wiring pattern and forming an opening reaching the wiring pattern;
(J) A method for manufacturing a semiconductor device comprising a step of forming an external connection terminal.
[7] The method for manufacturing a semiconductor device according to [6], wherein the sealing temperature of the film for manufacturing a semiconductor device in the step (B) is 50 to 140 ° C. and the heating time is in the range of 10 to 300 seconds.
[8] The method for producing a semiconductor device according to [6], wherein the sealing pressure of the film for producing a semiconductor device in the step (B) is 0.2 to 2.0 MPa.

  According to the present invention, the step of sealing the semiconductor element, the step of forming the insulating layer on the active surface (front surface) of the semiconductor element, and the processing so that the passive surface (back surface) of the semiconductor element can be easily exposed. Thus, a wafer level semiconductor device that can be thinned, has low warpage, and has excellent heat dissipation can be efficiently provided at low cost.

It is a figure which shows the manufacturing method of the conventional semiconductor device. FIG. 2 is a diagram showing a conventional method for manufacturing a semiconductor device showing a continuation of FIG. 1. FIG. 3 is a diagram showing a conventional method for manufacturing a semiconductor device showing a continuation of FIG. 2. It is an end view which shows typically an example of the manufacturing method of the semiconductor device of this invention. FIG. 5 is an end view schematically showing an example of the method for manufacturing a semiconductor device of the present invention showing a continuation of FIG. 4. FIG. 6 is an end view schematically showing an example of the method for manufacturing a semiconductor device of the present invention showing a continuation of FIG. 5. FIG. 7 is an end view schematically showing one example of a method for manufacturing a semiconductor device of the present invention showing a continuation of FIG. 6.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

  Here, a method of manufacturing the semiconductor device shown in FIG. 7 (t) will be described from the mode shown in FIG. 4 (a). The method for manufacturing a semiconductor device according to the present embodiment is particularly suitable for a wafer level semiconductor device that is becoming smaller and thinner.

With reference to FIGS. 4 to 7, a film for manufacturing a semiconductor device of the present embodiment and a method for manufacturing a semiconductor device using the same will be described.
The film for manufacturing a semiconductor device of the present embodiment has a thermosetting resin composition layer 1 capable of sealing a semiconductor element and a thermosetting resin composition layer 2 capable of forming a wiring. .
Moreover, the film for manufacturing a semiconductor device of the present embodiment may have a support 3, and the thermosetting resin composition layer 1, the thermosetting resin composition layer 2, and the support 3 are in this order. Is preferably provided.
Below, the manufacturing method of the film for semiconductor device manufacture of this embodiment is demonstrated. The film for manufacturing a semiconductor device according to this embodiment includes, for example, a thermosetting resin composition layer 2 formed on one side of a support 3 and then a thermosetting resin composition layer on the thermosetting resin composition layer 2. 1 is obtained (see FIG. 4A).
Although the support body 3 is not specifically limited, For example, a SUS (stainless steel) board, a silicon wafer, a PET (polyethylene terephthalate) film, a polyimide film, copper foil, etc. are mentioned. The shape is not particularly limited, and it may be a circle, a square, a sheet, or a roll film.
The thermosetting resin composition layer 2 is formed using the thermosetting resin composition (II). In the case where the thermosetting resin composition layer (II) is a varnish in which the thermosetting resin composition (II) is liquid or a thermosetting resin composition (II) is dissolved or dispersed with a solvent, the thermosetting resin composition layer 2 is formed on one side of the support 3. It can form by passing through the process of apply | coating thermosetting resin composition (II), and the process of semi-hardening or drying. Examples of the step of applying the thermosetting resin composition (II) to one side of the support 3 include a method using a coater and a printing method. A method using a coater is not particularly limited, and for example, a die coater, a comma coater, a dip coater, or a spin coater can be used. The process of semi-curing or drying is not particularly limited, and for example, a hot plate or a drying furnace can be used.
Further, the thermosetting resin composition layer 2 can be formed on the support 3 using a film of the thermosetting resin composition (II). Although it does not specifically limit as a method of manufacturing the film of thermosetting resin composition (II), For example, the thermosetting resin composition ( And a method of applying II).
When a film of the thermosetting resin composition (II) is used, for example, the film is bonded to one side of the support 3 with a known vacuum laminator, roll laminator, press, or the like. The curable resin composition layer 2 can be formed. After the film is bonded to one side of the support 3, semi-curing or drying may be performed as necessary. When the film of the thermosetting resin composition (II) is used, the pressure, temperature, and time of the laminator in the bonding process are not particularly limited. For example, the film is bonded to one side of the support 3. It is preferable to select conditions that do not cause air entrapment. When a PET film is used as the support 3, it is preferable to select a temperature at which the PET film is not denatured as the semi-curing or drying temperature of the thermosetting resin composition (II).

  Next, the film for manufacturing a semiconductor device of this embodiment is obtained by forming the thermosetting resin composition layer 1 on the thermosetting resin composition layer 2. The thermosetting resin composition layer 1 is formed using the thermosetting resin composition (I). Although the formation method of the thermosetting resin composition layer 1 is not specifically limited, For example, it can form by the method similar to the process of forming the thermosetting resin composition layer 2.

Below, the manufacturing method of the semiconductor device using the film for semiconductor device manufacture of this embodiment is demonstrated.
The semiconductor manufacturing method of this embodiment is
(A) After forming the temporary fixing layer on the support, placing at least one semiconductor element so that the passive surface (back surface) of the semiconductor element and the temporary fixing layer are bonded together;
(B) a step of sealing with the film for manufacturing a semiconductor device of the present embodiment so as to cover an active surface (surface) of at least one semiconductor element;
(C) peeling the support plate and the temporary fixing layer to expose the passive surface (back surface) of the semiconductor element;
(D) grinding the second insulating layer (thermosetting resin composition layer 2) on the active surface (surface) of the semiconductor element to form an opening reaching the active surface (surface) of the semiconductor element;
(E) forming a seed layer on the insulating layer;
(F) forming a resist for circuit formation on the seed layer, and performing an exposure process and a development process to form a resist pattern for rewiring;
(G) forming a wiring pattern by an electroplating method, and removing the resist pattern by a peeling process;
(H) removing the seed layer;
(I) forming a third insulating layer on the wiring pattern and forming an opening reaching the wiring pattern;
(J) forming a terminal for external connection.

For example, first, a temporary fixing film 5 is bonded to one side of the support plate 4 to provide a temporary fixing layer (FIG. 4B). Next, as shown in FIG. 4C, the semiconductor elements 6 are rearranged at a predetermined interval so that the passive surface (back surface) of the semiconductor elements 6 is bonded to the temporarily fixing film 5. The material of the support plate 4 is not particularly limited, but a SUS plate, a silicon wafer, or the like that has a small dimensional change due to heat is suitable. Similarly, the thickness of the support plate 4 is not particularly limited, but a thickness of 0.5 mm or more is suitable from the viewpoint of suppressing warpage. The temporary fixing film 5 is not particularly limited, and for example, commercially available materials can be used. When heat resistance is required for the temporary fixing film 5, for example, an amide bond obtained by a polycondensation reaction between a diamine compound described in JP 2010-254808 A and an aromatic polycarboxylic acid compound, or A polymer film having a specific structure having an imide bond can be used.

Next, using the film for manufacturing a semiconductor device of the present embodiment shown in FIG. 4A, the surface of the thermosetting resin composition layer 1 is a temporarily fixed film so as to cover at least one semiconductor element 6. The semiconductor element 6 is sealed so as to be bonded to the substrate 5. At this time, the first insulating layer made of the thermosetting resin composition layer 1 (hereinafter sometimes referred to as the first insulating layer) is formed on the side surface of the semiconductor element 6. A second insulating layer (hereinafter sometimes referred to as a second insulating layer) made of the thermosetting resin composition layer 2 is formed thereon. An insulating layer refers to the state which the thermosetting resin composition layer hardened | cured. In the said process, a 1st insulating layer and a 2nd insulating layer are formed by passing through the process of bonding the film for semiconductor device manufacture with a well-known vacuum laminator, a roll laminator, a press machine. The sealing temperature at this time is preferably 50 to 140 ° C, more preferably 70 to 100 ° C. When the sealing temperature is 50 ° C. or higher, filling of the resin tends to be easy. On the other hand, in the case of 140 ° C. or lower, it tends to be easy to peel off the support 3 such as PET after sealing.
Moreover, the sealing time in this case becomes like this. Preferably it is 10 to 300 seconds, More preferably, it is 30 to 120 seconds. When the sealing time is 10 seconds or more, there is a tendency that the resin is sufficiently filled. On the other hand, when it is 300 seconds or less, good productivity is obtained. The sealing pressure is preferably 0.2 to 2.0 MPa, more preferably 0.2 to 1.0 MPa. When the sealing pressure is 0.2 MPa or more, there is a tendency that the resin is sufficiently filled. On the other hand, when the pressure is 2.0 MPa or less, an insulating layer having a sufficient thickness tends to be formed on the active surface (surface) of the semiconductor element 6. Next, post-curing of the thermosetting resin composition is performed at a predetermined temperature and time. Although post-curing temperature is not specifically limited, Preferably it is 120-200 degreeC, More preferably, it is 150-180 degreeC. The post-curing time is not particularly limited, but is preferably 15 to 180 minutes, and more preferably 30 to 120 minutes.

It is preferable the thickness _{T 3} of the semiconductor device 6 first difference in thickness _{T 1} of the insulating layer _{1 (T} 3 -T 1) is 10μm or less (see FIG. 4 (d)). When (T ₃ -T ₁ ) is 10 μm or less, the smoothness of the second insulating layer 2 tends to be good. Moreover, by reducing the T ₁ than T _3, the active surface of the semiconductor element 6 (surface) it is possible to reach the thermosetting resin composition layer 2, the wiring formation is facilitated.

The thickness T ₂ of the second insulating layer 2 is preferably in the range of 5 to 50 μm, more preferably in the range of 10 to 30 μm (see FIG. 4D). If T ₂ is equal to or greater than 5 [mu] m, it is easy to form a good insulating layer smoothness on the semiconductor element 6. On the other hand, in the case of 50 μm or less, it tends to be easy to provide a fine opening diameter by grinding.

  Next, as shown in FIGS. 5 (e) and 5 (f), the substrate is placed on a hot plate set at a predetermined temperature, the support plate 4 and the temporary fixing film 5 are removed, and the passive surface (back surface) of the semiconductor element is removed. Expose. The temperature of the hot plate is not particularly limited, and a temperature suitable for the characteristics of the temporary fixing film 5 can be selected.

  Next, as shown in FIG. 5G, the second insulating layer 2 is ground by an alkali treatment, and an opening to the semiconductor element 6 is provided in the second insulating layer 2. The alkali treatment liquid to be used is not particularly limited, and a desmear treatment liquid, a resist peeling liquid, or the like can be used. The pH can be adjusted according to the opening diameter. A desmear process can be implemented by immersing a to-be-processed board | substrate in liquid mixture, such as a sodium permanganate liquid, sodium hydroxide liquid, potassium permanganate liquid, chromium liquid, a sulfuric acid, for example. Specifically, after the substrate to be treated is swelled with hot water or a predetermined swelling liquid, residues, etc. are removed with sodium permanganate liquid, etc., and reduction (neutralization) is performed, followed by washing with water and washing with hot water. , Dry. If sufficient effects of roughening and residue removal are not obtained even if the treatment is performed once, the treatment may be performed a plurality of times. The desmear process is not limited to the above. Further, after the desmear treatment, the thermosetting resin composition may be thermally cured again. Although the effect of the second thermosetting is different depending on the thermosetting resin used, not only can the thermosetting be performed sufficiently to reduce unreacted substances and the glass transition temperature, but also lower the thermal expansion. Because you can.

  Next, as shown in FIG. 5H, a seed layer 7 is provided on the second insulating layer by electroless copper plating or the like. The thickness of the seed layer 7 is not particularly limited, but usually 0.1 to 1.0 μm is preferably used. The seed layer 7 can be formed by using a sputtering method in addition to the electroless copper plating method, and various formation layers can be selected, for example, Ti is deposited before copper is deposited.

Next, a circuit forming resist 8 is laminated on the seed layer 7, and a predetermined portion of the circuit forming resist 8 is exposed by irradiating actinic rays through a mask pattern, and the circuit forming resist 8 in the exposed portion is photocured. An exposure process to be performed, and a development process is performed on the unexposed part to form a rewiring resist pattern. A known light source can be used as the actinic ray light source. For example, a source that emits ultraviolet rays such as a carbon arc lamp, a mercury vapor arc lamp, an ultrahigh pressure mercury lamp, a high pressure mercury lamp, or a xenon lamp can be used. Further, direct drawing direct laser exposure may be used. The amount of exposure varies depending on the apparatus used and the composition of the resist 8 for circuit formation, but is preferably 10 to 600 mJ / cm ² , more preferably 20 to 400 mJ / cm ² . When the exposure amount is 10 to 600 mJ / cm ² , good photocuring is obtained, and the opening shape of the circuit forming resist 8 tends to be obtained stably. The circuit forming resist 8 can be either liquid or film. In the case of liquid, it can be applied using a printing machine. In the case of a film, it can be attached using a roll laminator or a vacuum laminator.

  Next, by removing the circuit forming resist 8 other than the exposed portion by development, a resist pattern is formed as shown in FIG. 5I (development process). As the developer used at this time, for example, an alkaline developer of a dilute solution of sodium carbonate (1 to 5% by mass aqueous solution) at 20 to 50 ° C. is used, and known spraying, rocking dipping, brushing, scraping and the like are known. Develop by the method of.

  Next, as shown in FIG. 6J, a copper wiring pattern 9 is formed on the seed layer 7 by electroplating. The wiring pattern 9 preferably has a thickness of 1 to 20 μm. Next, as shown in FIG. 6 (k), the circuit forming resist (resist pattern) 8 is peeled and removed by a peeling solution.

  Next, as shown in FIG. 6L, the seed layer 7 exposed on the surface of the first insulating layer 1 is removed by an etching solution.

  Next, as shown in FIG. 6 (m), a third insulating layer 10 made of a thermosetting resin composition is formed on the wiring pattern 9, and an alkali treatment is performed as shown in FIG. 7 (n). Thus, an opening reaching the wiring pattern 9 is formed. Although it does not specifically limit about the 3rd insulating layer 10 and its formation method, For example, the method similar to the 1st insulating layer 1 can be used. The alkali treatment is not particularly limited, and for example, the aforementioned alkali treatment technique can be used.

  Next, as shown in FIG. 7 (o), electroless nickel plating and gold plating 11 can be performed on the wiring pattern 9 exposed from the opening provided in the third insulating layer 10. Although the plating thickness is not particularly limited, for example, the nickel plating thickness is preferably 1 to 10 μm and the gold plating thickness is preferably about 0.1 μm.

  Next, as shown in FIG. 7 (p), a conductive material as the external connection terminal 12 is formed in the opening of the third insulating layer 10. The conductive material is not particularly limited, but it is preferable to use Sn-Ag or Sn-Ag-Cu solder from the viewpoint of environmental protection. Cu posts may be formed using a circuit forming resist.

  Next, by dicing into pieces using a dicer, the semiconductor device shown in FIG. 7 (q) can be obtained.

  The semiconductor device obtained by the method for manufacturing a semiconductor device of the present invention thus obtained is particularly suitable for a wafer level semiconductor device that is becoming smaller and thinner.

  Next, although the thermosetting resin composition used for the film for semiconductor device manufacture of this embodiment is demonstrated, this invention is not limited to these resin compositions.

  The thermosetting resin composition (I) and the thermosetting resin composition (II) include a thermosetting resin. The thermosetting resin is not particularly limited, but includes, for example, at least one selected from the group consisting of epoxy resins, thermosetting polyimide resins, cyanate resins, phenol resins, and polyamideimide resins. preferable.

  The epoxy resin is not particularly limited. For example, bisphenol S type epoxy such as bisphenol A type epoxy resin, bisphenol F type epoxy resin, novolac phenol type epoxy resin, biphenyl type epoxy resin, bisphenol S diglycidyl ether and the like. Resins, naphthalene type epoxy resins, dicyclopentadiene type epoxy resins, bixylenol type epoxy resins such as bixylenol diglycidyl ether, hydrogenated bisphenol A type epoxy resins such as hydrogenated bisphenol A glycidyl ether, and their dibasic acid modifications A diglycidyl ether type epoxy resin may be used. These may be used alone or in combination of two or more.

Examples of commercially available epoxy resins include DIC Corporation, trade name: EXA4700 (tetrafunctional naphthalene type epoxy resin), Nippon Kayaku Co., Ltd., trade name: NC-7000 (naphthalene skeleton-containing polyfunctional solid epoxy resin), and the like. Naphthalene type epoxy resin; Nippon Kayaku Co., Ltd., trade name: EPPN-502H (trisphenol epoxy resin ("EPPN" is a registered trademark)) and other condensates of aromatic aldehydes having phenolic hydroxyl groups Epoxidized product (trisphenol type epoxy resin); dicyclopentadiene such as DIC Corporation, trade name: EPICLON HP-7200H (dicyclopentadiene skeleton-containing polyfunctional solid epoxy resin ("EPICLON" is a registered trademark)) Aralkyl epoxy resin; manufactured by Nippon Kayaku Co., Ltd. Name: biphenyl aralkyl type epoxy resin such as NC-3000H (biphenyl skeleton-containing polyfunctional solid epoxy resin); manufactured by DIC Corporation, trade name: EPICLON N660, EPICLON N690, manufactured by Nippon Kayaku Co., Ltd., trade name: EOCN-104S ("EOCN" is a registered trademark) and other novolak-type epoxy resins; Nissan Chemical Industries, Ltd., trade name: TEPIC ("TEPIC" is a registered trademark) and other tris (2,3-epoxypropyl) isocyanates Nurate, manufactured by DIC Corporation, trade names: EPICLON 860, EPICLON 900-IM, EPICLON EXA-4816, EPICLON EXA-4822, manufactured by Asahi Kasei E-Materials Corporation, trade name: Araldite AER280 ("Araldite" is a registered trademark), Nissin Chemical Product name: Epototo YD-134 ("Epototo" is a registered trademark), Mitsubishi Chemical Corporation, product names: jER834, jER872 ("jER" is a registered trademark), Sumitomo Chemical Co., Ltd. Made by company, trade name: ELA-134 etc. bisphenol A type epoxy resin; made by DIC Corporation, trade name: EPICLON HP-4032 etc. naphthalene type epoxy resin; made by DIC Corporation, trade name: EPICLON N-740 etc. Examples thereof include phenol novolac type epoxy resins, epoxy resins of phenol and salicylaldehyde condensates; Nippon Kayaku Co., Ltd., trade name: EPPN-500 series. These epoxy resins may be used alone or in combination of two or more.
Among the above epoxy resins, biphenyl aralkyl type epoxy resins such as Nippon Kayaku Co., Ltd., trade name: NC-3000H (biphenyl skeleton-containing polyfunctional solid epoxy resin) are excellent in terms of excellent adhesion and insulation with copper. Moreover, it is more preferable to use Nippon Kayaku Co., Ltd. make and brand name: EPPN-500 series at the point from which a crosslinking density is high and high Tg is obtained.
The content of the epoxy resin is preferably 30 to 90 parts by mass and more preferably 40 to 80 parts by mass with respect to 100 parts by mass of the resin component excluding the inorganic filler component.

  As the curing agent combined with the epoxy resin, various conventionally known epoxy resin curing agents or epoxy resin curing accelerators can be blended. For example, phenol resins, imidazole compounds, acid anhydrides, aliphatic amines, alicyclic polyamines, aromatic polyamines, tertiary amines, dicyandiamide, guanidines, or epoxy adducts or microencapsulated products thereof, triphenyl Curing agents or accelerators such as phosphine, tetraphenylphosphonium, organophenyl compounds such as tetraphenylborate, organoboron compounds, DBU (1,8-diazabicyclo (4.5.0) undecene-7) or derivatives thereof Regardless of the above, known and commonly used ones can be used alone or in combination of two or more. Although it will not specifically limit if hardening of an epoxy resin is advanced, Specifically, 4, 4'- diamino diphenyl sulfone, 4, 4'-bis (4-aminophenoxy) biphenyl, 2, 2-bis [4- (4-Aminophenoxy) phenyl] propane, 1,3-bis (4-aminophenoxy) benzene, 1,4-bis (4-aminophenoxy) benzene, trimethylenebis (4-aminobenzoate), 3,3 ′ -Dimethyl-4,4'-diaminobiphenyl, 2,2'-dimethyl-4,4'-diaminobiphenyl, 4,4'-diaminodiphenyl ether, 3,4'-diaminodiphenyl ether, bis [4- (4-amino Phenoxy) phenyl] sulfone, bis [4- (3-aminophenoxy) phenyl] sulfone, 9,9′-bis (4-aminophenyl) sulfone Oren, 2,2-bis [4- (4-aminophenoxy) phenyl] hexafluoropropane can illustrate, may be used alone, or two or more.

  The thermosetting polyimide resin of the thermosetting resin composition used in the present embodiment preferably contains a maleimide compound having at least two unsaturated N-substituted maleimide groups in the molecular structure. Specifically, for example, N, N′-ethylene bismaleimide, N, N′-hexamethylene bismaleimide, N, N ′-(1,3-phenylene) bismaleimide, N, N ′-[1,3 -(2-methylphenylene)] bismaleimide, N, N '-[1,3- (4-methylphenylene)] bismaleimide, N, N'-(1,4-phenylene) bismaleimide, bis (4- Maleimidophenyl) methane, bis (3-methyl-4-maleimidophenyl) methane, 3,3-dimethyl-5,5-diethyl-4,4-diphenylmethane bismaleimide, bis (4-maleimidophenyl) ether, bis (4 -Maleimidophenyl) sulfone, bis (4-maleimidophenyl) sulfide, bis (4-maleimidophenyl) ketone, bis (4-maleimidocyclohexyl) ) Methane, 1,4-bis (4-maleimidophenyl) cyclohexane, 1,4-bis (maleimidomethyl) cyclohexane, 1,4-bis (maleimidomethyl) benzene, 1,3-bis (4-maleimidophenoxy) benzene 1,3-bis (3-maleimidophenoxy) benzene, bis [4- (3-maleimidophenoxy) phenyl] methane, bis [4- (4-maleimidophenoxy) phenyl] methane, 1,1-bis [4- (3-maleimidophenoxy) phenyl] ethane, 1,1-bis [4- (4-maleimidophenoxy) phenyl] ethane, 1,2-bis [4- (3-maleimidophenoxy) phenyl] ethane, 1,2- Bis [4- (4-maleimidophenoxy) phenyl] ethane, 2,2-bis [4- (3-maleimidophenoxy) ) Phenyl] propane, 2,2-bis [4- (4-maleimidophenoxy) phenyl] propane, 2,2-bis [4- (3-maleimidophenoxy) phenyl] butane, 2,2-bis [4- ( 4-maleimidophenoxy) phenyl] butane, 2,2-bis [4- (3-maleimidophenoxy) phenyl] -1,1,1,3,3,3-hexafluoropropane, 2,2-bis [4- (4-maleimidophenoxy) phenyl] -1,1,1,3,3,3-hexafluoropropane, 4,4-bis (3-maleimidophenoxy) biphenyl, 4,4-bis (4-maleimidophenoxy) biphenyl Bis [4- (3-maleimidophenoxy) phenyl] ketone, bis [4- (4-maleimidophenoxy) phenyl] ketone, 2,2′-bis (4-ma Imidophenyl) disulfide, bis (4-maleimidophenyl) disulfide, bis [4- (3-maleimidophenoxy) phenyl] sulfide, bis [4- (4-maleimidophenoxy) phenyl] sulfide, bis [4- (3-maleimide) Phenoxy) phenyl] sulfoxide, bis [4- (4-maleimidophenoxy) phenyl] sulfoxide, bis [4- (3-maleimidophenoxy) phenyl] sulfone, bis [4- (4-maleimidophenoxy) phenyl] sulfone, bis [ 4- (3-maleimidophenoxy) phenyl] ether, bis [4- (4-maleimidophenoxy) phenyl] ether, 1,4-bis [4- (4-maleimidophenoxy) -α, α-dimethylbenzyl] benzene, 1,3-bis [4- (4-maleimi Phenoxy) -α, α-dimethylbenzyl] benzene, 1,4-bis [4- (3-maleimidophenoxy) -α, α-dimethylbenzyl] benzene, 1,3-bis [4- (3-maleimidophenoxy) -Α, α-dimethylbenzyl] benzene, 1,4-bis [4- (4-maleimidophenoxy) -3,5-dimethyl-α, α-dimethylbenzyl] benzene, 1,3-bis [4- (4 -Maleimidophenoxy) -3,5-dimethyl-α, α-dimethylbenzyl] benzene, 1,4-bis [4- (3-maleimidophenoxy) -3,5-dimethyl-α, α-dimethylbenzyl] benzene, 1,3-bis [4- (3-maleimidophenoxy) -3,5-dimethyl-α, α-dimethylbenzyl] benzene, polyphenylmethanemaleimide, and these Reimido compounds may be used as a mixture of two or more may be used alone.

  The maleimide compound polymerization catalyst is not particularly limited as long as a known bismaleimide resin composition polymerization catalyst is used, but imidazoles, tertiary amines, quaternary ammonium salts, boron trifluoride amine complexes, Examples include ion catalysts such as organophosphines and organophosphonium salts, and radical polymerization initiators such as organic peroxides, hydroperoxides, and azoisobutyronitrile. Although the addition amount of a polymerization catalyst should just be determined according to the objective, it is desirable to set it as 0.01-3 mass% with respect to all the resin components from the surface of the stability of a bismaleimide resin composition.

The thermosetting resin composition (I) and the thermosetting resin composition (II) of the present embodiment preferably contain an inorganic filler.
The inorganic filler is not particularly limited. For example, barium sulfate, barium titanate, amorphous silica, crystalline silica, fused silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, Examples include extender pigments such as aluminum hydroxide, silicon nitride, and aluminum nitride, and metal powders such as copper, tin, zinc, nickel, silver, palladium, aluminum, iron, cobalt, gold, and platinum. These may be used alone or in combination of two or more.

  When a silica filler is used, it is also preferable to use a silane coupling agent in order to suppress aggregation and disperse in the resin. The silane coupling agent is not particularly limited. For example, alkyl silane, alkoxy silane, vinyl silane, epoxy silane, amino silane, acrylic silane, methacryl silane, mercapto silane, sulfide silane, isocyanate silane, sulfur silane, styryl silane. And alkylchlorosilane. These may be used alone or in combination of two or more.

  The thermosetting resin composition (I) preferably contains an inorganic filler having a maximum particle size of 20 μm or less and an average particle size of 5 μm or less. The inorganic material has a maximum particle size of 10 μm or less and an average particle size of 3 μm or less. More preferably, a filler is included.

The thermosetting resin composition (II) preferably contains an inorganic filler having a maximum particle size of 5 μm or less and an average particle size of 1 μm or less, and has a maximum particle size of 1 μm or less and an average particle size of 300 nm or less. More preferably, a filler is included.
The maximum particle size and the average particle size of the inorganic filler here are the dynamic light scattering nanotrack particle size distribution meter manufactured by Nikkiso Co., Ltd., trade name: UPA-EX150 (manufactured by Nikkiso Co., Ltd. (“Nanotrack” is , Registered trademark.)) Or a laser diffraction scattering type microtrack particle size distribution meter, trade name: MT-3100 (manufactured by Nikkiso Co., Ltd. ("Microtrack" is a registered trademark)).
The filling amount of the inorganic filler contained in the thermosetting resin composition (I) is preferably 30 to 95% by mass and more preferably 55 to 90% by mass with respect to the solid content of the resin. When the filling amount of the inorganic filler is 30% by mass or more, the warp of the semiconductor device tends to be small. When the filling amount of the inorganic filler is 95% by mass or less, moderate resin fluidity is obtained and the semiconductor element tends to be sealed.

  The filling amount of the inorganic filler contained in the thermosetting resin composition (II) is preferably 30% by mass or less, more preferably 10% by mass or less, based on the solid content of the resin. When the filling amount of the inorganic filler is 30% by mass or less, the inorganic filler does not easily fall out and the adhesion of the plating tends to be good.

  As mentioned above, although the manufacturing method of the semiconductor device which concerns on this invention, and embodiment of the thermosetting resin composition were described, this invention is not necessarily limited to embodiment mentioned above, It changes suitably in the range which does not deviate from the meaning. May be performed.

<Manufacture of thermosetting resin composition (I)>
The following thermosetting resin compositions A to C were prepared as the thermosetting resin composition (I) for forming the first insulating layer of the semiconductor device.

<Thermosetting resin composition A>
As the epoxy resin, 70 parts by mass of a biphenyl aralkyl type epoxy resin, trade name: NC-3000H (manufactured by Nippon Kayaku Co., Ltd.) was used.
Curing Agent Synthesis Example 1: Heat and coolable reaction vessel equipped with a thermometer, a stirrer, and a moisture quantifier with a reflux condenser, in a 2 liter reaction vessel, bis (4-aminophenyl) sulfone: 26.40 g, 2,2′-bis [4- (4-maleimidophenoxy) phenyl] propane: 484.50 g, p-aminobenzoic acid: 29.10 g, and dimethylacetamide: 360.00 g were added and reacted at 140 ° C. for 5 hours. Thus, a solution of a curing agent (A-1) having a sulfone group in the molecular main chain and having an acidic substituent and an unsaturated N-substituted maleimide group was obtained. 30 parts by mass of this curing agent was blended.

  As the inorganic filler component, silica filler having an average particle size of 50 nm and silane coupling treatment with vinylsilane was used. In addition, the inorganic filler component was blended so as to be 30% by mass with respect to the solid content of the resin. The dispersion state is a dynamic light scattering nanotrack particle size distribution analyzer, trade name: UPA-EX150 (manufactured by Nikkiso Co., Ltd.), and a laser diffraction scattering microtrack particle size distribution analyzer, trade name: MT-3100 (manufactured by Nikkiso Co., Ltd.). ) To confirm that the maximum particle size is 1 μm or less.

<Thermosetting resin composition B>
As the epoxy resin, 70 parts by mass of a biphenyl aralkyl type epoxy resin, trade name: NC-3000H (manufactured by Nippon Kayaku Co., Ltd.) was used.
Curing Agent Synthesis Example 2: Wandamine HM (WHM) [(4,4′-diamino) dicyclohexylmethane, manufactured by Shin Nippon Chemical Co., Ltd., trade name (“Wandamine” is a registered trademark)] as a diamine compound] 52.7 g 3 g of 3,3′-dihydroxy-4,4′-diaminobiphenyl as a diamine having a reactive functional group, 108 g of trimellitic anhydride (TMA) as a tricarboxylic acid anhydride, and N-methyl-2 as an aprotic polar solvent -Pyrrolidone (NMP) 1281g was put, the temperature in a flask was set to 80 degreeC, and it stirred for 30 minutes. After completion of the stirring, 192 g of toluene was further added as an aromatic hydrocarbon azeotropic with water, and the temperature in the flask was raised to 160 ° C. and refluxed for 2.5 hours. After confirming that the theoretical amount of water was stored in the moisture determination receiver and that no water distilling was observed, the temperature in the flask was adjusted to 180 ° C. while removing water and toluene in the moisture determination receiver. And toluene in the reaction solution was removed. After cooling the solution in the flask to 60 ° C., hydrogenated α, ω-polybutadiene dicarboxylic acid (trade name: CI, manufactured by Nippon Soda Co., Ltd.) as a dicarboxylic acid having a long-chain hydrocarbon chain skeleton (about 50 carbon atoms). -1000) 309.5 g was added and stirred for 10 minutes. After the completion of stirring, 119.7 g of 4,4′-diphenylmethane diisocyanate (MDI) was added as a diisocyanate, and the temperature in the flask was raised to 160 ° C. for 2 hours to obtain a resin solution. It was 47000 when the weight average molecular weight (Mw) of this polyamideimide resin solution was measured by the gel permeation chromatography. The average reactive functional group number N per polyamideimide molecule was 4.4. 30 parts by mass of this curing agent was blended. As an inorganic filler component, the same thing as the thermosetting resin composition A was used.

<Manufacture of film for manufacturing semiconductor devices>
A varnish of the thermosetting resin composition (II) was prepared as shown below.

  After blending 13.5 g of N, N-dimethylacetamide (DMAc) with 1.5 g of phenolic hydroxyl group-containing polybutadiene-modified polyamide (Nippon Kayaku Co., Ltd., trade name: BPAM-155), biphenylaralkyl epoxy resin ( Nippon Kayaku Co., Ltd., trade name: NC-3000H) 10 g, Novolac type phenolic resin (DIC Corporation, trade name: TD-2090) 3.6 g, 2-phenylimidazole (Shikoku Chemicals Co., Ltd.) as a curing accelerator 0.1 g of company-made product name: 2PZ was diluted with a mixed solvent consisting of DMAc and methyl ethyl ketone after adding 0.9 g of fumed silica (manufactured by Nippon Aerosil Co., Ltd., product name: R972) (solid content concentration) About 25% by weight). Thereafter, a resin varnish of the thermosetting resin composition (II) was obtained using a disperser (trade name: Nanomizer (“Nanomizer” is a registered trademark)) manufactured by Yoshida Kikai Kogyo Co., Ltd.).

The resin varnish of the obtained thermosetting resin composition (II) was applied onto a polyethylene terephthalate film (trade name: G2-16, manufactured by Teijin Limited) having a thickness of 16 μm as the support 3, and then hot air convection The thermosetting resin composition layer 2 was obtained on the support 3 by drying at 180 ° C. for about 10 minutes using a type dryer.
Next, the varnish of the thermosetting resin composition A or B is applied onto the thermosetting resin composition layer 2 provided on the support 3 by using a bar coater, and dried at 100 ° C. for 10 minutes, and the semiconductor An apparatus manufacturing film was obtained (see FIG. 4A). At this time, the thermosetting resin composition A or B was applied so that the thermosetting resin composition layer 1, the thermosetting resin composition layer 2, and the support 3 were provided in this order. Moreover, the film thickness of the thermosetting resin composition layer 1 prepared 60-410 micrometers.

  Next, a polyethylene film (manufactured by Tamapoly Co., Ltd., trade name: NF-15) is provided on the surface opposite to the side in contact with the support 3 so that dust or the like does not adhere to the film for manufacturing a semiconductor device. As pasted together.

<Preparation of support plate with temporary fixing film>
First, a SUS plate having a diameter of 220 mm and a thickness of 1.5 mm was prepared as the support plate 4. Next, the temporary fixing film 5 was attached to one side of the SUS plate using a laminator (see FIG. 4B).

  The temporary fixing film 5 protruding from the SUS plate was cut off with a cutter knife.

<Arrangement of semiconductor elements>
Next, as shown in FIG. 4C, a semiconductor element 6 (product name: CC80-0101JY, manufactured by Waltz Co., Ltd.) of 7.3 mm × 7.3 mm is temporarily fixed to the passive surface (back surface) of the semiconductor element 6. The film 5 was arranged in a lattice shape so that the films 5 were stuck together. The number of mounted semiconductor elements 6 was 193, and the pitch was 9.6 mm in both the vertical and horizontal directions. A die sorter (manufactured by Canon Machinery Inc., trade name: CAP3500) was used for the arrangement of the semiconductor elements 6. The load at the time of arrangement was 1 kgf per semiconductor element.

  The protective film of the obtained film for manufacturing a semiconductor device was peeled off and placed so that the active surface (surface) of the semiconductor element 6 and the thermosetting resin composition layer 1 were in contact with each other. A press-type vacuum laminator (manufactured by Meiki Seisakusho Co., Ltd., trade name: MVLP-500 ("MVLP" is a registered trademark)) is used on the active surface (front surface) of the semiconductor element 6 and between the plurality of semiconductor elements 6 In addition, the thermosetting resin composition layer 1 serving as the first insulating layer was filled, and a second insulating layer capable of forming a wiring was formed on the active surface (front surface) of the semiconductor element 6. The pressing conditions were a hot plate temperature of 50 to 80 ° C., a vacuuming time of 20 seconds, a laminating press time of 5 to 30 seconds, an atmospheric pressure of 4 kPa or less, and a pressing pressure of 0.1 to 0.4 MPa. Next, heat curing was performed in a clean oven at 120 to 170 ° C. for 30 minutes to 1 hour.

  Table 1 shows the specifications of the semiconductor devices in the examples and the sealing conditions at the time of manufacture.

  Thereafter, as shown in FIGS. 5E and 5F, the support plate 4 and the temporary fixing film 5 were peeled off on a 200 ° C. hot plate. Next, as shown in FIG. 5G, desmear treatment was performed under the conditions shown in Table 2, the insulating layer was ground, and an opening reaching the semiconductor element 6 was provided in the second insulating layer 2. Then, as shown in FIG.5 (h), the seed layer 7 with a thickness of 1 micrometer was formed on the 2nd insulating layer 2 which consists of a thermosetting resin composition by the electroless copper plating method.

Next, as shown in FIG. 5 (i), circuit forming resist 8 (manufactured by Hitachi Chemical Co., Ltd., trade name: Phototec RY-3525) is stuck on the thermosetting resin composition layer 2 with a roll laminator, The photo tool which formed the pattern was closely_contact | adhered, and exposure was performed by the energy amount of 100 mJ / cm < ² > using the Oak Manufacturing Co., Ltd. brand name: EXM-1201 type | mold exposure machine. Subsequently, spray development was performed for 90 seconds with a 1 mass% sodium carbonate aqueous solution at 30 ° C. to form a resist pattern for circuit formation. Next, as shown in FIG. 6J, a copper wiring pattern 9 having a thickness of 5 μm was formed on the seed layer 7 by electroplating. Next, as shown in FIG. 6 (k), after the circuit forming resist 8 is peeled off by a peeling solution, the seed layer 7 exposed on the surface of the second insulating layer 2 is peeled off as shown in FIG. 6 (l). Was removed with an etching solution.

  Next, a third insulating layer 10 is formed on the wiring pattern 9 and the second insulating layer 2 (see FIG. 6 (m)), and the desmear treatment shown in Table 2 is performed. An opening reaching the pattern 9 was provided (see FIG. 7 (n)). As the thermosetting resin composition of the third insulating layer, the same thermosetting resin composition as that of the first insulating layer was used, and the thickness was 20 μm. Thereafter, using a commercially available electroless nickel / gold plating solution, a plating process was performed on the wiring pattern so that the nickel plating thickness was 3 μm and the gold plating thickness was 0.1 μm (see FIG. 7 (o)). Next, an Sn—Ag—Cu based solder ball to be the external connection terminal 12 was mounted on the electroless nickel / gold plating 11 by reflow mounting (see FIG. 7 (p)). Next, the semiconductor device was diced into pieces of 9.3 mm × 9.3 mm by dicing (blade width 0.3 mm) to obtain a semiconductor device shown in FIG. 7 (q).

About the curvature of the molding after forming the 1st and 2nd insulating layers and performing predetermined thermosetting, the range of diameter 200mm is measured under room temperature (25 degreeC), and it evaluates based on the following references | standards did.
○: Warpage amount is less than 1 mm.
Δ: Warpage amount is 1 mm or more and less than 2 mm.
X: Warpage amount is 2 mm or more.

The embedding property of the thermosetting resin composition after forming the first and second insulating layers and performing predetermined thermosetting was visually confirmed and evaluated based on the following criteria.
○: The resin is sufficiently embedded between the semiconductor elements, and there is no unfilled portion.
X: The thing with an unfilled part between semiconductor elements.

For the smoothness of the thermosetting resin composition on the active surface (surface) side of the semiconductor element after the first and second insulating layers are formed and subjected to predetermined thermosetting, a surface roughness meter is used. The level difference of the active surface of the semiconductor element was measured and evaluated based on the following criteria.
○: The level difference on the surface of the thermosetting resin composition is less than 2 μm.
(Triangle | delta): The level | step difference of the surface of a thermosetting resin composition is 2 micrometers or more and less than 5 micrometers.
X: The level | step difference of the surface of a thermosetting resin composition is 5 micrometers or more.

About the wall surface smoothness of the opening part of a 2nd insulating layer, it observed with the electron microscope and evaluated based on the following references | standards.
○: The wall surface is smooth.
X: A step on the wall surface.

  These measurements and observation results are summarized in Table 3. This process is not limited to a wafer level semiconductor device, but can be applied to all semiconductor devices and component-embedded substrates that need to be reduced in size and thickness, such as a package-on-package rewiring process.

  As is apparent from Tables 1 and 3, in the example of the present invention, a semiconductor device having an insulating layer with good warpage, embedding property, smoothness, opening property, and smoothness can be obtained. According to the film for manufacturing a semiconductor device of the present invention and the method for manufacturing a semiconductor device using the film, it is possible to efficiently provide a wafer level semiconductor device that can be thinned, has a small warpage, and is excellent in heat dissipation at low cost. Can do.

1 First thermosetting resin composition layer (insulating layer)
2 Second thermosetting resin composition layer (insulating layer)
3 Support 4 Support Plate 5 Temporary Fixing Film 6 Semiconductor Element 7 Seed Layer 8 Circuit Forming Resist (Resist Pattern)
9 Wiring pattern 10 Third thermosetting resin composition (insulating layer)
11 Electroless nickel / gold plating 12 External connection terminal

Claims (8)

  The film for semiconductor device manufacture which has the thermosetting resin composition layer 1 which can seal a semiconductor element, and the thermosetting resin composition layer 2 which can form wiring.   The film for manufacturing a semiconductor device according to claim 1, further comprising a support, wherein the thermosetting resin composition layer 1, the thermosetting resin composition layer 2, and the support are provided in this order.   Furthermore, the thermosetting resin composition layer 1 and the thermosetting resin composition layer 2 contain an inorganic filler, and the filling amount of the inorganic filler contained in the thermosetting resin composition layer 1 is based on the solid content of the resin. The film for manufacturing a semiconductor device according to claim 1, wherein the film is 30 to 95% by mass and the filling amount of the inorganic filler contained in the thermosetting resin composition layer 2 is 30% by mass or less.   The maximum particle size of the inorganic filler contained in the thermosetting resin composition layer 1 is 20 μm or less, the average particle size is 5 μm or less, and the maximum particle size of the inorganic filler contained in the thermosetting resin composition layer 2 is The film for manufacturing a semiconductor device according to claim 3, wherein the film is 5 μm or less and the average particle size is 1 μm or less.   The semiconductor device which uses the film for semiconductor device manufacture as described in any one of Claims 1-4. (A) after forming the temporary fixing layer on the support plate, placing at least one semiconductor element so that the passive surface (back surface) of the semiconductor element and the temporary fixing layer are bonded together;
(B) sealing with the film for manufacturing a semiconductor device according to any one of claims 1 to 4 so as to cover an active surface (front surface) of at least one semiconductor element;
(C) peeling the support plate and the temporary fixing layer to expose the passive surface (back surface) of the semiconductor element;
(D) grinding the second insulating layer on the active surface (front surface) of the semiconductor element to form an opening reaching the active surface (front surface) of the semiconductor element;
(E) forming a seed layer on the insulating layer;
(F) forming a resist for circuit formation on the seed layer, and performing an exposure process and a development process to form a resist pattern for rewiring;
(G) forming a wiring pattern by an electroplating method, and removing the resist pattern by a peeling process;
(H) removing the seed layer;
(I) forming a third insulating layer on the wiring pattern and forming an opening reaching the wiring pattern;
(J) A method for manufacturing a semiconductor device comprising a step of forming an external connection terminal.   The method for manufacturing a semiconductor device according to claim 6, wherein the sealing temperature of the film for manufacturing a semiconductor device in the step (B) is 50 to 140 ° C. and the heating time is in the range of 10 to 300 seconds.   The method for manufacturing a semiconductor device according to claim 6, wherein the sealing pressure of the film for manufacturing a semiconductor device in the step (B) is 0.2 to 2.0 MPa.

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