JP2015079849A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP2015079849A
JP2015079849A JP2013216007A JP2013216007A JP2015079849A JP 2015079849 A JP2015079849 A JP 2015079849A JP 2013216007 A JP2013216007 A JP 2013216007A JP 2013216007 A JP2013216007 A JP 2013216007A JP 2015079849 A JP2015079849 A JP 2015079849A
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insulating film
mask insulating
semiconductor device
boron
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光泰 掛布
Mitsuyasu Kakefu
光泰 掛布
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can inhibit auto-doping or diffusion of boron in a mask oxide film to inside a semiconductor substrate and reduce deterioration in reverse withstand voltage performance and gate failure.SOLUTION: A manufacturing method of forming on a predetermined position of a surface of an n-type semiconductor substrate 20, a semiconductor device having a p-type isolation region 6 which contacts the semiconductor substrate from the surface to reach a p-type semiconductor layer on a rear face opposite to the substrate surface comprises: a first step of forming a mask insulation film 21 having a required film thickness on the surface of the n-type substrate 20 and an opening 22 in the mask insulation film 21; a second step of ion implanting a p-type impurity from the surface; a third step of removing a p-type impurity implantation layer 21a in the mask insulation film 21 caused by the ion implantation; and a fourth step of diffusing the ion implantation layer 22b formed in the opening 22 to a depth which reaches the p-type semiconductor layer on the rear face by a heat treatment to form the p-type isolation region 6.

Description

本発明は、高温長時間拡散を伴う深い不純物拡散層の形成工程を有する半導体装置の製造方法およびその半導体装置に関する。特には、電力変換装置などに用いられる逆阻止ＩＧＢＴに関する。ＩＧＢＴは絶縁ゲート型バイポーラトランジスタの略称である。   The present invention relates to a method of manufacturing a semiconductor device having a step of forming a deep impurity diffusion layer accompanied by high-temperature and long-time diffusion, and the semiconductor device. In particular, the present invention relates to a reverse blocking IGBT used in a power converter or the like. IGBT is an abbreviation for an insulated gate bipolar transistor.

逆阻止ＩＧＢＴ１００は、通常のＩＧＢＴと同様に、図２の要部断面図に示すようにｎ型半導体基板１の中央部分に配置される活性領域１４中の表面にゲート酸化膜１３ｂを介して形成されるゲート電極１３ａからなる積層構造のＭＯＳ構造１３を備える。その半導体基板１の反対側の裏面には、ｐ型コレクタ層１６を介してコレクタ電極１７を有する。前記活性領域１４の外周には接合終端領域９が取り巻き、さらにその外周を取り巻くとともに、特に半導体基板１の両面間に跨る拡散領域からなるｐ型分離領域６を有する構造が逆阻止ＩＧＢＴの特徴である。このｐ型分離領域６をｐ型コレクタ層１６に接続させることにより、ｐ型コレクタ層１６の接合終端を表面側の接合終端領域９表面に露出させ絶縁膜で保護することができるので、ＩＧＢＴの逆耐圧が安定し、その耐圧信頼性を高めることができる。半導体基板の厚さは耐圧クラスが６００Ｖ〜１２００Ｖの場合、耐圧に対応して、それぞれ５０〜２００μｍ程度にされることが好ましい。   The reverse blocking IGBT 100 is formed on the surface in the active region 14 disposed in the central portion of the n-type semiconductor substrate 1 through the gate oxide film 13b as shown in the cross-sectional view of the main part in the same manner as the normal IGBT. A MOS structure 13 having a laminated structure composed of the gate electrode 13a is provided. On the reverse side of the semiconductor substrate 1, a collector electrode 17 is provided via a p-type collector layer 16. The junction termination region 9 surrounds the outer periphery of the active region 14, further surrounds the outer periphery thereof, and in particular, a structure having a p-type isolation region 6 composed of a diffusion region straddling both surfaces of the semiconductor substrate 1 is a feature of the reverse blocking IGBT. is there. By connecting the p-type isolation region 6 to the p-type collector layer 16, the junction termination of the p-type collector layer 16 can be exposed to the surface of the junction termination region 9 on the surface side and protected by an insulating film. The reverse breakdown voltage is stabilized, and the breakdown voltage reliability can be increased. When the withstand voltage class is 600V to 1200V, the thickness of the semiconductor substrate is preferably about 50 to 200 μm corresponding to the withstand voltage.

半導体基板に選択的に不純物をイオン注入した後、この不純物を熱拡散により深い不純物拡散層（分離領域）を形成する熱処理工程に先立ち、マスクとなる絶縁膜にイオン注入された不純物の外方拡散を防止するため、マスク絶縁膜やフィールド酸化膜を除去する技術が開示されている。また、マスク絶縁膜とフィールド酸化膜を除去した後、新たな酸化膜を形成することで、不純物のオートドーピングを防止する製造方法についても開示されている（特許文献１）。   After selectively ion-implanting impurities into the semiconductor substrate, prior to the heat treatment step of forming a deep impurity diffusion layer (isolation region) by thermal diffusion, the impurities are diffused outwardly into the insulating film serving as a mask. In order to prevent this, a technique for removing the mask insulating film and the field oxide film is disclosed. Also disclosed is a manufacturing method that prevents autodoping of impurities by forming a new oxide film after removing the mask insulating film and the field oxide film (Patent Document 1).

不純物のイオン注入後に、マスクとして用いたシリコン酸化膜からリンやボロンの原子濃度が高い注入層だけを除去した後、熱拡散を行うプロセスが開示されている（特許文献２）。   After impurity ion implantation, a process is disclosed in which only an implanted layer having a high atomic concentration of phosphorus or boron is removed from a silicon oxide film used as a mask, and then thermal diffusion is performed (Patent Document 2).

特開平５−６２９２２号公報（要約、請求項２）JP-A-5-62922 (summary, claim 2) 特開昭５７−１０２６２号公報（５ページの１〜５行目）JP-A-57-10262 (1st to 5th lines on page 5)

従来のｐ型分離領域の形成方法を図７の（ａ）〜（ｅ）に示す。厚さ５００μｍ前後で、不純物濃度３×１０13〜１．５×１０14ｃｍ-3のｎ型ＦＺ（Ｆｌｏａｔｉｎｇ Ｚｏｎｅ）半導体基板２０を用いる。このｎ型半導体基板２０の表面に厚さに０．８〜１．６μｍの初期酸化膜２１を形成した（ａ）後、後工程で半導体基板２０に形成される活性領域と接合終端領域の外周に位置する部分の初期酸化膜２１に選択的にエッチングして開口部２２を形成する（ｂ）。この初期酸化膜２１の開口部２２から半導体基板２０中にドーズ量５×１０15ｃｍ-2のボロンを矢印２２ａのようにイオン注入してイオン注入層２２ｂを形成する（ｃ）。開口部２２以外の初期酸化膜２１は、半導体基板２０へのボロンの注入を防ぐマスクとして機能するように、イオン注入の際にほとんどのボロンが突き抜けることなく酸化膜内に留まる厚さにされる必要がある。以降、初期酸化膜をマスク絶縁膜２１とも称する。 A conventional method for forming a p-type isolation region is shown in FIGS. An n-type FZ (Floating Zone) semiconductor substrate 20 having a thickness of about 500 μm and an impurity concentration of 3 × 10 13 to 1.5 × 10 14 cm −3 is used. After the initial oxide film 21 having a thickness of 0.8 to 1.6 μm is formed on the surface of the n-type semiconductor substrate 20 (a), the outer periphery of the active region and the junction termination region formed in the semiconductor substrate 20 in a later process The opening 22 is formed by selectively etching the initial oxide film 21 located at the position (b). An ion implantation layer 22b is formed by ion-implanting boron having a dose amount of 5 × 10 15 cm −2 into the semiconductor substrate 20 from the opening 22 of the initial oxide film 21 as indicated by an arrow 22a (c). The initial oxide film 21 other than the opening 22 has a thickness that allows most of boron to remain in the oxide film without being penetrated during ion implantation so as to function as a mask that prevents boron implantation into the semiconductor substrate 20. There is a need. Hereinafter, the initial oxide film is also referred to as a mask insulating film 21.

その後、ボロンが含まれるマスク絶縁膜２１を完全に除去するかまたは完全に残した状態で、１３００℃の酸素雰囲気中で、イオン注入層２２ｂ内のボロンを深さ５０〜２００μｍまで熱拡散させてｐ型分離領域６を形成する（ｄ）。図７の（ｄ）では酸化膜２１を完全に残した状態でｐ型分離領域６を形成する場合を示している。ｐ型分離領域６の拡散深さを５０μｍとするためには１３００℃で１００時間、拡散深さを２００μｍとするためには１３００度で３００時間程度の高温長時間の熱処理を行う必要がある。ｐ型分離領域６の形成後、マスク絶縁膜２１を全面除去する（ｅ）。   Thereafter, the boron in the ion implantation layer 22b is thermally diffused to a depth of 50 to 200 μm in an oxygen atmosphere at 1300 ° C. with the mask insulating film 21 containing boron completely removed or left completely. A p-type isolation region 6 is formed (d). FIG. 7D shows the case where the p-type isolation region 6 is formed with the oxide film 21 completely left. In order to set the diffusion depth of the p-type isolation region 6 to 50 μm, it is necessary to perform heat treatment at 1300 ° C. for 100 hours, and in order to set the diffusion depth to 200 μm, heat treatment at a high temperature for about 300 hours at 1300 ° C. After the formation of the p-type isolation region 6, the mask insulating film 21 is entirely removed (e).

しかしながら、前述の図７（ｄ）で説明したｐ型分離領域６の形成のためにする高温長時間の熱拡散処理前のプロセスが、（ｄ）と異なりマスク絶縁膜２１を完全に除去するプロセスの場合、イオン注入層２２ｂ中のボロンが高温長時間の熱拡散処理中に基板表面から飛び出して外方拡散し、再び基板内に再拡散する現象が起きる。この現象をオートドーピングという。このオートドーピングにより半導体基板の望まれない表面にボロンが導入される領域が形成される。この結果、オートドーピングがプロセス中に起きることがある製造方法で作製された逆阻止ＩＧＢＴでは、その順耐圧が上昇して逆耐圧が低下し、さらに逆漏れ電流が増加する問題の発生することがある。そこで、従来、実際には、低下耐圧を想定して、予め、その分シリコン基板の比抵抗を高くし基板も厚くしておくことにより低下耐圧を補う方策が採られた。ところが、基板を厚くすることはデバイスのオン電圧を増大させ、オン電圧とターンオフ損失のトレードオフ関係を悪化させる問題が避けられない。   However, unlike the process (d), the process before the thermal diffusion process for a long period of time for forming the p-type isolation region 6 described with reference to FIG. 7 (d) is a process for completely removing the mask insulating film 21. In this case, a phenomenon occurs in which boron in the ion-implanted layer 22b jumps out of the substrate surface during the high-temperature and long-time thermal diffusion process, diffuses outward, and re-diffuses into the substrate again. This phenomenon is called autodoping. By this auto doping, a region where boron is introduced is formed on an undesired surface of the semiconductor substrate. As a result, in a reverse blocking IGBT manufactured by a manufacturing method in which auto-doping may occur during the process, the forward breakdown voltage increases, the reverse breakdown voltage decreases, and the reverse leakage current increases. is there. Therefore, in the past, in practice, a measure was taken to compensate for the reduced withstand voltage by increasing the specific resistance of the silicon substrate and increasing the thickness of the silicon substrate in advance by assuming a reduced withstand voltage. However, increasing the thickness of the substrate inevitably increases the on-voltage of the device and inevitably deteriorates the trade-off relationship between the on-voltage and the turn-off loss.

一方、高温長時間の熱拡散処理を行う前に、マスク絶縁膜を完全に残すプロセスでは、高温長時間の熱拡散処に伴って半導体基板内に導入される高濃度酸素の外方拡散がマスク絶縁膜により抑制される。その結果、半導体基板の表面が高酸素濃度となり、結晶欠陥を伴う酸素析出物が発生し、面あれという状態が生じる。この面あれのある半導体基板表面に形成されるゲート酸化膜には、欠陥が多く取り込まれるので、ゲート不良の原因となり易くゲート不良が増加することが問題となる。この問題は前述のマスク絶縁膜を完全に除去した後に高温長時間拡散を行うプロセスでは生じない。さらに完全にマスク絶縁膜を残すプロセスの場合、酸化膜中にイオン注入されたボロンが高温で長時間の熱拡散処理によって酸化膜を突き抜けて半導体基板中に拡散する現象も問題となる。   On the other hand, in the process of leaving the mask insulation film completely before performing the high-temperature and long-time thermal diffusion treatment, the outward diffusion of high-concentration oxygen introduced into the semiconductor substrate along with the high-temperature and long-time thermal diffusion treatment is masked. Suppressed by the insulating film. As a result, the surface of the semiconductor substrate has a high oxygen concentration, oxygen precipitates accompanied by crystal defects are generated, and a state of surface roughness occurs. Since many defects are taken in the gate oxide film formed on the surface of the semiconductor substrate having the rough surface, there is a problem that gate defects are liable to cause gate defects and increase. This problem does not occur in a process in which diffusion is performed at a high temperature for a long time after the mask insulating film is completely removed. Further, in the process of completely leaving the mask insulating film, the phenomenon that boron ion-implanted into the oxide film penetrates the oxide film and diffuses into the semiconductor substrate at a high temperature for a long time by thermal diffusion treatment becomes a problem.

本発明は、以上説明した問題点を解消するためになされたものである。すなわち、本発明の目的は、オートドーピングを抑制し、またはマスク絶縁膜中のボロンが半導体基板内に拡散することを抑え、逆耐圧の低下およびゲート不良を少なくすることができる半導体装置の製造方法およびその半導体装置を提供することである。   The present invention has been made to solve the problems described above. That is, an object of the present invention is to provide a semiconductor device manufacturing method capable of suppressing autodoping or suppressing boron in a mask insulating film from diffusing into a semiconductor substrate and reducing reverse breakdown voltage and gate defects. And a semiconductor device thereof.

本発明は、前記課題を解決するために、第１導電型半導体基板の一方の主面にＭＯＳゲート構造を含む活性領域と該領域を取り巻く接合終端領域、他方の主面には第２導電型半導体層をそれぞれ有し、前記活性領域と前記接合終端領域とを取り巻く位置に、一方の主面から対向する他方の主面の前記第２導電型半導体層に至り接触する第２導電型分離領域を有する半導体装置を形成するための製造方法が、前記第１導電型半導体基板の一方の主面に所要の膜厚を有するマスク絶縁膜と該マスク絶縁膜の前記位置に前記第２導電型分離領域形成用の開口部とを形成する第１工程と、前記一方の主面から、所要のドーズ量と加速エネルギーにより、第２導電型不純物をイオン注入する第２工程と、該イオン注入により前記マスク絶縁膜中に形成された第２導電型不純物注入層を除去して前記マスク絶縁膜を薄化する第３工程と、前記開口部からイオン注入された第２導電型不純物を前記他方の主面の第２導電型半導体層部分に達する深さまで熱処理により拡散させて前記第２導電型分離領域を形成する第４工程とを有する半導体装置の製造方法とする。   In order to solve the above problems, the present invention provides an active region including a MOS gate structure on one main surface of a first conductivity type semiconductor substrate, a junction termination region surrounding the region, and a second conductivity type on the other main surface. A second conductivity type isolation region having a semiconductor layer and in contact with the second conductivity type semiconductor layer on the other main surface opposite to the main surface at a position surrounding the active region and the junction termination region A manufacturing method for forming a semiconductor device comprising: a mask insulating film having a required film thickness on one main surface of the first conductive type semiconductor substrate; and the second conductive type separation at the position of the mask insulating film. A first step of forming an opening for forming a region; a second step of ion-implanting a second conductivity type impurity from the one main surface with a required dose and acceleration energy; and Formed in mask insulation film A third step of thinning the mask insulating film by removing the second conductivity type impurity implantation layer; and a second conductivity type semiconductor on the other main surface by ion implantation of the second conductivity type impurity from the opening. And a fourth step of forming the second conductivity type isolation region by diffusion to a depth reaching the layer portion by heat treatment.

前記第３工程で薄化されるマスク絶縁膜の残膜厚さが０．３μｍ以上０．４μｍ以下であることが好ましい。また、前記第３工程において、前記マスク絶縁膜のうち、該マスク絶縁膜中にイオン注入される第２導電型不純物の飛程とその標準偏差の６倍との和以上の膜厚を除去することが好ましい。   The residual film thickness of the mask insulating film thinned in the third step is preferably 0.3 μm or more and 0.4 μm or less. Further, in the third step, the film thickness of the mask insulating film that is equal to or larger than the sum of the range of the second conductivity type impurity ion-implanted into the mask insulating film and 6 times its standard deviation is removed. It is preferable.

前記第４工程で形成される前記第２導電型分離領域の、前記開口部からの深さが５０μｍ〜２００μｍであることが好適である。
前記製造方法により製造される半導体装置が逆阻止ＩＧＢＴであることが望ましい。 It is preferable that the second conductivity type separation region formed in the fourth step has a depth of 50 μm to 200 μm from the opening.
It is desirable that the semiconductor device manufactured by the manufacturing method is a reverse blocking IGBT.

本発明によれば、オートドーピングを抑制し、またはマスク絶縁膜中のボロンが半導体基板内に拡散することを抑え、逆耐圧の低下およびゲート不良を少なくすることができる半導体装置の製造方法およびその半導体装置を提供することができる。   According to the present invention, a method of manufacturing a semiconductor device capable of suppressing auto-doping or suppressing boron in a mask insulating film from diffusing into a semiconductor substrate and reducing a decrease in reverse breakdown voltage and gate defects, and the method thereof A semiconductor device can be provided.

本発明の実施例１にかかるｐ型分離領域の形成工程を示す半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate which shows the formation process of the p-type isolation | separation area | region concerning Example 1 of this invention. 逆阻止ＩＧＢＴの要部断面図である。It is principal part sectional drawing of reverse blocking IGBT. 分離領域形成後の半導体基板表面内でドーピングしていない部分の深さ方向のボロン濃度分布図である。（ａ）は従来のマスク絶縁膜をすべて除去した場合、（ｂ）は本発明を用いた場合である。It is a boron concentration distribution diagram of the depth direction of the part which is not doped in the semiconductor substrate surface after isolation region formation. (A) shows the case where the conventional mask insulating film is completely removed, and (b) shows the case where the present invention is used. 逆耐圧とボロン層がエッチングで除去されたマスク絶縁膜膜厚との間の関係図である。FIG. 5 is a relationship diagram between a reverse breakdown voltage and a film thickness of a mask insulating film from which a boron layer is removed by etching. 順耐圧とボロン層がエッチングで除去されたマスク絶縁膜膜厚との間の関係図である。FIG. 6 is a relationship diagram between a forward breakdown voltage and a thickness of a mask insulating film from which a boron layer is removed by etching. ゲート不良とエッチングで除去されたマスク絶縁膜膜厚との間の関係図である。It is a relationship figure between the gate defect and the mask insulating film thickness removed by the etching. 従来のｐ型分離領域の形成工程を示す半導体基板の要部断面図である。It is principal part sectional drawing of the semiconductor substrate which shows the formation process of the conventional p-type isolation region.

以下、本発明の半導体装置の製造方法にかかる実施例について、図面を参照して詳細に説明する。本明細書および添付図面においては、ｎまたはｐを冠記した層や領域では、それぞれ電子または正孔が多数キャリアであることを意味する。また、ｎやｐに付す＋および−は、それぞれ相対的に不純物濃度が高いまたは低いことを意味する。なお、以下の実施例の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。また、実施例で説明される添付図面は、見易くまたは理解し易くするために正確なスケール、寸法比で描かれていない。本発明はその要旨を超えない限り、以下に説明する実施例の記載に限定されるものではない。   Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is relatively high or low, respectively. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. In addition, the accompanying drawings described in the embodiments are not drawn to an accurate scale and dimensional ratio for easy understanding and understanding. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

本発明の実施例１にかかるｐ型分離領域６の形成方法を図１の（ａ）〜（ｅ）に示す。厚さ５００μｍ前後で、不純物濃度が３×１０13〜１．５×１０14ｃｍ-3のｎ型ＦＺ半導体基板２０を用いる。このｎ型半導体基板２０の表面に厚さに０．８〜１．６μｍの初期酸化膜２１を形成した（ａ）後、後工程で半導体基板２０に形成される活性領域と接合終端領域の外周に位置する部分の初期酸化膜２１に開口部２２を選択的エッチングで形成する（ｂ）。（ｂ）以降の初期酸化膜をマスク絶縁膜２１とも称する。このマスク絶縁膜２１の開口部２２から半導体基板２０中にドーズ量５×１０15ｃｍ-2のボロンを矢印２２ａで示すようにイオン注入してイオン注入層２２ｂを形成する（ｃ）。 A method for forming the p-type isolation region 6 according to Example 1 of the present invention is shown in FIGS. An n-type FZ semiconductor substrate 20 having a thickness of about 500 μm and an impurity concentration of 3 × 10 13 to 1.5 × 10 14 cm −3 is used. After the initial oxide film 21 having a thickness of 0.8 to 1.6 μm is formed on the surface of the n-type semiconductor substrate 20 (a), the outer periphery of the active region and the junction termination region formed in the semiconductor substrate 20 in a later process An opening 22 is formed by selective etching in the initial oxide film 21 located at the position (b). (B) The subsequent initial oxide film is also referred to as a mask insulating film 21. An ion implantation layer 22b is formed by ion implantation of boron having a dose of 5 × 10 15 cm −2 into the semiconductor substrate 20 from the opening 22 of the mask insulating film 21 as indicated by an arrow 22a (c).

ボロンのイオン注入の加速エネルギー（ｋｅＶ）はｐ型分離領域６の拡散深さに応じて変えることになる。耐圧６００Ｖのデバイスでは４５ｋｅＶの加速エネルギー、耐圧１２００Ｖでは２００ｋｅＶの加速エネルギーがそれぞれ好ましい。開口部２２以外のマスク絶縁膜２１は、半導体基板２０へのボロンの注入を防ぐマスクとして機能するように、イオン注入の際に、ほとんどのボロンが突き抜けることなく酸化膜内に留まる膜厚の酸化膜２１ｂとイオン注入されたボロンがほとんど無い酸化膜２１ａとを有する。酸化膜２１ａは少なくとも３００ｎｍ以上の膜厚を必要とする。酸化膜２１ｂは、ボロンのイオン注入の加速エネルギーによってその飛程Ｒｐが変わるので、飛程Ｒｐに応じてその膜厚を変える必要がある。マスク絶縁膜２１から酸化膜２１ｂをエッチングにより除去した残りの酸化膜２１ａの厚さが少なくとも３００ｎｍ以上を必要とする理由は、膜厚が３００ｎｍ以下になると、ピンホールや表面結晶欠陥などの影響が急に増加し、オートドーピングへのマスク効果が急減するからである。   The acceleration energy (keV) of boron ion implantation is changed according to the diffusion depth of the p-type isolation region 6. An acceleration energy of 45 keV is preferable for a device with a withstand voltage of 600 V, and an acceleration energy of 200 keV is preferable for a withstand voltage of 1200 V. The mask insulating film 21 other than the opening 22 functions as a mask for preventing boron from being implanted into the semiconductor substrate 20 so that most of the boron remains in the oxide film without being penetrated during ion implantation. A film 21b and an oxide film 21a with almost no ion-implanted boron are included. The oxide film 21a needs to have a thickness of at least 300 nm. Since the range Rp of the oxide film 21b changes depending on the acceleration energy of boron ion implantation, it is necessary to change the thickness of the oxide film 21b according to the range Rp. The reason why the remaining oxide film 21a after removing the oxide film 21b from the mask insulating film 21 by etching needs to be at least 300 nm or more is that when the film thickness is 300 nm or less, the influence of pinholes, surface crystal defects, etc. This is because it increases rapidly and the mask effect on autodoping decreases rapidly.

本発明にかかる実施例１では、前述のように注入ボロンが単にマスク絶縁膜２１を突き抜けない膜厚にするのではなく、注入ボロンを含まない酸化膜２１ａを予めマスク絶縁膜２１に付加しておき、注入ボロンの熱拡散前に、注入ボロンを含む酸化膜２１ｂをエッチングで除去し、ボロンを含まない酸化膜２１ａだけを残すプロセスを特徴としている。例えば、加速エネルギーが４５ｋｅＶの場合、ボロンのイオン注入の飛程Ｒｐは約１４５ｎｍであるが、その飛程Ｒｐには６σ分のばらつきがあることを考慮しても、マスク絶縁膜２１の厚さを８００ｎｍ（０．８μｍ）とすると、注入ボロンがマスク絶縁膜２１を突き抜けることが実質的に無い酸化膜２１ｂ膜厚と、ボロンをほとんど含まない酸化膜２１ａ膜厚が３００ｎｍ以上という膜厚条件を満たすことができるので好ましい。また、加速エネルギーが２００ｋｅＶの場合、ボロンの飛程Ｒｐは５６４ｎｍであり、前述と同様に６σ分のばらつきを考慮しても、マスク絶縁膜２１の厚さを１６００ｎｍ（１．６μｍ）とすると、前述の酸化膜２１ｂと酸化膜２１ａとの膜厚条件を満たすことができるので好ましい。   In the first embodiment according to the present invention, as described above, the implantation boron does not simply have a thickness that does not penetrate the mask insulating film 21, but an oxide film 21a that does not contain implantation boron is added to the mask insulating film 21 in advance. The process is characterized in that the oxide film 21b containing implanted boron is removed by etching before the thermal diffusion of the implanted boron, leaving only the oxide film 21a not containing boron. For example, when the acceleration energy is 45 keV, the boron ion implantation range Rp is about 145 nm, but the thickness of the mask insulating film 21 is considered even if the range Rp varies by 6σ. Is set to 800 nm (0.8 μm), the film thickness conditions are such that the implanted boron film through which the implanted boron does not substantially penetrate through the mask insulating film 21 and the oxide film 21a film that hardly contains boron are 300 nm or more. It is preferable because it can be satisfied. Further, when the acceleration energy is 200 keV, the boron range Rp is 564 nm, and the thickness of the mask insulating film 21 is 1600 nm (1.6 μm) even if the variation of 6σ is taken into consideration as described above. This is preferable because the film thickness conditions of the oxide film 21b and the oxide film 21a can be satisfied.

前述の（ｃ）工程後に、マスク絶縁膜２１から酸化膜２１ｂ部分をエッチングにより除去して薄化し酸化膜２１ａを残す。１３００℃の酸素雰囲気中での長時間処理により、イオン注入層２２ｂ内のボロンを深さ５０〜２００μｍまで熱拡散させてｐ型分離領域６を形成する（ｄ）。例えば、ｐ型分離領域６の拡散深さを５０μｍとするためには１３００℃で１００時間程度、拡散深さを２００μｍとするためには１３００度で３００時間程度の熱処理を行う必要がある。このように、実施例１では、注入ボロンをほとんど含まない酸化膜２１ａをマスクとして高温長時間拡散処理を行うので、オートドーピングやボロンを含む酸化膜２１ｂからのボロンの突き抜けによる望まれないｐ型領域の形成を防ぐことができる。   After the step (c) described above, the oxide film 21b portion is removed from the mask insulating film 21 by etching to leave the oxide film 21a. By long-time treatment in an oxygen atmosphere at 1300 ° C., boron in the ion implantation layer 22b is thermally diffused to a depth of 50 to 200 μm to form the p-type isolation region 6 (d). For example, in order to set the diffusion depth of the p-type isolation region 6 to 50 μm, it is necessary to perform heat treatment at 1300 ° C. for about 100 hours, and in order to set the diffusion depth to 200 μm, it is necessary to perform heat treatment at 1300 degrees for about 300 hours. As described above, in the first embodiment, the high-temperature and long-time diffusion treatment is performed using the oxide film 21a containing almost no implanted boron as a mask. Therefore, the p-type is not desired due to auto-doping or boron penetration from the oxide film 21b containing boron. Region formation can be prevented.

本発明にかかる、マスク絶縁膜２１のエッチングにより、注入ボロンが含まれない残膜がある状態と、マスク絶縁膜２１をすべて除去した状態とで、深い分離拡散領域の形成後のボロンのオートドーピングによる望まれないｐ型領域の形成の有無を調べた結果を、図３に示す。望まれない領域にｐ型領域が形成されると、このｐ型領域が形成されている場所はＩＧＢＴの表面側の主要な半導体機能領域であるＭＯＳゲート構造を形成する場所でもあるので、正常なＭＯＳゲート構造が形成できなくなり、特性不良が増加する。図３（ａ）はマスク絶縁膜２１をすべて除去した場合にオートドーピングにより形成された望まれない場所へのｐ型領域の不純物濃度を示す。半導体基板の最表面から約０．２μｍの深さまで、１０15ｃｍ-3以上のボロン濃度が検出されている。更に、半導体基板の内部でも２〜３×１０14ｃｍ-3のボロン濃度のところがあり、ｎ型半導体基板２０の不純物濃度３×１０13〜１．５×１０14ｃｍ-3より高濃度の部分があるのでｐ型領域が形成されている可能性がある。またはｐ型領域が形成されないときでも、ボロンの不純物濃度が半導体基板の不純物濃度に近いので、ｐ型とｎ型の不純物が相殺されてｎ型としての不純物濃度が低下することがある。（ｂ）は本発明にかかる製造方法による、マスク絶縁膜２１から注入ボロンが含まれる膜厚をエッチングで除去しボロンを含まない残膜を残して分離拡散領域を形成する場合である。（ｂ）から、半導体基板の最表面を除いてボロン濃度が１０14ｃｍ-3以下に抑えられており、ｐ型領域がほとんど形成されていない事がわかる。また、半導体基板の内部ではボロン濃度はほとんど検出限界以下と、ｎ型半導体基板２０の不純物濃度３×１０13〜１．５×１０14ｃｍ-3より低濃度であるので、ｐ型領域はほとんど形成されないことが分かる。 The auto-doping of boron after the formation of the deep isolation diffusion region in the state where there is a residual film not containing implanted boron and the state where all of the mask insulating film 21 is removed by etching of the mask insulating film 21 according to the present invention. FIG. 3 shows the result of examining the presence or absence of formation of an undesired p-type region. When a p-type region is formed in an undesired region, the place where the p-type region is formed is also a place where a MOS gate structure which is a main semiconductor functional region on the surface side of the IGBT is formed. The MOS gate structure cannot be formed and the characteristic defect increases. FIG. 3A shows the impurity concentration of the p-type region in an undesired place formed by autodoping when the mask insulating film 21 is completely removed. A boron concentration of 10 15 cm −3 or more has been detected from the outermost surface of the semiconductor substrate to a depth of about 0.2 μm. Further, there is a boron concentration of 2 to 3 × 10 14 cm −3 inside the semiconductor substrate, and a portion of the n-type semiconductor substrate 20 having an impurity concentration higher than 3 × 10 13 to 1.5 × 10 14 cm −3. Therefore, there is a possibility that a p-type region is formed. Even when the p-type region is not formed, the impurity concentration of boron is close to the impurity concentration of the semiconductor substrate, so that the p-type and n-type impurities may cancel each other and the n-type impurity concentration may decrease. (B) shows a case where the film thickness including the implanted boron is removed from the mask insulating film 21 by etching and the separation diffusion region is formed leaving the remaining film not including boron by the manufacturing method according to the present invention. From (b), it can be seen that the boron concentration is suppressed to 10 14 cm −3 or less except for the outermost surface of the semiconductor substrate, and the p-type region is hardly formed. In addition, since the boron concentration is almost below the detection limit inside the semiconductor substrate and is lower than the impurity concentration of 3 × 10 13 to 1.5 × 10 14 cm −3 of the n-type semiconductor substrate 20, the p-type region is almost all. It can be seen that it is not formed.

次に、前述した飛程Ｒｐのばらつきを考慮した上で、マスク絶縁膜２１中への注入ボロンの深さおよびこの注入ボロンを含む酸化膜２１ｂをエッチングで除去する必要のある厚さおよび残りの酸化膜２１ａである残膜厚さについて、詳細に説明する。すなわち、ボロンのイオン注入時の加速エネルギーによる実際の飛程Ｒｐはばらつきを有していて、その平均値（中心値）を飛程Ｒｐ、その標準偏差シグマ（σ）をΔＲｐとすると、前述した加速エネルギーが４５ｋｅＶの場合の飛程Ｒｐ１４５ｎｍに対するΔＲｐ（σ）は４５ｎｍのばらつきであった。この場合、飛程Ｒｐの前後６シグマ（６σ）の分布範囲内にはほとんどの注入ボロンが含まれると考えられる。Ｒｐ＋６シグマ（６σ）は、１４５＋６×４５＝４１５ｎｍとなる。従って、ボロンの加速エネルギーが４５ｋｅＶのとき、マスク絶縁膜２１の厚さ８００ｎｍから４１５ｎｍの厚さをエッチングなどで除去すれば、残りの酸化膜２１ａの残膜厚さ３８５ｎｍ中には注入されたボロンはほとんど含まれないことになり、しかも、残膜厚さに求められる最少膜厚３００ｎｍ以上も満たす。従って、逆にマスク絶縁膜２１の膜厚Ｘを求める場合は、膜厚Ｘ≧３００ｎｍ＋膜厚２１ｂであり、加速エネルギーが４５ｋｅＶの場合はマスク絶縁膜２１中に注入ボロンが含まれる膜厚２１ｂが前述のように４１５ｎｍとなるから、少なくとも７１５ｎｍ以上あれば前述の膜厚条件を満たすこととなり、エッチング誤差を含めて考えると、８００ｎｍ程度の膜厚が好適である。   Next, in consideration of the above-described variation in the range Rp, the depth of implanted boron into the mask insulating film 21, the thickness required to remove the oxide film 21b containing this implanted boron by etching, and the remaining The remaining film thickness that is the oxide film 21a will be described in detail. That is, the actual range Rp due to the acceleration energy at the time of boron ion implantation has variations, and the average value (center value) is the range Rp and the standard deviation sigma (σ) is ΔRp. When the acceleration energy is 45 keV, ΔRp (σ) with respect to the range Rp145 nm was a variation of 45 nm. In this case, it is considered that most implanted boron is included in the distribution range of 6 sigma (6σ) before and after the range Rp. Rp + 6 sigma (6σ) is 145 + 6 × 45 = 415 nm. Therefore, when the acceleration energy of boron is 45 keV, if the thickness of 800 to 415 nm of the mask insulating film 21 is removed by etching or the like, boron implanted into the remaining film thickness of 385 nm of the remaining oxide film 21a. In other words, the minimum film thickness of 300 nm or more required for the remaining film thickness is satisfied. Therefore, conversely, when the film thickness X of the mask insulating film 21 is obtained, the film thickness X ≧ 300 nm + the film thickness 21b, and when the acceleration energy is 45 keV, the film thickness 21b including implanted boron in the mask insulating film 21 is Since the thickness is 415 nm as described above, the above-described film thickness condition is satisfied if it is at least 715 nm or more, and a thickness of about 800 nm is preferable considering the etching error.

同様に加速エネルギーが２００ｋｅＶのとき、マスク絶縁膜２１の厚さ１６００ｎｍからＲｐ５６４ｎｍとΔＲｐ（σ）９５ｎｍの６シグマ（６σ）分との和の１１３５ｎｍの厚さをエッチングなどで除去すれば、残りの酸化膜２１ａの残膜厚さ４６５ｎｍ中には注入されたボロンはほとんど含まれない。   Similarly, when the acceleration energy is 200 keV, if the thickness of 1135 nm which is the sum of 6 sigma (6σ) of Rp564 nm and ΔRp (σ) 95 nm is removed from the thickness 1600 nm of the mask insulating film 21 by etching or the like, the remaining The remaining film thickness of 465 nm of the oxide film 21a contains almost no implanted boron.

図４は、本発明にかかる、耐圧６００Ｖの逆阻止ＩＧＢＴの逆耐圧とマスク絶縁膜２１から前述したイオン注入されたボロンを含む６σ膜厚を除去した残りの膜厚（残膜）との関係を示す図である。図４から、マスク絶縁膜２１（初期酸化膜）の膜厚８００ｎｍそのままでは、逆耐圧が６５０Ｖ程度であり、マスク絶縁膜２１を表面からエッチングするにつれて、逆耐圧が上昇し、４００ｎｍ程度エッチングすると、逆耐圧が７４０Ｖで最も高くなり、さらに４００ｎｍ程度を超えて残膜厚が減少すると逆耐圧も減少することを示している。本発明では、特には、オートドーピングの抑制に効果がある３００ｎｍ以上の残膜厚であって、ボロンの高温長時間熱拡散処理前にマスク絶縁膜２１中のボロンを、前述のように飛程の中心値から６σの範囲までの厚さ、すなわち、耐圧６００Ｖでは４１５ｎｍ程度、例えば、４００ｎｍの膜厚を除去した残膜厚４００ｎｍ以下が好ましい。図４から残膜厚３００ｎｍ〜４００ｎｍにおける逆耐圧は７３０Ｖから７４０Ｖである。同じ残膜範囲の場合の順耐圧について、本発明にかかる、順耐圧に関する同様の関係図である図５から残膜厚３００ｎｍ〜４００ｎｍの範囲の順耐圧は約７４０Ｖ〜７６０Ｖであることが分かる。   FIG. 4 shows the relationship between the reverse breakdown voltage of the reverse blocking IGBT having a breakdown voltage of 600 V according to the present invention and the remaining film thickness (residual film) obtained by removing the 6σ film thickness including the above-described ion-implanted boron from the mask insulating film 21. FIG. From FIG. 4, when the thickness of the mask insulating film 21 (initial oxide film) is 800 nm, the reverse breakdown voltage is about 650 V, and the reverse breakdown voltage increases as the mask insulating film 21 is etched from the surface. It shows that the reverse breakdown voltage is highest at 740 V, and that the reverse breakdown voltage decreases when the remaining film thickness is reduced beyond about 400 nm. In the present invention, in particular, the residual film thickness of 300 nm or more that is effective in suppressing autodoping, and boron in the mask insulating film 21 before the high-temperature and long-time thermal diffusion treatment of boron is used as described above. The thickness from the center value of 6σ to the range of 6σ, that is, about 415 nm at a withstand voltage of 600 V, for example, a remaining film thickness of 400 nm or less after removing a film thickness of 400 nm is preferable. From FIG. 4, the reverse breakdown voltage in the remaining film thickness of 300 nm to 400 nm is 730V to 740V. Regarding the forward breakdown voltage in the case of the same remaining film range, it can be seen from FIG. 5 which is the same relational diagram regarding the forward breakdown voltage according to the present invention that the forward breakdown voltage in the range of the remaining film thickness of 300 nm to 400 nm is about 740V to 760V.

前述の説明に記載の数値と、前記説明に無いボロンの加速エネルギー１００ｋｅＶの場合について求めた飛程Ｒｐ、ΔＲｐ、６σ、初期酸化膜（マスク絶縁膜２１）の厚さ、薄化後の残膜（酸化膜２１ａ）の厚さの上限、下限などについて、下記表１にまとめた。   The numerical values described in the above description, the range Rp, ΔRp, 6σ, the thickness of the initial oxide film (mask insulating film 21), and the remaining film after thinning obtained for the case of the acceleration energy of boron of 100 keV not described above The upper limit and lower limit of the thickness of (oxide film 21a) are summarized in Table 1 below.

Figure 2015079849
次に、図１（ｅ）のように、オートドーピングマスクとして用いた酸化膜２１ａをすべてエッチングにより除去する。
Figure 2015079849
 Next, as shown in FIG. 1E, all the oxide film 21a used as the auto-doping mask is removed by etching.

図６は、本発明にかかる、耐圧６００Ｖの逆阻止ＩＧＢＴのゲート不良率とマスク絶縁膜から前述したイオン注入されたボロンを含む６σの膜厚を除去した残りの膜厚（残膜）との関係を示す図である。図６から本発明によれば、１００ｎｍ以上４００ｎｍ以下の残膜厚であれば、ゲート不良の原因となる高濃度酸素に起因する結晶欠陥が基板表面に形成されないので、ゲート不良が実質的に無いことを示している。   FIG. 6 shows the gate defect rate of the reverse blocking IGBT having a withstand voltage of 600 V according to the present invention and the remaining film thickness (residual film) obtained by removing the film thickness of 6σ including the aforementioned ion-implanted boron from the mask insulating film. It is a figure which shows a relationship. According to the present invention from FIG. 6, if the remaining film thickness is 100 nm or more and 400 nm or less, crystal defects due to high-concentration oxygen that causes gate defects are not formed on the substrate surface, so that there is substantially no gate defects. It is shown that.

その後、前記図２に記載されているフィールド酸化膜２ａを新たに全面に形成した後、ＭＯＳ構造１３、ｐ型ベース領域１０、ｎ型エミッタ領域１１、エミッタ電極１２、フィールドリミッティングリング７、フィールドプレート８などの活性領域お１４よび接合終端領域９内に周知のＩＧＢＴ表面構造を形成する。その後、電子線などの照射と熱処理により所望の少数キャリアライフタイムとなるように調整する。次に、半導体基板２０を裏面から研削して耐圧に対応する基板厚さに薄くする。裏面研削後の薄くされた半導体基板の符号を１とする。さらに、裏面からのボロンのイオン注入によりｐ型コレクタ層１６を形成し、その外周でｐ型分離領域６と接触させ、次に、このｐ型分離領域６表面にオーミック接触するコレクタ電極１７を形成する。このようにして本発明の半導体装置の製造方法により製造された逆阻止ＩＧＢＴは半導体基板１のＩＧＢＴ表面構造が、側面の高濃度ｐ型分離領域６と裏面のｐ型コレクタ層１６とにより囲まれているので、通常のＩＧＢＴにように、ｐ型コレクタ層１６と半導体基板１の間にある逆耐圧接合の終端が何ら保護機能の無い基板１側面には露出しない。その結果、本発明にかかる逆阻止ＩＧＢＴはエミッタ側を正、コレクタ側を負とする逆電圧を印加した際にも、空乏層がデバイス側面に露出せず、信頼性が高く安定した逆耐圧を得ることができる。   Thereafter, after the field oxide film 2a shown in FIG. 2 is newly formed on the entire surface, the MOS structure 13, the p-type base region 10, the n-type emitter region 11, the emitter electrode 12, the field limiting ring 7, the field A well-known IGBT surface structure is formed in the active region 14 such as the plate 8 and the junction termination region 9. Thereafter, adjustment is made so as to achieve a desired minority carrier lifetime by irradiation with an electron beam or the like and heat treatment. Next, the semiconductor substrate 20 is ground from the back surface to reduce the substrate thickness corresponding to the pressure resistance. The reference numeral of the thinned semiconductor substrate after back grinding is 1. Further, a p-type collector layer 16 is formed by ion implantation of boron from the back surface, and is brought into contact with the p-type isolation region 6 at the outer periphery thereof. Next, a collector electrode 17 is formed in ohmic contact with the surface of the p-type isolation region 6. To do. In the reverse blocking IGBT manufactured by the method of manufacturing a semiconductor device of the present invention, the IGBT surface structure of the semiconductor substrate 1 is surrounded by the high-concentration p-type isolation region 6 on the side surface and the p-type collector layer 16 on the back surface. Therefore, as in a normal IGBT, the termination of the reverse breakdown voltage junction between the p-type collector layer 16 and the semiconductor substrate 1 is not exposed on the side surface of the substrate 1 without any protective function. As a result, the reverse blocking IGBT according to the present invention does not expose the depletion layer to the side surface of the device even when a reverse voltage is applied with the emitter side being positive and the collector side being negative. Can be obtained.

以上説明した本発明にかかる実施例１によれば、耐圧６００Ｖの逆阻止ＩＧＢＴを製造する際に、マスク絶縁膜の厚さを８００ｎｍ（０．８μｍ）とし、加速エネルギー４５ｋｅＶのボロンをイオン注入後、マスク絶縁膜を残膜厚０．３〜０．４μｍ程度に薄くしてから、ボロンの熱拡散処理をして深い分離領域を形成する製造方法とする。この実施例１の製造方法によれば、マスク絶縁膜（初期酸化膜）中のボロンが実質的に完全に除去される程度にマスク絶縁膜が薄くされるので、基板表面近傍に取り込まれた高濃度酸素の外方拡散が促進され、基板表面は十分に低酸素濃度状態にすることができる。その結果、基板表面に酸素析出物（面あれ）の生成が抑制され基板の表面における面あれ状態が緩和される。また、酸化膜にイオン注入されたボロン注入層のみの厚さをエッチングで除去し、ボロンをほとんど含まない厚さの酸化膜を残すことにより、次工程の高温長時間の拡散工程で、酸化膜中のボロンが酸化膜を突き抜けて半導体基板内へ拡散するのを確実に抑制すると共に、ボロンのオートドーピングに対してはマスク効果を有することができる。そのためには、高温長時間拡散工程前のマスク絶縁膜エッチングで、残膜厚の上限値が０．４μｍとなるように、ボロンの飛程より６シグマ分以上の深さまでエッチングして薄くすることが好ましい。また残膜厚の下限値を０．３μｍとし、これ以上の厚さが好ましいとした理由は、酸化膜がこれ以上薄くなると酸化膜のピンホールや欠陥の発生確率が極めて大きくなり、オートドーピングの抑制効果が小さくなるからである。   According to the first embodiment of the present invention described above, when manufacturing a reverse blocking IGBT having a breakdown voltage of 600 V, the thickness of the mask insulating film is set to 800 nm (0.8 μm), and boron having an acceleration energy of 45 keV is ion-implanted. Then, after the mask insulating film is thinned to a remaining film thickness of about 0.3 to 0.4 μm, a thermal isolation treatment of boron is performed to form a deep isolation region. According to the manufacturing method of the first embodiment, the mask insulating film is thinned to such an extent that boron in the mask insulating film (initial oxide film) is substantially completely removed. The outward diffusion of the concentration oxygen is promoted, and the substrate surface can be brought into a sufficiently low oxygen concentration state. As a result, the generation of oxygen precipitates (surface roughness) on the substrate surface is suppressed, and the surface roughness state on the substrate surface is relaxed. Also, the thickness of only the boron implanted layer ion-implanted into the oxide film is removed by etching, leaving an oxide film having a thickness that hardly contains boron, so that the oxide film can be used in the next high-temperature long-time diffusion process. It is possible to reliably suppress the boron inside from penetrating the oxide film and diffusing into the semiconductor substrate, and to have a masking effect on boron auto-doping. For that purpose, the mask insulation film is etched before the high temperature and long time diffusion process, and is etched to a depth of 6 sigma or more from the boron range so that the upper limit of the remaining film thickness becomes 0.4 μm. Is preferred. In addition, the lower limit of the remaining film thickness is set to 0.3 μm, and a thickness larger than this is preferable. When the oxide film becomes thinner, the probability of occurrence of pinholes and defects in the oxide film becomes extremely large, and auto-doping This is because the suppression effect is reduced.

実施例１に記載の本発明によれば、逆耐圧を低下させることなく、ゲート不良を１％以下に抑えることができる。さらに酸化膜中のボロンが半導体基板へ拡散することを抑制すると共にボロンのオートドーピングを抑制し、逆耐圧の低下を抑制することにより、初期のシリコン基板の比抵抗を小さくでき、さらに基板の厚さを薄くでき、オン電圧が低減される。また基板が薄い分、分離拡散層は浅くなり、高温拡散の熱処理時間が短くなる。   According to the present invention described in the first embodiment, the gate defect can be suppressed to 1% or less without reducing the reverse breakdown voltage. Furthermore, by suppressing the diffusion of boron in the oxide film to the semiconductor substrate and suppressing the autodoping of boron, and suppressing the decrease in reverse breakdown voltage, the specific resistance of the initial silicon substrate can be reduced, and the thickness of the substrate can be reduced. The on-voltage can be reduced. In addition, since the substrate is thin, the separation diffusion layer becomes shallow, and the heat treatment time for high-temperature diffusion is shortened.

１ 半導体基板
２ａ フィールド酸化膜
６ ｐ型分離領域
７ フィールドリミッティングリング
８ フィールドプレート
９ 接合終端領域
１０ ｐ型ベース領域
１１ ｎ型エミッタ領域
１２ エミッタ電極
１３ ＭＯＳ構造
１３ａ ゲート電極
１３ｂ ゲート酸化膜
１４ 活性領域
１６ ｐ型コレクタ層
１７ コレクタ電極
２０ 半導体基板
２１ 初期酸化膜、マスク絶縁膜
２１ａ ボロンを含む酸化膜
２１ｂ ボロンを含まない酸化膜
２２ 開口部
２２ａ イオン注入
２２ｂ イオン注入層
１００ 逆阻止ＩＧＢＴ 1 semiconductor substrate 2a field oxide film 6 p-type isolation region 7 field limiting ring 8 field plate 9 junction termination region 10 p-type base region 11 n-type emitter region 12 emitter electrode 13 MOS structure 13a gate electrode 13b gate oxide film 14 active region 16 p-type collector layer 17 collector electrode 20 semiconductor substrate 21 initial oxide film, mask insulating film 21a oxide film containing boron 21b oxide film not containing boron 22 opening 22a ion implantation 22b ion implantation layer 100 reverse blocking IGBT

Claims (5)

第１導電型半導体基板の一方の主面にＭＯＳゲート構造を含む活性領域と該領域を取り巻く接合終端領域、他方の主面には第２導電型半導体層をそれぞれ有し、前記活性領域と前記接合終端領域とを取り巻く位置に、一方の主面から対向する他方の主面の前記第２導電型半導体層に至り接触する第２導電型分離領域を有する半導体装置を形成するための製造方法が、前記第１導電型半導体基板の一方の主面に所要の膜厚を有するマスク絶縁膜と該マスク絶縁膜の前記位置に前記第２導電型分離領域形成用の開口部とを形成する第１工程と、前記一方の主面から、所要のドーズ量と加速エネルギにより、第２導電型不純物をイオン注入する第２工程と、該イオン注入により前記マスク絶縁膜中に形成された第２導電型不純物注入層を除去して前記マスク絶縁膜を薄化する第３工程と、前記開口部からイオン注入された第２導電型不純物を前記他方の主面の第２導電型半導体層部分に達する深さまで熱処理により拡散させて前記第２導電型分離領域を形成する第４工程とを有することを特徴とする半導体装置の製造方法。 An active region including a MOS gate structure and a junction termination region surrounding the active region on one main surface of the first conductive type semiconductor substrate, and a second conductive type semiconductor layer on the other main surface, respectively, A manufacturing method for forming a semiconductor device having a second conductivity type isolation region in contact with the second conductivity type semiconductor layer on the other main surface opposite to one main surface at a position surrounding the junction termination region. Forming a mask insulating film having a required film thickness on one main surface of the first conductive type semiconductor substrate and an opening for forming the second conductive type isolation region at the position of the mask insulating film; A step, a second step of ion-implanting a second conductivity type impurity from the one main surface with a required dose and acceleration energy, and a second conductivity type formed in the mask insulating film by the ion implantation. Before removing the impurity implantation layer A third step of thinning the mask insulating film; and a second conductive type impurity ion-implanted from the opening is diffused by heat treatment to a depth reaching the second conductive type semiconductor layer portion of the other main surface, and the first And a fourth step of forming a two-conductivity type isolation region. 前記第３工程で薄化される前記マスク絶縁膜の残膜厚さが、３００ｎｍ以上で、４００ｎｍ以下であることを特徴とする請求項１記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein a residual film thickness of the mask insulating film thinned in the third step is not less than 300 nm and not more than 400 nm. 前記第３工程において、前記マスク絶縁膜のうち、該マスク絶縁膜中にイオン注入される第２導電型不純物の飛程とその標準偏差の６倍との和以上の膜厚を除去することを特徴とする請求項１記載の半導体装置の製造方法。 In the third step, removing a thickness of the mask insulating film equal to or greater than the sum of the range of the second conductivity type impurity ion-implanted into the mask insulating film and 6 times its standard deviation. The method of manufacturing a semiconductor device according to claim 1, wherein: 前記第４工程で形成される前記第２導電型分離領域の、前記開口部からの深さが５０μｍ〜２００μｍであることを特徴とする請求項１記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductivity type isolation region formed in the fourth step has a depth from the opening of 50 μm to 200 μm. 前記請求項１記載の半導体装置の製造方法により製造される半導体装置が逆阻止ＩＧＢＴであることを特徴とする半導体装置。 A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a reverse blocking IGBT.
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