JP2023010539A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device having a high withstand voltage and in which an n-type oxide gallium semiconductor layer and an electrode layer constitute a Schottky junction.SOLUTION: A semiconductor device of the present disclosure includes: an n-type gallium oxide semiconductor layer having a central region and a periphery region having a donor concentration lower than that of the central region; an electrode layer which is laminated on the n-type gallium oxide semiconductor layer and constitutes a Schottky junction with the n-type gallium oxide semiconductor layer in the central region when viewed from the lamination direction; and a first p-type nickel oxide semiconductor layer which is laminated on the n-type gallium oxide semiconductor layer while partially located between the n-type gallium oxide semiconductor layer and the electrode layer and in which an outer peripheral end part at the periphery region side is present on the periphery region when viewed from the lamination direction.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to semiconductor devices.

Patent document 1 discloses a semiconductor device made of semiconductor SiC, having a termination region around an active region, and having a passivation film covering the surface of the termination region, wherein the passivation film contacts the surface of the termination region. a silicon oxide film; a second silicon oxide film stacked over the first silicon oxide film and in contact with the first silicon oxide film; and a contacting third silicon oxide film. The same document discloses that in the semiconductor device, the termination region may have an FLR (field limiting ring) structure.

JP 2016-81981 A

In a semiconductor device in which an n-type gallium oxide semiconductor layer and an electrode layer form a Schottky junction, a p-type nickel oxide semiconductor layer can be employed in a peripheral breakdown voltage structure. However, it is difficult to reduce the acceptor density of the p-type nickel oxide semiconductor layer. Therefore, the electric field concentrates on the outer peripheral edge of the p-type nickel oxide semiconductor layer in contact with the electrode layer, and dielectric breakdown is likely to occur.

Therefore, in a semiconductor device in which an n-type gallium oxide semiconductor and an electrode layer form a Schottky junction, suppression of dielectric breakdown, that is, improvement in withstand voltage is required.

An object of the present disclosure is to provide a semiconductor device having a high withstand voltage and in which an n-type gallium oxide semiconductor layer and an electrode layer form a Schottky junction.

The inventors have found that the above objects can be achieved by the following means:
<<Aspect 1>>
an n-type gallium oxide semiconductor layer having a central region and a peripheral region having a lower donor density than the central region;
an electrode layer stacked on the n-type gallium oxide semiconductor layer and forming a Schottky junction with the n-type gallium oxide semiconductor layer in the central region when viewed in the stacking direction; laminated on the n-type gallium oxide semiconductor layer so as to be partially located between the n-type gallium oxide semiconductor layer and the electrode layer, and when viewed from the lamination direction, the peripheral region a semiconductor device having a first p-type nickel oxide semiconductor layer, the outer peripheral edge of which is located in the peripheral region.
<<Aspect 2>>
The semiconductor device according to mode 1, wherein the peripheral region has a donor density of 5.0×10 ¹⁵ cm ⁻³ or less.
<<Aspect 3>>
The semiconductor device according to mode 1 or 2, wherein the central region has a donor density of 1.0×10 ¹⁶ cm ⁻³ or more.
<<Aspect 4>>
The semiconductor device according to any one of modes 1 to 3, wherein the first p-type nickel oxide semiconductor layer is positioned so as to straddle the central region and the peripheral region when viewed from the stacking direction. .
<<Aspect 5>>
When the thickness of the central region of the n-type gallium oxide semiconductor layer is t, and the width of the portion of the first p-type nickel oxide semiconductor layer located in the central region is x, x/t >0.50.
<<Aspect 6>>
The semiconductor device according to any one of aspects 1 to 5, wherein the donor is Sn or Si.
<<Aspect 7>>
7. The semiconductor device according to any one of modes 1 to 6, wherein the peripheral region is doped with acceptors and thus has a lower donor density than the central region.
<<Aspect 8>>
The semiconductor device according to aspect 7, wherein the acceptor is N or Mg.
<<Aspect 9>>
In the peripheral region on the side of the n-type gallium oxide semiconductor layer on which the first p-type nickel oxide semiconductor layer is laminated, a plurality of The semiconductor device according to any one of modes 1 to 8, having a second p-type nickel oxide semiconductor layer of
<<Aspect 10>>
The n-type gallium oxide semiconductor layer has a plurality of trench structures on the side where the first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are laminated,
The first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are respectively stacked in recesses of the trench structure,
The semiconductor device according to aspect 9.
<<Aspect 11>>
The semiconductor device according to any one of aspects 1 to 10, which is a pn diode, a JBS diode, a metal oxide semiconductor field effect transistor, or a junction field effect transistor.
<<Aspect 12>>
The semiconductor according to any one of aspects 1 to 11, comprising forming the peripheral region of the n-type gallium oxide semiconductor layer by reducing the donor density by ion irradiation or heating in an oxygen atmosphere. Method of manufacturing the device.
<<Aspect 13>>
13. The method according to aspect 12, wherein ions of an acceptor element, hydrogen, or helium are irradiated in the ion irradiation.
<<Aspect 14>>
14. The method according to mode 12 or 13, wherein the n-type gallium oxide semiconductor layer is annealed after the ion irradiation.
<<Aspect 15>>
14. The method according to aspect 12 or 13, wherein the n-type gallium oxide semiconductor layer is not annealed after the ion irradiation.

According to the present disclosure, it is possible to provide a semiconductor device having high withstand voltage and having a Schottky junction between an n-type gallium oxide semiconductor layer and an electrode layer.

FIG. 1 is a schematic diagram of a semiconductor device 1 according to the first embodiment of the present disclosure. FIG. 2 is a schematic diagram of a semiconductor device 2 different from the embodiments of the present disclosure. FIG. 3 is a schematic diagram of the semiconductor device 1 according to the first embodiment of the present disclosure. FIG. 4 is a schematic diagram of a semiconductor device 3 of Comparative Example 2. As shown in FIG. FIG. 5 is a schematic diagram of a semiconductor device 4 of Comparative Example 3. As shown in FIG. FIG. 6 is a schematic diagram of the semiconductor device 5 of Example 1. FIG. 7 is a graph showing the relationship between the depth of the n-type gallium oxide semiconductor layer after ion implantation and the Mg density in Example 7. FIG. 8 is a graph showing the relationship between the depth of the n-type gallium oxide semiconductor layer after heat treatment in the air atmosphere and the Mg density in Example 8. FIG.

Hereinafter, embodiments of the present disclosure will be described in detail. It should be noted that the present disclosure is not limited to the following embodiments, and various modifications can be made within the scope of the gist of the disclosure.

A semiconductor device according to the present disclosure includes an n-type gallium oxide semiconductor layer having a central region and a peripheral region having a lower donor density than the central region, and is stacked on the n-type gallium oxide semiconductor layer and in the stacking direction. the electrode layer forming a Schottky junction with the n-type gallium oxide semiconductor layer in the central region when viewed from above, and partially located between the n-type gallium oxide semiconductor layer and the electrode layer. and a first p-type nickel oxide semiconductor layer stacked on the n-type gallium oxide semiconductor layer, and having an outer peripheral edge on the peripheral region side in the peripheral region when viewed in the stacking direction there is

In a semiconductor device in which an n-type gallium oxide semiconductor layer and an electrode layer form a Schottky junction, if a p-type nickel oxide semiconductor layer is used for the peripheral voltage resistance structure, dielectric breakdown is likely to occur. This is because it is difficult to reduce the acceptor density of the p-type nickel oxide semiconductor layer, so that the electric field tends to concentrate on the outer peripheral edge of the p-type nickel oxide semiconductor layer in contact with the electrode layer.

In the semiconductor device of the present disclosure, when viewed from the stacking direction, the peripheral edge of the first p-type nickel oxide semiconductor layer on the side of the peripheral region is in the peripheral region of the n-type gallium oxide semiconductor layer. This peripheral region has a lower donor density than the central region. This suppresses concentration of an electric field at the outer peripheral edge of the first p-type nickel oxide semiconductor layer in contact with the electrode layer. Therefore, dielectric breakdown is suppressed in the semiconductor device of the present disclosure.

FIG. 1 is a schematic diagram of a semiconductor device 1 according to the first embodiment of the present disclosure.

As shown in FIG. 1, a semiconductor device 1 according to the first embodiment of the present disclosure includes a central region 11 and an n-type gallium oxide semiconductor layer 10 having a peripheral region 13 with a lower donor density than the central region 11. , stacked on the n-type gallium oxide semiconductor layer 10 and forming a Schottky junction with the n-type gallium oxide semiconductor layer 10 in the central region 11 when viewed from the stacking direction. The electrode layer 20 and the n-type gallium oxide semiconductor layer 10 are laminated on the n-type gallium oxide semiconductor layer 10 so as to be partially located between the n-type gallium oxide semiconductor layer 10 and the first electrode layer 20, and from the lamination direction It has a first p-type nickel oxide semiconductor layer 40 whose outer peripheral edge on the side of the peripheral region 13 is in the peripheral region 13 when viewed.

In the semiconductor device 1 according to the first embodiment of the present disclosure, the second electrode layer is formed on the surface of the n-type gallium oxide semiconductor layer 10 on which the first electrode layer 20 is not laminated. 30 are stacked. In addition, the second electrode layer 30 forms an ohmic junction with the n-type gallium oxide semiconductor layer 10 .

In addition, "C" in FIG. 1 indicates the central region side, and "O" indicates the peripheral region side. Note that “central region side C” and “peripheral region side O” merely indicate directions, and the “central region side C” of a certain component does not necessarily correspond to the n-type gallium oxide semiconductor layer when viewed from the stacking direction. It is not meant to overlap with 10 central regions. The same applies to the "peripheral area side O".

In the semiconductor device 1 according to the first embodiment of the present disclosure, when viewed from the stacking direction, the outer peripheral end portion of the first p-type nickel oxide semiconductor layer 40 on the peripheral region side O is the n-type gallium oxide semiconductor layer. 10 in the peripheral region 13 . Here, the peripheral region 13 has a lower donor density than the central region 11 . This suppresses concentration of the electric field at the outer peripheral edge of the first p-type nickel oxide semiconductor layer 40 in contact with the first electrode layer 20 . Therefore, dielectric breakdown is suppressed in the semiconductor device 1 according to the first embodiment of the present disclosure.

Note that FIG. 1 is not meant to limit the semiconductor device of the present disclosure.

FIG. 2 is a schematic diagram of a semiconductor device 2 different from the embodiments of the present disclosure.

As shown in FIG. 2 , the semiconductor device 2 different from the embodiment of the present disclosure has no difference in donor density between the central region 11 and the peripheral region 13 . In general, p-type nickel oxide semiconductors have a high acceptor density. Therefore, in such a semiconductor device 2, the electric field is concentrated at the outer peripheral end portion of the first p-type nickel oxide semiconductor layer 40 in contact with the first electrode layer 20, and dielectric breakdown is likely to occur.

The semiconductor device of the present disclosure is, for example, a diode, more specifically a pn diode or JBS diode, or a transistor, more specifically a metal oxide semiconductor field effect transistor (MOSFET) or junction It may be a Junction Field Effect Transistor (JFET).

<<n-type gallium oxide semiconductor layer>>
The n-type gallium oxide semiconductor layer has a central region and a peripheral region. The peripheral region has a lower donor density than the central region.

The n-type gallium oxide semiconductor layer may be formed, for example, on a gallium oxide single crystal layer. More specifically, the n-type gallium oxide semiconductor layer may be, for example, an epitaxial layer.

The gallium oxide single crystal layer can be, for example, a layer of α-Ga ₂ O ₃ single crystal, β-Ga ₂ O ₃ single crystal, or Ga ₂ O ₃ single crystal having another crystal structure, preferably β - Ga ₂ O ₃ single crystal layer.

The n-type gallium oxide semiconductor layer contains donors. The donor can be Sn or Si, for example.

<Central area>
The central region can include at least the active region of the Schottky diode, in which the electrode layers are arranged. Note that the active region is a portion in which a semiconductor element is formed.

The central region has a higher donor density than the peripheral region.

The donor density in the central region can be 1.0×10 ¹⁶ cm ⁻³ or higher.

The donor density in the central region may be 1.0×10 ¹⁶ cm ⁻³ or more and 1.0×10 ¹⁸ cm ⁻³ or less.

The donor density in the central region is 1.0×10 ¹⁶ cm ^-3 or more, 2.0×10 ¹⁶ cm ^-3 or more, 5.0×10 ¹⁶ cm ^-3 or more, or 1.0×10 ¹⁷ cm ^-3 1.0×10 ¹⁸ cm ⁻³ or less, 5.0×10 ¹⁷ cm ⁻³ or less, 2.0×10 ¹⁷ cm ⁻³ or less, or 1.0×10 ¹⁷ cm ⁻³ or less can be

<Peripheral area>
The peripheral area is an area surrounding the central area. The peripheral region has a lower donor density than the central region.

The donor density in the peripheral region may be 5.0×10 ¹⁵ cm ⁻³ or less.

The donor density in the peripheral region may be less than or equal to 5.0×10 ¹⁵ cm ⁻³ and greater than or equal to 0.0 cm ⁻³ .

The donor density in the peripheral region may be 5.0×10 ¹⁵ cm ⁻³ or less, or 1.0×10 ¹⁵ cm ⁻³ or less, or 0.0×10 10 cm ⁻³ or more, or 5.0×10 ¹⁰ cm ⁻³ . 2.0×10 ¹⁴ cm ⁻³ or more, or 1.0×10 ¹⁵ cm ⁻³ or more.

The peripheral region can be doped with acceptors so that the peripheral region has a lower donor density than the central region. In this case, for example, after forming an n-type gallium oxide semiconductor layer uniformly doped with donors, a portion of the n-type gallium oxide semiconductor layer that is to be the peripheral region is subsequently doped with acceptors, thereby simplifying the process. A central region and a peripheral region can be formed in the .

Doping of the acceptor into the n-type gallium oxide semiconductor layer is performed, for example, before stacking the first p-type nickel oxide semiconductor layer or the first and second p-type nickel oxide semiconductor layers on the n-type gallium oxide semiconductor layer. It may be performed by ion implantation.

The acceptor can be N, or Mg, for example.

《Electrode layer》
The electrode layer is laminated on the n-type gallium oxide semiconductor layer. The electrode layer forms a Schottky junction with the n-type gallium oxide semiconductor layer in the central region when the semiconductor device is viewed from the stacking direction.

The electrode layer can be made of any material capable of forming a Schottky junction with the n-type gallium oxide semiconductor layer at least at the portion in contact with the n-type gallium oxide semiconductor layer.

Examples of materials capable of forming a Schottky junction with the n-type gallium oxide semiconductor layer include, but are not limited to, Ti, Ni, Fe, Cu, Mo, W, Pt, and the like.

The electrode layer may be formed on the n-type gallium oxide semiconductor layer by any film forming method, for example. The film forming method for forming the electrode layer is, for example, physical vapor deposition, more specifically vacuum vapor deposition, molecular beam vapor deposition, ion plating, ion beam vapor deposition, conventional sputtering, magnetron sputtering, or ion beam sputtering. can be

It should be noted that the semiconductor device of the present disclosure may have an n ⁺ -type gallium oxide substrate and another electrode layer on the opposite side of the surface of the n-type gallium oxide semiconductor layer to the side on which the electrode layers are stacked. can. In the following, the n ⁺ -type gallium oxide substrate is omitted for simplicity.

This separate electrode layer can form an ohmic contact with the n-type gallium oxide semiconductor layer at least at a portion in contact with the n-type gallium oxide semiconductor layer.

This separate electrode layer can be made of any material capable of forming an ohmic contact with the n-type gallium oxide semiconductor layer at least at the portion in contact with the n-type gallium oxide semiconductor layer.

Materials capable of forming an ohmic contact with the n-type gallium oxide semiconductor layer include, but are not limited to, Ti and the like.

This separate electrode layer can also be formed by the same method as the electrode layer.

<<First p-type nickel oxide semiconductor layer>>
The semiconductor device of the present disclosure includes a first p-type nickel oxide semiconductor laminated on the n-type gallium oxide semiconductor layer so as to be partially positioned between the n-type gallium oxide semiconductor layer and the electrode layer. has layers. The first p-type nickel oxide semiconductor layer has an outer peripheral edge on the peripheral region side in the peripheral region when the semiconductor device is viewed from the stacking direction.

The first p-type nickel oxide semiconductor layer can be doped with an acceptor.

The acceptor can be Li, Cu or Ag, for example.

The acceptor density in the first p-type nickel oxide semiconductor layer can be 1.0×10 ¹⁸ cm ⁻³ or more.

The acceptor density in the first p-type nickel oxide semiconductor layer may be 1.0×10 ¹⁸ cm ⁻³ or more and 1.0×10 ²⁰ cm ⁻³ or less.

The acceptor density in the first p-type nickel oxide semiconductor layer is 1.0×10 ¹⁸ cm ⁻³ or more, 2.0×10 ¹⁸ cm ⁻³ or more, 5.0×10 ¹⁸ cm ⁻³ or more, or 1.0×10 18 cm −3 or more. It may be 0×10 ¹⁹ cm ⁻³ or more, 1.0×10 ²⁰ cm ⁻³ or less, 5.0×10 ¹⁹ cm ⁻³ or less, 2.0×10 ¹⁹ cm ⁻³ or less, or 1.0 It may be x10 ¹⁹ cm ^-3 or less.

Doping of the acceptor into the first p-type nickel oxide semiconductor layer can be performed, for example, by doping during film formation.

When viewed in the stacking direction, the first p-type nickel oxide semiconductor layer can be positioned across the central region and the peripheral region. As a result, when the semiconductor device is viewed from the stacking direction, the first p-type nickel oxide semiconductor layer has a portion in the central region and a portion in the peripheral region.

Here, as shown in FIG. 3, in the semiconductor device 1 of the present disclosure, the drift layer thickness of the central region 11 of the n-type gallium oxide semiconductor layer 10 is t (not including the n ⁺ gallium oxide semiconductor layer), In addition, it is preferable that x/t>0.50, where x is the width of the portion of the first p-type nickel oxide semiconductor layer 40 located in the central region 11 . In addition, "thickness" means the maximum thickness of the drift layer. Also, "width" means the maximum width.

Note that FIG. 3 is not meant to limit the semiconductor device of the present disclosure.

When the portion of the first p-type nickel oxide semiconductor layer in the central region is small, that is, when x/t is small, the breakdown voltage of the semiconductor device can be improved. increases.

When x/t>0.50, the withstand voltage can be improved while maintaining the resistivity of the semiconductor device.

Also, x/t≦2.00 may be satisfied.

x/t can be greater than 0.50, 0.80 or greater, 1.00 or greater, or 1.50 or greater, and 2.00 or less, 1.80 or less, 1.60 or less, or 1.50 or less can be

The width of the first p-type nickel oxide semiconductor layer may be, for example, 1.0 μm to 10.0 μm. In addition, "width" means the maximum width.

The width of the first p-type nickel oxide semiconductor layer may be 1.0 μm or more, 2.0 μm or more, 3.0 μm or more, or 5.0 μm or more, and may be 10.0 μm or less, 8.0 μm or less, 60.0 μm or less. It may be 0 μm or less, or 5.0 μm or less.

Note that the first p-type nickel oxide semiconductor layer is stacked in a recess of a trench structure formed on the surface of the n-type gallium oxide semiconductor layer on which the electrode layer is stacked, for example. can be done.

<<Second p-type nickel oxide semiconductor layer>>
In the semiconductor device of the present disclosure, the peripheral region of the n-type gallium oxide semiconductor layer on the side where the first p-type nickel oxide semiconductor layer is laminated is spaced apart from each other in the direction from the central region to the peripheral region. , a plurality of second p-type nickel oxide semiconductor layers. The plurality of second p-type nickel oxide semiconductor layers can function as a peripheral breakdown voltage structure together with the first p-type nickel oxide semiconductor layer.

The acceptor density in the second p-type nickel oxide semiconductor layer may be the same as the acceptor density in the first p-type nickel oxide semiconductor layer.

The width of the second p-type nickel oxide semiconductor layer may be, for example, 1.0 μm to 10.0 μm. In addition, "width" means the maximum width.

The width of the second p-type nickel oxide semiconductor layer may be 1.0 μm or more, 2.0 μm or more, 3.0 μm or more, or 4.0 μm or more, and may be 10.0 μm or less, 9.0 μm or less, 80.0 μm or less. It may be 0 μm or less, or 7.0 μm or less.

The distance between the second p-type nickel oxide semiconductor layers adjacent to each other and/or between the first p-type nickel oxide semiconductor layer and the second p-type nickel oxide semiconductor layer adjacent to each other is, for example, 0.5 μm to 5 μm. 0 μm. Note that the "interval" means the shortest distance between adjacent p-type nickel oxide semiconductor layers.

The spacing may be 0.5 μm or more, 1.0 μm or more, 1.5 μm or more, or 2.0 μm or more, and 5.0 μm or less, 4.5 μm or less, 4.0 μm or less, or 3.5 μm or less. It's okay.

Note that the second p-type nickel oxide semiconductor layer is laminated in a concave portion of a trench structure formed on the surface of the n-type gallium oxide semiconductor layer on which the electrode layer is laminated, for example. can be done.

《Trench structure》
The n-type gallium oxide semiconductor layer can have a plurality of trench structures on the side where the first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are laminated. The first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers can be laminated within the recess of the trench structure.

A trench structure can be formed, for example, by etching an n-type gallium oxide semiconductor layer. The etching can be performed by masking the portion of the surface of the n-type gallium oxide semiconductor layer that will be the convex portion of the trench structure. After etching, the masking is removed. Thereafter, a p-type nickel oxide semiconductor layer is deposited on the surface of the n-type gallium oxide semiconductor layer by, for example, physical vapor deposition. Finally, the p-type nickel oxide semiconductor layer laminated on the convex portion of the trench structure is removed while leaving the p-type nickel oxide semiconductor layer laminated in the concave portion of the trench structure. Thereby, a structure in which the first and second p-type nickel oxide semiconductor layers are stacked in the concave portion of the trench structure can be formed.

<<Method for Manufacturing Semiconductor Device>>
A method of manufacturing a semiconductor device according to the present disclosure includes forming a peripheral region of an n-type gallium oxide semiconductor layer by reducing the donor density by ion irradiation or heating in an oxygen atmosphere.

<Ion irradiation>
A method of manufacturing a semiconductor device according to the present disclosure includes forming a peripheral region of an n-type gallium oxide semiconductor layer by reducing the donor density by ion irradiation.

In the method of manufacturing a semiconductor device according to the present disclosure, a precursor of an n-type gallium oxide semiconductor layer, eg, a gallium oxide layer having a predetermined donor density, is irradiated with ions to reduce the donor density in the portion.

In the ion irradiation, ions of an acceptor element, hydrogen, or helium may be irradiated. Examples of acceptor elements include Mg, N, and Ga.

When hydrogen or helium is irradiated in the ion irradiation, the donor can be reduced to a deeper region of the gallium oxide semiconductor layer.

Although the n-type gallium oxide semiconductor layer may be annealed after the ion irradiation, it is preferable not to anneal from the viewpoint of improving productivity. The “annealing treatment” is, for example, heat treatment in an inert gas atmosphere. The heat treatment temperature of the “annealing treatment” is, for example, 800° C. or higher.

<Heating in an oxygen atmosphere>
A method of manufacturing a semiconductor device according to the present disclosure includes forming a peripheral region of an n-type gallium oxide semiconductor layer by heating in an oxygen atmosphere.

In the method for manufacturing a semiconductor layer of the present disclosure, the principle that the donor density can be reduced by heating in an oxygen atmosphere is not limited to this, but defects that compensate for donors are generated on the surface of the gallium oxide layer. It is thought that this is due to the lower donor density.

In the method for manufacturing a semiconductor device of the present disclosure, a precursor of an n-type gallium oxide semiconductor layer, for example, a gallium oxide layer having a predetermined donor density is heated in an oxygen atmosphere to form an n-type gallium oxide semiconductor layer. forming the peripheral region of The central region of the n-type gallium oxide semiconductor layer has a higher donor density than the peripheral region. , the donor density should be lowered only in the locations that should be the peripheral regions.

“Under an oxygen atmosphere” means an atmosphere containing oxygen, and may be, for example, an air atmosphere. The concentration of oxygen in the oxygen atmosphere is not particularly limited, but for example, the volume ratio of oxygen to the entire atmosphere can be 5.0% to 40.0%. The volume ratio of oxygen may be 5.0% or more, 10.0% or more, 15.0% or more, or 20.0% or more, and may be 40.0% or less, 35.0% or less, 30.0% or more. % or less, or 25.0% or less.

The heating temperature is not particularly limited as long as the temperature is high enough to reduce the donor density of the gallium oxide layer.

The heating temperature may be, for example, 600°C to 900°C. The heating temperature may be 600° C. or higher, 650° C. or higher, 675° C. or higher, or 700° C. or higher, and may be 900° C. or lower, 850° C. or lower, 800° C. or lower, or 750° C. or lower.

Note that the heating may be performed before or after forming the first or second p-type nickel oxide semiconductor layer on the n-type gallium oxide semiconductor layer. In some cases, it is preferred to heat prior to nickel oxide formation.

<<Examples 1 to 6 and Comparative Examples 1 to 3>>
<Comparative Example 1>
A Schottky diode was formed by forming a Pt electrode layer on an n-type gallium oxide semiconductor layer having a donor density Nd of 1.2×10 ¹⁶ cm ⁻³ . Although the n-type gallium oxide semiconductor layer is held on the n ⁺ -type gallium oxide semiconductor substrate (650 μm thick), it is omitted in the figure. This was used as a semiconductor device of Comparative Example 1. The thickness of the n-type gallium oxide semiconductor layer was 10 μm.

<Comparative Example 2>
The same as Comparative Example 1 except that a p-type nickel oxide semiconductor layer having an effective acceptor density Na of 1.0×10 ¹⁹ cm ⁻³ was formed as a guard ring (GR) at the end of the Schottky diode. Thus, a semiconductor device of Comparative Example 2 was manufactured.

Specifically, the semiconductor device 3 of Comparative Example 2 had a configuration as shown in FIG.

As shown in FIG. 4 , in the semiconductor device 3 of Comparative Example 2, the first electrode layer 20 is stacked on one surface of the n-type gallium oxide semiconductor layer 10 . The first electrode layer 20 forms a Schottky junction with the n-type gallium oxide semiconductor layer 10 . In the semiconductor device 3 of Comparative Example 2, the second electrode layer 30 is stacked on the other surface of the n-type gallium oxide semiconductor layer 10 . The second electrode layer 30 forms an ohmic junction with the n-type gallium oxide semiconductor layer 10 .

In FIG. 4, the semiconductor device 3 of Comparative Example 2 has a guard ring 60 arranged so as to be partially positioned between the n-type gallium oxide semiconductor layer 10 and the first electrode layer 20. there is The guard ring layer is a p-type nickel oxide semiconductor layer.

<Comparative Example 3>
At the end of the Schottky diode, a plurality of p-type nickel oxide semiconductor layers having an effective acceptor density Na of 1.0×10 ¹⁹ cm ⁻³ are formed as a peripheral breakdown voltage structure to form a field limiting ring (FLR). A semiconductor device of Comparative Example 3 was manufactured in the same manner as in Comparative Example 1, except that the semiconductor device of Comparative Example 3 was manufactured. Here, the width of the p-type nickel oxide semiconductor layer was 2.5 μm. Moreover, the distance between the p-type nickel oxide semiconductor layers adjacent to each other was 5.0 μm.

Specifically, the semiconductor device 4 of Comparative Example 3 had a configuration as shown in FIG.

<Example 1>
A semiconductor device of Example 1 was fabricated in the same manner as in Comparative Example 3, except that the donor density Nd in the peripheral region of the n-type gallium oxide semiconductor layer was lowered. As a result, the donor density Nd of the portion of the n-type gallium oxide semiconductor layer surrounding the outer peripheral edge of the p-type nickel oxide semiconductor layer sandwiched between the electrode layer and the n-type gallium oxide semiconductor layer on the side of the peripheral region is In the n-type gallium oxide semiconductor layer, the donor density Nd of the portion surrounding the other portion of the p-type nickel oxide semiconductor layer is lower than Nd.

In the semiconductor device of Example 1, the central region had a donor density of 1.2×10 ¹⁶ cm ⁻³ and the peripheral region had an effective donor density of 0.0 cm ⁻³ .

The semiconductor device 5 of Example 1 had a configuration as shown in FIG. Here, in the semiconductor device 5 of Example 1, the center of the p-type nickel oxide semiconductor layer sandwiched between the electrode layer and the n-type gallium oxide semiconductor layer with respect to the thickness t of the n-type gallium oxide semiconductor layer 10 The ratio x/t of the width x of the portion in the region was 1.50.

<Example 2>
A semiconductor device of Example 2 was fabricated in the same manner as in Example 1, except that the donor density in the peripheral region was 1.0×10 ¹⁵ cm ⁻³ .

<Example 3>
A semiconductor device of Example 3 was fabricated in the same manner as in Example 1, except that the donor density in the peripheral region was 5.0×10 ¹⁵ cm ⁻³ .

<Example 4>
A semiconductor device of Example 4 was fabricated in the same manner as in Example 1 except that x/t was set to 0.8.

<Example 5>
A semiconductor device of Example 5 was fabricated in the same manner as in Example 1 except that x/t was set to 0.53.

<Example 6>
A semiconductor device of Example 5 was fabricated in the same manner as in Example 1 except that x/t was set to 0.50.

<Withstanding voltage test>
A voltage was applied in the forward direction to the semiconductor device of each example, and the voltage when dielectric breakdown occurred was measured.

<Resistivity measurement test>
The resistivity was measured for the semiconductor device of each example.

<result>
Table 1 shows the configuration of the semiconductor device of each example and the results of the withstand voltage test and the resistivity measurement test.

As shown in Table 1, in Comparative Example 1 which did not have a peripheral withstand voltage structure, dielectric breakdown occurred at the edge of the electrode layer at only 78V.

Comparative Examples 2 and 3, which had a peripheral breakdown voltage structure but had no difference in donor density between the central region and the peripheral region, had higher breakdown voltages than Comparative Example 1 (694 V and 844 V, respectively).

In Examples 1 to 6, which had a peripheral breakdown voltage structure and the donor density in the peripheral region was lower than the donor density in the central region, the breakdown voltage was 1200 V or more, especially 1500 V in Examples 1, 2, and 4 to 6. Thus, the pressure resistance was much higher than that of Comparative Examples 1-3.

In Examples 1 to 5, in which x/t was greater than 0.5, the resistivity was 16.0 mΩcm ² , which was maintained at the same level as Comparative Example 1. On the other hand, in Example 6 in which x/t was 0.5, the resistivity was 16.1 mΩcm ² and an increase in resistivity was observed.

Although not shown as an example, further reduction of x/t resulted in a much higher breakdown voltage than Comparative Examples 1-3, but a further increase in resistivity was observed.

<<Examples 7 and 8, and Comparative Example 4>>
<Example 7>
A semiconductor device of Example 7 was manufactured as follows.

A metal mask was formed in the center of the gallium oxide layer with a donor density of 1.2×10 ¹⁶ cm ⁻³ , ion implantation using Mg ions was performed only in the peripheral portion, and subsequent annealing was not performed. After that, a peripheral withstand voltage structure was formed in the same manner as in Comparative Example 3.

Here, ion implantation was performed at 140 keV and a dose of 5×10 ¹⁴ cm ⁻² . As a result of this ion implantation, ion implantation defects were formed at a depth of 500 nm from the surface, and as a result, the donor density decreased and semi-insulation was achieved as shown in FIG. As shown in FIG. 7, the depth of the region where the donor density decreased was 0.5 μm from the surface of the gallium oxide layer.

The semiconductor device of Example 7 had a configuration similar to that shown in FIG.

When a breakdown voltage test was conducted on the semiconductor device of Example 7, the dielectric breakdown voltage was improved to 970V.

<Example 8>
A semiconductor device of Example 8 was manufactured as follows.

A metal mask was formed in the center of the gallium oxide layer with a donor density of 1.2×10 ¹⁶ cm ⁻³ and heat treatment was performed at 700° C. for 10 minutes in an air atmosphere. As a result, a decrease in donor density was observed on the surface of the gallium oxide substrate as shown in FIG. As shown in FIG. 8, the depth of the regions where the donor density was reduced ranged from 1.5 μm to 2.0 μm.

A semiconductor device as shown in FIG. 6 was formed on the gallium oxide layer thus obtained, and a withstand voltage test was conducted.

<Comparative Example 4>
A semiconductor device of Comparative Example 4 was manufactured as follows.

A NiO layer with a thickness of 100 nm with an acceptor density of 1-2×10 ²⁰ cm ⁻³ was formed on a gallium oxide layer with a donor density of 1.2×10 ¹⁶ cm ⁻³ to form a pn diode.

5, NiO layers (second p-type nickel oxide semiconductor layers) with a width of 2.5 μm are arranged at intervals of 5.0 μm in the peripheral region 13 of the semiconductor device 2 of Comparative Example 4, A peripheral voltage-resistant structure was formed. Ni was formed on NiO to form an ohmic electrode.

In this semiconductor device 2, since the donor density of the peripheral breakdown voltage structure formed in the peripheral region 13 is not lowered, dielectric breakdown occurred at 800V as a result of the breakdown voltage test.

1 to 5 semiconductor device 10 n-type gallium oxide semiconductor layer 11 central region 13 peripheral region 20 first electrode layer 30 second electrode layer 40 first p-type nickel oxide semiconductor layer 50 second p-type nickel oxide semiconductor layer 60 Guard ring C Central area side O Peripheral area side

Claims (15)

an n-type gallium oxide semiconductor layer having a central region and a peripheral region having a lower donor density than the central region;
an electrode layer stacked on the n-type gallium oxide semiconductor layer and forming a Schottky junction with the n-type gallium oxide semiconductor layer in the central region when viewed in the stacking direction; laminated on the n-type gallium oxide semiconductor layer so as to be partially located between the n-type gallium oxide semiconductor layer and the electrode layer, and when viewed from the lamination direction, the peripheral region a semiconductor device having a first p-type nickel oxide semiconductor layer, the outer peripheral edge of which is located in the peripheral region. 2. The semiconductor device according to claim 1, wherein said peripheral region has a donor density of 5.0*10< ¹⁵ >cm<^-3> or less. 3. The semiconductor device according to claim 1, wherein the central region has a donor density of 1.0*10< ¹⁶ >cm< ^-3 > or more. 4. The semiconductor according to any one of claims 1 to 3, wherein said first p-type nickel oxide semiconductor layer is positioned across said central region and said peripheral region when viewed in the stacking direction. Device. When the thickness of the central region of the n-type gallium oxide semiconductor layer is t, and the width of the portion of the first p-type nickel oxide semiconductor layer located in the central region is x, x/t 5. The semiconductor device of claim 4, wherein >0.50. 6. The semiconductor device according to claim 1, wherein said donor is Sn or Si. 7. The semiconductor device according to claim 1, wherein said peripheral region is doped with acceptors and has a lower donor density than said central region. 8. The semiconductor device according to claim 7, wherein said acceptor is N or Mg. In the peripheral region on the side of the n-type gallium oxide semiconductor layer on which the first p-type nickel oxide semiconductor layer is laminated, a plurality of 9. The semiconductor device according to claim 1, comprising a second p-type nickel oxide semiconductor layer of The n-type gallium oxide semiconductor layer has a plurality of trench structures on the side where the first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are laminated,
The first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are respectively stacked in recesses of the trench structure,
10. The semiconductor device according to claim 9. The semiconductor device according to any one of claims 1 to 10, which is a pn diode, a JBS diode, a metal oxide semiconductor field effect transistor or a junction field effect transistor. 12. The method according to any one of claims 1 to 11, comprising forming the peripheral region of the n-type gallium oxide semiconductor layer by reducing the donor density by ion irradiation or heating in an oxygen atmosphere. A method of manufacturing a semiconductor device. 13. The method according to claim 12, wherein in said ion irradiation, ions of an acceptor element, hydrogen, or helium are irradiated. 14. The method according to claim 12, wherein the n-type gallium oxide semiconductor layer is annealed after the ion irradiation. 14. The method according to claim 12, wherein the n-type gallium oxide semiconductor layer is not annealed after the ion irradiation.

Images