JP2015060841A - Silicon carbide semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit fluctuation of electrical characteristics in a silicon carbide semiconductor device, which is caused from fluctuation in activation rate of an ion-implanted impurity.SOLUTION: A silicon carbide semiconductor device 10 comprises: a base region 3 which is formed by ion implanting an impurity into a drift layer 2 composed of a silicon carbide and has an impurity concentration distribution of a retro-grade profile. After performing a heat treatment for electrically activating the impurity ion implanted into the base region 3, a surface layer of a semiconductor layer, which is damaged by the heat treatment is removed. At this time, a thickness of the drift layer 2 to be removed is determined based on a calculation result of an activation rate of the impurity.

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a technique for suppressing variation in electrical characteristics of a silicon carbide semiconductor device.

  Silicon carbide is known as a semiconductor material that has an excellent physical property value and enables the realization of a power device with high breakdown voltage and low loss. In order to control the conductivity of the silicon carbide crystal, ion implantation of impurities and heat treatment for activating the implanted impurities are effective.

  As the impurity implanted into the silicon carbide crystal, aluminum is mainly used as the p-type impurity, and nitrogen is mainly used as the n-type impurity. The temperature at which the implanted impurities are activated is about 1700 ° C. in the case of aluminum and about 1500 ° C. in the case of nitrogen. In order to electrically activate the impurities in the silicon carbide crystal, the temperature is extremely high. Heat treatment is required.

  In general, in heat treatment at a high temperature of about 1700 ° C., the temperature inside the furnace is often measured by using a radiation thermometer from the outside of the furnace and fed back to the heater output. However, in this method, silicon and carbon released from the silicon carbide substrate, carbon generated from the carbon or graphite film protecting the silicon carbide substrate surface during heat treatment, and substances generated from the members constituting the inner wall of the furnace are included. As a result, the opening window for the monitor is fogged and the measurement accuracy is lowered. In addition, a method of directly measuring the temperature in the furnace using a thermocouple can be used, but at a high temperature of 1700 ° C. or higher, the thermocouple is consumed heavily by repeated heat treatment, and stable temperature management is performed over a long period of time. It ’s difficult.

  The activation rate of the ion-implanted impurity is sensitive to temperature. According to Non-Patent Document 1 below, the temperature dependency of the activation rate of aluminum is 0.56% in the range of 1600 ° C. to 1700 ° C. / 7 ° C within the range of 1700 ° C to 1800 ° C. For example, when the heat treatment temperature is 1700 ° C., a difference of 4% to 29% occurs in the activation rate of impurities even if an error of only 3% occurs in the set temperature.

  The difference in the activation rate of the impurities causes a difference in the threshold voltage of a semiconductor device such as a MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor). Although depending on the concentration profile of the ion-implanted impurity, when the impurity concentration is constant in the depth direction, the variation in threshold voltage is equivalent to the variation in activation rate.

  In order to suppress variation in the activation rate of impurities in the silicon carbide substrate, it is conceivable to sufficiently increase the heat treatment time. However, even if the surface of the silicon carbide substrate is protected with a carbon or graphite film as in Patent Document 1, excessive heat treatment increases the roughness of the surface of the silicon carbide and effectively moves the channel of the MOSFET formed using the surface. The degree decreases (Non-Patent Document 2).

  Silicon carbide semiconductor devices still have a large yield reduction due to crystal defects, and in many cases, a plurality of elements having a small area are connected in parallel to obtain a large current. Variations in threshold voltage and on-resistance not only lower the current-carrying capacity, but also cause current concentration at a specific location and cause breakdown. Therefore, in order to utilize the silicon carbide semiconductor device, it is indispensable to suppress the characteristic variation for each element.

  In addition to silicon carbide semiconductors, after forming a plurality of unit FET (Field Effect Transistor) structures on the wafer, gate threshold voltage is measured for each unit FET structure, and impurity activation is performed based on the measurement results. Patent Document 2 below proposes a technique for compensating for the unevenness of the characteristics of the unit FET structure by setting the heating conditions, thereby making the characteristics of the semiconductor device uniform.

JP 2007-115875 A JP 2008-306047 A

Kimoto et al., Electrical Engineering C, Vol.122, No.1, 2002, pp.17-22. Yu Anne Zeng, Marvin H. White, Mrinal K. Das, "Electron transport modeling in the inversion layers of 4H and 6H-SiC MOSFETs on implanted regions," Solid-State Electronics 49 (2005) 1017-1028. M. Rambach, F. Schmid, M. Krieger, L. Frey, AJ Bauer, G. Pensl, H. Ryssel, "Implantation and annealing of aluminum in 4H silicon carbide," Nuclear Instruments and Methods in Physics Research B 237 (2005 ) 68-71.

  As described above, high-temperature heat treatment is effective for controlling the conductivity of the silicon carbide crystal for impurity implantation by ion implantation and electrical activation. However, it is difficult to directly monitor the furnace temperature in a high-temperature heat treatment, and a difference between the set temperature and the actual temperature tends to occur. Further, since the temperature is high, a slight error becomes a large temperature difference.

  It has been found that the activation rate of impurities in the silicon carbide crystal strongly depends on the heat treatment temperature for activation, and varies greatly due to temperature control errors in the heat treatment. The variation in the activation rate of the impurity results in a variation in the effective impurity concentration, which greatly affects the electrical characteristics of the semiconductor device, and in particular causes variations in the threshold voltage and on-resistance.

  The present invention has been made to solve the above-described problems. In a silicon carbide semiconductor device, electrical characteristics (threshold voltage and channel associated therewith) due to variations in the activation rate of ion-implanted impurities. The purpose is to suppress variations in mobility, on-resistance, and the like.

  A method for manufacturing a silicon carbide semiconductor device according to a first aspect of the present invention includes: (a) Impurity concentration distribution of a retrograde profile is obtained by ion-implanting impurities into a semiconductor layer made of silicon carbide formed on a substrate. A step of forming a base region, a step of performing a heat treatment for electrically activating the impurity ion-implanted into the semiconductor layer, and a step of activating the impurity after the step of (b). And a step (d) of removing the surface of the semiconductor layer, and the thickness of removing the surface of the semiconductor layer in the step (d) is calculated in the step (c). It is determined based on the activation rate of the impurities.

  A method for manufacturing a silicon carbide semiconductor device according to a second aspect of the present invention includes: (a) forming a base region by ion-implanting impurities into a semiconductor layer made of silicon carbide formed on a substrate; b) performing a heat treatment for electrically activating the impurities ion-implanted into the semiconductor layer; (c) calculating an activation rate of the impurities after the step (b); And a step of forming a gate oxide film on the surface of the semiconductor layer, and the specific parameter of the gate oxide film formed in the step (d) is the activity of the impurity calculated in the step (c) It is determined based on the conversion rate.

  According to the present invention, it is possible to prevent a reduction in reproducibility of electrical characteristics such as a threshold voltage and channel mobility and on-resistance associated therewith due to variation in activation rates of impurities implanted into the semiconductor layer.

It is the graph which showed the trade-off between the threshold voltage of silicon carbide MOSFET, and the effective mobility of a channel. It is the graph which showed the impurity concentration profile with respect to the depth direction of a board | substrate when ion-implanting an impurity so that it may become a retrograde profile in a base region. It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on embodiment of this invention. It is process drawing which shows the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment of this invention. It is process drawing which shows the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment of this invention. It is process drawing which shows the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment of this invention. It is process drawing which shows the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment of this invention. It is process drawing which shows the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment of this invention. It is process drawing which shows the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment of this invention. It is process drawing which shows the manufacturing method of the silicon carbide semiconductor device which concerns on embodiment of this invention. It is the graph which showed the surface roughness of the silicon carbide board | substrate with respect to the heat processing temperature.

<Embodiment 1>
FIG. 1 is a graph showing a trade-off between threshold voltage and effective channel mobility in a MOSFET manufactured using silicon carbide. MOSFETs manufactured using silicon carbide have a stronger trade-off relationship between threshold voltage and effective mobility than those manufactured using silicon. For this reason, a shift in the activation rate of impurities in the semiconductor layer of silicon carbide not only affects the threshold voltage but also affects the effective mobility. Since the on-resistance of the MOSFET depends on both the threshold voltage and the effective mobility, the variation in the on-resistance due to the variation in the activation rate appears very remarkably in the MOSFET manufactured using silicon carbide.

  The activation rate of the impurity in the silicon carbide crystal can be calculated from the electrical characteristics of the region into which the impurity is ion-implanted. For example, the effective acceptor concentration can be calculated by measuring the capacitance of the ion-implanted region of the acceptor type impurity using a mercury probe after the heat treatment for activating the impurity, and the activation of the impurity from the acceptor concentration The rate can be calculated. Further, as shown in Non-Patent Document 3 above, if the sheet resistance of the region into which the acceptor-type impurity is ion-implanted is measured after the heat treatment for activating the impurity, the heat treatment adds to the silicon carbide semiconductor layer. Since the amount of heat generated can be calculated, the activation rate of impurities can also be calculated from the amount of heat.

Next, the relationship between the activation rate of the impurities ion-implanted into the base region of the MOSFET and the threshold voltage will be described. First, a case where the acceptor concentration in the base region is constant in the depth direction will be described. Assuming that the activation rate of the ion-implanted aluminum as an acceptor is 80% and there is no fixed charge in the gate oxide film and no interface state between the gate oxide film and the semiconductor layer, the thickness of the gate oxide film is In order to obtain a threshold voltage of 3 V at 50 nm, it is only necessary that the acceptor exists at a concentration of 7.2 × 10 ¹⁶ cm ⁻³ from the surface of the semiconductor layer to the depth at which the depletion layer extends. When the activation rate is 70% at the same acceptor concentration, the threshold voltage is 2.76V, and when the activation rate is 60%, the threshold voltage is reduced to 2.51V.

Thus, the threshold voltage decreases as the impurity activation rate decreases, but the threshold voltage can also be controlled by the thickness of the gate oxide film. If the gate oxide film is thickened, the threshold voltage is increased. it can. As in the above example, when the acceptor concentration is 7.2 × 10 ¹⁶ cm ⁻³ and the activation rate is 60%, the threshold voltage can be 3 V if the thickness of the gate oxide film is 61 nm. The thickness of the gate oxide film can be adjusted by the temperature and time for thermal growth when the gate oxide film is formed by thermal oxidation, and is adjusted by the deposition time when the gate oxide film is formed by chemical vapor deposition. it can.

Next, the case where the acceptor concentration distribution in the base region is a retrograde profile having a low concentration on the surface and a high concentration in a deep part will be described. For example, when a retrograde profile as shown in FIG. 2 is formed by ion implantation at 600 keV, the surface is removed by sacrificial oxidation treatment, and the interface between the gate oxide film and the semiconductor layer is deepened from the surface of the semiconductor layer before sacrificial oxidation treatment. If the thickness of the gate oxide film is 50 nm and the dose is 1.41 × 10 ¹⁴ cm ⁻² , the threshold value is 80% of the activation rate. The voltage becomes 3V. Under the same conditions, when the activation rate becomes 70%, the threshold voltage becomes 2.86V, and when the activation rate becomes 60%, the threshold voltage decreases to 2.71V. It can be seen that by making the acceptor concentration distribution in the base region a retrograde profile, the transistor characteristics become slightly stronger against variations in the activation rate of the impurities than when the acceptor concentration is constant in the depth direction.

  In addition, when the impurity concentration distribution in the base region is a retrograde profile, the threshold voltage can be controlled by changing the thickness (depth) for removing the substrate surface without changing the gate oxide film formation conditions. it can. For example, in the case of the retrograde profile shown in FIG. 2, when the activation rate is 60%, the thickness removed by the sacrificial oxidation process is increased by 27 nm, and the interface between the gate oxide film and the semiconductor layer is the semiconductor before the sacrificial oxidation process. If the position is 127 nm deep from the surface of the layer (broken line B), the threshold voltage can be 3V.

  In the first embodiment, a base region having a retrograde profile impurity concentration distribution is formed in a silicon carbide semiconductor layer, and then the thickness of the surface layer of the semiconductor layer is removed by sacrificial oxidation treatment or dry etching. By adjusting according to the activation rate of the impurity implanted into the gate electrode, the threshold voltage, the channel mobility associated therewith, and the electrical characteristics such as on-resistance are set to desired values.

  FIG. 3 is a cross sectional view showing a configuration of silicon carbide semiconductor device 10 formed by the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Here, MOSFET is shown as silicon carbide semiconductor device 10.

  Silicon carbide semiconductor device 10 is formed using substrate 1 made of silicon carbide of the first conductivity type. A drift layer 2, which is a semiconductor layer made of silicon carbide of the first conductivity type, is formed on the substrate 1, and base regions 3 of the second conductivity type are separated from each other on the upper layer portion of the drift layer 2. Is formed. A source region 4 of the first conductivity type is formed on the surface of each base region 3. Below, the part which consists of the board | substrate 1 and the drift layer 2 in which the base region 3 and the source region 4 were formed may be called a "base | substrate."

  A gate oxide film 5 is formed on the drift layer 2 so as to straddle adjacent base regions 3, and a gate electrode 6 is formed thereon. The gate oxide film 5 and the gate electrode 6 cover the drift layer 2 between the adjacent base regions 3, and their end portions reach the source region 4 in the base region 3. A source electrode 7 electrically connected to the source region 4 is formed on the drift layer 2. Further, a drain electrode 8 is formed on the lower surface of the substrate 1.

  When a voltage is applied to gate electrode 6 of silicon carbide semiconductor device 10, an inversion channel layer is formed on the surface of base region 3 located under gate electrode 6, and thereby, between source region 4 and drift layer 2. A path for the charge to flow is created. Hereinafter, a region where the inversion channel layer of the base region 3 is formed is referred to as a “channel region”.

  When silicon carbide semiconductor device 10 is an n-channel MOSFET (when the first conductivity type is n-type and the second conductivity type is p-type), the carriers are electrons. In this case, electrons flowing from the source region 4 through the inversion channel layer to the drift layer 2 reach the drain electrode 8 through the drift layer 2 and the substrate 1 according to the electric field generated by the voltage applied to the drain electrode 8. . That is, when a voltage is applied to the gate electrode 6, a current flows from the drain electrode 8 to the source electrode 7.

  When silicon carbide semiconductor device 10 is a p-channel MOSFET (when the first conductivity type is p-type and the second conductivity type is n-type), the carriers are holes. In this case, holes injected from the drain electrode 8 reach the base region 3 through the drift layer 2. The holes that have reached the base region 3 reach the source region 4 through the inversion channel layer on the surface of the base region 3 according to the potential of the source electrode 7. That is, by applying a voltage to the gate electrode 6, holes flow from the drain electrode 8 to the source electrode 7.

  Hereinafter, a method for manufacturing silicon carbide semiconductor device 10 shown in FIG. 3 will be described. 4 to 10 are process diagrams showing the manufacturing method.

First, a drift layer 2 made of a silicon carbide epitaxial layer of the first conductivity type is formed on the first conductivity type substrate 1 using an epitaxial crystal growth method (FIG. 4). The thickness of the drift layer 2 is desirably about 5 to 50 μm, and the impurity concentration of the drift layer 2 is desirably about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ . By forming the drift layer 2 under these conditions, a vertical type high breakdown voltage MOSFET having a breakdown voltage of several hundred V to 5 kV or more can be realized. As the plane orientation of the substrate 1, (0001) plane, (000-1) plane, (11-20) plane, or the like can be used. Further, as the polytype of the substrate 1, any of 4H, 6H, and 3C can be used.

  Next, a mask in which the formation region of the base region 3 is opened is formed on the drift layer 2 using photolithography. Examples of the mask material include resist, silicon dioxide, or silicon nitride. Then, the base region 3 is formed by ion-implanting impurities of the second conductivity type into the drift layer 2 using the mask as an impurity implantation blocking film (FIG. 5). FIG. 5 shows a state after removing the mask used at the time of ion implantation.

  When silicon carbide semiconductor device 10 is an n-channel MOSFET, for example, boron (B) or aluminum (Al) can be used as the second conductivity type impurity implanted into base region 3. When silicon carbide semiconductor device 10 is a p-channel MOSFET, for example, phosphorus (P) or nitrogen (N) can be used as the second conductivity type impurity implanted into base region 3.

In the present embodiment, the impurity concentration distribution of the base region 3 is set to a retrograde profile. The depth of the base region 3 is, for example, about 0.5 to 3 μm within a range not exceeding the thickness of the drift layer 2. Further, the impurity concentration of the second conductivity type in the base region 3 needs to exceed the impurity concentration of the first conductivity type in the drift layer 2 and is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

  Next, a mask in which the formation region of the source region 4 is opened is formed on the drift layer 2 using photolithography. Then, the source region 4 is formed inside each base region 3 by ion-implanting the first conductivity type impurity into the drift layer 2 using the mask as an impurity implantation blocking film (FIG. 6). FIG. 6 shows a state after removing the mask used at the time of ion implantation.

  When silicon carbide semiconductor device 10 is an n-channel MOSFET, for example, phosphorus or nitrogen can be used as the first conductivity type impurity implanted into source region 4, and silicon carbide semiconductor device 10 is a p-channel MOSFET. As the second conductivity type impurity implanted into the source region 4, for example, boron or aluminum can be used.

The depth of the source region 4 is set to be shallower than the depth of the base region 3. The impurity concentration of the first conductivity type implanted into the source region 4 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ .

  Through the steps so far, the “base” of silicon carbide semiconductor device 10 formed of substrate 1, drift layer 2, base region 3 and source region 4 is formed.

  Subsequently, the substrate is heat-treated using a heat treatment apparatus, and the impurities implanted into the substrate are electrically activated. This heat treatment is performed in an inert gas such as argon or nitrogen or in vacuum under a high temperature condition of, for example, 1500 to 2000 ° C., for example, for about 30 seconds to 1 hour. In this heat treatment, a carbon film or a graphite film may be deposited on the surface in advance in order to prevent the surface of the substrate from becoming rough.

  Next, using a heat-treated substrate or another substrate heat-treated at the same time, impurities are ion-implanted to form a base region 3 (particularly, a region where the base region 3 is exposed on the surface of the drift layer 2) or Capacitance measurement or sheet resistance measurement of another region having the same impurity concentration profile is performed. Then, based on the data obtained by this measurement, the activation rate of the second conductivity type impurity implanted into the base region 3 is calculated.

  Subsequently, the surface layer of the substrate is removed by sacrificial oxidation treatment or dry etching in order to remove damage to the surface of the substrate (the surfaces of the drift layer 2, the base region 3 and the source region 4) caused by ion implantation or heat treatment. At this time, the depth for removing the surface layer of the substrate is determined based on the calculation result of the activation rate of the impurity implanted into the base region 3. Thereby, even if the activation rate of the impurity implanted into base region 3 varies, variation in electrical characteristics such as threshold voltage of silicon carbide semiconductor device 10 can be suppressed.

  When the surface layer of the substrate is removed by dry etching, the thickness (depth) of removing the surface layer in the surface of the substrate can be changed by forming a mask with a resist or the like. As a result, even when the impurity activation rate varies within the plane of the substrate, it is possible to suppress variations in electrical characteristics such as threshold voltage of silicon carbide semiconductor device 10.

  Next, a gate oxide film 5 made of a silicon dioxide film is formed on the surface of the substrate (FIG. 7). The silicon dioxide film may be formed by a technique of depositing a silicon dioxide film on the surface of the substrate by chemical vapor deposition, or by thermally oxidizing the surface of the aircraft in an atmosphere containing oxygen. You may carry out by the method of forming.

Subsequently, nitriding treatment is performed on the gate oxide film 5. The nitridation treatment of the gate oxide film 5 is performed by at least one of nitrogen monoxide (NO) gas, dinitrogen monoxide (N ₂ O) gas, nitrogen dioxide (NO ₂ ) gas, and ammonia (NH ₃ ) gas. Alternatively, it is carried out by heat-treating the substrate in an atmosphere such as a mixed gas of two or more gases, or a mixed gas of these gases and an inert gas. The temperature of this heat treatment is desirably in the range of 1150 ° C to 1350 ° C.

  Next, a conductive film as a material for the gate electrode 6 is formed on the gate oxide film 5 and patterned by using a photoengraving technique to form the gate electrode 6 (FIG. 8). The end of the gate electrode 6 is located on the source region 4 and is patterned into a shape that covers the channel region in the base region 3 and the drift layer 2 between the base regions 3. The gate electrode 6 is preferably formed so as to overlap the source region 4 by about 10 nm to 5 μm in plan view. By doing so, the influence of the fringe effect at the end of the gate electrode 6 is suppressed, and a voltage is uniformly applied to the surface (channel region) of the base region 3, so that an inversion channel layer is reliably formed in the channel region. be able to.

  The material of the gate electrode 6 is n-type or p-type polycrystalline silicon (polysilicon), n-type or p-type polycrystalline silicon carbide, or a low resistance high material such as aluminum, titanium, molybdenum, tantalum, niobium and tungsten. Examples thereof include a melting point metal or a nitride of such a high melting point low resistance metal.

  After patterning the gate electrode 6, the gate oxide film 5 is patterned by using a photoengraving technique to expose the surface of the source region 4 and the surface of the base region 3 (parts different from the channel region) (FIG. 9). At this time, the end portion of the gate oxide film 5 after patterning may be positioned outside the end portion of the gate electrode 6 (the gate oxide film 5 has a longer shape than the gate electrode 6). Thereby, electrical isolation between the gate electrode 6 and the source electrode 7 to be formed later can be ensured.

  Next, a conductive film as a material for the source electrode 7 is formed and patterned to form the source electrode 7 on the exposed surfaces of the base region 3 and the source region 4 (FIG. 10). Finally, by forming drain electrode 8 on the back surface of substrate 1, the element structure of silicon carbide semiconductor device 10 shown in FIG. 3 is completed.

  As a material of the source electrode 7 and the drain electrode 8, aluminum, nickel, titanium, gold, or a composite thereof can be used. Further, in order to obtain ohmic contact between the source electrode 7 and the substrate 1, a heat treatment at about 1000 ° C. may be performed after the source electrode 7 and the drain electrode 8 are formed.

  As described above, in the present embodiment, the impurity concentration distribution of the second conductivity type in the base region 3 is set to the retrograde profile, and the surface layer of the substrate (the surface layer of the drift layer 2, the base region 3 and the source region 4) is sacrificed. The thickness to be removed by oxidation treatment or dry etching is determined based on the calculation result of the activation rate of the second conductivity type impurity implanted into the base region 3. That is, the position of the interface between the gate oxide film 5 and the substrate (particularly the base region 3) is adjusted according to the activation rate of the impurity. Thereby, even if the activation rate of the impurities implanted into base region 3 varies, the threshold voltage of silicon carbide semiconductor device 10 and the electrical characteristics such as channel mobility and on-resistance associated therewith are set to desired values. They can be set and their variation is suppressed. Therefore, the reproducibility of the electrical characteristics of silicon carbide semiconductor device 10 can be enhanced.

  In the present embodiment, an example is shown in which the electrical characteristics such as the threshold voltage of silicon carbide semiconductor device 10 are controlled by adjusting the thickness for removing the surface layer (damage layer) of the substrate. The electrical characteristics of the silicon semiconductor device 10 may be controlled by other methods. For example, since the threshold voltage of silicon carbide semiconductor device 10 also varies depending on the thickness of gate oxide film 5, the thickness of gate oxide film 5 is used to control the threshold voltage of silicon carbide semiconductor device 10. It may be a parameter.

The threshold voltage of silicon carbide semiconductor device 10 can also be controlled by the fixed charge density in gate oxide film 5 and the interface state density at the interface between gate oxide film 5 and the substrate (semiconductor layer). Therefore, they may be used as parameters for controlling the threshold voltage of silicon carbide semiconductor device 10. For example, when the acceptor concentration in the base region 3 is 7.2 × 10 ¹⁶ cm ⁻³ , the activation rate is 60%, and the thickness of the gate oxide film is 50 nm, the fixed charges in the gate oxide film 5 and the gate oxide film 5 Assuming that there is no interface state between the semiconductor layer and the semiconductor layer, the threshold voltage is 2.51 V. Under the same conditions, the fixed charge density and the interface state density are increased by 2.1 × 10 ¹¹ cm ^−2. Then, the threshold voltage can be 3V.

  The fixed charge density in the gate oxide film and the interface state density at the interface with the semiconductor layer can be adjusted by the conditions of the post-annealing performed after the gate oxide film is formed. The concentration, the processing temperature, the processing time, the temperature lowering atmosphere, and the like are parameters for adjusting them.

<Embodiment 2>
The value of the amount of heat applied to the silicon carbide semiconductor layer by the heat treatment can also be calculated from the surface roughness of the semiconductor layer after the heat treatment. FIG. 11 shows the surface roughness (RMS: Root-mean-square) of the semiconductor layer after the heat treatment. When the heat treatment temperature is changed from 1600 ° C. to 1750 ° C., it can be seen that the surface roughness increases as the heat treatment temperature increases. This surface roughness depends on the atmosphere in the furnace where the heat treatment is performed, the quality of the graphite or carbon film that protects the surface of the semiconductor layer, and the type and concentration of impurities to be ion-implanted, but these conditions are the same. If there is, the reproducibility of the surface roughness is high. Therefore, by acquiring these series of data, the surface roughness of the region into which the impurities are ion-implanted can be calculated, and the heat treatment temperature can be calculated from the surface roughness. If the heat treatment temperature is known, the amount of heat applied to the semiconductor layer by the heat treatment can be known, and the impurity activation rate can be calculated from the amount of heat.

  Therefore, in Embodiment 2, the surface roughness of the substrate after the heat treatment is measured before the step of removing the surface layer (damage layer) of the substrate, and the activation rate of impurities in the substrate is determined from the measurement result. The thickness of the gate oxide film 5 is adjusted based on the calculation result. Thereby, even when the activation rate of the impurity implanted into base region 3 varies, the electrical characteristics such as the threshold voltage of silicon carbide semiconductor device 10 can be adjusted to be constant.

  A method for manufacturing the silicon carbide semiconductor device according to the second embodiment will be described. First, the drift layer 2 is formed on the substrate 1 and the base region 3 and the source region 4 are formed in the drift layer 2 by a method similar to that described in Embodiment 1 with reference to FIGS. Thus, the base body of silicon carbide semiconductor device 10 is formed. Further, a heat treatment is performed to electrically activate impurities implanted into the substrate. Similarly to the first embodiment, this heat treatment is also performed in an inert gas such as argon or nitrogen or in vacuum under a high temperature condition of, for example, 1500 to 2000 ° C., for example, for about 30 seconds to 1 hour.

  In Embodiment 2, the surface of the substrate is then observed with an atomic force microscope (AFM) or the like using a heat-treated substrate or another substrate heat-treated at the same time, and the surface roughness of the substrate is determined. Ask. Then, the amount of heat applied to the substrate by heat treatment is calculated from the surface roughness of the substrate, and the activation rate of impurities in the silicon carbide crystal is calculated from the amount of heat.

  Subsequently, the surface layer of the substrate is removed to a certain depth by sacrificial oxidation treatment or dry etching in order to remove damage to the surface of the substrate (the surfaces of the drift layer 2, the base region 3 and the source region 4) caused by ion implantation or heat treatment. To do.

  Next, a gate oxide film 5 is formed on the surface of the substrate. In the second embodiment, the thickness of the gate oxide film 5 is determined based on the activation rate of the second conductivity type impurity implanted into the base region 3. Thereby, the threshold voltage of silicon carbide semiconductor device 10 and the accompanying electrical characteristics such as channel mobility and on-resistance are set to desired values.

  Thereafter, gate electrode 6, source electrode 7 and drain electrode 8 are formed as in the first embodiment, thereby completing the element structure of silicon carbide semiconductor device 10 shown in FIG.

  As described above, in the second embodiment, the thickness of the gate oxide film 5 is determined based on the activation rate of the second conductivity type impurity implanted into the base region 3. Thereby, even if the activation rate of the impurities implanted into base region 3 varies, the threshold voltage of silicon carbide semiconductor device 10 and the electrical characteristics such as channel mobility and on-resistance associated therewith are set to desired values. They can be set and their variation is suppressed. Therefore, the same effect as in the first embodiment can be obtained.

  Also in the present embodiment, the threshold voltage of silicon carbide semiconductor device 10 is controlled by adjusting the fixed charge density in gate oxide film 5 and the interface state density at the interface between gate oxide film 5 and the substrate (semiconductor layer). It may be performed as a parameter.

<Embodiment 3>
In the first and second embodiments, a heat treatment step for activating impurities implanted into the substrate, a step of calculating the activation rate of the impurities, a step of removing the surface layer of the substrate, and the gate oxide film 5 are formed. The process is in a series of flows. As the difference between the set temperature of the heat treatment furnace and the actual heat treatment temperature, there can be considered a short-term deviation that occurs in each treatment and a long-term deviation that gradually increases over a long period.

  The latter deviation is necessarily required to feed back the calculated activation rate to a parameter for controlling the electrical characteristics of the silicon carbide semiconductor device 10 in the process from the start to the completion of the production of one silicon carbide semiconductor device 10. There is no. Therefore, even if the activation rate calculated once is taken over and fed back while the semiconductor element is manufactured a plurality of times, variations in the electrical characteristics of silicon carbide semiconductor device 10 due to the latter deviation can be suppressed. That is, based on the activation rate value calculated using another substrate processed at the same time, control of the electrical characteristics of silicon carbide semiconductor device 10 (the removal thickness of the surface layer of the substrate, the gate oxide film 5 Even if the thickness, the fixed charge density in the gate oxide film 5 or the interface state density at the interface between the gate oxide film 5 and the substrate is adjusted, a certain effect can be obtained.

  As described above, according to the present invention, due to variations in the activation rate of impurities in the substrate, the threshold voltage of the silicon carbide semiconductor device and the associated channel mobility, on-resistance, and other electrical characteristics It is possible to prevent the reproducibility from being lowered. For example, by suppressing variation in characteristics among multiple chips, the decrease in current carrying capacity and current concentration when multiple elements are connected in parallel can be dramatically improved, and destruction of each element can be avoided. Can do. Even when a single chip is used, variations in threshold voltage and channel mobility in the chip can be suppressed, and local low resistance portions can be prevented from being formed in the chip. As a result, current can be prevented from concentrating at a specific location in the chip, and element breakdown can be avoided.

  The present invention is widely applicable to insulated gate transistor elements such as MOSFETs and IGBTs (Insulated Gate Bipolar Transistors) having a silicon dioxide film formed on a silicon carbide substrate layer as a gate insulating film.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 substrate, 2 drift layer, 3 base region, 4 source region, 5 gate oxide film, 6 gate electrode, 7 source electrode, 8 drain electrode, 10 silicon carbide semiconductor device.

Claims (11)

(A) forming a base region having an impurity concentration distribution of a retrograde profile by ion-implanting impurities into a semiconductor layer made of silicon carbide formed on a substrate;
(B) performing a heat treatment for electrically activating the impurities implanted into the semiconductor layer;
(C) calculating the activation rate of the impurities after the step (b);
(D) removing the surface of the semiconductor layer;
With
A thickness of removing the surface of the semiconductor layer in the step (d) is determined based on an activation rate of the impurity calculated in the step (c). . (A) forming a base region by ion-implanting impurities into a semiconductor layer made of silicon carbide formed on a substrate;
(B) performing a heat treatment for electrically activating the impurities implanted into the semiconductor layer;
(C) calculating the activation rate of the impurities after the step (b);
(D) forming a gate oxide film on the surface of the semiconductor layer;
With
The specific parameter of the gate oxide film formed in the step (d) is determined based on the activation rate of the impurity calculated in the step (c). . The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the heat treatment in the step (b) is performed at a temperature of 1500 to 2000 ° C. for about 10 seconds to 1 hour. 3. The silicon carbide semiconductor device according to claim 1, wherein in the step (c), the activation rate of the impurity is calculated from electrical characteristics of a region of the semiconductor layer into which the impurity is ion-implanted. Method. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the step (c), the activation rate of the impurities is calculated from a surface roughness of the semiconductor layer after the step (b). . The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step (c) is performed using a semiconductor layer formed on the semiconductor layer or another substrate processed at the same time. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step (d) is performed by dry etching of the surface of the semiconductor layer. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step (d) is performed by sacrificial oxidation treatment of the surface of the semiconductor layer. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the specific parameter of the gate oxide film is a thickness of the gate oxide film. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the specific parameter of the gate oxide film is an interface state density between the gate oxide film and the semiconductor layer. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the specific parameter of the gate oxide film is a fixed charge density in the gate oxide film.

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