JP2007305655A - Method of controlling manufacturing process of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of controlling the manufacturing process of a semiconductor device for reducing wafer in-plane variations in the element characteristics of the semiconductor device by a simple method. <P>SOLUTION: The in-plane distribution of the element characteristics of the semiconductor device is predicted from the in-plane distribution of a processing result obtained by a first process (steps S2, S3). Optimum processing conditions having the in-plane distribution, where the predicted in-plane distribution of the element characteristics is canceled, are obtained as the processing conditions of a second process as the next process (steps S4, S5). The second process is processed based on the processing conditions. As a result, variations in the in-plane distribution of the element characteristics is reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of controlling a manufacturing process so that variation in element characteristics of the semiconductor device is minimized in a manufacturing process of manufacturing a semiconductor device by sequentially processing a semiconductor substrate through a plurality of processes.

  In manufacturing a semiconductor device, how much variation in element characteristics is allowed is a very important problem from the viewpoint of quality and cost. When variation in element characteristics is largely allowed, a semiconductor circuit composed of the elements has to secure a large operation margin, and as a result, quality is reduced in terms of power consumption and reliability. On the other hand, when the variation in element characteristics is allowed to be small, a great deal of management is required to suppress fluctuations in the element manufacturing process, and as a result, the manufacturing cost of the element increases.

  In a general semiconductor device manufacturing process, a semiconductor device (chip) composed of a plurality of electronic elements such as transistors, resistors, and capacitors and wirings that electrically connect them is formed on a single semiconductor substrate (wafer). A method is adopted in which a plurality of semiconductor substrates are arranged and a plurality of semiconductor substrates are collectively processed (lot). In such a method of manufacturing a semiconductor device, the element characteristics of the semiconductor device, for example, variations in the threshold voltage of the MOS transistor, etc., are components that vary within a chip, components that vary between chips, components that vary within a lot, or It is classified as a component that varies between lots.

  In order to manufacture a high-quality and low-cost semiconductor device, it is necessary to control the semiconductor device manufacturing apparatus with high precision mutually so as to suppress the characteristic variation of the semiconductor elements of the respective components. It is very important in manufacturing.

  In order to solve this problem, for example, in the exposure and development process, the finish result of the exposure process of a lot is measured, the deviation from the measurement result and the design value is calculated, and the exposure conditions for correcting the deviation are as follows: This is reflected in the lot processing, and a feedback type control method is adopted that reduces variations in device characteristics between lots.

Further, for example, in Patent Document 1, in a process of processing a semiconductor substrate (for example, a chemical mechanical polishing process for flattening the substrate surface), a processing result (for example, a first process process) applied to the substrate is performed. From the in-plane distribution data of the respective substrates of the polishing speed according to the polishing conditions) and the processing result of the second processing step (for example, the polishing speed under the second polishing condition), the difference between the two processing steps for each in-plane position A correlation function for each in-plane position is obtained as data, a substrate in-plane distribution under a desired processing condition (for example, polishing condition) is calculated from the correlation function, and the substrate is processed based on this in-plane distribution characteristic. A method of suppressing variation in processing results between wafers by controlling the system is shown.
JP 2002-0184733 A

  With the above feedforward control method, it is possible to improve the in-wafer uniformity of the processing result. However, when the correlation function representing the difference in the in-plane distribution has a complicated function form, the man-hour for calculating the desired processing condition increases, so it is appropriate to use a too complex function form. Instead, an approximate function form must be used from the viewpoint of processing cost. For this reason, there is a limit to ensuring uniformity, and the cost for the processing increases as the processing for increasing the uniformity is performed. Therefore, it is necessary to allow some variation in the wafer surface as a result of processing.

  Furthermore, in the manufacture of semiconductor devices, the direction of deviation from the design value of the processing result of one process and the direction of deviation from the design value of the processing result of another process are different from the design value of the characteristics of the semiconductor element. In some cases, it may be increased, and conversely, the deviation from the design value of the characteristics of the semiconductor element may be reduced. In the control method of the semiconductor device manufacturing apparatus by the feed-forward method that enhances the uniformity of the in-plane distribution of the processing results described above, the correlation between the element characteristics of the semiconductor elements and the processing results is not taken into consideration. There is a limit to reducing the characteristic variation.

  The present invention has been made in view of the above points, and a main object of the present invention is to provide a method of controlling a manufacturing process of a semiconductor device that can reduce in-wafer variation in element characteristics of the semiconductor device by a simple method. There is.

  The method for controlling a manufacturing process of a semiconductor device according to the present invention is the next process based on the processing result of the first process in the manufacturing process of manufacturing a semiconductor device by sequentially processing a semiconductor substrate in a plurality of processes. 2 is a control method for determining the processing conditions of the second process, the first step of processing the semiconductor substrate in the first process to obtain the first processing result, and the surface in the substrate of the first processing result A second step of measuring an in-plane distribution; a third step of calculating an in-plane distribution of element characteristics of the semiconductor device predicted from the in-plane distribution of the first processing result; and an in-plane of predicted element characteristics. A fourth step of calculating an in-plane distribution of the second processing result in the second step in which it is predicted that an element characteristic having an in-plane distribution opposite to the distribution is obtained; and a second processing result The in-plane distribution is expected to be obtained. A fifth step of determining the processing conditions of the process, and having a sixth step of processing a semiconductor substrate by the process conditions of the second step.

  According to such a method, the in-plane distribution of the element characteristics is predicted from the in-plane distribution of the processing result obtained in the first step, and the predicted processing condition of the second step, which is the next step, is predicted. By obtaining an optimal processing condition having an in-plane distribution that cancels out the in-plane distribution of element characteristics, and performing the second process based on this processing condition, variation in the in-plane distribution of element characteristics is reduced. A semiconductor device having uniform element characteristics can be obtained by a simple method that can be controlled.

  In a preferred embodiment, in the third step, the predicted in-plane distribution of the element characteristics is a database in which a correlation between the first processing result in the first process and the element characteristics of the semiconductor element is recorded in advance. Is calculated from

  In the fourth step, the predicted in-plane distribution of the second treatment result is calculated from a database in which the correlation between the second processing result in the second step and the element characteristics of the semiconductor element is recorded in advance. Is done.

  Further, in the fifth step, the predicted process condition of the second process is a database in which the correlation between the process condition of the second process and the second process result obtained from the process condition is recorded in advance. Determined from.

  In a preferred embodiment, the second step is preferably executed while the second processing result is controlled so as to have a predetermined in-plane distribution.

  In a preferred embodiment, in at least one of the third step and the fourth step, the in-plane distribution of the element characteristics or the in-plane distribution of the second processing result is the measured first processing result. Is calculated by simulation based on the in-plane distribution.

  In a preferred embodiment, in the plurality of steps, a step of adding a relationship between a processing result obtained by processing in each step and element characteristics of a semiconductor device manufactured by sequentially processing in the plurality of steps to a database. It has further.

  In a preferred embodiment, the first step is a gate insulating film forming step, the first processing result is a film thickness of the gate insulating film, and the second step is a gate electrode forming step. The second processing result is the gate length dimension.

  At this time, the processing condition of the second step is preferably an exposure condition for forming a pattern of the gate electrode.

  In a preferred embodiment, the first step is a gate electrode formation step, the first processing result is a gate length dimension, the second step is a source / drain formation step, and the second step The processing result is the activation heat treatment temperature of the source / drain implanted impurities.

  At this time, the processing conditions of the second step are preferably lamp heating conditions for performing an activation heat treatment of the source / drain implanted impurities.

  Another method for controlling a manufacturing process of a semiconductor device according to the present invention includes a first processing result of a first process and a first process in a manufacturing process of manufacturing a semiconductor device by sequentially processing a semiconductor substrate in a plurality of processes. A control method for determining processing conditions for a third step, which is the next step of the second step, based on a second processing result of the second step following the step, wherein the semiconductor substrate is formed in the first step. And obtaining the in-plane distribution of the first processing result in the substrate, and processing the semiconductor substrate processed in the first step in the second step to obtain a second processing result substrate. An in-plane distribution of the first processing result using a step of obtaining an in-plane distribution in the plane, and a response function having the first processing result, the second processing result, and the processing conditions of the third step as variables. , An in-plane distribution of the second processing result, and a plurality of processing conditions in the third step Calculating a plurality of in-plane distributions of element characteristics of the semiconductor device from a typical in-plane distribution, and a third process for minimizing variations in the in-plane distribution from the plurality of in-plane distributions of element characteristics. And a step of determining a virtual in-plane distribution of the processing conditions, and a step of processing the semiconductor substrate in a third process according to one processing condition of the third process.

  According to the method for controlling a manufacturing process of a semiconductor device according to the present invention, the in-plane distribution of element characteristics is predicted from the in-plane distribution of the processing result obtained in the first process, and the second process, which is the next process, is predicted. By obtaining an optimal processing condition having an in-plane distribution that cancels out the predicted in-plane distribution of the element characteristic as a processing condition, and performing the second process based on the processing condition, the element characteristic is obtained. The variation in the in-plane distribution can be controlled to be small.

  Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of simplicity. In addition, this invention is not limited to the following embodiment.

(First embodiment)
FIG. 1 is a flowchart showing a method for controlling a manufacturing process of a semiconductor device according to the first embodiment of the present invention. The semiconductor device is manufactured by sequentially processing a semiconductor substrate in a number of processes. Here, an arbitrary process is described as a first process and a second process that is the next process. To do. Note that the first step and the second step are not necessarily continuous steps.

  As shown in the flowchart of FIG. 1, first, a semiconductor substrate is processed in the first step to obtain a first processing result (first step S <b> 1), and then a surface in the substrate of the first processing result is obtained. The internal distribution is measured (second step S2).

  Next, the predicted in-plane distribution of element characteristics of the semiconductor device is calculated from the in-plane distribution of the first processing result (third step S3). This is calculated from the database D1 in which the correlation between the first processing result in the first step and the element characteristics of the semiconductor element is recorded in advance.

  Next, in the second step in which it is predicted that an “element characteristic having the opposite in-plane distribution” is obtained with respect to the “in-plane distribution of the predicted element characteristic” calculated in the third step S3. The in-plane distribution of the second processing result is calculated (fourth step S4). This is calculated from the database D2 in which the correlation between the second processing result in the second step and the element characteristics of the semiconductor element is recorded in advance. Here, the “element characteristic having an opposite in-plane distribution” means an element characteristic having an in-plane distribution in which the magnitude relationship is opposite to the predicted average value of the element characteristic. .

  Next, the processing condition of the second step that is predicted to obtain the “in-plane distribution of the second processing result” calculated in the fourth step S4 is determined (fifth step S5). This is determined from the database S3 in which the correlation between the processing condition of the second step and the second processing result obtained from the processing condition is recorded in advance.

  Finally, the semiconductor substrate is processed according to the processing conditions of the second process determined in the fifth step S5 (sixth step S6). Note that the second step is executed under control so that the second processing result obtained by the second step has a predetermined in-plane distribution.

  According to the control method of the present invention, the in-plane distribution of the element characteristics is predicted from the in-plane distribution of the processing result obtained in the first step, and this prediction is made as the processing condition of the second step which is the next step. By obtaining an optimum processing condition having an in-plane distribution that cancels out the in-plane distribution of element characteristics, and performing the second process based on this processing condition, variation in the in-plane distribution of element characteristics is reduced. Can be small.

  In addition, the “in-plane distribution of element characteristics”, “in-plane distribution of the second processing result”, and “processing conditions of the second step” calculated in the third to fifth steps are used for the calculation. Necessary data can be stored in advance in a database and can be calculated based on the data stored in the database, so that it can be obtained by simple data processing. Furthermore, the data stored in these databases can be fed back with high accuracy by accumulating the processing results of each process in the database every time a semiconductor device manufacturing process is completed. Effective for reduction. Further, in at least one of the third step and the fourth step, the in-plane distribution of the element characteristics or the in-plane distribution of the second processing result becomes the measured in-plane distribution of the first processing result. Based on this, it may be calculated by simulation.

  Next, the configuration of a control system for carrying out the control method of the present invention will be described with reference to the block diagram shown in FIG. Each block shown here is provided for the sake of convenience in order to explain the functions of the system. For example, these functions may be realized in one apparatus.

  This control system includes a measurement unit 11, a calculation unit 12, a database 13, and a control unit 14 for a device that processes the second step.

  The measuring means 11 measures the first processing result obtained by processing the semiconductor substrate in the first step, and outputs in-plane distribution data of the first processing result. The calculation means 12 sequentially calculates “in-plane distribution of element characteristics”, “in-plane distribution of second processing result”, and “processing conditions of the second step” in the third to fifth steps.

  The database 13 includes “correlation between the first processing result and the element characteristic of the semiconductor element”, “correlation between the second processing result and the element characteristic of the semiconductor element”, and “processing conditions of the second step”. And the correlation between the second processing result obtained from the processing conditions ”. And in the calculating means 12, the required calculation in each of the third to fifth steps is executed using these data recorded in the database 13.

  The control means 14 of the apparatus for processing the second process executes the process of the second process according to the “processing condition of the second process” finally obtained by the calculation means. Note that the apparatus for processing the second step has a function of controlling the second processing result obtained by the second step so as to have a predetermined in-plane distribution.

(Example 1 of the first embodiment)
An example in which the control method of the present invention is applied to a MOS transistor forming process in a semiconductor device manufacturing process will be described with reference to FIGS.

  FIG. 3 is a flowchart showing the control method of the present invention in which the first step is a gate insulating film forming step and the second step is a gate electrode forming step. The database 13 includes “a correlation between the change in the thickness of the gate insulating film and the change in the driving force of the MOS transistor” as shown in FIG. 4 and the “change in the gate length dimension and the MOS as shown in FIG. "Correlation with change in driving force of transistor" and "Correlation between change from design value of gate pattern exposure amount and design value of gate length after development" as shown in FIG. Stored in advance.

  As shown in FIG. 3, first, after forming a gate insulating film on a semiconductor substrate (wafer) (first step S11), the film thickness measuring means 11 is used to form the inside of the wafer as shown in FIG. For each shot, the thickness of the gate insulating film is measured, and the in-plane distribution of the shift amount from the design value of the gate insulating film is determined (second step S12). FIG. 7B is a table showing the results. FIGS. 7C and 7D show the shift amount from the design value of the gate insulating film thickness along the X-axis and Y-axis in the wafer. The in-plane distribution of is shown. As shown in FIGS. 7C and 7D, the gate insulating film is 5% thicker than the design value at the wafer center and 5% thinner than the design value at the wafer periphery. Distribution. The measured data may be temporarily stored in the database 13.

  Next, the predicted element characteristics of the MOS transistor, for example, the in-plane distribution of the transistor driving force, are calculated from the in-plane distribution of the film thickness of the gate insulating film (third step S13). This can be easily calculated using the “correlation between the change in film thickness of the gate insulating film and the change in driving force of the MOS transistor” (see FIG. 4) stored in the database D11.

  FIG. 8 shows the in-plane distribution (only in the X-axis direction) of the transistor driving force calculated from the in-plane distribution of the film thickness of the gate insulating film shown in FIG. Unless special control is performed in the previous process, as shown in FIG. 8, it is predicted that the transistor driving force is reduced by 10% from the design value at the wafer central portion and increased by 10% at the wafer peripheral portion.

  Next, it is predicted that a “transistor driving force having an opposite in-plane distribution” is obtained with respect to the “predicted in-plane distribution of transistor driving force” calculated in the third step S13. The in-plane distribution of “dimension” is calculated (fourth step S14). This can be easily calculated using the “correlation between the change in the gate length dimension and the change in the driving force of the MOS transistor” (see FIG. 5) stored in the database D12.

  FIG. 9 shows an in-plane distribution (only in the X-axis direction) of the gate length dimension calculated from the in-plane distribution of the transistor driving force shown in FIG. The amount of change from the design value of the gate length that cancels the amount of change from the design value of the transistor driving force is calculated for each shot in the wafer surface. As shown in FIG. 9, the gate length may be reduced by 8% from the design value at the wafer central portion, and the gate length may be increased by 12% from the design value at the wafer peripheral portion.

  Next, the exposure condition of the gate electrode pattern that is predicted to obtain the “in-plane distribution of the gate length dimension” calculated in the fourth step S14 is determined (fifth step S15). This can be easily done using the “correlation between the change amount from the design value of the gate pattern exposure amount and the change amount from the design value of the developed gate length” stored in the database D13 (see FIG. 6). Can be calculated.

  FIG. 10 shows the in-plane distribution (only in the X-axis direction) of the exposure condition of the gate electrode pattern calculated from the in-plane distribution of the gate length dimension shown in FIG. As shown in FIG. 10, the exposure amount of the exposure apparatus is increased by 10% from the design value at the wafer central portion, and the exposure amount is decreased by 15% from the design value at the wafer peripheral portion.

  Finally, the gate electrode pattern is exposed under the gate electrode pattern exposure conditions determined in the fifth step S15, and the gate electrode formation process is executed (sixth step S16).

  FIG. 11 shows the distribution in the wafer surface of the MOS transistor driving force when the control method according to the present invention is not used and FIG. 12 shows the case where the control method according to the present invention is used. The variation in transistor driving force is also caused by variations in steps other than the first step (the step of forming the gate insulating film) and the second step (the step of forming the gate electrode). Therefore, even if the control method according to the present invention is used. Although not completely zero, by using the control method according to the present invention, the variation in transistor driving force can be reduced from ± 30% to ± 25%.

(Example 2 of the first embodiment)
Another example in which the control method of the present invention is applied to the MOS transistor forming process will be described with reference to FIGS.

  FIG. 13 is a flowchart showing the control method of the present invention in which the first step is a gate electrode formation step and the second step is a source / drain formation step. Subsequent to the gate electrode formation step (second step) in the first embodiment, by applying the control method of the present invention to the subsequent source / drain formation step, the device characteristics of the MOS transistor (transistor driving capability) ) In-plane variation can be expected to be further reduced.

  In executing the present embodiment, the database 13 includes “correlation between the change in the gate length dimension and the change in the driving force of the MOS transistor” as shown in FIG. "Correlation between change in activation heat treatment temperature of implanted impurity of drain and change in driving power of MOS transistor" and "change amount of heating lamp input power of lamp heating device as shown in FIG. The correlation with the amount of change in the surface temperature of the wafer ”is stored in advance.

  As shown in FIG. 13, first, after forming a gate electrode on a semiconductor substrate (wafer) on which a gate insulating film is formed (first step S21), using the dimension measuring and fixing means 11, FIG. ), The gate length dimension is measured for each shot in the wafer, and the in-plane distribution of the amount of change from the design value of the gate length is obtained (second step S22). FIG. 16B is a table showing the results. FIGS. 16C and 16D are in-plane distributions of changes from the design values of the gate length along the X and Y axes in the wafer. Indicates. As shown in FIGS. 16C and 16D, the gate length has a concentric distribution that is 10% shorter than the design value at the wafer center and 10% longer than the design value at the wafer periphery. The measured data may be temporarily stored in the database 13.

  Next, the predicted element characteristics of the MOS transistor, for example, the in-plane distribution of the transistor driving force, are calculated from the in-plane distribution of the gate length dimension (third step S23). This can be easily calculated using “correlation between dimensional change of gate length and change in driving force of MOS transistor” (see FIG. 5) stored in database D21.

  FIG. 17 shows the in-plane distribution (only in the X-axis direction) of the transistor driving force calculated from the in-plane distribution of the gate length shown in FIG. Unless special control is performed in the previous step, as shown in FIG. 17, it is predicted that the transistor driving force will increase by 15% from the design value at the wafer central portion and increase by 8% at the wafer peripheral portion.

  Next, it is predicted that “transistor driving force having opposite in-plane distribution” is obtained with respect to “predicted in-plane distribution of transistor driving force” calculated in the third step S23. The in-plane distribution of “the activation heat treatment temperature of the drain implantation impurity” is calculated (fourth step S24). This can be easily calculated using “correlation between change in activation heat treatment temperature of source / drain implanted impurities and change in driving power of MOS transistor” (see FIG. 14) stored in database D22. Can do.

  FIG. 18 shows the in-plane distribution (only in the X-axis direction) of the activation heat treatment temperature calculated from the in-plane distribution of the transistor driving force shown in FIG. The amount of change in the heat treatment temperature that cancels the amount of change from the design value of the transistor driving force is calculated for each shot in the wafer surface. As shown in FIG. 18, the heat treatment temperature may be lowered by 15% from the design value at the wafer central portion, and the heat treatment temperature may be raised by 5% from the design value at the wafer peripheral portion.

  Next, the heating condition of the lamp heating apparatus that is predicted to obtain the “in-plane distribution of heat treatment temperature” calculated in the fourth step S24 is determined (fifth step S25). This is based on "correlation between the amount of change in the heating lamp input power of the lamp heating device and the amount of change in the surface temperature of the wafer when the lamp is heated" stored in the database D23 (see FIG. 15). It can be easily calculated.

  FIG. 19 shows the in-plane distribution (only in the X-axis direction) of the heating condition (input power) of the lamp heating calculated from the in-plane distribution of the heat treatment temperature shown in FIG. As shown in FIG. 19, the input power is reduced by 10% from the design value at the wafer central portion, and the exposure amount is increased by 5% from the design value at the wafer peripheral portion.

  Finally, activation heat treatment is performed on the source / drain implanted impurities under the heating conditions of the lamp heating apparatus determined in the fifth step S25, and the source / drain formation process is executed (sixth step S26).

  The reduction in variation in device characteristics (transistor driving force) in this embodiment can be explained in terms of phenomena as follows. That is, the element characteristics of the MOS transistor are bounded by the effective gate length (channel distance between the source and drain), but this effective gate length can be uniquely determined by the finished dimensions of the gate electrode. If the finished dimensions (gate length) vary, the effective gate length also varies. However, since the source and drain are formed by ion-implanting impurities using the gate electrode as a mask and then heat-treating the implanted impurities, the effective gate length varies depending on the heat treatment conditions. Therefore, if the heat treatment conditions can be controlled locally within the wafer surface, the variation in the gate electrode finish size can be achieved by heat-treating the implanted impurities at a heat treatment temperature having an in-plane distribution opposite to the in-plane distribution of the gate electrode finish size. Can be offset.

(Example of heat treatment apparatus in Example 2)
A typical configuration of a heat treatment apparatus for performing activation heat treatment of source / drain implanted impurities in the second embodiment will be described.

  FIG. 20 is a cross-sectional view of the lamp heating device, which includes a stage 100 that holds the wafer 103, a lamp 101 that heats the wafer 103, and a control device 102 that controls input power to the lamp 101. The wafer 103 is placed on the stage 100, and the surface of the wafer 103 is heated by the lamp 101 to perform heat treatment for activating the source / drain impurities. In order to make the temperature distribution of the heat treatment uniform within the wafer surface, heating is performed by the lamp 101 while the stage 100 is rotated. Here, a plurality of lamps 101 are arranged so as to cover the entire wafer surface, and the input power to the lamps can be individually controlled by the control device 102. Accordingly, by changing the input power of the heating lamp, the activation heat treatment of the source / drain implanted impurities can be performed at the heat treatment temperature having a desired in-plane distribution.

  FIG. 21 is a diagram showing an example of another heat treatment apparatus, in which a function for lowering the temperature of a part of the wafer is added to obtain an in-plane distribution of a desired heat treatment temperature.

As shown in FIG. 21, a nozzle 204 that ejects an inert gas, for example, N ₂ is disposed on the back side of the wafer 203. By discharging the inert gas emitted from the nozzle 204 to the back surface of the wafer, the surface temperature of the wafer hit by the inert gas can be lowered. Here, by moving the nozzle 204 in the radial direction of the wafer 203, an inert gas can be discharged to any part of the wafer 203. Further, by changing the discharge amount of the inert gas, it is possible to cause an arbitrary temperature change in the wafer surface.

  22A shows the temperature distribution in the wafer surface when the discharge amount P of the inert gas is constant, and FIG. 22B shows the position r of the nozzle 204 and the discharge amount P of the inert gas. The temperature distribution in the wafer surface in the case of being made is shown.

(Second Embodiment)
FIG. 23 is a flowchart showing a method for controlling the manufacturing process of the semiconductor device according to the second embodiment of the present invention. The control method in the present embodiment obtains the processing conditions of the third step based on the processing results of the first step and the second step. In the present embodiment, the first step, the second step, and the third step are not necessarily continuous steps.

  As shown in FIG. 23, first, the semiconductor substrate is processed in the first step, and the in-plane distribution in the substrate of the first processing result is acquired (step S31). Next, in the second step, the semiconductor substrate processed in the first step is processed to obtain an in-plane distribution in the substrate of the second processing result (step S32).

  Next, using the first processing result, the second processing result, and the correlation F31 between the processing conditions of the third step and the element characteristics of the semiconductor device, the first processing acquired in step S31 and step S32. A plurality of in-plane distributions of element characteristics of the semiconductor device are calculated from the in-plane distribution of the result, the in-plane distribution of the second processing result, and the virtual in-plane distribution of the plurality of processing conditions in the third step ( Step S33).

  Next, from the plurality of in-plane distributions of the element characteristics calculated in step S33, a virtual in-plane distribution of the processing condition of the third step that minimizes the variation in the in-plane distribution is determined (S34). . Then, the semiconductor substrate is processed in the third step according to one processing condition of the third step determined in step S34 (step S35).

  According to the control method of the present embodiment, element characteristics are obtained from the in-plane distribution of the processing results obtained in the first step and the second step, and the virtual in-plane distribution of a plurality of processing conditions in the third step. The in-plane distribution is predicted, the processing condition of the third step that minimizes the variation in the in-plane distribution is obtained, and the processing of the third step is performed based on this processing condition, thereby obtaining the element characteristics. Variation in in-plane distribution can be reduced.

  The virtual in-plane distribution of the plurality of processing conditions in the third step is stored in advance in the database D31. Further, the in-plane distributions of the first and second processing results acquired in steps S31 and S32 may be temporarily stored in the database D31.

(Example of the second embodiment)
An example in which the control method of the second embodiment is applied to a MOS transistor forming process in a semiconductor device manufacturing process will be described with reference to FIG.

  Here, a case where the first step is a gate insulating film formation step, the second step is a gate electrode formation step, and the third step is a heat treatment step for impurity activation of source / drain implantation will be described. .

In the control method of this embodiment, a relational expression representing the relationship between the processing results of the first to third steps and the final semiconductor element characteristics is introduced. That is, the gate insulating film thickness Gox as the processing result of the first step, the gate electrode dimension Lg as the processing result of the second step, and the heat treatment temperature RTAtemp for impurity activation as the processing result of the third step As a variable, a relational expression (response function) for obtaining semiconductor element characteristics, for example, the driving power Ids of a MOS transistor
Ids = Function (Gox, Lg, RTAtemp) (Formula 1)
Is introduced. Here, the response function Function represents an arbitrary function form. Usually, since the driving force Ids often does not change linearly with respect to Gox, Lg, and RTAtemp, the response function Function is, for example, the following quadratic expression Ids = aGox ² + bGox + cLg ² + dLg + eRTTAtemp ² + fRTAtemp + Const.
Can be expressed as Here, Const. Is a constant term, and the coefficients a to f may be determined by performing a prototype experiment or may be determined by simulation.

  As shown in FIG. 24, first, an in-plane distribution of the film thickness of the gate insulating film is acquired as a processing result of the formation process of the gate insulating film (step S41). This processing result is stored in the database D1. Next, an in-plane distribution of the gate length dimension is acquired as a processing result of the gate electrode formation step after the gate oxide film is formed (step S42). This processing result is stored in the database D2.

  Next, the in-plane distribution of the film thickness of the gate insulating film obtained in Steps S41 and S42 using the above (Formula 1) or (Formula 2) as the correlation function F41 between the element characteristics and the processing results of each step, The in-plane distribution of the driving force of the transistor is calculated from the in-plane distribution of the gate length dimension and the in-plane distribution of the virtual activation heat treatment temperature (step S43). Here, a plurality of virtual activation heat treatment temperature in-plane distributions are stored in the database D43, and the in-plane distribution of the driving force of the transistor can be calculated by the number of virtual activation heat treatment temperatures. .

  Next, from the plurality of in-plane distributions of the transistor driving force calculated in step S43, the in-plane distribution of the processing conditions that minimizes the variation in the in-plane distribution is determined (S44). Then, the impurity activation heat treatment step is executed according to the heat treatment conditions determined in step S44.

  FIGS. 25A to 25C compare variations in transistor driving force when three virtual heat treatment temperature distributions are used, and show the smallest heat treatment temperature distribution 2. As a result, a semiconductor device with small variation in characteristics can be manufactured by executing the heat treatment step of the third step using the heating condition having the heat treatment temperature distribution 2 as the condition of the activation heat treatment step.

  As mentioned above, although this invention was demonstrated by suitable embodiment, such description is not a limitation matter and of course, various modifications are possible. For example, in the above-described embodiment, the driving capability of the MOS transistor is described as an example of the element characteristics of the semiconductor device, but the same effect can be obtained for other element characteristics.

  ADVANTAGE OF THE INVENTION According to this invention, the control method of the manufacturing process of the semiconductor device which can reduce the wafer in-plane variation of the element characteristic of a semiconductor device with a simple method can be provided.

3 is a flowchart showing a method for controlling the manufacturing process of the semiconductor device according to the first embodiment of the present invention. It is the block diagram which showed the structure of the system for enforcing the control method in the 1st Embodiment of this invention. It is the flowchart which showed the control method of the manufacturing process of the semiconductor device in Example 1 of the 1st Embodiment of this invention. It is the figure which showed the relationship between the change rate from the design value of the gate insulating film thickness in this invention, and the change rate from the design value of MOS transistor driving force. It is the figure which showed the relationship between the change rate from the design value of the gate length dimension in this invention, and the change rate from the design value of MOS transistor driving force. It is the figure which showed the relationship between the variation | change_quantity from the design value of the gate pattern exposure amount in this invention, and the change rate from the design value of the gate pattern dimension after image development. FIG. 2 is a diagram showing an in-plane distribution of the thickness of the gate insulating film in the present invention, where (a) shows each shot in the wafer, and (b) shows a measurement result of the thickness of the gate insulating film. (C) is the figure which showed the in-plane distribution of the film thickness of the gate insulating film along the X axis in a wafer, (d) is the in-plane distribution of the film thickness of the gate insulating film in the Y axis in a wafer. FIG. It is the figure which showed the in-plane distribution of the transistor driving force computed from the in-plane distribution of the film thickness of the gate insulating film in this invention. It is the figure which showed the in-plane distribution of the gate length computed from the in-plane distribution of the transistor driving force in this invention. It is the figure which showed the in-plane distribution of the exposure conditions of the gate electrode pattern computed from the in-plane distribution of the gate length in this invention. When the control method according to the present invention is not used, it is a diagram showing in-plane distribution of MOS transistor driving force. When the control method by this invention is used, it is the figure which showed in-plane distribution of MOS transistor drive force. It is the flowchart which showed the control method of the manufacturing process of the semiconductor device in Example 2 of the 1st Embodiment of this invention. It is the figure which showed the relationship between the change of the activation heat processing temperature of the implantation impurity of the source / drain in this invention, and the driving force change of a MOS transistor. It is the figure which showed the correlation with the variation | change_quantity of the heating lamp input power in this invention, and the variation | change_quantity of the surface temperature of a wafer. FIG. 2 is a diagram showing an in-plane distribution of gate length dimensions in the present invention, (a) is a diagram showing each shot in the wafer, (b) is a diagram showing measurement results of the gate length dimension, and (c) is a wafer. The figure which showed the in-plane distribution of the gate length dimension along the X-axis in the inside, (d) is the figure which showed the in-plane distribution of the gate length dimension along the Y-axis in the wafer. It is the figure which showed the in-plane distribution of the transistor driving force computed from the in-plane distribution of the film thickness of the gate length dimension in this invention. It is the figure which showed the in-plane distribution of the activation heat processing temperature computed from the in-plane distribution of the transistor drive force in this invention. It is the figure which showed the in-plane distribution of the heating conditions of the lamp heating computed from the in-plane distribution of the activation heat processing temperature in this invention. It is the figure which showed the structure of the heat processing apparatus which performs the activation heat processing of the source / drain implantation impurity in this invention. It is the figure which showed the structure of the other heat processing apparatus which performs the activation heat processing of the source / drain implantation impurity in this invention. FIG. 4 is a diagram showing the temperature distribution in the wafer surface of the heat treatment apparatus according to the present invention, where (a) shows the temperature distribution in the wafer surface when the discharge amount of the inert gas is constant, and (b) shows the position of the nozzle and It is the figure which showed the temperature distribution in the wafer surface at the time of changing the discharge amount of an inert gas. 7 is a flowchart illustrating a method for controlling a manufacturing process of a semiconductor device according to a second embodiment of the present invention. It is the flowchart which showed the control method of the manufacturing process of the semiconductor device in the Example of the 2nd Embodiment of this invention. It is the figure which showed distribution of the transistor driving force in the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Measuring means 12 Calculation means 13 Database 14 Control means 100, 200 Stage 101, 210 Lamp 102, 202 Control apparatus 103, 203 Wafer 204 Nozzle

Claims (12)

In a manufacturing process for manufacturing a semiconductor device by sequentially processing a semiconductor substrate in a plurality of processes, a control method for determining processing conditions of a second process, which is a next process, based on a processing result of the first process. ,
A first step of processing the semiconductor substrate in the first step to obtain a first processing result;
A second step of measuring an in-plane distribution of the first processing result in the substrate;
A third step of calculating an in-plane distribution of element characteristics of the semiconductor device predicted from an in-plane distribution of the first processing result;
A first in-plane distribution of a second processing result in the second step in which it is predicted that an element characteristic having an in-plane distribution opposite to the predicted in-plane distribution of the element characteristic is obtained. 4 steps,
A fifth step of determining a processing condition of the second step in which an in-plane distribution of the second processing result is predicted to be obtained;
A method for controlling a manufacturing process of a semiconductor device, comprising: a sixth step of processing the semiconductor substrate according to processing conditions of the second process.   In the third step, the in-plane distribution of the predicted element characteristics is calculated from a database in which a correlation between the first processing result in the first process and the element characteristics of the semiconductor element is recorded in advance. The method for controlling a manufacturing process of a semiconductor device according to claim 1, wherein:   In the fourth step, the predicted in-plane distribution of the second treatment result is a database in which a correlation between the second processing result in the second step and the element characteristics of the semiconductor element is recorded in advance. The method of controlling a manufacturing process of a semiconductor device according to claim 1, wherein the control method is calculated from:   In the fifth step, the predicted processing condition of the second process is recorded in advance as a correlation between the processing condition of the second process and the second processing result obtained from the processing condition. The method for controlling a manufacturing process of a semiconductor device according to claim 1, wherein the method is determined from a database.   2. The method of controlling a semiconductor device manufacturing process according to claim 1, wherein the second step is executed while the second processing result is controlled so as to have a predetermined in-plane distribution. 3. .   In at least one of the third step and the fourth step, the in-plane distribution of the element characteristics or the in-plane distribution of the second processing result is the surface of the measured first processing result. 2. The method for controlling a manufacturing process of a semiconductor device according to claim 1, wherein the method is calculated by simulation based on the internal distribution.   In the plurality of processes, the method further includes a step of adding a relationship between a processing result obtained by processing in each process and an element characteristic of a semiconductor device manufactured by sequentially processing in the plurality of processes to the database. The method for controlling a manufacturing process of a semiconductor device according to claim 2, wherein the method is a manufacturing method of the semiconductor device. The first step is a gate insulating film forming step, and the first processing result is a film thickness of the gate insulating film,
2. The method of controlling a semiconductor device manufacturing process according to claim 1, wherein the second step is a gate electrode forming step, and the second processing result is the gate length dimension. 3.   9. The method of controlling a semiconductor device manufacturing process according to claim 8, wherein the processing condition of the second process is an exposure condition for forming a pattern of the gate electrode. The first step is a gate electrode forming step, and the first processing result is the gate length dimension,
2. The semiconductor device according to claim 1, wherein the second process is a source / drain formation process, and the second process result is an activation heat treatment temperature of a source / drain implantation impurity. 3. Method of controlling the manufacturing process.   11. The method of controlling a semiconductor device manufacturing process according to claim 10, wherein the processing condition of the second step is a lamp heating condition for performing an activation heat treatment of the source / drain implanted impurities. In a manufacturing process of manufacturing a semiconductor device by sequentially processing a semiconductor substrate in a plurality of processes, the first processing result of the first process and the second processing result of the second process following the first process On the basis of the control method for determining the processing conditions of the third step, which is the next step of the second step,
Processing the semiconductor substrate in the first step to obtain an in-plane distribution of the first processing result in the substrate;
Processing the semiconductor substrate processed in the first step in the second step to obtain an in-plane distribution in the substrate of the second processing result;
The in-plane distribution of the first processing result and the second processing result using a response function having the first processing result, the second processing result, and the processing condition of the third step as variables. Calculating a plurality of in-plane distributions of element characteristics of the semiconductor device from an in-plane distribution and a virtual in-plane distribution of a plurality of processing conditions in the third step;
Determining, from a plurality of in-plane distributions of the element characteristics, a virtual in-plane distribution of one processing condition of the third step that minimizes variation in the in-plane distribution;
And a step of processing the semiconductor substrate in the third step according to one processing condition of the third step.

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