JP2015023777A - Two-stage change prevention apparatus for high-voltage inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of an inverter device having a multiple configuration, in which, since a two-stage change is prevented by selecting a pattern by using a switching pattern table, variations in switching elements configuring the inverter may cause on/off timing of switching to be deviated to make it impossible to completely prevent the two-stage change.SOLUTION: A two-stage change prevention apparatus includes a switching hold circuit that holds an output of a PWM signal for a predetermined time, and a dead-time generation circuit that delays an output of the switching hold circuit by a predetermined time, and outputs it as a switching signal of each single-phase inverter. The switching hold circuit includes a hold time counter circuit having a count section that starts a count when detecting a voltage edge of the single-phase inverter, and a determination section that outputs a signal Sh when the count value is other than 0, and a hold circuit that holds the output of the PWM signal for the predetermined time by the signal Sh.

Description

  The present invention relates to a two-stage change preventing device for a cell multiplex power converter (high voltage inverter).

  One of the circuit systems constituting the high voltage inverter is a serial multiplexing system. The serial multiplex system has a plurality of DC link portions insulated by input transformers, and can output a total of DC voltages corresponding to the number of connected stages by connecting single-phase inverters called cell units in multiple stages.

  FIG. 13 shows an example of an inverter having a two-stage configuration. INV-u1, INV-u2, INV-v1, INV-v2, INV-w1, and INV-w2 are cell units (single-phase inverters) for each phase. ), Vu-1, vu-2, vv1, vv2v, 1vw1, vw2 are U, V. It is the output voltage of each single-phase inverter of W phase. The single-phase inverter is configured by a single-phase full bridge including switching elements U11 to U14 as shown in FIG. D is a rectifier.

  When an inductive load such as a motor is directly driven using a high-voltage inverter configured by connecting a plurality of single-phase inverters in series, a surge voltage applied to the load may cause the load to deteriorate. In particular, the phase shift control method, which is a control method used in high-voltage inverters, causes a phenomenon of two-stage change because the output voltage of two inverters is applied to the line voltage of the load. It is known from Patent Document 1 that this two-stage change adversely affects the electric insulation of the motor. In Patent Document 1, the change rate of the voltage command value is controlled and a two-stage change is caused by using a switching table. The two-step change is prevented by prohibiting the switching pattern.

JP 2006-109688 A

  In Patent Document 1, since the time change rate of the voltage command value is limited, there is a problem that an error between the voltage command value and the output voltage increases. In addition, since the normal phase shift control method cannot be applied, the update frequency and sampling period of the voltage command value are also limited to the carrier frequency, and high-speed response cannot be realized. Furthermore, because it is feedforward control that prevents a two-stage change by selecting a pattern using a switching pattern table, there is a deviation in switching on / off timing due to factors such as variations in the switching elements that make up the inverter. There is a problem that the two-stage change cannot be prevented completely. FIG. 15 shows this state. If a deviation occurs in the on / off timing, there is a possibility that a pseudo two-stage change in which the voltages of two single-phase inverters are switched in a short period th may occur. In FIG. 15, vdc indicates the output voltage for one single-phase inverter.

  An object of the present invention is to provide a two-stage change prevention device for a high-voltage inverter that is not affected by a sudden change in command value or a variation in switching timing of switching elements.

The present invention is a multiple inverter device configured by connecting a plurality of single-phase inverters in series, and performs PWM control using a phase shift control method.
A PWM generation circuit that generates a PWM signal based on an input three-phase voltage command and a carrier frequency signal, and a rising / falling state of a detected output voltage of each single-phase inverter, and a generated PWM A switching hold circuit that holds the output of the signal for a predetermined time, and a dead time generation circuit that delays the output of the switching hold circuit for a predetermined time and outputs it as a switching signal of each single-phase inverter,
The switching hold circuit is
Hold time counter circuit having a counting unit that starts counting to a preset set value when a voltage edge of a single-phase inverter is detected, and a determination unit that outputs a signal Sh when the count value by the count unit is other than 0 And a hold circuit that receives the signal Sh output from the hold time counter circuit and holds the output of the PWM signal for a predetermined time by the signal Sh,
The switching hold circuit has a number corresponding to the number of each single-phase inverter.

  Each switching hold circuit of the present invention includes an up edge counter that detects a rising edge of a voltage and a down edge counter that detects a falling edge of the voltage.

  Further, according to the present invention, the hold period th during which the switching hold circuit holds the PWM signal is such that an average period th-max = 1 generated by switching when the number of serially connected stages of the single-phase inverter is n and the carrier frequency is fc. This is characterized in that / 2nfc is the upper limit value of the hold period th and the lower limit value of the hold period th is in the range of td ≦ th <1 / 2nfc with the dead time as td.

  As described above, according to the present invention, the switching hold circuit includes the count unit that starts counting when the voltage edge of the single-phase inverter is detected, and the determination unit that outputs the signal Sh when the count value is other than 0. The hold time counter circuit is configured to hold the output of the PWM signal for a predetermined time by the signal Sh. As a result, an arbitrary hold period can be set, so that the problem of extremely short pulse of the line voltage can be solved, and a two-stage change of the line voltage can be prevented against a sudden change in command value and a variation in switching timing of the switching element. .

  In addition, since it is not necessary to limit the temporal change in the voltage command value as in the prior art, errors in the output voltage and output current with respect to the command value can be reduced. Furthermore, the update frequency of the voltage command value and the sampling period are not limited by the carrier frequency, and a higher speed response than the prior art can be realized.

The block diagram of the high voltage inverter apparatus which shows embodiment of this invention. The block diagram of a hold circuit (for one single phase inverter). The block diagram of a hold time counter circuit (for one single phase inverter). The block diagram of an edge detection circuit. The timing chart of a switching hold circuit. The block diagram of a hold time counter circuit (for one single phase inverter). The block diagram of an edge detection circuit. The timing chart of a switching hold circuit. The timing chart of a switching hold circuit. The timing chart of a switching hold circuit. The timing chart of a switching hold circuit. In the timing chart of the switching hold circuit, (a) is when th <td, and (b) is when th> 1 / 2nfc. The block diagram of a high voltage inverter. The block diagram of a single phase inverter. Explanatory drawing of generation | occurrence | production of pseudo | simulation two steps change.

  The high-voltage inverter device according to the present invention includes a PWM generation circuit that generates a PWM signal based on an input three-phase voltage command and a carrier frequency signal, and a rising / falling state of an output voltage detected by each single-phase inverter. A switching hold circuit that grasps and holds the output of the PWM signal for a predetermined time, and a dead time generation circuit that delays the output of the switching hold circuit for a predetermined time and outputs it as a switching signal of each single-phase inverter.

  The switching hold circuit includes a count unit that starts counting when a voltage edge of the single-phase inverter is detected, and a hold time counter circuit that includes a determination unit that outputs a signal Sh when the count value is other than 0, A hold circuit that holds the output of the PWM signal for a predetermined time by the signal Sh is provided. This will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of a control apparatus for a high-voltage inverter according to an embodiment of the present invention, and shows an example of an inverter having a two-stage configuration in the same manner as FIG.
1 is a CPU that generates a three-phase voltage command v ^* ref and a carrier frequency command, and 2 is a carrier signal generation unit that generates a phase difference signal having a predetermined phase difference based on the carrier frequency command from the CPU 1. Output to the PWM generation circuit 3. The PWM generation circuit 3 generates PWM signals pwmu 1, pwmu 2, pwmv 1, pwmv 2, pwmw 1, pwmw 2 of each single-phase inverter based on the voltage command value v * ref, and outputs them to the switching hold circuit 4.

  The switching hold circuit 4 has a circuit having the functions shown in FIGS. 2 and 3, and the detected output voltages vu-1, vu-2, vv1, vv2v, 1vw1, vw2 of each single-phase inverter. Is entered. Then, the gate signal is maintained while the detected output voltage is in the high state, and switching to other single-phase inverters other than the single-phase inverter is prohibited, thereby preventing a two-stage change. The output of the switching hold circuit 4 is output as a gate signal of the switching element of each single-phase inverter through the dead time generation circuit 5.

   FIG. 2 shows a hold circuit in the switching hold circuit 4, which is representatively for the single-phase inverter INV-u1, but in the case of the inverter configuration of FIG. 1, it has six hold circuits. .

  FIG. 3 shows a hold time counter circuit. Reference numeral 21 denotes an edge detection unit. The edge detection unit 21 receives a detection signal of each output voltage of the single-phase inverter and detects an edge. Each detection signal includes two detection signals as shown in FIG. It is detected by an edge detection circuit composed of a flip-flop circuit and an EXOR circuit. The detected edge signal (for example, vv1-edg of vv1) is input to the enable terminal EN of the count unit 26 via the OR circuit 23 and the AND circuit 24. One terminal of the AND circuit 24 is an inverting terminal. A preset value is stored in the count unit 26 in advance, and the output of the edge detection unit 21 is input when the terminal Full is low.

  The clock signal is input to the CLK terminal of the count unit 26, and the signal of the addition function unit 25 that adds +1 to the count value is input to the D terminal and is output from the terminal Q. A determination unit 27 determines whether or not the input value to the determination unit is 0. If the input value is not 0, Sh-u1 is high, and if it is 0, Sh-u1 is determined to be low.

  FIG. 5 is a timing chart of the switching hold circuit 4. Here, the single-phase inverter INV-u1 is shown as a representative. In FIG. 5, for the sake of simplicity, the dead time is ignored and displayed. FIG. 5A shows a case where the PWM signal pwmu1 from the PWM signal generation circuit 3 generates a falling edge when the output voltage vv1 of the single-phase inverter INV-v1 is a rising edge, and FIG. This shows a case where the PWM signal pwmu1 generates a rising edge when the voltage vv1 is in a rising state.

  That is, when the rising edge of vv1 is detected in the counter function shown in FIG. 3, the counter 26 starts counting, Sh-u1 becomes high, and the hold of the PWM signal pwmu1 is started. Then, the hold is released after the hold period th, and the switching hold circuit 4 outputs a signal pwmpu1 that changes later than the pwmu1 by the hold period th. This signal pwmpu1 is output to the single-phase inverter INV-u1 via the dead time generation circuit 3, the inverter is driven, and vu1 is output by turning on the switching element.

  In the operation shown in FIG. 5, vu1 is output with a delay of the hold period th from vv1. At this time, the gate signal to the single-phase inverter is delayed by the dead time in the dead time generation circuit 5, but this delay can be ignored and it is possible to prevent the two-stage change and the pseudo two-stage change.

  In FIG. 5, only the line voltage vu1−vv1 is shown. However, in the case of an inverter having a three-phase two-stage configuration, for example, when the detection voltage vv1 is used as a reference, the edge change prohibition determination is as shown in Table 1.

  FIG. 6 shows a hold time counter function according to the second embodiment, which includes two sets of hold time counter circuits C-1 (up edge counter) and C-2 (down edge counter) and an up edge. And the down edge are detected separately, and the same reference numerals are given to the same functional parts as in FIG. Sh-u1 is output from the output circuit 28 of the two sets of hold time counter circuits. The output circuit 28 receives the pwmu1 of the PWM signal from the PWM generation circuit 3 and its inverted signal, obtains a logical product of the output of the hold time counter circuit, and outputs Sh-u1.

  FIG. 7 shows a configuration diagram of the edge detection circuit 21a used in FIG. 6, and the same reference numerals are given to the same functional parts as those in FIG. That is, two AND circuits are connected to the output side of two flip-flop circuits, and one terminal is set as an inverting terminal and outputs as vv1-upedg and vv1-downedg.

8 to 11 show examples of waveforms when the hold time counter circuit of FIG. 6 is used. In this case as well, the dead time is ignored for the sake of simplicity.
FIG. 8 is a waveform diagram when vu1 is a down edge when vv1 is an up edge. In this case, since vv1 is an up edge, the up edge counter C-1 in FIG. 6 detects the edge and starts counting. .

  If pwmu1 changes to the down edge in spite of the fact that the hold period th has not elapsed in the middle of the count, it causes a two-stage change or a pseudo two-stage change. However, the hold time counter circuit of FIG. The output Sh-u1 is set to high, and the hold circuit shown in FIG. Therefore, the following operation is the same as that of the first embodiment, and vu1 is output after the hold period th from the edge change of vv1.

  FIG. 9 shows an example of a waveform when vu1 is up edge when vv1 is up edge. In this case, since vv1 is an up edge, the up edge counter C-1 in FIG. 6 detects the edge and starts counting. At this time, even if vu1 changes the up edge, a two-stage change or a pseudo two-stage change does not occur. Therefore, the hold time counter circuit in FIG. 6 sets Sh-u1 low, and the hold circuit in FIG. Therefore, vu1 is output regardless of the hold period th.

  FIG. 10 shows a waveform example when vu1 is an up edge when vv1 is a down edge. In this case, since vv1 is a down edge, the down edge counter C-2 in FIG. 6 detects the edge and starts counting. At this time, if vu1 changes the up edge even though the hold period th has not elapsed, there is a possibility of causing a two-stage change or a pseudo two-stage change. However, the hold time counter circuit of FIG. Is set to high, and the hold circuit of FIG. 2 performs the hold operation. Therefore, vu1 is output after the hold period th elapses from the edge change of vv1.

  FIG. 11 shows an example of a waveform when vu1 becomes a down edge when vv1 is a down edge. In this case, since vv1 is a down edge, the up edge counter C-1 in FIG. 6 detects the edge and starts counting. At this time, even if vu1 changes the down edge, it may cause a two-stage change or a pseudo two-stage change. However, the hold time counter circuit in FIG. 6 sets Sh-u1 to low and the hold circuit in FIG. Does not hold. Therefore, vu1 is output regardless of the hold period th.

This embodiment relates to the calculation of the hold period th of the counter in the first and second embodiments.
In general, when phase shift control is applied to an inverter device configured by connecting n-phase single-phase inverters in series, since n carriers equal to the number of inverter stages n are used, assuming that the carrier frequency is fc, the entire inverter device Can be expressed as nfc which is n times the carrier frequency. Therefore, the average period th _- max in which switching occurs can be expressed by the following equation.
th _- max = 1 / 2nfc
Since this average period th_max is an average period until a single-phase inverter other than itself switches in the same phase, there is no need to consider switching of the in-phase single-phase inverter as long as it is a hold period within this period. Therefore, the average period th_max may be set as the design upper limit value of the hold time.

Next, the lower limit value of the hold time th is designed. If the lower limit value of the hold time is shorter than the dead time td provided in the switching element, there is a possibility that the two-stage change cannot be prevented from rising simultaneously with the edge detection due to variations in the constant of the switching element. Therefore, the lower limit value of the hold time may be set longer than the dead time td. Therefore, the hold time th may be designed within the range of the following equation.
td ≦ th <1 / 2nfc
FIG. 12 shows a timing chart of the switching hold circuit (INV-u1). FIG. 12 (a) shows a waveform when th is the lower limit, and FIG. 12 (b) shows a waveform when th is the upper limit. As shown in FIG. 12A, when the hold time th is the lower limit, there is a possibility that a pseudo two-stage change occurs in which the output voltage change (for 2 Vdc) of two single-phase inverters occurs in a short period. is there.

On the other hand, in the case of the upper limit shown in FIG. 12B, an edge change occurs before the set hold time th elapses, so switching other than the reference single-phase inverter (other than vu1) is prohibited, and the command value It becomes impossible to output the street output voltage.
Therefore, in this embodiment, the upper limit value and the lower limit value are set so that the hold time th is longer than the dead time td, thereby preventing a two-stage change or a pseudo two-stage change.

1 ... CPU
2 ... Carrier signal generation unit 3 ... PWM generation circuit 4 ... Switching hold circuit 5 ... Dead time generation circuit 21 ... Edge detection circuit 23 ... OR circuit 24 ... AND circuit 25 ... Addition function unit 26 ... Count unit 27 ... Determination unit 28 ... Output circuit

Claims (3)

In a multiple inverter device configured by connecting a plurality of single-phase inverters in series and performing PWM control using a phase shift control method,
A PWM generation circuit that generates a PWM signal based on an input three-phase voltage command and a carrier frequency signal, and a rising / falling state of a detected output voltage of each single-phase inverter, and a generated PWM A switching hold circuit that holds the output of the signal for a predetermined time, and a dead time generation circuit that delays the output of the switching hold circuit for a predetermined time and outputs it as a switching signal of each single-phase inverter,
The switching hold circuit is
Hold time counter circuit having a counting unit that starts counting to a preset set value when a voltage edge of a single-phase inverter is detected, and a determination unit that outputs a signal Sh when the count value by the count unit is other than 0 And a hold circuit that receives the signal Sh output from the hold time counter circuit and holds the output of the PWM signal for a predetermined time by the signal Sh,
2. The two-stage change prevention device for a high-voltage inverter, wherein the switching hold circuit is configured with a number corresponding to the number of each single-phase inverter. 2. The two-stage change prevention for a high-voltage inverter according to claim 1, wherein each switching hold circuit includes an up edge counter for detecting a rising edge of a voltage and a down edge counter for detecting a falling edge of the voltage. apparatus. The hold period th during which the switching hold circuit holds the PWM signal is defined as an average period th-max = 1 / 2nfc that occurs in switching, where n is the number of serially connected stages of the single-phase inverter and fc is the carrier frequency. 3. The two-stage change prevention of a high-voltage inverter according to claim 1, wherein the upper limit value of th is set, and the lower limit value of the hold period th is set in a range of td ≦ th <1 / 2nfc with a dead time td. apparatus.

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