JPH05207750A - Inverter unit - Google Patents

Abstract

PURPOSE:To provide a stably operable series multiplex inverter unit in which such switching condition as may cause breakdown of switching element is eliminated. CONSTITUTION:A phase U output voltage command vu* is compared with two carrier signals Ec1, Ec2, respectively, through comparators 31U, 32U. Output signals 711U and 712U from the comparators 31U, 32U are employed as input signals to a second protective circuit 6U whereas output signals 731U, 732U from the second protective circuit 6U and inverted signals 733U, 734U thereof are employed as input signals to a first protective circuit 4U. Output signals 721U-724U from the first protective circuit 4U are employed as gate signals for turning the switching elements S1U-S4U ON/OFF and the gate signals are amplified through gate amplifiers 51U-54U before they are fed to the switching elements S1U-S4U.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial multiple inverter device, and more particularly to an inverter device for preventing a switching element from being destroyed due to an overvoltage of a voltage applied to a switching element which constitutes an inverter. ..

[0002]

2. Description of the Related Art Generally, a PWM inverter device is used to control the rotation speed of an AC motor, but the output voltage of a normal PWM inverter is configured to change between positive and negative two levels. However, there is a problem that the harmonic components included in the output current are large.

Therefore, conventionally, as a method for reducing the harmonic component contained in the output current of the PWM inverter, Japanese Patent Laid-Open Publication No.
As described in No. 56-74088, there is proposed a method of multiplexing PWM inverters in series and changing the output voltage of the inverters between positive, zero and negative three levels to reduce the harmonic components. ing.

FIG. 7 shows a detailed circuit configuration of the serial multiple inverter. In the figure, 11 is a DC power supply, and the smoothing capacitors 12 and 13 connected in series are the DC power supply 1
1 is connected in parallel. The interconnection point between these two smoothing capacitors 12 and 13 is used as a power supply neutral point.

The switching circuit 14 comprises switching elements S1U to S4W, flywheel diodes D1U to D4W and clamp diodes CD1U to CD2W for clamping each output terminal U, V, W to a neutral potential. The relationship between the on / off state of each of the U-phase switching elements S1U to S1W and the output voltage is as shown in FIG.

Next, FIG. 9 shows the configuration of a control circuit for performing pulse width modulation (PWM) on the serial multiple inverter. In the figure, U-phase output voltage command vu * and two carrier signals Ec
1 and Ec2 are compared by the comparators 31U and 32U. The output signals 711U and 712U of the comparators 31U and 32U and their inverted signals 713U and 714U are input to the protection circuit 4U. The output signals 721U to 724U of the protection circuit 4U are switching elements S1U.
~ S4U is a gate signal for turning on and off, amplified by gate amplifiers 51U to 54U, and supplied to switching elements S1U to S4U.

The protection circuit 4U is composed of delay circuits 411U to 414U and AND circuits 421U to 424U.
By generating the output signals 721U to 724U in which the rising of 714U is delayed, a short circuit due to the arc extinction delay of the switching element is prevented. The switching elements are operated by the same circuit for the V phase and the W phase.

FIG. 10 shows the relationship between the output voltage command, the carrier signal, the PWM signal and the output voltage in the PWM control circuit shown in FIG. However, this waveform diagram does not consider the delay operation by the protection circuit. S1U and S3U and S2U and S4U
By operating in a conjugate relationship with each other, three-level voltages of zero and ± E can be output, and output harmonics can be reduced as compared with a normal two-level inverter.

FIG. 11 shows details of operation waveforms of the PWM control circuit shown in FIG. In the figure, comparators 31U, 32
By comparing the voltage command vu * with the carrier wave signals Ec1 and Ec2 by U, the PWM signals 711U to 714U are obtained. Protection circuit
The output signal of 4U 721U～724U is a signal delayed rise of the PWM signal 711U~714U by time t _d, the gate amplifier 51
It is supplied to the switching elements S1U to S4U via U, 52U, 53U and 54U.

In the switching elements S1U to S4U, the timing from ON to OFF is delayed by the turn-off time t _OFF, but if t _d > t _OFF , S1U and S3U or S2U and S4U will not be turned on at the same time, and Therefore, since an excessive voltage is not applied to one switching element, each switching element is protected.

In the serial multiple inverter, the switching elements are connected in series so that if the absolute values (E) of the positive and negative output voltages of the DC power supply are equal, the voltage applied to the switching elements is reduced to about one half. Therefore, a switching element having a small rated voltage can be used. That is, in the serial multiplex inverter of FIG. 7, the voltage applied to each switching element is E or less, the switching element having the rated voltage E can be used to operate at the output voltage ± E, and the applied voltage of the switching element is 2E. It is possible to use a switching element whose rated voltage is half that of a normal two-level inverter.

[0012]

In the PWM control circuit shown in FIG. 9, output signals 711U, 7 of comparators 31U, 32U are provided.
12 and 13 show switching states when 12U simultaneously changes from a high level (hereinafter referred to as "Hi") to a low level (hereinafter referred to as "Lo"). 11 shows the state when the output current is positive, and FIG. 12 shows the state when the output current is negative.

Due to the operation of the protection circuit 4U, the switching element S1U is turned off, the switching element S3U is turned on, the switching element S2U is turned off, and the switching element S4U is turned on. Therefore, from the state (a) in which S1U and S3U are on, the state in which S1U or S3U is off
(b1) or (b2), all switching elements are off (c), S2U or S4U is off (d1) or (d2), S2U and S4U are on (e ), The state changes, and three or more switching elements do not turn on at the same time. However, which of S1U and S2U is turned off first, and which of S3U and S4U is turned on first depends on the characteristics of each switching element and gate amplifier.

When the output current in FIG. 11 is positive, S2
When U turns off first and only S1U turns on (b2), S2
Since the full voltage 2E of the DC power supply is applied to U, the switching element may be destroyed. Further, when the output current in FIG. 12 is negative and S4U is turned on first and only S4U is turned on (d2), the total voltage 2E of the DC power supply is applied to S3U, which destroys the switching element. May occur.

The present invention has been made in view of the above circumstances, and provides an inverter device that operates stably in a serial multiplex inverter by eliminating the switching state that may damage the switching element as described above. The purpose is to

[0016]

SUMMARY OF THE INVENTION An inverter device of the present invention is an inverter device configured to include a plurality of switching elements connected in series to a DC power supply and capable of outputting a voltage of three or more levels per phase, It is characterized in that it has a control means for controlling the firing of the plurality of switching elements so that the output voltage is switched one level at a time. The inverter device of the present invention includes a plurality of switching elements connected in series to a DC power source,
In an inverter device configured to be capable of outputting a voltage of three or more levels per phase, when any two or more switching elements of the plurality of switching elements are simultaneously fired, the switching elements closer to the output terminal are sequentially output. When igniting and extinguishing a plurality of switching elements at the same time, a control means is provided for extinguishing the switching elements in order from the farthest switching element to the output terminal.

Further, the inverter device of the present invention includes a plurality of switching elements connected in series to a DC power supply and is configured to be capable of outputting a voltage of three or more levels per phase. When a switching element near the terminal is extinguished, it is prohibited to ignite the switching element, and when a switching element farther from the output terminal than a certain switching element is ignited, the switching element is extinguished. It is characterized by having control means for prohibiting arcing.

Further, in the inverter device of the present invention, both terminals of the first to fourth series-connected four switching elements are connected between both ends of the DC power source having the neutral point output terminal, and the second and The interconnection point of the third switching element is connected to the inverter output terminal, and the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements are in the DC power supply. An inverter device configured to be connected to a characteristic point through a diode, and to be ON / OFF controlled by the first and third switching elements and the second and fourth switching elements in a conjugate relationship with each other. In (1), when the output voltage shifts from a positive state to a negative state, or when the output voltage shifts from a negative state to a positive state, the output voltage must be set to zero once. Characterized in that it has a control means for performing an arc control points of the first to fourth switching elements so as to elapse state.

Also, in the inverter device of the present invention, both terminals of the first to fourth switching elements connected in series are connected between both ends of the DC power source having the neutral point output terminal, and the second and The interconnection point of the third switching element is connected to the inverter output terminal, and the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements are in the DC power supply. An inverter device configured to be connected to a characteristic point through a diode, and to be ON / OFF controlled by the first and third switching elements and the second and fourth switching elements in a conjugate relationship with each other. In the state where the first and second switching elements are turned on and the third and fourth switching elements are turned off, the third and fourth switching elements are turned on. And when the first and second switching elements are turned off, or when the third and fourth switching elements are turned on and the first and second switching elements are turned off. When the switching element of No. 4 is turned off and the first and second switching elements are turned on, the second element is always turned on.
And a control means for controlling ignition of the first to fourth switching elements so that a state in which the third switching element is turned on and the first and fourth switching elements are turned off is passed. Characterize.

The control means may include a first comparator for comparing a voltage command and a carrier signal, and a second comparator for comparing the voltage command and the carrier signal shifted by a predetermined DC level. And a protection circuit for delaying the output signals of the first and second comparators so as to shift the firing or extinguishing timing of the first and second switching elements when the voltage command suddenly changes. It is characterized by having.

[0021]

In the inverter device having the above-mentioned structure, the plurality of switching elements are ignited by the control means so that the output voltage is switched one level at a time.

Further, in the inverter device having the above-mentioned configuration, when any two or more switching elements among the plurality of switching elements are simultaneously fired, the switching elements closer to the output terminal are fired in order, and the plurality of switching elements are turned on. In the case of simultaneously extinguishing the switching elements, the switching elements are controlled to be extinguished by the control means so that the switching elements farthest from the output terminal are sequentially extinguished.

Further, in the above-described inverter device, when a switching element closer to the output terminal than a certain switching element is extinguished, it is prohibited to fire the switching element, and the switching element is farther from the output terminal than the certain switching element. When the switching element is ignited, each switching element is ignited by the control means so as to prohibit extinguishing the switching element.

Further, in the above-configured inverter device, when the output voltage is changed from the positive state to the negative state or when the output voltage is changed from the negative state to the positive state, the output voltage is always set to zero. Ignition control of the first to fourth switching elements is performed by the control means so that the state of turning on is passed.

In the inverter device having the above structure, the first
And a state in which the third and fourth switching elements are turned on and the first and second switching elements are turned off from a state in which the second switching element is turned on and the third and fourth switching elements are turned off Or when the third and fourth switching elements are turned on and the first
And the third and fourth switching elements are turned off from the state in which the second and second switching elements are turned off, and the first and second switching elements are turned off.
When the switching element is turned on, the control means always causes the second and third switching elements to be turned on and the first and fourth switching elements to be turned off. The fourth four switching elements are ignition-controlled.

Specifically, referring to FIG. 11 and FIG.
There is a possibility that the switching element may be destroyed when the switching element is turned off and the switching element farther from the output terminal than the switching element is turned on. By providing means for prohibiting the above states (b2) and (d2), there is no risk of breaking the switching element.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. Since the configurations of the inverter and its control device are the same for each phase, only the U phase is shown in this specification, but the other phases have the same configuration.

FIG. 1 shows the configuration of an embodiment of the inverter according to the present invention. In the figure, the U-phase output voltage command vu * and the two carrier signals Ec1 and Ec2 are compared to each other by the comparator 31.
U and 32U are compared. Output signal 711U of comparator 31U
And the output signal 712U of the comparator 32U is input to the second protection circuit 6U, and the output signals 731U and 732U of the second protection circuit 6U,
And inverted signals 733U and 734U of 731U and 732U are input to the first protection circuit 4U.

Further, the output signals 721U ... Of the first protection circuit 4U
724U serves as a gate signal for turning on / off the switching elements S1U to S4U, and this gate signal is amplified by the gate amplifiers 51U to 54U, and then the switching element S1U.
~ S4U supplied.

The first protection circuit 4U includes delay circuits 411U to 41U.
4U and AND circuit 421U to 424U, input signal 731U
Outputs signals 721U to 724U in which the rising of ˜734U is delayed by t _d . The second protection circuit 6U includes delay circuits 611U-
612U, an AND circuit 62U, and an OR circuit 63U, and an output signal 73 during a period when the input signal 712U is "Lo" and during a delay time t _{d2 after} the input signal 712U changes from "Lo" to "Hi".
1U is as a "Lo", the period of the delay time t _d2 after changing the "Lo" from the input signal 711U is "Hi" is a period and the input signal 711U is "Hi" is output signal 732U is "Hi "To be.

Next, FIG. 2 shows operation waveforms of the PWM modulation circuit of FIG. By comparing the voltage command vu * with the carrier wave signals Ec1 and Ec2 by the comparators 31U and 32U, the PWM signal 7
Get 11U to 712U. During a normal operation in which the voltage command vu * continuously changes, the input / output signals of the second protection circuit are the same.
At this time, the output signals 721U to 724U from the first protection circuit are
Output signals 731U and 732U of the protection circuit and its inverted signal 73
It is a signal in which the rising edges of 3U and 734U are delayed by the time t _d1 .

In the switching elements S1U to S4U, the timing from ON to OFF is the turn-off time t _OFF.
However, if t _d1 > t _OFF , the switching elements are protected without turning on S1U and S3U or S2U and S4U at the same time.

On the other hand, the voltage command vu * suddenly changes and the comparator 3
During a transient operation in which the output signal 711U of 1U and the output signal 712U of the comparator 32U change simultaneously, switching is performed by shifting the output signal change timing by the second protection circuit and inserting a state in which the output voltage is 0. Even if there are variations in the characteristics of the elements, it is possible to avoid a switching state in which the switching elements may be destroyed.

The delay time t _d1 of the delay circuit in the first protection circuit is set in consideration of ensuring the protection operation and reducing the influence on the PWM control.
And slightly larger than the turn-off time t _OFF of 1U~S4U. In addition, the delay time t of the delay circuit of the second protection circuit
_{The d2} is set to about the turn-off time of the switching elements S1U to S4U in consideration of variations in switching characteristics of the elements. As a result, when the inverter output changes from the negative state (-E) to the positive state (+ E) at the times tn, tn + 1 when the voltage command vu * changes transiently in FIG. State (+ E) to negative state (-
When changing to E), the state where the output voltage of the inverter becomes zero once passes.

According to this embodiment, in the DC multiplex inverter, when the output voltage is changed from the positive state to the negative state, or when the output voltage is changed from the negative state to the positive state, the output voltage is always changed. It is possible to prevent the switching element from being broken by passing the state of zero.

FIG. 3 shows another embodiment of the inverter device according to the present invention. In the figure, the U-phase output voltage command vu * and the two carrier signals Ec1 and Ec2 are compared to each other by the comparator 31.
U and 32U are compared.

Further, the output signal 711U of the comparator 31U, the output signal 712U of the comparator 32U and the inverted signals 713U and 714U thereof are inputted to the first protection circuit 4U, and the output signals 741U to 744U of the first protection circuit 4U are inputted. It is input to the second protection circuit 6U.

Output signals 751U to 754U of the second protection circuit 6U
Is a gate signal for turning on / off the switching elements S1U to S4U, amplified by the gate amplifiers 51U to 54U, and supplied to the switching elements S1U to S4U.

The first protection circuit 4U comprises delay circuits 411U-41.
4U and AND circuit 421U to 424U, input signal 711U
The rise of ~714U outputs a signal 741U~744U that delaying t _d. The second protection circuit 6U includes delay circuits 611U to 614U.
And the AND circuits 621U and 622U and the OR circuits 631U and 632U, the period during which the input signal 742U is "Lo" and the input signal 742U
Is changed from "Lo" to "Hi", the output signal 751U is set to "Lo" and the input signal 741U is set to "Hi" during the delay time t _d2.
And a period of delay time t _d2 after the input signal 741U changes from "Hi" to "Lo", the output signal 752U is "Hi", and the input signal 744U is "Lo". The output signal 753U is set to "Lo" during the delay time t _d2 after the input signal 744U changes from "Lo" to "Hi".
Is "Hi" and the output signal 752U is "Hi" during the delay time t _{d2 after} the input signal 743U changes from "Hi" to "Lo".
To be

FIG. 4 shows operation waveforms of the PWM modulation circuit of FIG. As shown in the figure, the output signal 741U of the first protection circuit
Up to 744U are signals obtained by delaying the rising edges of the input signals 711U to 714U by t _d1 . In the switching elements S1U to S4U,
The switching operation is delayed by the turn-off time t _{OFF with} respect to the gate signal although the transition from on to off occurs, but t _d1
If> t _OFF , S1U and S3U or S2U and S4U are not turned on at the same time, and the switching element is protected.

On the other hand, the voltage command vu * suddenly changes and the comparator 3
During the transient operation in which the output signal 711U of 1U and the output signal 712U of the comparator 32U change at the same time, the timing of changing the output signal by the second protection circuit 6U is shifted to insert a state in which the output voltage of the inverter becomes 0. As a result, even if the characteristics of the switching element vary, it is possible to avoid a switching state in which the switching element may be destroyed.

The delay time t _d1 of the delay circuit in the first protection circuit 4U is taken into consideration in order to ensure the protection operation and reduce the influence on the PWM control, and the turn-off time t of the switching elements S1U to S4U. Slightly larger than _OFF . In addition, the delay time t of the delay circuit of the second protection circuit
_{The d2} is set to about the turn-off time of the switching elements S1U to S4U in consideration of variations in switching characteristics of the elements. As a result, when the switching elements S1U and S2U are turned on at the same time, the switching element S2U close to the output terminal U
When the switching elements S1U and S2U are simultaneously turned off, the switching element S1U farther from the output terminal U is turned off.

According to this embodiment as described above,
In a DC multiplex inverter, when two or more switching elements are simultaneously turned on, the switching element close to the output terminal is turned on, and when two or more switching elements are simultaneously turned off, the switching element far from the output terminal is turned off. It is possible to prevent the switching element from being broken.

FIG. 4 is a diagram showing still another embodiment of the inverter device according to the present invention. This embodiment is an embodiment for controlling the control of the inverter by software such as a microcomputer, and FIG. 6 is a flowchart of the control program. The control program is started by an interrupt signal synchronized with the carrier wave cycle. In the control program, first, the U-phase output voltage command vu * is read, and the next output voltage V _{N + 1} is determined from this and the phase of the carrier wave. Next, the output time T for changing the output voltage
Calculate _{N + 1} . Here, the current output voltage V _N and the next output voltage V _{N + 1} are compared, and if V _N and V _{N + 1} have opposite polarities,
First, at time T _{N + 1} , the voltage "0" is output, and after that T _d , the voltage V
Output _{N + 1} .

With the control program having the above-mentioned configuration, a state in which the output voltage is 0 is inserted during the transient operation in which the voltage command vu * suddenly changes and the output voltage changes from positive to negative or from negative to positive. Even if there are variations in the characteristics of the switching element, it is possible to avoid a switching state in which the switching element may be destroyed. The delay time _Td is set to about the turn-off time of the switching elements S1U to S4U in consideration of variations in switching characteristics of the elements.

According to this embodiment, in the DC multiplex inverter, when the output voltage is changed from the positive state to the negative state, or when the output voltage is changed from the negative state to the positive state, the output voltage is always changed. It is possible to prevent the switching element from being broken by passing the state of zero.

FIG. 5 shows the configuration of another embodiment of the inverter device according to the present invention. This embodiment relates to a 4-level inverter in which six switching elements are connected in series.

The U-phase output voltage command vu * and the two carrier signals Ec1, Ec2, Ec3 are compared by the comparators 31U, 32U, 33U. Output signals of comparators 31U to 33U 711U to 713U
Is the input signal of the second protection circuit 6U, and the output signals 731U to 733U of the second protection circuit 6U and the inverted signals 734U and 736U of 731U to 733U are the input signals of the first protection circuit 4U. The output signals 721U to 726U of the first protection circuit 4U are used as gate signals for turning on / off the switching elements S1U to S6U, and the gate signals are used as gate amplifiers 51U to 56U.
It is amplified by and supplied to the switching elements S1U to S6U.

The first protection circuit 4U comprises delay circuits 411U-41.
6U and AND circuit 421U-426U, input signal 731U
Outputs signals 721U to 726U in which the rise of ˜736U is delayed by t _d .

The second protection circuit 6U includes delay circuits 611U to 61U.
4U, AND circuits 621U and 622U, and OR circuits 631U and 632U, and an output signal 73 during a period when the output signal 733U is "Lo" and a period of delay time t _d2 after changing from "Lo" to "Hi".
2U is "Lo", and the output signal 731U is "Lo" during the period when the output signal 732U is "Lo" and during the delay time t _d2 after changing from "Lo" to "Hi". Output signal 731U
Is "Hi" and during a period of delay time t _d2 after changing from "Hi" to "Lo", the output signal 732U is set to "Hi", and the output signal 731U is set to "Hi". "Hi" to "Lo"
Output signal 732U is "H" during the delay time t _d2 after the change to
be i ".

The voltage command vu * suddenly changes and the comparator 31U ...
During the transient operation in which two or more output signals of the 33U output signals 711U to 713U change at the same time, the second protection circuit shifts the output signal change timing to set the output voltage to 1
By sequentially changing the levels, it is possible to avoid a switching state in which the switching element may be destroyed even if the characteristics of the switching element vary.

According to the present embodiment, in the DC multiplex inverter, when the output voltage is changed by two levels or more at the same time, the output voltage is always changed one level at a time and the switching element can be prevented from being destroyed.

[0053]

According to the present invention, when the output voltage is switched, the switching element can be controlled so that it is switched one level at a time and the destruction of the switching element can be prevented.

Further, according to the present invention, when a plurality of switching elements are simultaneously fired, the switching elements closer to the output terminal are sequentially fired, and when a plurality of switching elements are simultaneously extinguished, they are far from the output terminal. It is possible to extinguish the arc in order from the switching element and prevent the switching element from being broken.

Further, according to the present invention, when a switching element closer to the output terminal than a certain switching element is extinguished, the ignition of the switching element is prohibited.
When a switching element farther from the output terminal than a certain switching element is ignited, extinguishing the switching element can be prohibited, and destruction of the switching element can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an inverter device according to the present invention.

FIG. 2 is a waveform diagram showing an operating state of the inverter device shown in FIG.

FIG. 3 is a block diagram showing the configuration of another embodiment of the inverter device according to the present invention.

FIG. 4 is a waveform diagram showing an operating state of the inverter device shown in FIG.

FIG. 5 is a flowchart showing the control contents of the inverter device to which the present invention is applied.

FIG. 6 is a block diagram showing a configuration of still another embodiment of the inverter device according to the present invention.

FIG. 7 is a circuit diagram showing a configuration of a serial multiple inverter.

8 is an explanatory diagram showing a relationship between a switching state and an output voltage of the serial multiple inverter shown in FIG.

FIG. 9 is a block diagram showing a configuration of a conventional PWM control circuit.

10 is an operation waveform diagram of the PWM control circuit shown in FIG.

11 is a detailed operation waveform diagram of the PWM control circuit shown in FIG.

FIG. 12 is an explanatory diagram showing a transition of a switching state when the output current is positive.

FIG. 13 is an explanatory diagram showing a transition of a switching state when the output current is negative.

[Explanation of symbols]

 1 series multiple inverter 2 electric motor 4U 1st protection circuit 6U 2nd protection circuit 31U comparator 32U comparator 51U gate amplifier 52U gate amplifier 53U gate amplifier 54U gate amplifier S1U switching element S2U switching element S3U switching element S4U switching element D1U fly Wheel diode D2U Flywheel diode D3U Flywheel diode D4U Flywheel diode CD1U Clamp diode CD2U Clamp diode

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Toshiaki Okuyama 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Kenzo Kamiyama 5-2-1 Omika Town, Hitachi City, Ibaraki Prefecture Ceremony company Hitachi Ltd. Omika factory

Claims (6)

[Claims] 1. In an inverter device including a plurality of switching elements connected in series to a DC power supply and capable of outputting a voltage of three or more levels per phase, when switching the output voltage, be sure to switch by one level at a time. An inverter device having control means for controlling the firing of the plurality of switching elements. 2. An inverter device comprising a plurality of switching elements connected in series to a DC power supply and capable of outputting a voltage of three or more levels per phase, wherein any two of the plurality of switching elements are provided. When the above switching elements are simultaneously ignited, a control means for sequentially igniting the switching elements closer to the output terminal, and in the case of simultaneously extinguishing a plurality of switching elements, sequentially extinguishing the switching elements distant from the output terminal, An inverter device characterized by having. 3. In an inverter device including a plurality of switching elements connected in series to a DC power supply and capable of outputting a voltage of three or more levels per phase, a switching element closer to an output terminal than a certain switching element is When the arc is extinguished, it is prohibited to ignite the switching element, and when the switching element farther from the output terminal than a certain switching element is ignited, it is prohibited to extinguish the switching element. An inverter device having a control means. 4. A direct current power supply having a neutral point output terminal is connected to both terminals of four switching elements, which are first to fourth series-connected terminals, between the two terminals of the second and third switching elements. The interconnection point is connected to the inverter output terminal, and the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements are connected to the neutral point of the DC power source and the diode. In the inverter device configured to be connected and connected, and the first and third switching elements and the second and fourth switching elements are on / off controlled in a conjugate relationship with each other, the output voltage is positive. When the state is changed to the negative state, or when the output voltage is changed from the negative state to the positive state, it is necessary to make the output voltage zero state. An inverter device comprising control means for controlling ignition of the first to fourth switching elements. 5. A direct current power source having a neutral point output terminal is connected to both terminals of four switching elements, which are first to fourth series-connected terminals, between the two terminals of the second and third switching elements. The interconnection point is connected to the inverter output terminal, and the interconnection point of the first and second switching elements and the interconnection point of the third and fourth switching elements are connected to the neutral point of the DC power source and the diode. In the inverter device, the first and third switching elements and the second and fourth switching elements are connected on and off and controlled to be turned on and off in a conjugate relationship with each other. The second switching element is turned on, and the third and fourth switching elements are turned off, the third and fourth switching elements are turned on, and the first and second switches are turned on. The third and fourth switching elements are turned on and the first and second switching elements are turned off, the third and fourth switching elements are turned off, When the first and second switching elements are turned on, the second and third switching elements are always turned on and the first and fourth switching elements are turned off. An inverter device comprising control means for controlling firing of the first to fourth switching elements. 6. The control means comprises: a first comparator for comparing a voltage command and a carrier wave signal; and a second comparator for comparing the voltage command and the carrier wave signal shifted by a predetermined DC level. And the first and second comparators for shifting the firing or extinguishing timings of the first and second switching elements and the third and fourth switching elements when the voltage command suddenly changes. 6. The inverter device according to claim 4 or 5, further comprising a protection circuit that delays the output signal of.